1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* ISA extensions available in 64-bit mode only. */
808 static const i386_cpu_flags cpu_64_flags
= CPU_ANY_64_FLAGS
;
810 /* If we have selected a cpu we are generating instructions for. */
811 static int cpu_arch_tune_set
= 0;
813 /* Cpu we are generating instructions for. */
814 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
816 /* CPU instruction set architecture used. */
817 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of instruction set architecture used. */
820 i386_cpu_flags cpu_arch_isa_flags
;
822 /* If set, conditional jumps are not automatically promoted to handle
823 larger than a byte offset. */
824 static bool no_cond_jump_promotion
= false;
826 /* This will be set from an expression parser hook if there's any
827 applicable operator involved in an expression. */
830 expr_operator_present
,
834 /* Encode SSE instructions with VEX prefix. */
835 static unsigned int sse2avx
;
837 /* Encode aligned vector move as unaligned vector move. */
838 static unsigned int use_unaligned_vector_move
;
840 /* Maximum permitted vector size. */
841 #define VSZ_DEFAULT VSZ512
842 static unsigned int vector_size
= VSZ_DEFAULT
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
977 #define VECARCH(n, e, d, v) \
978 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
979 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
981 static const arch_entry cpu_arch
[] =
983 /* Do not replace the first two entries - i386_target_format() and
984 set_cpu_arch() rely on them being there in this order. */
985 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
986 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
987 ARCH (i8086
, UNKNOWN
, NONE
, false),
988 ARCH (i186
, UNKNOWN
, 186, false),
989 ARCH (i286
, UNKNOWN
, 286, false),
990 ARCH (i386
, I386
, 386, false),
991 ARCH (i486
, I486
, 486, false),
992 ARCH (i586
, PENTIUM
, 586, false),
993 ARCH (pentium
, PENTIUM
, 586, false),
994 ARCH (i686
, I686
, 686, false),
995 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
996 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
997 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
998 ARCH (pentium4
, PENTIUM4
, P4
, false),
999 ARCH (prescott
, NOCONA
, CORE
, false),
1000 ARCH (nocona
, NOCONA
, NOCONA
, false),
1001 ARCH (yonah
, CORE
, CORE
, true),
1002 ARCH (core
, CORE
, CORE
, false),
1003 ARCH (merom
, CORE2
, CORE2
, true),
1004 ARCH (core2
, CORE2
, CORE2
, false),
1005 ARCH (corei7
, COREI7
, COREI7
, false),
1006 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1007 ARCH (k6
, K6
, K6
, false),
1008 ARCH (k6_2
, K6
, K6_2
, false),
1009 ARCH (athlon
, ATHLON
, ATHLON
, false),
1010 ARCH (sledgehammer
, K8
, K8
, true),
1011 ARCH (opteron
, K8
, K8
, false),
1012 ARCH (k8
, K8
, K8
, false),
1013 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1014 ARCH (bdver1
, BD
, BDVER1
, false),
1015 ARCH (bdver2
, BD
, BDVER2
, false),
1016 ARCH (bdver3
, BD
, BDVER3
, false),
1017 ARCH (bdver4
, BD
, BDVER4
, false),
1018 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1019 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1020 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1021 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1022 ARCH (btver1
, BT
, BTVER1
, false),
1023 ARCH (btver2
, BT
, BTVER2
, false),
1025 SUBARCH (8087, 8087, ANY_8087
, false),
1026 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1027 SUBARCH (287, 287, ANY_287
, false),
1028 SUBARCH (387, 387, ANY_387
, false),
1029 SUBARCH (687, 687, ANY_687
, false),
1030 SUBARCH (cmov
, CMOV
, CMOV
, false),
1031 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1032 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1033 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1034 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1035 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1036 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1037 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1038 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1039 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1040 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1041 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1042 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1043 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1044 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1045 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1046 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1047 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1048 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1049 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1050 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1051 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1052 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1053 SUBARCH (smx
, SMX
, SMX
, false),
1054 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1055 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1056 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1057 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1058 SUBARCH (aes
, AES
, ANY_AES
, false),
1059 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1060 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1061 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1062 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1063 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1064 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1065 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1066 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1067 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1068 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1069 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1070 SUBARCH (cx16
, CX16
, CX16
, false),
1071 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1072 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1073 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1074 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1075 SUBARCH (hle
, HLE
, HLE
, false),
1076 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1077 SUBARCH (tsx
, TSX
, TSX
, false),
1078 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1079 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1080 SUBARCH (nop
, NOP
, NOP
, false),
1081 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1082 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1083 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1084 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1085 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1086 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1087 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1088 SUBARCH (abm
, ABM
, ABM
, false),
1089 SUBARCH (bmi
, BMI
, BMI
, false),
1090 SUBARCH (tbm
, TBM
, TBM
, false),
1091 SUBARCH (adx
, ADX
, ADX
, false),
1092 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1093 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1094 SUBARCH (smap
, SMAP
, SMAP
, false),
1095 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1096 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1097 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1098 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1099 SUBARCH (se1
, SE1
, SE1
, false),
1100 SUBARCH (clwb
, CLWB
, CLWB
, false),
1101 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1102 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1103 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1104 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1105 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1106 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1107 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1108 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1109 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1110 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1111 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1112 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1113 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1114 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1115 SUBARCH (ibt
, IBT
, IBT
, false),
1116 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1117 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1118 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1119 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1120 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1121 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1122 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1123 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1124 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1125 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1126 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1127 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1128 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1129 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1130 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1131 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1132 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1133 ANY_AVX512_VP2INTERSECT
, reset
),
1134 SUBARCH (tdx
, TDX
, TDX
, false),
1135 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1136 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1137 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1138 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1139 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1140 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1141 SUBARCH (kl
, KL
, ANY_KL
, false),
1142 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1143 SUBARCH (uintr
, UINTR
, UINTR
, false),
1144 SUBARCH (hreset
, HRESET
, HRESET
, false),
1145 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1146 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1147 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1148 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1149 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1150 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1151 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1152 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1153 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1154 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1155 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1156 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1157 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1158 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1159 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1160 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1161 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1162 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1163 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1170 /* Like s_lcomm_internal in gas/read.c but the alignment string
1171 is allowed to be optional. */
1174 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1181 && *input_line_pointer
== ',')
1183 align
= parse_align (needs_align
- 1);
1185 if (align
== (addressT
) -1)
1200 bss_alloc (symbolP
, size
, align
);
1205 pe_lcomm (int needs_align
)
1207 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1211 const pseudo_typeS md_pseudo_table
[] =
1213 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1214 {"align", s_align_bytes
, 0},
1216 {"align", s_align_ptwo
, 0},
1218 {"arch", set_cpu_arch
, 0},
1222 {"lcomm", pe_lcomm
, 1},
1224 {"ffloat", float_cons
, 'f'},
1225 {"dfloat", float_cons
, 'd'},
1226 {"tfloat", float_cons
, 'x'},
1227 {"hfloat", float_cons
, 'h'},
1228 {"bfloat16", float_cons
, 'b'},
1230 {"slong", signed_cons
, 4},
1231 {"insn", s_insn
, 0},
1232 {"noopt", s_ignore
, 0},
1233 {"optim", s_ignore
, 0},
1234 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1235 {"code16", set_code_flag
, CODE_16BIT
},
1236 {"code32", set_code_flag
, CODE_32BIT
},
1238 {"code64", set_code_flag
, CODE_64BIT
},
1240 {"intel_syntax", set_intel_syntax
, 1},
1241 {"att_syntax", set_intel_syntax
, 0},
1242 {"intel_mnemonic", set_intel_mnemonic
, 1},
1243 {"att_mnemonic", set_intel_mnemonic
, 0},
1244 {"allow_index_reg", set_allow_index_reg
, 1},
1245 {"disallow_index_reg", set_allow_index_reg
, 0},
1246 {"sse_check", set_check
, 0},
1247 {"operand_check", set_check
, 1},
1248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1249 {"largecomm", handle_large_common
, 0},
1251 {"file", dwarf2_directive_file
, 0},
1252 {"loc", dwarf2_directive_loc
, 0},
1253 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1256 {"secrel32", pe_directive_secrel
, 0},
1257 {"secidx", pe_directive_secidx
, 0},
1262 /* For interface with expression (). */
1263 extern char *input_line_pointer
;
1265 /* Hash table for instruction mnemonic lookup. */
1266 static htab_t op_hash
;
1268 /* Hash table for register lookup. */
1269 static htab_t reg_hash
;
1271 /* Various efficient no-op patterns for aligning code labels.
1272 Note: Don't try to assemble the instructions in the comments.
1273 0L and 0w are not legal. */
1274 static const unsigned char f32_1
[] =
1276 static const unsigned char f32_2
[] =
1277 {0x66,0x90}; /* xchg %ax,%ax */
1278 static const unsigned char f32_3
[] =
1279 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1280 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1281 static const unsigned char f32_5
[] =
1282 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1283 static const unsigned char f32_6
[] =
1284 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1285 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1286 static const unsigned char f32_8
[] =
1287 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1288 static const unsigned char f64_3
[] =
1289 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1290 static const unsigned char f64_4
[] =
1291 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1292 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1293 static const unsigned char f64_6
[] =
1294 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1295 static const unsigned char f64_7
[] =
1296 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1297 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1298 static const unsigned char f64_9
[] =
1299 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1300 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1301 static const unsigned char f16_3
[] =
1302 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1303 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1304 static const unsigned char f16_5
[] =
1305 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1306 static const unsigned char jump_disp8
[] =
1307 {0xeb}; /* jmp disp8 */
1308 static const unsigned char jump32_disp32
[] =
1309 {0xe9}; /* jmp disp32 */
1310 static const unsigned char jump16_disp32
[] =
1311 {0x66,0xe9}; /* jmp disp32 */
1312 /* 32-bit NOPs patterns. */
1313 static const unsigned char *const f32_patt
[] = {
1314 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1316 /* 64-bit NOPs patterns. */
1317 static const unsigned char *const f64_patt
[] = {
1318 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1320 /* 16-bit NOPs patterns. */
1321 static const unsigned char *const f16_patt
[] = {
1322 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1324 /* nopl (%[re]ax) */
1325 static const unsigned char alt_3
[] =
1327 /* nopl 0(%[re]ax) */
1328 static const unsigned char alt_4
[] =
1329 {0x0f,0x1f,0x40,0x00};
1330 /* nopl 0(%[re]ax,%[re]ax,1) */
1331 #define alt_5 (alt_6 + 1)
1332 /* nopw 0(%[re]ax,%[re]ax,1) */
1333 static const unsigned char alt_6
[] =
1334 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1335 /* nopl 0L(%[re]ax) */
1336 static const unsigned char alt_7
[] =
1337 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1338 /* nopl 0L(%[re]ax,%[re]ax,1) */
1339 #define alt_8 (alt_9 + 1)
1340 /* nopw 0L(%[re]ax,%[re]ax,1) */
1341 static const unsigned char alt_9
[] =
1342 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1343 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1344 #define alt_10 (alt_11 + 1)
1345 /* data16 nopw %cs:0L(%eax,%eax,1) */
1346 static const unsigned char alt_11
[] =
1347 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1348 /* 32-bit and 64-bit NOPs patterns. */
1349 static const unsigned char *const alt_patt
[] = {
1350 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1351 alt_9
, alt_10
, alt_11
1354 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1355 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1358 i386_output_nops (char *where
, const unsigned char *const *patt
,
1359 int count
, int max_single_nop_size
)
1362 /* Place the longer NOP first. */
1365 const unsigned char *nops
;
1367 if (max_single_nop_size
< 1)
1369 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1370 max_single_nop_size
);
1374 nops
= patt
[max_single_nop_size
- 1];
1375 last
= count
% max_single_nop_size
;
1378 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1379 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1383 nops
= patt
[last
- 1];
1384 memcpy (where
+ offset
, nops
, last
);
1389 fits_in_imm7 (offsetT num
)
1391 return (num
& 0x7f) == num
;
1395 fits_in_imm31 (offsetT num
)
1397 return (num
& 0x7fffffff) == num
;
1400 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1401 single NOP instruction LIMIT. */
1404 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1406 const unsigned char *const *patt
= NULL
;
1407 int max_single_nop_size
;
1408 /* Maximum number of NOPs before switching to jump over NOPs. */
1409 int max_number_of_nops
;
1411 switch (fragP
->fr_type
)
1416 case rs_machine_dependent
:
1417 /* Allow NOP padding for jumps and calls. */
1418 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1419 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1426 /* We need to decide which NOP sequence to use for 32bit and
1427 64bit. When -mtune= is used:
1429 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1430 PROCESSOR_GENERIC32, f32_patt will be used.
1431 2. For the rest, alt_patt will be used.
1433 When -mtune= isn't used, alt_patt will be used if
1434 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1437 When -march= or .arch is used, we can't use anything beyond
1438 cpu_arch_isa_flags. */
1440 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1443 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1444 /* Limit number of NOPs to 2 in 16-bit mode. */
1445 max_number_of_nops
= 2;
1449 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1450 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1452 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1453 explicitly disabled. */
1454 switch (fragP
->tc_frag_data
.tune
)
1456 case PROCESSOR_UNKNOWN
:
1457 /* We use cpu_arch_isa_flags to check if we SHOULD
1458 optimize with nops. */
1459 if (fragP
->tc_frag_data
.isanop
)
1463 case PROCESSOR_PENTIUMPRO
:
1464 case PROCESSOR_PENTIUM4
:
1465 case PROCESSOR_NOCONA
:
1466 case PROCESSOR_CORE
:
1467 case PROCESSOR_CORE2
:
1468 case PROCESSOR_COREI7
:
1469 case PROCESSOR_GENERIC64
:
1471 case PROCESSOR_ATHLON
:
1473 case PROCESSOR_AMDFAM10
:
1475 case PROCESSOR_ZNVER
:
1477 if (fragP
->tc_frag_data
.cpunop
)
1481 case PROCESSOR_I386
:
1482 case PROCESSOR_I486
:
1483 case PROCESSOR_PENTIUM
:
1484 case PROCESSOR_I686
:
1485 case PROCESSOR_IAMCU
:
1486 case PROCESSOR_GENERIC32
:
1488 case PROCESSOR_NONE
:
1494 switch (fragP
->tc_frag_data
.tune
)
1496 case PROCESSOR_UNKNOWN
:
1497 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1498 PROCESSOR_UNKNOWN. */
1503 /* We use cpu_arch_isa_flags to check if we CAN optimize
1505 if (fragP
->tc_frag_data
.isanop
)
1509 case PROCESSOR_NONE
:
1514 if (patt
!= alt_patt
)
1516 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1517 : ARRAY_SIZE (f64_patt
);
1518 /* Limit number of NOPs to 2 for older processors. */
1519 max_number_of_nops
= 2;
1523 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1524 /* Limit number of NOPs to 7 for newer processors. */
1525 max_number_of_nops
= 7;
1530 limit
= max_single_nop_size
;
1532 if (fragP
->fr_type
== rs_fill_nop
)
1534 /* Output NOPs for .nop directive. */
1535 if (limit
> max_single_nop_size
)
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("invalid single nop size: %d "
1539 "(expect within [0, %d])"),
1540 limit
, max_single_nop_size
);
1544 else if (fragP
->fr_type
!= rs_machine_dependent
)
1545 fragP
->fr_var
= count
;
1547 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1549 /* Generate jump over NOPs. */
1550 offsetT disp
= count
- 2;
1551 if (fits_in_imm7 (disp
))
1553 /* Use "jmp disp8" if possible. */
1555 where
[0] = jump_disp8
[0];
1561 unsigned int size_of_jump
;
1563 if (flag_code
== CODE_16BIT
)
1565 where
[0] = jump16_disp32
[0];
1566 where
[1] = jump16_disp32
[1];
1571 where
[0] = jump32_disp32
[0];
1575 count
-= size_of_jump
+ 4;
1576 if (!fits_in_imm31 (count
))
1578 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1579 _("jump over nop padding out of range"));
1583 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1584 where
+= size_of_jump
+ 4;
1588 /* Generate multiple NOPs. */
1589 i386_output_nops (where
, patt
, count
, limit
);
1593 operand_type_all_zero (const union i386_operand_type
*x
)
1595 switch (ARRAY_SIZE(x
->array
))
1606 return !x
->array
[0];
1613 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1615 switch (ARRAY_SIZE(x
->array
))
1631 x
->bitfield
.class = ClassNone
;
1632 x
->bitfield
.instance
= InstanceNone
;
1636 operand_type_equal (const union i386_operand_type
*x
,
1637 const union i386_operand_type
*y
)
1639 switch (ARRAY_SIZE(x
->array
))
1642 if (x
->array
[2] != y
->array
[2])
1646 if (x
->array
[1] != y
->array
[1])
1650 return x
->array
[0] == y
->array
[0];
1658 _is_cpu (const i386_cpu_attr
*a
, enum i386_cpu cpu
)
1662 case Cpu287
: return a
->bitfield
.cpu287
;
1663 case Cpu387
: return a
->bitfield
.cpu387
;
1664 case Cpu3dnow
: return a
->bitfield
.cpu3dnow
;
1665 case Cpu3dnowA
: return a
->bitfield
.cpu3dnowa
;
1666 case CpuAVX
: return a
->bitfield
.cpuavx
;
1667 case CpuHLE
: return a
->bitfield
.cpuhle
;
1668 case CpuAVX512F
: return a
->bitfield
.cpuavx512f
;
1669 case CpuAVX512VL
: return a
->bitfield
.cpuavx512vl
;
1670 case Cpu64
: return a
->bitfield
.cpu64
;
1671 case CpuNo64
: return a
->bitfield
.cpuno64
;
1673 gas_assert (cpu
< CpuAttrEnums
);
1675 return a
->bitfield
.isa
== cpu
+ 1u;
1679 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1681 return _is_cpu(&t
->cpu
, cpu
);
1685 maybe_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1687 return _is_cpu(&t
->cpu_any
, cpu
);
1690 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1692 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1693 i386_cpu_flags f
= { .array
[0] = 0 };
1695 switch (ARRAY_SIZE(a
.array
))
1698 f
.array
[CpuAttrEnums
/ bps
]
1699 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1700 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1701 f
.array
[CpuAttrEnums
/ bps
+ 1]
1702 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1709 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1715 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1717 switch (ARRAY_SIZE(x
->array
))
1736 return !x
->array
[0];
1743 cpu_flags_equal (const union i386_cpu_flags
*x
,
1744 const union i386_cpu_flags
*y
)
1746 switch (ARRAY_SIZE(x
->array
))
1749 if (x
->array
[4] != y
->array
[4])
1753 if (x
->array
[3] != y
->array
[3])
1757 if (x
->array
[2] != y
->array
[2])
1761 if (x
->array
[1] != y
->array
[1])
1765 return x
->array
[0] == y
->array
[0];
1773 cpu_flags_check_cpu64 (const insn_template
*t
)
1775 return flag_code
== CODE_64BIT
1776 ? !t
->cpu
.bitfield
.cpuno64
1777 : !t
->cpu
.bitfield
.cpu64
;
1780 static INLINE i386_cpu_flags
1781 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1783 switch (ARRAY_SIZE (x
.array
))
1786 x
.array
[4] &= y
.array
[4];
1789 x
.array
[3] &= y
.array
[3];
1792 x
.array
[2] &= y
.array
[2];
1795 x
.array
[1] &= y
.array
[1];
1798 x
.array
[0] &= y
.array
[0];
1806 static INLINE i386_cpu_flags
1807 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1809 switch (ARRAY_SIZE (x
.array
))
1812 x
.array
[4] |= y
.array
[4];
1815 x
.array
[3] |= y
.array
[3];
1818 x
.array
[2] |= y
.array
[2];
1821 x
.array
[1] |= y
.array
[1];
1824 x
.array
[0] |= y
.array
[0];
1832 static INLINE i386_cpu_flags
1833 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1835 switch (ARRAY_SIZE (x
.array
))
1838 x
.array
[4] &= ~y
.array
[4];
1841 x
.array
[3] &= ~y
.array
[3];
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1860 static INLINE
bool need_evex_encoding (void)
1862 return i
.vec_encoding
== vex_encoding_evex
1863 || i
.vec_encoding
== vex_encoding_evex512
1867 #define CPU_FLAGS_ARCH_MATCH 0x1
1868 #define CPU_FLAGS_64BIT_MATCH 0x2
1870 #define CPU_FLAGS_PERFECT_MATCH \
1871 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1873 /* Return CPU flags match bits. */
1876 cpu_flags_match (const insn_template
*t
)
1878 i386_cpu_flags cpu
, active
, all
= cpu_flags_from_attr (t
->cpu
);
1879 i386_cpu_flags any
= cpu_flags_from_attr (t
->cpu_any
);
1880 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1882 all
.bitfield
.cpu64
= 0;
1883 all
.bitfield
.cpuno64
= 0;
1884 gas_assert (!any
.bitfield
.cpu64
);
1885 gas_assert (!any
.bitfield
.cpuno64
);
1887 if (cpu_flags_all_zero (&all
) && cpu_flags_all_zero (&any
))
1889 /* This instruction is available on all archs. */
1890 return match
| CPU_FLAGS_ARCH_MATCH
;
1893 /* This instruction is available only on some archs. */
1895 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1896 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1898 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1899 know that EVEX encoding will be needed. */
1900 if ((any
.bitfield
.cpuavx
|| any
.bitfield
.cpuavx2
|| any
.bitfield
.cpufma
)
1901 && (any
.bitfield
.cpuavx512f
|| any
.bitfield
.cpuavx512vl
))
1903 if (need_evex_encoding ())
1905 any
.bitfield
.cpuavx
= 0;
1906 any
.bitfield
.cpuavx2
= 0;
1907 any
.bitfield
.cpufma
= 0;
1909 /* need_evex_encoding() isn't reliable before operands were
1911 else if (i
.operands
)
1913 any
.bitfield
.cpuavx512f
= 0;
1914 any
.bitfield
.cpuavx512vl
= 0;
1919 if (flag_code
!= CODE_64BIT
)
1920 active
= cpu_flags_and_not (cpu_arch_flags
, cpu_64_flags
);
1922 active
= cpu_arch_flags
;
1923 cpu
= cpu_flags_and (all
, active
);
1924 if (cpu_flags_equal (&cpu
, &all
))
1926 /* AVX and AVX2 present at the same time express an operand size
1927 dependency - strip AVX2 for the purposes here. The operand size
1928 dependent check occurs in check_vecOperands(). */
1929 if (any
.bitfield
.cpuavx
&& any
.bitfield
.cpuavx2
)
1930 any
.bitfield
.cpuavx2
= 0;
1932 cpu
= cpu_flags_and (any
, active
);
1933 if (cpu_flags_all_zero (&any
) || !cpu_flags_all_zero (&cpu
))
1935 if (all
.bitfield
.cpuavx
)
1937 /* We need to check SSE2AVX with AVX. */
1938 if (!t
->opcode_modifier
.sse2avx
1939 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1940 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 match
|= CPU_FLAGS_ARCH_MATCH
;
1949 static INLINE i386_operand_type
1950 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1952 if (x
.bitfield
.class != y
.bitfield
.class)
1953 x
.bitfield
.class = ClassNone
;
1954 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1955 x
.bitfield
.instance
= InstanceNone
;
1957 switch (ARRAY_SIZE (x
.array
))
1960 x
.array
[2] &= y
.array
[2];
1963 x
.array
[1] &= y
.array
[1];
1966 x
.array
[0] &= y
.array
[0];
1974 static INLINE i386_operand_type
1975 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1977 gas_assert (y
.bitfield
.class == ClassNone
);
1978 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1980 switch (ARRAY_SIZE (x
.array
))
1983 x
.array
[2] &= ~y
.array
[2];
1986 x
.array
[1] &= ~y
.array
[1];
1989 x
.array
[0] &= ~y
.array
[0];
1997 static INLINE i386_operand_type
1998 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2000 gas_assert (x
.bitfield
.class == ClassNone
||
2001 y
.bitfield
.class == ClassNone
||
2002 x
.bitfield
.class == y
.bitfield
.class);
2003 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2004 y
.bitfield
.instance
== InstanceNone
||
2005 x
.bitfield
.instance
== y
.bitfield
.instance
);
2007 switch (ARRAY_SIZE (x
.array
))
2010 x
.array
[2] |= y
.array
[2];
2013 x
.array
[1] |= y
.array
[1];
2016 x
.array
[0] |= y
.array
[0];
2024 static INLINE i386_operand_type
2025 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2027 gas_assert (y
.bitfield
.class == ClassNone
);
2028 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2030 switch (ARRAY_SIZE (x
.array
))
2033 x
.array
[2] ^= y
.array
[2];
2036 x
.array
[1] ^= y
.array
[1];
2039 x
.array
[0] ^= y
.array
[0];
2047 static const i386_operand_type anydisp
= {
2048 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2060 operand_type_check (i386_operand_type t
, enum operand_type c
)
2065 return t
.bitfield
.class == Reg
;
2068 return (t
.bitfield
.imm8
2072 || t
.bitfield
.imm32s
2073 || t
.bitfield
.imm64
);
2076 return (t
.bitfield
.disp8
2077 || t
.bitfield
.disp16
2078 || t
.bitfield
.disp32
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp64
2086 || t
.bitfield
.baseindex
);
2095 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2096 between operand GIVEN and opeand WANTED for instruction template T. */
2099 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2102 return !((i
.types
[given
].bitfield
.byte
2103 && !t
->operand_types
[wanted
].bitfield
.byte
)
2104 || (i
.types
[given
].bitfield
.word
2105 && !t
->operand_types
[wanted
].bitfield
.word
)
2106 || (i
.types
[given
].bitfield
.dword
2107 && !t
->operand_types
[wanted
].bitfield
.dword
)
2108 || (i
.types
[given
].bitfield
.qword
2109 && (!t
->operand_types
[wanted
].bitfield
.qword
2110 /* Don't allow 64-bit (memory) operands outside of 64-bit
2111 mode, when they're used where a 64-bit GPR could also
2112 be used. Checking is needed for Intel Syntax only. */
2114 && flag_code
!= CODE_64BIT
2115 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2116 || t
->operand_types
[wanted
].bitfield
.class == Accum
2117 || t
->opcode_modifier
.isstring
))))
2118 || (i
.types
[given
].bitfield
.tbyte
2119 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2122 /* Return 1 if there is no conflict in SIMD register between operand
2123 GIVEN and opeand WANTED for instruction template T. */
2126 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2129 return !((i
.types
[given
].bitfield
.xmmword
2130 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2131 || (i
.types
[given
].bitfield
.ymmword
2132 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2133 || (i
.types
[given
].bitfield
.zmmword
2134 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2135 || (i
.types
[given
].bitfield
.tmmword
2136 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2139 /* Return 1 if there is no conflict in any size between operand GIVEN
2140 and opeand WANTED for instruction template T. */
2143 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2146 return (match_operand_size (t
, wanted
, given
)
2147 && !((i
.types
[given
].bitfield
.unspecified
2148 && !i
.broadcast
.type
2149 && !i
.broadcast
.bytes
2150 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2151 || (i
.types
[given
].bitfield
.fword
2152 && !t
->operand_types
[wanted
].bitfield
.fword
)
2153 /* For scalar opcode templates to allow register and memory
2154 operands at the same time, some special casing is needed
2155 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2156 down-conversion vpmov*. */
2157 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2158 && t
->operand_types
[wanted
].bitfield
.byte
2159 + t
->operand_types
[wanted
].bitfield
.word
2160 + t
->operand_types
[wanted
].bitfield
.dword
2161 + t
->operand_types
[wanted
].bitfield
.qword
2162 > !!t
->opcode_modifier
.broadcast
)
2163 ? (i
.types
[given
].bitfield
.xmmword
2164 || i
.types
[given
].bitfield
.ymmword
2165 || i
.types
[given
].bitfield
.zmmword
)
2166 : !match_simd_size(t
, wanted
, given
))));
2169 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2170 operands for instruction template T, and it has MATCH_REVERSE set if there
2171 is no size conflict on any operands for the template with operands reversed
2172 (and the template allows for reversing in the first place). */
2174 #define MATCH_STRAIGHT 1
2175 #define MATCH_REVERSE 2
2177 static INLINE
unsigned int
2178 operand_size_match (const insn_template
*t
)
2180 unsigned int j
, match
= MATCH_STRAIGHT
;
2182 /* Don't check non-absolute jump instructions. */
2183 if (t
->opcode_modifier
.jump
2184 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2187 /* Check memory and accumulator operand size. */
2188 for (j
= 0; j
< i
.operands
; j
++)
2190 if (i
.types
[j
].bitfield
.class != Reg
2191 && i
.types
[j
].bitfield
.class != RegSIMD
2192 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2195 if (t
->operand_types
[j
].bitfield
.class == Reg
2196 && !match_operand_size (t
, j
, j
))
2202 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2203 && !match_simd_size (t
, j
, j
))
2209 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2210 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2216 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2223 if (!t
->opcode_modifier
.d
)
2226 /* Check reverse. */
2227 gas_assert (i
.operands
>= 2);
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 unsigned int given
= i
.operands
- j
- 1;
2233 /* For FMA4 and XOP insns VEX.W controls just the first two
2234 register operands. */
2235 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2236 given
= j
< 2 ? 1 - j
: j
;
2238 if (t
->operand_types
[j
].bitfield
.class == Reg
2239 && !match_operand_size (t
, j
, given
))
2242 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2243 && !match_simd_size (t
, j
, given
))
2246 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2247 && (!match_operand_size (t
, j
, given
)
2248 || !match_simd_size (t
, j
, given
)))
2251 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2255 return match
| MATCH_REVERSE
;
2259 operand_type_match (i386_operand_type overlap
,
2260 i386_operand_type given
)
2262 i386_operand_type temp
= overlap
;
2264 temp
.bitfield
.unspecified
= 0;
2265 temp
.bitfield
.byte
= 0;
2266 temp
.bitfield
.word
= 0;
2267 temp
.bitfield
.dword
= 0;
2268 temp
.bitfield
.fword
= 0;
2269 temp
.bitfield
.qword
= 0;
2270 temp
.bitfield
.tbyte
= 0;
2271 temp
.bitfield
.xmmword
= 0;
2272 temp
.bitfield
.ymmword
= 0;
2273 temp
.bitfield
.zmmword
= 0;
2274 temp
.bitfield
.tmmword
= 0;
2275 if (operand_type_all_zero (&temp
))
2278 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2282 i
.error
= operand_type_mismatch
;
2286 /* If given types g0 and g1 are registers they must be of the same type
2287 unless the expected operand type register overlap is null.
2288 Intel syntax sized memory operands are also checked here. */
2291 operand_type_register_match (i386_operand_type g0
,
2292 i386_operand_type t0
,
2293 i386_operand_type g1
,
2294 i386_operand_type t1
)
2296 if (g0
.bitfield
.class != Reg
2297 && g0
.bitfield
.class != RegSIMD
2298 && (g0
.bitfield
.unspecified
2299 || !operand_type_check (g0
, anymem
)))
2302 if (g1
.bitfield
.class != Reg
2303 && g1
.bitfield
.class != RegSIMD
2304 && (g1
.bitfield
.unspecified
2305 || !operand_type_check (g1
, anymem
)))
2308 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2309 && g0
.bitfield
.word
== g1
.bitfield
.word
2310 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2311 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2312 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2313 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2314 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2317 /* If expectations overlap in no more than a single size, all is fine. */
2318 g0
= operand_type_and (t0
, t1
);
2319 if (g0
.bitfield
.byte
2323 + g0
.bitfield
.xmmword
2324 + g0
.bitfield
.ymmword
2325 + g0
.bitfield
.zmmword
<= 1)
2328 i
.error
= register_type_mismatch
;
2333 static INLINE
unsigned int
2334 register_number (const reg_entry
*r
)
2336 unsigned int nr
= r
->reg_num
;
2338 if (r
->reg_flags
& RegRex
)
2341 if (r
->reg_flags
& RegVRex
)
2347 static INLINE
unsigned int
2348 mode_from_disp_size (i386_operand_type t
)
2350 if (t
.bitfield
.disp8
)
2352 else if (t
.bitfield
.disp16
2353 || t
.bitfield
.disp32
)
2360 fits_in_signed_byte (addressT num
)
2362 return num
+ 0x80 <= 0xff;
2366 fits_in_unsigned_byte (addressT num
)
2372 fits_in_unsigned_word (addressT num
)
2374 return num
<= 0xffff;
2378 fits_in_signed_word (addressT num
)
2380 return num
+ 0x8000 <= 0xffff;
2384 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2389 return num
+ 0x80000000 <= 0xffffffff;
2391 } /* fits_in_signed_long() */
2394 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2399 return num
<= 0xffffffff;
2401 } /* fits_in_unsigned_long() */
2403 static INLINE valueT
extend_to_32bit_address (addressT num
)
2406 if (fits_in_unsigned_long(num
))
2407 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2409 if (!fits_in_signed_long (num
))
2410 return num
& 0xffffffff;
2417 fits_in_disp8 (offsetT num
)
2419 int shift
= i
.memshift
;
2425 mask
= (1 << shift
) - 1;
2427 /* Return 0 if NUM isn't properly aligned. */
2431 /* Check if NUM will fit in 8bit after shift. */
2432 return fits_in_signed_byte (num
>> shift
);
2436 fits_in_imm4 (offsetT num
)
2438 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2439 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2442 static i386_operand_type
2443 smallest_imm_type (offsetT num
)
2445 i386_operand_type t
;
2447 operand_type_set (&t
, 0);
2448 t
.bitfield
.imm64
= 1;
2450 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2452 /* This code is disabled on the 486 because all the Imm1 forms
2453 in the opcode table are slower on the i486. They're the
2454 versions with the implicitly specified single-position
2455 displacement, which has another syntax if you really want to
2457 t
.bitfield
.imm1
= 1;
2458 t
.bitfield
.imm8
= 1;
2459 t
.bitfield
.imm8s
= 1;
2460 t
.bitfield
.imm16
= 1;
2461 t
.bitfield
.imm32
= 1;
2462 t
.bitfield
.imm32s
= 1;
2464 else if (fits_in_signed_byte (num
))
2466 if (fits_in_unsigned_byte (num
))
2467 t
.bitfield
.imm8
= 1;
2468 t
.bitfield
.imm8s
= 1;
2469 t
.bitfield
.imm16
= 1;
2470 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2471 t
.bitfield
.imm32
= 1;
2472 t
.bitfield
.imm32s
= 1;
2474 else if (fits_in_unsigned_byte (num
))
2476 t
.bitfield
.imm8
= 1;
2477 t
.bitfield
.imm16
= 1;
2478 t
.bitfield
.imm32
= 1;
2479 t
.bitfield
.imm32s
= 1;
2481 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2483 t
.bitfield
.imm16
= 1;
2484 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2485 t
.bitfield
.imm32
= 1;
2486 t
.bitfield
.imm32s
= 1;
2488 else if (fits_in_signed_long (num
))
2490 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_unsigned_long (num
))
2495 t
.bitfield
.imm32
= 1;
2501 offset_in_range (offsetT val
, int size
)
2507 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2508 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2510 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2512 case sizeof (val
): return val
;
2516 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2517 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2518 (uint64_t) val
, (uint64_t) (val
& mask
));
2523 static INLINE
const char *insn_name (const insn_template
*t
)
2525 return &i386_mnemonics
[t
->mnem_off
];
2538 a. PREFIX_EXIST if attempting to add a prefix where one from the
2539 same class already exists.
2540 b. PREFIX_LOCK if lock prefix is added.
2541 c. PREFIX_REP if rep/repne prefix is added.
2542 d. PREFIX_DS if ds prefix is added.
2543 e. PREFIX_OTHER if other prefix is added.
2546 static enum PREFIX_GROUP
2547 add_prefix (unsigned int prefix
)
2549 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2552 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2553 && flag_code
== CODE_64BIT
)
2555 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2556 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2557 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2558 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2569 case DS_PREFIX_OPCODE
:
2572 case CS_PREFIX_OPCODE
:
2573 case ES_PREFIX_OPCODE
:
2574 case FS_PREFIX_OPCODE
:
2575 case GS_PREFIX_OPCODE
:
2576 case SS_PREFIX_OPCODE
:
2580 case REPNE_PREFIX_OPCODE
:
2581 case REPE_PREFIX_OPCODE
:
2586 case LOCK_PREFIX_OPCODE
:
2595 case ADDR_PREFIX_OPCODE
:
2599 case DATA_PREFIX_OPCODE
:
2603 if (i
.prefix
[q
] != 0)
2611 i
.prefix
[q
] |= prefix
;
2614 as_bad (_("same type of prefix used twice"));
2620 update_code_flag (int value
, int check
)
2622 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2624 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2626 as_error (_("64bit mode not supported on `%s'."),
2627 cpu_arch_name
? cpu_arch_name
: default_arch
);
2631 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2633 as_error (_("32bit mode not supported on `%s'."),
2634 cpu_arch_name
? cpu_arch_name
: default_arch
);
2638 flag_code
= (enum flag_code
) value
;
2640 stackop_size
= '\0';
2644 set_code_flag (int value
)
2646 update_code_flag (value
, 0);
2650 set_16bit_gcc_code_flag (int new_code_flag
)
2652 flag_code
= (enum flag_code
) new_code_flag
;
2653 if (flag_code
!= CODE_16BIT
)
2655 stackop_size
= LONG_MNEM_SUFFIX
;
2659 set_intel_syntax (int syntax_flag
)
2661 /* Find out if register prefixing is specified. */
2662 int ask_naked_reg
= 0;
2665 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2668 int e
= get_symbol_name (&string
);
2670 if (strcmp (string
, "prefix") == 0)
2672 else if (strcmp (string
, "noprefix") == 0)
2675 as_bad (_("bad argument to syntax directive."));
2676 (void) restore_line_pointer (e
);
2678 demand_empty_rest_of_line ();
2680 intel_syntax
= syntax_flag
;
2682 if (ask_naked_reg
== 0)
2683 allow_naked_reg
= (intel_syntax
2684 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2686 allow_naked_reg
= (ask_naked_reg
< 0);
2688 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2690 register_prefix
= allow_naked_reg
? "" : "%";
2694 set_intel_mnemonic (int mnemonic_flag
)
2696 intel_mnemonic
= mnemonic_flag
;
2700 set_allow_index_reg (int flag
)
2702 allow_index_reg
= flag
;
2706 set_check (int what
)
2708 enum check_kind
*kind
;
2713 kind
= &operand_check
;
2724 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2727 int e
= get_symbol_name (&string
);
2729 if (strcmp (string
, "none") == 0)
2731 else if (strcmp (string
, "warning") == 0)
2732 *kind
= check_warning
;
2733 else if (strcmp (string
, "error") == 0)
2734 *kind
= check_error
;
2736 as_bad (_("bad argument to %s_check directive."), str
);
2737 (void) restore_line_pointer (e
);
2740 as_bad (_("missing argument for %s_check directive"), str
);
2742 demand_empty_rest_of_line ();
2746 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2747 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2750 static const char *arch
;
2752 /* Intel MCU is only supported on ELF. */
2758 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2759 use default_arch. */
2760 arch
= cpu_arch_name
;
2762 arch
= default_arch
;
2765 /* If we are targeting Intel MCU, we must enable it. */
2766 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2767 == new_flag
.bitfield
.cpuiamcu
)
2770 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2775 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2777 if (cpu_sub_arch_name
)
2778 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2779 pfx
, name
, (const char *) NULL
);
2781 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2784 static void isa_enable (unsigned int idx
)
2786 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2788 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2790 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2791 cpu_arch_flags
= flags
;
2794 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2797 static void isa_disable (unsigned int idx
)
2799 i386_cpu_flags flags
2800 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2802 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2804 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2805 cpu_arch_flags
= flags
;
2809 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2813 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2815 typedef struct arch_stack_entry
2817 const struct arch_stack_entry
*prev
;
2820 i386_cpu_flags flags
;
2821 i386_cpu_flags isa_flags
;
2822 enum processor_type isa
;
2823 enum flag_code flag_code
;
2824 unsigned int vector_size
;
2826 bool no_cond_jump_promotion
;
2828 static const arch_stack_entry
*arch_stack_top
;
2836 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2838 as_bad (_("missing cpu architecture"));
2839 input_line_pointer
++;
2843 e
= get_symbol_name (&s
);
2846 if (strcmp (string
, "push") == 0)
2848 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2850 top
->name
= cpu_arch_name
;
2851 if (cpu_sub_arch_name
)
2852 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2854 top
->sub_name
= NULL
;
2855 top
->flags
= cpu_arch_flags
;
2856 top
->isa
= cpu_arch_isa
;
2857 top
->isa_flags
= cpu_arch_isa_flags
;
2858 top
->flag_code
= flag_code
;
2859 top
->vector_size
= vector_size
;
2860 top
->stackop_size
= stackop_size
;
2861 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2863 top
->prev
= arch_stack_top
;
2864 arch_stack_top
= top
;
2866 (void) restore_line_pointer (e
);
2867 demand_empty_rest_of_line ();
2871 if (strcmp (string
, "pop") == 0)
2873 const arch_stack_entry
*top
= arch_stack_top
;
2876 as_bad (_(".arch stack is empty"));
2877 else if (top
->flag_code
!= flag_code
2878 || top
->stackop_size
!= stackop_size
)
2880 static const unsigned int bits
[] = {
2886 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2887 bits
[top
->flag_code
],
2888 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2892 arch_stack_top
= top
->prev
;
2894 cpu_arch_name
= top
->name
;
2895 free (cpu_sub_arch_name
);
2896 cpu_sub_arch_name
= top
->sub_name
;
2897 cpu_arch_flags
= top
->flags
;
2898 cpu_arch_isa
= top
->isa
;
2899 cpu_arch_isa_flags
= top
->isa_flags
;
2900 vector_size
= top
->vector_size
;
2901 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2906 (void) restore_line_pointer (e
);
2907 demand_empty_rest_of_line ();
2911 if (strcmp (string
, "default") == 0)
2913 if (strcmp (default_arch
, "iamcu") == 0)
2914 string
= default_arch
;
2917 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2919 cpu_arch_name
= NULL
;
2920 free (cpu_sub_arch_name
);
2921 cpu_sub_arch_name
= NULL
;
2922 cpu_arch_flags
= cpu_unknown_flags
;
2923 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2924 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2925 if (!cpu_arch_tune_set
)
2926 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2928 vector_size
= VSZ_DEFAULT
;
2930 j
= ARRAY_SIZE (cpu_arch
) + 1;
2934 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2936 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2937 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2941 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2943 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2945 as_bad (_("64bit mode not supported on `%s'."),
2947 (void) restore_line_pointer (e
);
2948 ignore_rest_of_line ();
2952 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2954 as_bad (_("32bit mode not supported on `%s'."),
2956 (void) restore_line_pointer (e
);
2957 ignore_rest_of_line ();
2961 cpu_arch_name
= cpu_arch
[j
].name
;
2962 free (cpu_sub_arch_name
);
2963 cpu_sub_arch_name
= NULL
;
2964 cpu_arch_flags
= cpu_arch
[j
].enable
;
2965 cpu_arch_isa
= cpu_arch
[j
].type
;
2966 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2967 if (!cpu_arch_tune_set
)
2968 cpu_arch_tune
= cpu_arch_isa
;
2970 vector_size
= VSZ_DEFAULT
;
2972 pre_386_16bit_warned
= false;
2976 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2981 (void) restore_line_pointer (e
);
2983 switch (cpu_arch
[j
].vsz
)
2989 #ifdef SVR4_COMMENT_CHARS
2990 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2992 if (*input_line_pointer
== '/')
2995 ++input_line_pointer
;
2996 switch (get_absolute_expression ())
2998 case 512: vector_size
= VSZ512
; break;
2999 case 256: vector_size
= VSZ256
; break;
3000 case 128: vector_size
= VSZ128
; break;
3002 as_bad (_("Unrecognized vector size specifier"));
3003 ignore_rest_of_line ();
3010 vector_size
= VSZ_DEFAULT
;
3014 demand_empty_rest_of_line ();
3019 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3021 /* Disable an ISA extension. */
3022 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3023 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3024 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3028 if (cpu_arch
[j
].vsz
== vsz_set
)
3029 vector_size
= VSZ_DEFAULT
;
3031 (void) restore_line_pointer (e
);
3032 demand_empty_rest_of_line ();
3037 if (j
== ARRAY_SIZE (cpu_arch
))
3038 as_bad (_("no such architecture: `%s'"), string
);
3040 *input_line_pointer
= e
;
3042 no_cond_jump_promotion
= 0;
3043 if (*input_line_pointer
== ','
3044 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3046 ++input_line_pointer
;
3047 e
= get_symbol_name (&s
);
3050 if (strcmp (string
, "nojumps") == 0)
3051 no_cond_jump_promotion
= 1;
3052 else if (strcmp (string
, "jumps") == 0)
3055 as_bad (_("no such architecture modifier: `%s'"), string
);
3057 (void) restore_line_pointer (e
);
3060 demand_empty_rest_of_line ();
3063 enum bfd_architecture
3066 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3068 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3069 || flag_code
== CODE_64BIT
)
3070 as_fatal (_("Intel MCU is 32bit ELF only"));
3071 return bfd_arch_iamcu
;
3074 return bfd_arch_i386
;
3080 if (startswith (default_arch
, "x86_64"))
3082 if (default_arch
[6] == '\0')
3083 return bfd_mach_x86_64
;
3085 return bfd_mach_x64_32
;
3087 else if (!strcmp (default_arch
, "i386")
3088 || !strcmp (default_arch
, "iamcu"))
3090 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3093 as_fatal (_("Intel MCU is 32bit ELF only"));
3094 return bfd_mach_i386_iamcu
;
3097 return bfd_mach_i386_i386
;
3100 as_fatal (_("unknown architecture"));
3103 #include "opcodes/i386-tbl.h"
3108 /* Support pseudo prefixes like {disp32}. */
3109 lex_type
['{'] = LEX_BEGIN_NAME
;
3111 /* Initialize op_hash hash table. */
3112 op_hash
= str_htab_create ();
3115 const insn_template
*const *sets
= i386_op_sets
;
3116 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3118 /* Type checks to compensate for the conversion through void * which
3119 occurs during hash table insertion / lookup. */
3120 (void) sizeof (sets
== ¤t_templates
->start
);
3121 (void) sizeof (end
== ¤t_templates
->end
);
3122 for (; sets
< end
; ++sets
)
3123 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3124 as_fatal (_("duplicate %s"), insn_name (*sets
));
3127 /* Initialize reg_hash hash table. */
3128 reg_hash
= str_htab_create ();
3130 const reg_entry
*regtab
;
3131 unsigned int regtab_size
= i386_regtab_size
;
3133 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3135 switch (regtab
->reg_type
.bitfield
.class)
3138 if (regtab
->reg_type
.bitfield
.dword
)
3140 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3143 else if (regtab
->reg_type
.bitfield
.tbyte
)
3145 /* There's no point inserting st(<N>) in the hash table, as
3146 parentheses aren't included in register_chars[] anyway. */
3147 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3154 switch (regtab
->reg_num
)
3156 case 0: reg_es
= regtab
; break;
3157 case 2: reg_ss
= regtab
; break;
3158 case 3: reg_ds
= regtab
; break;
3163 if (!regtab
->reg_num
)
3168 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3169 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3173 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3178 for (c
= 0; c
< 256; c
++)
3180 if (ISDIGIT (c
) || ISLOWER (c
))
3182 mnemonic_chars
[c
] = c
;
3183 register_chars
[c
] = c
;
3184 operand_chars
[c
] = c
;
3186 else if (ISUPPER (c
))
3188 mnemonic_chars
[c
] = TOLOWER (c
);
3189 register_chars
[c
] = mnemonic_chars
[c
];
3190 operand_chars
[c
] = c
;
3192 #ifdef SVR4_COMMENT_CHARS
3193 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3194 operand_chars
[c
] = c
;
3198 operand_chars
[c
] = c
;
3201 mnemonic_chars
['_'] = '_';
3202 mnemonic_chars
['-'] = '-';
3203 mnemonic_chars
['.'] = '.';
3205 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3206 operand_chars
[(unsigned char) *p
] = *p
;
3207 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3208 operand_chars
[(unsigned char) *p
] = *p
;
3211 if (flag_code
== CODE_64BIT
)
3213 #if defined (OBJ_COFF) && defined (TE_PE)
3214 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3217 x86_dwarf2_return_column
= 16;
3219 x86_cie_data_alignment
= -8;
3220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3221 x86_sframe_cfa_sp_reg
= 7;
3222 x86_sframe_cfa_fp_reg
= 6;
3227 x86_dwarf2_return_column
= 8;
3228 x86_cie_data_alignment
= -4;
3231 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3232 can be turned into BRANCH_PREFIX frag. */
3233 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3238 i386_print_statistics (FILE *file
)
3240 htab_print_statistics (file
, "i386 opcode", op_hash
);
3241 htab_print_statistics (file
, "i386 register", reg_hash
);
3247 htab_delete (op_hash
);
3248 htab_delete (reg_hash
);
3253 /* Debugging routines for md_assemble. */
3254 static void pte (insn_template
*);
3255 static void pt (i386_operand_type
);
3256 static void pe (expressionS
*);
3257 static void ps (symbolS
*);
3260 pi (const char *line
, i386_insn
*x
)
3264 fprintf (stdout
, "%s: template ", line
);
3266 fprintf (stdout
, " address: base %s index %s scale %x\n",
3267 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3268 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3269 x
->log2_scale_factor
);
3270 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3271 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3272 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3273 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3274 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3275 (x
->rex
& REX_W
) != 0,
3276 (x
->rex
& REX_R
) != 0,
3277 (x
->rex
& REX_X
) != 0,
3278 (x
->rex
& REX_B
) != 0);
3279 for (j
= 0; j
< x
->operands
; j
++)
3281 fprintf (stdout
, " #%d: ", j
+ 1);
3283 fprintf (stdout
, "\n");
3284 if (x
->types
[j
].bitfield
.class == Reg
3285 || x
->types
[j
].bitfield
.class == RegMMX
3286 || x
->types
[j
].bitfield
.class == RegSIMD
3287 || x
->types
[j
].bitfield
.class == RegMask
3288 || x
->types
[j
].bitfield
.class == SReg
3289 || x
->types
[j
].bitfield
.class == RegCR
3290 || x
->types
[j
].bitfield
.class == RegDR
3291 || x
->types
[j
].bitfield
.class == RegTR
3292 || x
->types
[j
].bitfield
.class == RegBND
)
3293 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3294 if (operand_type_check (x
->types
[j
], imm
))
3296 if (operand_type_check (x
->types
[j
], disp
))
3297 pe (x
->op
[j
].disps
);
3302 pte (insn_template
*t
)
3304 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3305 static const char *const opc_spc
[] = {
3306 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3307 "XOP08", "XOP09", "XOP0A",
3311 fprintf (stdout
, " %d operands ", t
->operands
);
3312 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3313 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3314 if (opc_spc
[t
->opcode_space
])
3315 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3316 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3317 if (t
->extension_opcode
!= None
)
3318 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3319 if (t
->opcode_modifier
.d
)
3320 fprintf (stdout
, "D");
3321 if (t
->opcode_modifier
.w
)
3322 fprintf (stdout
, "W");
3323 fprintf (stdout
, "\n");
3324 for (j
= 0; j
< t
->operands
; j
++)
3326 fprintf (stdout
, " #%d type ", j
+ 1);
3327 pt (t
->operand_types
[j
]);
3328 fprintf (stdout
, "\n");
3335 fprintf (stdout
, " operation %d\n", e
->X_op
);
3336 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3337 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3338 if (e
->X_add_symbol
)
3340 fprintf (stdout
, " add_symbol ");
3341 ps (e
->X_add_symbol
);
3342 fprintf (stdout
, "\n");
3346 fprintf (stdout
, " op_symbol ");
3347 ps (e
->X_op_symbol
);
3348 fprintf (stdout
, "\n");
3355 fprintf (stdout
, "%s type %s%s",
3357 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3358 segment_name (S_GET_SEGMENT (s
)));
3361 static struct type_name
3363 i386_operand_type mask
;
3366 const type_names
[] =
3368 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3369 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3370 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3371 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3372 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3373 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3374 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3375 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3376 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3377 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3378 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3379 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3380 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3381 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3382 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3383 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3384 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3385 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3386 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3387 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3388 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3389 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3390 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3391 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3392 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3393 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3394 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3395 { { .bitfield
= { .class = SReg
} }, "SReg" },
3396 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3397 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3398 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3399 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3400 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3401 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3405 pt (i386_operand_type t
)
3408 i386_operand_type a
;
3410 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3412 a
= operand_type_and (t
, type_names
[j
].mask
);
3413 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3414 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3419 #endif /* DEBUG386 */
3421 static bfd_reloc_code_real_type
3422 reloc (unsigned int size
,
3425 bfd_reloc_code_real_type other
)
3427 if (other
!= NO_RELOC
)
3429 reloc_howto_type
*rel
;
3434 case BFD_RELOC_X86_64_GOT32
:
3435 return BFD_RELOC_X86_64_GOT64
;
3437 case BFD_RELOC_X86_64_GOTPLT64
:
3438 return BFD_RELOC_X86_64_GOTPLT64
;
3440 case BFD_RELOC_X86_64_PLTOFF64
:
3441 return BFD_RELOC_X86_64_PLTOFF64
;
3443 case BFD_RELOC_X86_64_GOTPC32
:
3444 other
= BFD_RELOC_X86_64_GOTPC64
;
3446 case BFD_RELOC_X86_64_GOTPCREL
:
3447 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3449 case BFD_RELOC_X86_64_TPOFF32
:
3450 other
= BFD_RELOC_X86_64_TPOFF64
;
3452 case BFD_RELOC_X86_64_DTPOFF32
:
3453 other
= BFD_RELOC_X86_64_DTPOFF64
;
3459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3460 if (other
== BFD_RELOC_SIZE32
)
3463 other
= BFD_RELOC_SIZE64
;
3466 as_bad (_("there are no pc-relative size relocations"));
3472 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3473 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3476 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3478 as_bad (_("unknown relocation (%u)"), other
);
3479 else if (size
!= bfd_get_reloc_size (rel
))
3480 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3481 bfd_get_reloc_size (rel
),
3483 else if (pcrel
&& !rel
->pc_relative
)
3484 as_bad (_("non-pc-relative relocation for pc-relative field"));
3485 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3487 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3489 as_bad (_("relocated field and relocation type differ in signedness"));
3498 as_bad (_("there are no unsigned pc-relative relocations"));
3501 case 1: return BFD_RELOC_8_PCREL
;
3502 case 2: return BFD_RELOC_16_PCREL
;
3503 case 4: return BFD_RELOC_32_PCREL
;
3504 case 8: return BFD_RELOC_64_PCREL
;
3506 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3513 case 4: return BFD_RELOC_X86_64_32S
;
3518 case 1: return BFD_RELOC_8
;
3519 case 2: return BFD_RELOC_16
;
3520 case 4: return BFD_RELOC_32
;
3521 case 8: return BFD_RELOC_64
;
3523 as_bad (_("cannot do %s %u byte relocation"),
3524 sign
> 0 ? "signed" : "unsigned", size
);
3530 /* Here we decide which fixups can be adjusted to make them relative to
3531 the beginning of the section instead of the symbol. Basically we need
3532 to make sure that the dynamic relocations are done correctly, so in
3533 some cases we force the original symbol to be used. */
3536 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3542 /* Don't adjust pc-relative references to merge sections in 64-bit
3544 if (use_rela_relocations
3545 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3549 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3550 and changed later by validate_fix. */
3551 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3552 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3555 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3556 for size relocations. */
3557 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3558 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3559 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3560 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3561 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3562 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3563 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3564 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3565 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3566 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3572 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3573 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3574 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3575 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3576 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3586 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3587 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3594 want_disp32 (const insn_template
*t
)
3596 return flag_code
!= CODE_64BIT
3597 || i
.prefix
[ADDR_PREFIX
]
3598 || (t
->mnem_off
== MN_lea
3599 && (!i
.types
[1].bitfield
.qword
3600 || t
->opcode_modifier
.size
== SIZE32
));
3604 intel_float_operand (const char *mnemonic
)
3606 /* Note that the value returned is meaningful only for opcodes with (memory)
3607 operands, hence the code here is free to improperly handle opcodes that
3608 have no operands (for better performance and smaller code). */
3610 if (mnemonic
[0] != 'f')
3611 return 0; /* non-math */
3613 switch (mnemonic
[1])
3615 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3616 the fs segment override prefix not currently handled because no
3617 call path can make opcodes without operands get here */
3619 return 2 /* integer op */;
3621 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3622 return 3; /* fldcw/fldenv */
3625 if (mnemonic
[2] != 'o' /* fnop */)
3626 return 3; /* non-waiting control op */
3629 if (mnemonic
[2] == 's')
3630 return 3; /* frstor/frstpm */
3633 if (mnemonic
[2] == 'a')
3634 return 3; /* fsave */
3635 if (mnemonic
[2] == 't')
3637 switch (mnemonic
[3])
3639 case 'c': /* fstcw */
3640 case 'd': /* fstdw */
3641 case 'e': /* fstenv */
3642 case 's': /* fsts[gw] */
3648 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3649 return 0; /* fxsave/fxrstor are not really math ops */
3657 install_template (const insn_template
*t
)
3663 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3664 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3666 if ((maybe_cpu (t
, CpuAVX
) || maybe_cpu (t
, CpuAVX2
)
3667 || maybe_cpu (t
, CpuFMA
))
3668 && (maybe_cpu (t
, CpuAVX512F
) || maybe_cpu (t
, CpuAVX512VL
)))
3670 if (need_evex_encoding ())
3672 i
.tm
.opcode_modifier
.vex
= 0;
3673 i
.tm
.cpu
.bitfield
.cpuavx512f
= i
.tm
.cpu_any
.bitfield
.cpuavx512f
;
3674 i
.tm
.cpu
.bitfield
.cpuavx512vl
= i
.tm
.cpu_any
.bitfield
.cpuavx512vl
;
3678 i
.tm
.opcode_modifier
.evex
= 0;
3679 if (i
.tm
.cpu_any
.bitfield
.cpuavx
)
3680 i
.tm
.cpu
.bitfield
.cpuavx
= 1;
3681 else if (!i
.tm
.cpu
.bitfield
.isa
)
3682 i
.tm
.cpu
.bitfield
.isa
= i
.tm
.cpu_any
.bitfield
.isa
;
3684 gas_assert (i
.tm
.cpu
.bitfield
.isa
== i
.tm
.cpu_any
.bitfield
.isa
);
3689 /* Note that for pseudo prefixes this produces a length of 1. But for them
3690 the length isn't interesting at all. */
3691 for (l
= 1; l
< 4; ++l
)
3692 if (!(t
->base_opcode
>> (8 * l
)))
3695 i
.opcode_length
= l
;
3698 /* Build the VEX prefix. */
3701 build_vex_prefix (const insn_template
*t
)
3703 unsigned int register_specifier
;
3704 unsigned int vector_length
;
3707 /* Check register specifier. */
3708 if (i
.vex
.register_specifier
)
3710 register_specifier
=
3711 ~register_number (i
.vex
.register_specifier
) & 0xf;
3712 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3715 register_specifier
= 0xf;
3717 /* Use 2-byte VEX prefix by swapping destination and source operand
3718 if there are more than 1 register operand. */
3719 if (i
.reg_operands
> 1
3720 && i
.vec_encoding
!= vex_encoding_vex3
3721 && i
.dir_encoding
== dir_encoding_default
3722 && i
.operands
== i
.reg_operands
3723 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3724 && i
.tm
.opcode_space
== SPACE_0F
3725 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3730 swap_2_operands (0, i
.operands
- 1);
3732 gas_assert (i
.rm
.mode
== 3);
3736 i
.rm
.regmem
= i
.rm
.reg
;
3739 if (i
.tm
.opcode_modifier
.d
)
3740 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3741 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3742 else /* Use the next insn. */
3743 install_template (&t
[1]);
3746 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3747 are no memory operands and at least 3 register ones. */
3748 if (i
.reg_operands
>= 3
3749 && i
.vec_encoding
!= vex_encoding_vex3
3750 && i
.reg_operands
== i
.operands
- i
.imm_operands
3751 && i
.tm
.opcode_modifier
.vex
3752 && i
.tm
.opcode_modifier
.commutative
3753 && (i
.tm
.opcode_modifier
.sse2avx
3754 || (optimize
> 1 && !i
.no_optimize
))
3756 && i
.vex
.register_specifier
3757 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3759 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3761 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3762 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3763 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3764 &i
.types
[i
.operands
- 3]));
3765 gas_assert (i
.rm
.mode
== 3);
3767 swap_2_operands (xchg
, xchg
+ 1);
3770 xchg
= i
.rm
.regmem
| 8;
3771 i
.rm
.regmem
= ~register_specifier
& 0xf;
3772 gas_assert (!(i
.rm
.regmem
& 8));
3773 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3774 register_specifier
= ~xchg
& 0xf;
3777 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3778 vector_length
= avxscalar
;
3779 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3781 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3787 /* Determine vector length from the last multi-length vector
3790 for (op
= t
->operands
; op
--;)
3791 if (t
->operand_types
[op
].bitfield
.xmmword
3792 && t
->operand_types
[op
].bitfield
.ymmword
3793 && i
.types
[op
].bitfield
.ymmword
)
3800 /* Check the REX.W bit and VEXW. */
3801 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3802 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3803 else if (i
.tm
.opcode_modifier
.vexw
)
3804 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3806 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3808 /* Use 2-byte VEX prefix if possible. */
3810 && i
.vec_encoding
!= vex_encoding_vex3
3811 && i
.tm
.opcode_space
== SPACE_0F
3812 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3814 /* 2-byte VEX prefix. */
3818 i
.vex
.bytes
[0] = 0xc5;
3820 /* Check the REX.R bit. */
3821 r
= (i
.rex
& REX_R
) ? 0 : 1;
3822 i
.vex
.bytes
[1] = (r
<< 7
3823 | register_specifier
<< 3
3824 | vector_length
<< 2
3825 | i
.tm
.opcode_modifier
.opcodeprefix
);
3829 /* 3-byte VEX prefix. */
3832 switch (i
.tm
.opcode_space
)
3838 i
.vex
.bytes
[0] = 0xc4;
3843 i
.vex
.bytes
[0] = 0x8f;
3849 /* The high 3 bits of the second VEX byte are 1's compliment
3850 of RXB bits from REX. */
3851 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3852 | (!dot_insn () ? i
.tm
.opcode_space
3853 : i
.insn_opcode_space
);
3855 i
.vex
.bytes
[2] = (w
<< 7
3856 | register_specifier
<< 3
3857 | vector_length
<< 2
3858 | i
.tm
.opcode_modifier
.opcodeprefix
);
3863 is_any_vex_encoding (const insn_template
*t
)
3865 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.evex
;
3869 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3871 unsigned int op
, bytes
;
3872 const i386_operand_type
*types
;
3874 if (i
.broadcast
.type
)
3875 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3877 gas_assert (intel_syntax
);
3879 for (op
= 0; op
< t
->operands
; ++op
)
3880 if (t
->operand_types
[op
].bitfield
.baseindex
)
3883 gas_assert (op
< t
->operands
);
3885 if (t
->opcode_modifier
.evex
!= EVEXDYN
)
3886 switch (i
.broadcast
.bytes
)
3889 if (t
->operand_types
[op
].bitfield
.word
)
3893 if (t
->operand_types
[op
].bitfield
.dword
)
3897 if (t
->operand_types
[op
].bitfield
.qword
)
3901 if (t
->operand_types
[op
].bitfield
.xmmword
)
3903 if (t
->operand_types
[op
].bitfield
.ymmword
)
3905 if (t
->operand_types
[op
].bitfield
.zmmword
)
3912 gas_assert (op
+ 1 < t
->operands
);
3914 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3915 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3916 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3918 types
= &i
.types
[op
+ 1];
3921 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3922 types
= &t
->operand_types
[op
];
3924 if (types
->bitfield
.zmmword
)
3926 else if (types
->bitfield
.ymmword
)
3932 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3933 insn_name (t
), bytes
* 8);
3938 /* Build the EVEX prefix. */
3941 build_evex_prefix (void)
3943 unsigned int register_specifier
, w
;
3944 rex_byte vrex_used
= 0;
3946 /* Check register specifier. */
3947 if (i
.vex
.register_specifier
)
3949 gas_assert ((i
.vrex
& REX_X
) == 0);
3951 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3952 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3953 register_specifier
+= 8;
3954 /* The upper 16 registers are encoded in the fourth byte of the
3956 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3957 i
.vex
.bytes
[3] = 0x8;
3958 register_specifier
= ~register_specifier
& 0xf;
3962 register_specifier
= 0xf;
3964 /* Encode upper 16 vector index register in the fourth byte of
3966 if (!(i
.vrex
& REX_X
))
3967 i
.vex
.bytes
[3] = 0x8;
3972 /* 4 byte EVEX prefix. */
3974 i
.vex
.bytes
[0] = 0x62;
3976 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3978 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3979 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3980 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3981 | (!dot_insn () ? i
.tm
.opcode_space
3982 : i
.insn_opcode_space
);
3984 /* The fifth bit of the second EVEX byte is 1's compliment of the
3985 REX_R bit in VREX. */
3986 if (!(i
.vrex
& REX_R
))
3987 i
.vex
.bytes
[1] |= 0x10;
3991 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3993 /* When all operands are registers, the REX_X bit in REX is not
3994 used. We reuse it to encode the upper 16 registers, which is
3995 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3996 as 1's compliment. */
3997 if ((i
.vrex
& REX_B
))
4000 i
.vex
.bytes
[1] &= ~0x40;
4004 /* EVEX instructions shouldn't need the REX prefix. */
4005 i
.vrex
&= ~vrex_used
;
4006 gas_assert (i
.vrex
== 0);
4008 /* Check the REX.W bit and VEXW. */
4009 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4010 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4011 else if (i
.tm
.opcode_modifier
.vexw
)
4012 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4014 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4016 /* The third byte of the EVEX prefix. */
4017 i
.vex
.bytes
[2] = ((w
<< 7)
4018 | (register_specifier
<< 3)
4019 | 4 /* Encode the U bit. */
4020 | i
.tm
.opcode_modifier
.opcodeprefix
);
4022 /* The fourth byte of the EVEX prefix. */
4023 /* The zeroing-masking bit. */
4024 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4025 i
.vex
.bytes
[3] |= 0x80;
4027 /* Don't always set the broadcast bit if there is no RC. */
4028 if (i
.rounding
.type
== rc_none
)
4030 /* Encode the vector length. */
4031 unsigned int vec_length
;
4033 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4037 /* Determine vector length from the last multi-length vector
4039 for (op
= i
.operands
; op
--;)
4040 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4041 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4042 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4044 if (i
.types
[op
].bitfield
.zmmword
)
4046 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4049 else if (i
.types
[op
].bitfield
.ymmword
)
4051 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4054 else if (i
.types
[op
].bitfield
.xmmword
)
4056 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4059 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4060 && op
== i
.broadcast
.operand
)
4062 switch (get_broadcast_bytes (&i
.tm
, true))
4065 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4068 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4071 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4080 if (op
>= MAX_OPERANDS
)
4084 switch (i
.tm
.opcode_modifier
.evex
)
4086 case EVEXLIG
: /* LL' is ignored */
4087 vec_length
= evexlig
<< 5;
4090 vec_length
= 0 << 5;
4093 vec_length
= 1 << 5;
4096 vec_length
= 2 << 5;
4101 vec_length
= 3 << 5;
4109 i
.vex
.bytes
[3] |= vec_length
;
4110 /* Encode the broadcast bit. */
4111 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4112 i
.vex
.bytes
[3] |= 0x10;
4114 else if (i
.rounding
.type
!= saeonly
)
4115 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4117 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4120 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4124 process_immext (void)
4128 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4129 which is coded in the same place as an 8-bit immediate field
4130 would be. Here we fake an 8-bit immediate operand from the
4131 opcode suffix stored in tm.extension_opcode.
4133 AVX instructions also use this encoding, for some of
4134 3 argument instructions. */
4136 gas_assert (i
.imm_operands
<= 1
4138 || (is_any_vex_encoding (&i
.tm
)
4139 && i
.operands
<= 4)));
4141 exp
= &im_expressions
[i
.imm_operands
++];
4142 i
.op
[i
.operands
].imms
= exp
;
4143 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4145 exp
->X_op
= O_constant
;
4146 exp
->X_add_number
= i
.tm
.extension_opcode
;
4147 i
.tm
.extension_opcode
= None
;
4154 switch (i
.tm
.opcode_modifier
.prefixok
)
4162 as_bad (_("invalid instruction `%s' after `%s'"),
4163 insn_name (&i
.tm
), i
.hle_prefix
);
4166 if (i
.prefix
[LOCK_PREFIX
])
4168 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4172 case PrefixHLERelease
:
4173 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4175 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4179 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4181 as_bad (_("memory destination needed for instruction `%s'"
4182 " after `xrelease'"), insn_name (&i
.tm
));
4189 /* Encode aligned vector move as unaligned vector move. */
4192 encode_with_unaligned_vector_move (void)
4194 switch (i
.tm
.base_opcode
)
4196 case 0x28: /* Load instructions. */
4197 case 0x29: /* Store instructions. */
4198 /* movaps/movapd/vmovaps/vmovapd. */
4199 if (i
.tm
.opcode_space
== SPACE_0F
4200 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4201 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4203 case 0x6f: /* Load instructions. */
4204 case 0x7f: /* Store instructions. */
4205 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4206 if (i
.tm
.opcode_space
== SPACE_0F
4207 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4208 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4215 /* Try the shortest encoding by shortening operand size. */
4218 optimize_encoding (void)
4222 if (i
.tm
.mnem_off
== MN_lea
)
4225 lea symbol, %rN -> mov $symbol, %rN
4226 lea (%rM), %rN -> mov %rM, %rN
4227 lea (,%rM,1), %rN -> mov %rM, %rN
4229 and in 32-bit mode for 16-bit addressing
4231 lea (%rM), %rN -> movzx %rM, %rN
4233 and in 64-bit mode zap 32-bit addressing in favor of using a
4234 32-bit (or less) destination.
4236 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4238 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4239 i
.tm
.opcode_modifier
.size
= SIZE32
;
4240 i
.prefix
[ADDR_PREFIX
] = 0;
4243 if (!i
.index_reg
&& !i
.base_reg
)
4246 lea symbol, %rN -> mov $symbol, %rN
4248 if (flag_code
== CODE_64BIT
)
4250 /* Don't transform a relocation to a 16-bit one. */
4252 && i
.op
[0].disps
->X_op
!= O_constant
4253 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4256 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4257 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4259 i
.tm
.base_opcode
= 0xb8;
4260 i
.tm
.opcode_modifier
.modrm
= 0;
4261 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4262 i
.types
[0].bitfield
.imm32
= 1;
4265 i
.tm
.opcode_modifier
.size
= SIZE16
;
4266 i
.types
[0].bitfield
.imm16
= 1;
4271 /* Subject to further optimization below. */
4272 i
.tm
.base_opcode
= 0xc7;
4273 i
.tm
.extension_opcode
= 0;
4274 i
.types
[0].bitfield
.imm32s
= 1;
4275 i
.types
[0].bitfield
.baseindex
= 0;
4278 /* Outside of 64-bit mode address and operand sizes have to match if
4279 a relocation is involved, as otherwise we wouldn't (currently) or
4280 even couldn't express the relocation correctly. */
4281 else if (i
.op
[0].disps
4282 && i
.op
[0].disps
->X_op
!= O_constant
4283 && ((!i
.prefix
[ADDR_PREFIX
])
4284 != (flag_code
== CODE_32BIT
4285 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4286 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4288 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4289 destination is going to grow encoding size. */
4290 else if (flag_code
== CODE_16BIT
4291 && (optimize
<= 1 || optimize_for_space
)
4292 && !i
.prefix
[ADDR_PREFIX
]
4293 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4297 i
.tm
.base_opcode
= 0xb8;
4298 i
.tm
.opcode_modifier
.modrm
= 0;
4299 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4300 i
.types
[0].bitfield
.imm32
= 1;
4302 i
.types
[0].bitfield
.imm16
= 1;
4305 && i
.op
[0].disps
->X_op
== O_constant
4306 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4307 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4309 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4310 i
.op
[0].disps
->X_add_number
&= 0xffff;
4313 i
.tm
.operand_types
[0] = i
.types
[0];
4317 i
.op
[0].imms
= &im_expressions
[0];
4318 i
.op
[0].imms
->X_op
= O_absent
;
4321 else if (i
.op
[0].disps
4322 && (i
.op
[0].disps
->X_op
!= O_constant
4323 || i
.op
[0].disps
->X_add_number
))
4328 lea (%rM), %rN -> mov %rM, %rN
4329 lea (,%rM,1), %rN -> mov %rM, %rN
4330 lea (%rM), %rN -> movzx %rM, %rN
4332 const reg_entry
*addr_reg
;
4334 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4335 addr_reg
= i
.base_reg
;
4336 else if (!i
.base_reg
4337 && i
.index_reg
->reg_num
!= RegIZ
4338 && !i
.log2_scale_factor
)
4339 addr_reg
= i
.index_reg
;
4343 if (addr_reg
->reg_type
.bitfield
.word
4344 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4346 if (flag_code
!= CODE_32BIT
)
4348 i
.tm
.opcode_space
= SPACE_0F
;
4349 i
.tm
.base_opcode
= 0xb7;
4352 i
.tm
.base_opcode
= 0x8b;
4354 if (addr_reg
->reg_type
.bitfield
.dword
4355 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4356 i
.tm
.opcode_modifier
.size
= SIZE32
;
4358 i
.op
[0].regs
= addr_reg
;
4363 i
.disp_operands
= 0;
4364 i
.prefix
[ADDR_PREFIX
] = 0;
4365 i
.prefix
[SEG_PREFIX
] = 0;
4369 if (optimize_for_space
4370 && i
.tm
.mnem_off
== MN_test
4371 && i
.reg_operands
== 1
4372 && i
.imm_operands
== 1
4373 && !i
.types
[1].bitfield
.byte
4374 && i
.op
[0].imms
->X_op
== O_constant
4375 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4378 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4380 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4381 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4383 i
.types
[1].bitfield
.byte
= 1;
4384 /* Ignore the suffix. */
4386 /* Convert to byte registers. */
4387 if (i
.types
[1].bitfield
.word
)
4389 else if (i
.types
[1].bitfield
.dword
)
4393 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4398 else if (flag_code
== CODE_64BIT
4399 && i
.tm
.opcode_space
== SPACE_BASE
4400 && ((i
.types
[1].bitfield
.qword
4401 && i
.reg_operands
== 1
4402 && i
.imm_operands
== 1
4403 && i
.op
[0].imms
->X_op
== O_constant
4404 && ((i
.tm
.base_opcode
== 0xb8
4405 && i
.tm
.extension_opcode
== None
4406 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4407 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4408 && (i
.tm
.base_opcode
== 0x24
4409 || (i
.tm
.base_opcode
== 0x80
4410 && i
.tm
.extension_opcode
== 0x4)
4411 || i
.tm
.mnem_off
== MN_test
4412 || ((i
.tm
.base_opcode
| 1) == 0xc7
4413 && i
.tm
.extension_opcode
== 0x0)))
4414 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4415 && i
.tm
.base_opcode
== 0x83
4416 && i
.tm
.extension_opcode
== 0x4)))
4417 || (i
.types
[0].bitfield
.qword
4418 && ((i
.reg_operands
== 2
4419 && i
.op
[0].regs
== i
.op
[1].regs
4420 && (i
.tm
.mnem_off
== MN_xor
4421 || i
.tm
.mnem_off
== MN_sub
))
4422 || i
.tm
.mnem_off
== MN_clr
))))
4425 andq $imm31, %r64 -> andl $imm31, %r32
4426 andq $imm7, %r64 -> andl $imm7, %r32
4427 testq $imm31, %r64 -> testl $imm31, %r32
4428 xorq %r64, %r64 -> xorl %r32, %r32
4429 subq %r64, %r64 -> subl %r32, %r32
4430 movq $imm31, %r64 -> movl $imm31, %r32
4431 movq $imm32, %r64 -> movl $imm32, %r32
4433 i
.tm
.opcode_modifier
.size
= SIZE32
;
4436 i
.types
[0].bitfield
.imm32
= 1;
4437 i
.types
[0].bitfield
.imm32s
= 0;
4438 i
.types
[0].bitfield
.imm64
= 0;
4442 i
.types
[0].bitfield
.dword
= 1;
4443 i
.types
[0].bitfield
.qword
= 0;
4445 i
.types
[1].bitfield
.dword
= 1;
4446 i
.types
[1].bitfield
.qword
= 0;
4447 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4450 movq $imm31, %r64 -> movl $imm31, %r32
4451 movq $imm32, %r64 -> movl $imm32, %r32
4453 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4454 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4455 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4456 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4459 movq $imm31, %r64 -> movl $imm31, %r32
4461 i
.tm
.base_opcode
= 0xb8;
4462 i
.tm
.extension_opcode
= None
;
4463 i
.tm
.opcode_modifier
.w
= 0;
4464 i
.tm
.opcode_modifier
.modrm
= 0;
4468 else if (optimize
> 1
4469 && !optimize_for_space
4470 && i
.reg_operands
== 2
4471 && i
.op
[0].regs
== i
.op
[1].regs
4472 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4473 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4476 andb %rN, %rN -> testb %rN, %rN
4477 andw %rN, %rN -> testw %rN, %rN
4478 andq %rN, %rN -> testq %rN, %rN
4479 orb %rN, %rN -> testb %rN, %rN
4480 orw %rN, %rN -> testw %rN, %rN
4481 orq %rN, %rN -> testq %rN, %rN
4483 and outside of 64-bit mode
4485 andl %rN, %rN -> testl %rN, %rN
4486 orl %rN, %rN -> testl %rN, %rN
4488 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4490 else if (i
.tm
.base_opcode
== 0xba
4491 && i
.tm
.opcode_space
== SPACE_0F
4492 && i
.reg_operands
== 1
4493 && i
.op
[0].imms
->X_op
== O_constant
4494 && i
.op
[0].imms
->X_add_number
>= 0)
4497 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4498 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4499 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4501 With <BT> one of bts, btr, and bts also:
4502 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4503 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4508 if (i
.tm
.extension_opcode
!= 4)
4510 if (i
.types
[1].bitfield
.qword
4511 && i
.op
[0].imms
->X_add_number
< 32
4512 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4513 i
.tm
.opcode_modifier
.size
= SIZE32
;
4516 if (i
.types
[1].bitfield
.word
4517 && i
.op
[0].imms
->X_add_number
< 16)
4518 i
.tm
.opcode_modifier
.size
= SIZE32
;
4521 if (i
.op
[0].imms
->X_add_number
< 16)
4522 i
.tm
.opcode_modifier
.size
= SIZE16
;
4526 else if (i
.reg_operands
== 3
4527 && i
.op
[0].regs
== i
.op
[1].regs
4528 && !i
.types
[2].bitfield
.xmmword
4529 && (i
.tm
.opcode_modifier
.vex
4530 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4531 && i
.tm
.opcode_modifier
.evex
4532 && (i
.vec_encoding
!= vex_encoding_evex
4533 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4534 || is_cpu (&i
.tm
, CpuAVX512VL
)
4535 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4536 && i
.types
[2].bitfield
.ymmword
))))
4537 && i
.tm
.opcode_space
== SPACE_0F
4538 && ((i
.tm
.base_opcode
| 2) == 0x57
4539 || i
.tm
.base_opcode
== 0xdf
4540 || i
.tm
.base_opcode
== 0xef
4541 || (i
.tm
.base_opcode
| 3) == 0xfb
4542 || i
.tm
.base_opcode
== 0x42
4543 || i
.tm
.base_opcode
== 0x47))
4546 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4548 EVEX VOP %zmmM, %zmmM, %zmmN
4549 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4550 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4551 EVEX VOP %ymmM, %ymmM, %ymmN
4552 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4553 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4554 VEX VOP %ymmM, %ymmM, %ymmN
4555 -> VEX VOP %xmmM, %xmmM, %xmmN
4556 VOP, one of vpandn and vpxor:
4557 VEX VOP %ymmM, %ymmM, %ymmN
4558 -> VEX VOP %xmmM, %xmmM, %xmmN
4559 VOP, one of vpandnd and vpandnq:
4560 EVEX VOP %zmmM, %zmmM, %zmmN
4561 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4562 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4563 EVEX VOP %ymmM, %ymmM, %ymmN
4564 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4565 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4566 VOP, one of vpxord and vpxorq:
4567 EVEX VOP %zmmM, %zmmM, %zmmN
4568 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4569 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4570 EVEX VOP %ymmM, %ymmM, %ymmN
4571 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4572 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4573 VOP, one of kxord and kxorq:
4574 VEX VOP %kM, %kM, %kN
4575 -> VEX kxorw %kM, %kM, %kN
4576 VOP, one of kandnd and kandnq:
4577 VEX VOP %kM, %kM, %kN
4578 -> VEX kandnw %kM, %kM, %kN
4580 if (i
.tm
.opcode_modifier
.evex
)
4582 if (i
.vec_encoding
!= vex_encoding_evex
)
4584 i
.tm
.opcode_modifier
.vex
= VEX128
;
4585 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4586 i
.tm
.opcode_modifier
.evex
= 0;
4587 i
.vec_encoding
= vex_encoding_vex
;
4590 else if (optimize
> 1)
4591 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4595 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4597 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4598 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4601 i
.tm
.opcode_modifier
.vex
= VEX128
;
4603 if (i
.tm
.opcode_modifier
.vex
)
4604 for (j
= 0; j
< 3; j
++)
4606 i
.types
[j
].bitfield
.xmmword
= 1;
4607 i
.types
[j
].bitfield
.ymmword
= 0;
4610 else if (i
.vec_encoding
!= vex_encoding_evex
4611 && !i
.types
[0].bitfield
.zmmword
4612 && !i
.types
[1].bitfield
.zmmword
4614 && !i
.broadcast
.type
4615 && !i
.broadcast
.bytes
4616 && i
.tm
.opcode_modifier
.evex
4617 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4618 || (i
.tm
.base_opcode
& ~4) == 0xdb
4619 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4620 && i
.tm
.extension_opcode
== None
)
4623 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4624 vmovdqu32 and vmovdqu64:
4625 EVEX VOP %xmmM, %xmmN
4626 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4627 EVEX VOP %ymmM, %ymmN
4628 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4630 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4632 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4634 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4636 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4637 VOP, one of vpand, vpandn, vpor, vpxor:
4638 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4639 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4640 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4641 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4642 EVEX VOP{d,q} mem, %xmmM, %xmmN
4643 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4644 EVEX VOP{d,q} mem, %ymmM, %ymmN
4645 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4647 for (j
= 0; j
< i
.operands
; j
++)
4648 if (operand_type_check (i
.types
[j
], disp
)
4649 && i
.op
[j
].disps
->X_op
== O_constant
)
4651 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4652 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4653 bytes, we choose EVEX Disp8 over VEX Disp32. */
4654 int evex_disp8
, vex_disp8
;
4655 unsigned int memshift
= i
.memshift
;
4656 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4658 evex_disp8
= fits_in_disp8 (n
);
4660 vex_disp8
= fits_in_disp8 (n
);
4661 if (evex_disp8
!= vex_disp8
)
4663 i
.memshift
= memshift
;
4667 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4670 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4671 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4672 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4673 i
.tm
.opcode_modifier
.vex
4674 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4675 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4676 /* VPAND, VPOR, and VPXOR are commutative. */
4677 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4678 i
.tm
.opcode_modifier
.commutative
= 1;
4679 i
.tm
.opcode_modifier
.evex
= 0;
4680 i
.tm
.opcode_modifier
.masking
= 0;
4681 i
.tm
.opcode_modifier
.broadcast
= 0;
4682 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4685 i
.types
[j
].bitfield
.disp8
4686 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4688 else if (optimize_for_space
4689 && i
.tm
.base_opcode
== 0x29
4690 && i
.tm
.opcode_space
== SPACE_0F38
4691 && i
.operands
== i
.reg_operands
4692 && i
.op
[0].regs
== i
.op
[1].regs
4693 && (!i
.tm
.opcode_modifier
.vex
4694 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4695 && !i
.tm
.opcode_modifier
.evex
)
4698 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4699 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4700 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4702 i
.tm
.opcode_space
= SPACE_0F
;
4703 i
.tm
.base_opcode
= 0x76;
4705 else if (((i
.tm
.base_opcode
>= 0x64
4706 && i
.tm
.base_opcode
<= 0x66
4707 && i
.tm
.opcode_space
== SPACE_0F
)
4708 || (i
.tm
.base_opcode
== 0x37
4709 && i
.tm
.opcode_space
== SPACE_0F38
))
4710 && i
.operands
== i
.reg_operands
4711 && i
.op
[0].regs
== i
.op
[1].regs
4712 && !i
.tm
.opcode_modifier
.evex
)
4715 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4716 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4717 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4718 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4719 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4720 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4722 i
.tm
.opcode_space
= SPACE_0F
;
4723 i
.tm
.base_opcode
= 0xef;
4724 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4726 if (i
.operands
== 2)
4728 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4734 i
.op
[2].regs
= i
.op
[0].regs
;
4735 i
.types
[2] = i
.types
[0];
4736 i
.flags
[2] = i
.flags
[0];
4737 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4739 i
.tm
.opcode_modifier
.sse2avx
= 0;
4741 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4742 i
.op
[1].regs
= i
.op
[0].regs
;
4745 else if (optimize_for_space
4746 && i
.tm
.base_opcode
== 0x59
4747 && i
.tm
.opcode_space
== SPACE_0F38
4748 && i
.operands
== i
.reg_operands
4749 && i
.tm
.opcode_modifier
.vex
4750 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4751 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4752 && i
.vec_encoding
!= vex_encoding_vex3
)
4755 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4757 i
.tm
.opcode_space
= SPACE_0F
;
4758 i
.tm
.base_opcode
= 0x6c;
4759 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4765 i
.op
[2].regs
= i
.op
[0].regs
;
4766 i
.types
[2] = i
.types
[0];
4767 i
.flags
[2] = i
.flags
[0];
4768 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4770 swap_2_operands (1, 2);
4774 /* Return non-zero for load instruction. */
4780 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4781 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4785 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4786 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4787 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4791 if (i
.tm
.mnem_off
== MN_pop
)
4795 if (i
.tm
.opcode_space
== SPACE_BASE
)
4798 if (i
.tm
.base_opcode
== 0x9d
4799 || i
.tm
.base_opcode
== 0x61)
4802 /* movs, cmps, lods, scas. */
4803 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4807 if (base_opcode
== 0x6f
4808 || i
.tm
.base_opcode
== 0xd7)
4810 /* NB: For AMD-specific insns with implicit memory operands,
4811 they're intentionally not covered. */
4814 /* No memory operand. */
4815 if (!i
.mem_operands
)
4820 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4823 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4825 /* test, not, neg, mul, imul, div, idiv. */
4826 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4830 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4833 /* add, or, adc, sbb, and, sub, xor, cmp. */
4834 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4837 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4838 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4839 && i
.tm
.extension_opcode
!= 6)
4842 /* Check for x87 instructions. */
4843 if ((base_opcode
| 6) == 0xdf)
4845 /* Skip fst, fstp, fstenv, fstcw. */
4846 if (i
.tm
.base_opcode
== 0xd9
4847 && (i
.tm
.extension_opcode
== 2
4848 || i
.tm
.extension_opcode
== 3
4849 || i
.tm
.extension_opcode
== 6
4850 || i
.tm
.extension_opcode
== 7))
4853 /* Skip fisttp, fist, fistp, fstp. */
4854 if (i
.tm
.base_opcode
== 0xdb
4855 && (i
.tm
.extension_opcode
== 1
4856 || i
.tm
.extension_opcode
== 2
4857 || i
.tm
.extension_opcode
== 3
4858 || i
.tm
.extension_opcode
== 7))
4861 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4862 if (i
.tm
.base_opcode
== 0xdd
4863 && (i
.tm
.extension_opcode
== 1
4864 || i
.tm
.extension_opcode
== 2
4865 || i
.tm
.extension_opcode
== 3
4866 || i
.tm
.extension_opcode
== 6
4867 || i
.tm
.extension_opcode
== 7))
4870 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4871 if (i
.tm
.base_opcode
== 0xdf
4872 && (i
.tm
.extension_opcode
== 1
4873 || i
.tm
.extension_opcode
== 2
4874 || i
.tm
.extension_opcode
== 3
4875 || i
.tm
.extension_opcode
== 6
4876 || i
.tm
.extension_opcode
== 7))
4882 else if (i
.tm
.opcode_space
== SPACE_0F
)
4884 /* bt, bts, btr, btc. */
4885 if (i
.tm
.base_opcode
== 0xba
4886 && (i
.tm
.extension_opcode
| 3) == 7)
4889 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4890 if (i
.tm
.base_opcode
== 0xc7
4891 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4892 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4893 || i
.tm
.extension_opcode
== 6))
4896 /* fxrstor, ldmxcsr, xrstor. */
4897 if (i
.tm
.base_opcode
== 0xae
4898 && (i
.tm
.extension_opcode
== 1
4899 || i
.tm
.extension_opcode
== 2
4900 || i
.tm
.extension_opcode
== 5))
4903 /* lgdt, lidt, lmsw. */
4904 if (i
.tm
.base_opcode
== 0x01
4905 && (i
.tm
.extension_opcode
== 2
4906 || i
.tm
.extension_opcode
== 3
4907 || i
.tm
.extension_opcode
== 6))
4911 dest
= i
.operands
- 1;
4913 /* Check fake imm8 operand and 3 source operands. */
4914 if ((i
.tm
.opcode_modifier
.immext
4915 || i
.reg_operands
+ i
.mem_operands
== 4)
4916 && i
.types
[dest
].bitfield
.imm8
)
4919 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4920 if (i
.tm
.opcode_space
== SPACE_BASE
4921 && ((base_opcode
| 0x38) == 0x39
4922 || (base_opcode
| 2) == 0x87))
4925 if (i
.tm
.mnem_off
== MN_xadd
)
4928 /* Check for load instruction. */
4929 return (i
.types
[dest
].bitfield
.class != ClassNone
4930 || i
.types
[dest
].bitfield
.instance
== Accum
);
4933 /* Output lfence, 0xfaee8, after instruction. */
4936 insert_lfence_after (void)
4938 if (lfence_after_load
&& load_insn_p ())
4940 /* There are also two REP string instructions that require
4941 special treatment. Specifically, the compare string (CMPS)
4942 and scan string (SCAS) instructions set EFLAGS in a manner
4943 that depends on the data being compared/scanned. When used
4944 with a REP prefix, the number of iterations may therefore
4945 vary depending on this data. If the data is a program secret
4946 chosen by the adversary using an LVI method,
4947 then this data-dependent behavior may leak some aspect
4949 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4950 && i
.prefix
[REP_PREFIX
])
4952 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4955 char *p
= frag_more (3);
4962 /* Output lfence, 0xfaee8, before instruction. */
4965 insert_lfence_before (void)
4969 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4972 if (i
.tm
.base_opcode
== 0xff
4973 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4975 /* Insert lfence before indirect branch if needed. */
4977 if (lfence_before_indirect_branch
== lfence_branch_none
)
4980 if (i
.operands
!= 1)
4983 if (i
.reg_operands
== 1)
4985 /* Indirect branch via register. Don't insert lfence with
4986 -mlfence-after-load=yes. */
4987 if (lfence_after_load
4988 || lfence_before_indirect_branch
== lfence_branch_memory
)
4991 else if (i
.mem_operands
== 1
4992 && lfence_before_indirect_branch
!= lfence_branch_register
)
4994 as_warn (_("indirect `%s` with memory operand should be avoided"),
5001 if (last_insn
.kind
!= last_insn_other
5002 && last_insn
.seg
== now_seg
)
5004 as_warn_where (last_insn
.file
, last_insn
.line
,
5005 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5006 last_insn
.name
, insn_name (&i
.tm
));
5017 /* Output or/not/shl and lfence before near ret. */
5018 if (lfence_before_ret
!= lfence_before_ret_none
5019 && (i
.tm
.base_opcode
| 1) == 0xc3)
5021 if (last_insn
.kind
!= last_insn_other
5022 && last_insn
.seg
== now_seg
)
5024 as_warn_where (last_insn
.file
, last_insn
.line
,
5025 _("`%s` skips -mlfence-before-ret on `%s`"),
5026 last_insn
.name
, insn_name (&i
.tm
));
5030 /* Near ret ingore operand size override under CPU64. */
5031 char prefix
= flag_code
== CODE_64BIT
5033 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5035 if (lfence_before_ret
== lfence_before_ret_not
)
5037 /* not: 0xf71424, may add prefix
5038 for operand size override or 64-bit code. */
5039 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5053 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5056 if (lfence_before_ret
== lfence_before_ret_or
)
5058 /* or: 0x830c2400, may add prefix
5059 for operand size override or 64-bit code. */
5065 /* shl: 0xc1242400, may add prefix
5066 for operand size override or 64-bit code. */
5081 /* Shared helper for md_assemble() and s_insn(). */
5082 static void init_globals (void)
5086 memset (&i
, '\0', sizeof (i
));
5087 i
.rounding
.type
= rc_none
;
5088 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5089 i
.reloc
[j
] = NO_RELOC
;
5090 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5091 memset (im_expressions
, '\0', sizeof (im_expressions
));
5092 save_stack_p
= save_stack
;
5095 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5096 parsing pass. Instead of introducing a rarely use new insn attribute this
5097 utilizes a common pattern between affected templates. It is deemed
5098 acceptable that this will lead to unnecessary pass 2 preparations in a
5099 limited set of cases. */
5100 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5102 return t
->opcode_modifier
.sse2avx
5103 /* Note that all SSE2AVX templates have at least one operand. */
5104 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5105 : (t
->opcode_space
== SPACE_0F
5106 && (t
->base_opcode
| 1) == 0xbf)
5107 || (t
->opcode_space
== SPACE_BASE
5108 && t
->base_opcode
== 0x63);
5111 /* This is the guts of the machine-dependent assembler. LINE points to a
5112 machine dependent instruction. This function is supposed to emit
5113 the frags/bytes it assembles to. */
5116 md_assemble (char *line
)
5119 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5120 const char *end
, *pass1_mnem
= NULL
;
5121 enum i386_error pass1_err
= 0;
5122 const insn_template
*t
;
5124 /* Initialize globals. */
5125 current_templates
= NULL
;
5129 /* First parse an instruction mnemonic & call i386_operand for the operands.
5130 We assume that the scrubber has arranged it so that line[0] is the valid
5131 start of a (possibly prefixed) mnemonic. */
5133 end
= parse_insn (line
, mnemonic
, false);
5136 if (pass1_mnem
!= NULL
)
5138 if (i
.error
!= no_error
)
5140 gas_assert (current_templates
!= NULL
);
5141 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5143 /* No point in trying a 2nd pass - it'll only find the same suffix
5145 mnem_suffix
= i
.suffix
;
5150 t
= current_templates
->start
;
5151 if (may_need_pass2 (t
))
5153 /* Make a copy of the full line in case we need to retry. */
5154 copy
= xstrdup (line
);
5157 mnem_suffix
= i
.suffix
;
5159 line
= parse_operands (line
, mnemonic
);
5167 /* Now we've parsed the mnemonic into a set of templates, and have the
5168 operands at hand. */
5170 /* All Intel opcodes have reversed operands except for "bound", "enter",
5171 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5172 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5173 intersegment "jmp" and "call" instructions with 2 immediate operands so
5174 that the immediate segment precedes the offset consistently in Intel and
5178 && (t
->mnem_off
!= MN_bound
)
5179 && !startswith (mnemonic
, "invlpg")
5180 && !startswith (mnemonic
, "monitor")
5181 && !startswith (mnemonic
, "mwait")
5182 && (t
->mnem_off
!= MN_pvalidate
)
5183 && !startswith (mnemonic
, "rmp")
5184 && (t
->mnem_off
!= MN_tpause
)
5185 && (t
->mnem_off
!= MN_umwait
)
5186 && !(i
.operands
== 2
5187 && operand_type_check (i
.types
[0], imm
)
5188 && operand_type_check (i
.types
[1], imm
)))
5191 /* The order of the immediates should be reversed
5192 for 2 immediates extrq and insertq instructions */
5193 if (i
.imm_operands
== 2
5194 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5195 swap_2_operands (0, 1);
5199 /* For USER_MSR instructions, imm32 stands for the name of an model specific
5200 register (MSR). That's an unsigned quantity, whereas all other insns with
5201 32-bit immediate and 64-bit operand size use sign-extended
5202 immediates (imm32s). Therefore these insns are special-cased, bypassing
5203 the normal handling of immediates here. */
5204 if (is_cpu(current_templates
->start
, CpuUSER_MSR
))
5206 for (j
= 0; j
< i
.operands
; j
++)
5208 if (operand_type_check(i
.types
[j
], imm
))
5209 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
5216 if (i
.disp_operands
&& !optimize_disp (t
))
5219 /* Next, we find a template that matches the given insn,
5220 making sure the overlap of the given operands types is consistent
5221 with the template operand types. */
5223 if (!(t
= match_template (mnem_suffix
)))
5225 const char *err_msg
;
5227 if (copy
&& !mnem_suffix
)
5232 pass1_err
= i
.error
;
5233 pass1_mnem
= insn_name (current_templates
->start
);
5237 /* If a non-/only-64bit template (group) was found in pass 1, and if
5238 _some_ template (group) was found in pass 2, squash pass 1's
5240 if (pass1_err
== unsupported_64bit
)
5246 switch (pass1_mnem
? pass1_err
: i
.error
)
5250 case operand_size_mismatch
:
5251 err_msg
= _("operand size mismatch");
5253 case operand_type_mismatch
:
5254 err_msg
= _("operand type mismatch");
5256 case register_type_mismatch
:
5257 err_msg
= _("register type mismatch");
5259 case number_of_operands_mismatch
:
5260 err_msg
= _("number of operands mismatch");
5262 case invalid_instruction_suffix
:
5263 err_msg
= _("invalid instruction suffix");
5266 err_msg
= _("constant doesn't fit in 4 bits");
5268 case unsupported_with_intel_mnemonic
:
5269 err_msg
= _("unsupported with Intel mnemonic");
5271 case unsupported_syntax
:
5272 err_msg
= _("unsupported syntax");
5275 as_bad (_("unsupported instruction `%s'"),
5276 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5278 case unsupported_on_arch
:
5279 as_bad (_("`%s' is not supported on `%s%s'"),
5280 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5281 cpu_arch_name
? cpu_arch_name
: default_arch
,
5282 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5284 case unsupported_64bit
:
5285 if (ISLOWER (mnem_suffix
))
5287 if (flag_code
== CODE_64BIT
)
5288 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5289 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5292 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5293 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5298 if (flag_code
== CODE_64BIT
)
5299 as_bad (_("`%s' is not supported in 64-bit mode"),
5300 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5302 as_bad (_("`%s' is only supported in 64-bit mode"),
5303 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5306 case invalid_sib_address
:
5307 err_msg
= _("invalid SIB address");
5309 case invalid_vsib_address
:
5310 err_msg
= _("invalid VSIB address");
5312 case invalid_vector_register_set
:
5313 err_msg
= _("mask, index, and destination registers must be distinct");
5315 case invalid_tmm_register_set
:
5316 err_msg
= _("all tmm registers must be distinct");
5318 case invalid_dest_and_src_register_set
:
5319 err_msg
= _("destination and source registers must be distinct");
5321 case unsupported_vector_index_register
:
5322 err_msg
= _("unsupported vector index register");
5324 case unsupported_broadcast
:
5325 err_msg
= _("unsupported broadcast");
5327 case broadcast_needed
:
5328 err_msg
= _("broadcast is needed for operand of such type");
5330 case unsupported_masking
:
5331 err_msg
= _("unsupported masking");
5333 case mask_not_on_destination
:
5334 err_msg
= _("mask not on destination operand");
5336 case no_default_mask
:
5337 err_msg
= _("default mask isn't allowed");
5339 case unsupported_rc_sae
:
5340 err_msg
= _("unsupported static rounding/sae");
5342 case invalid_register_operand
:
5343 err_msg
= _("invalid register operand");
5345 case internal_error
:
5346 err_msg
= _("internal error");
5349 as_bad (_("%s for `%s'"), err_msg
,
5350 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5356 if (sse_check
!= check_none
5357 /* The opcode space check isn't strictly needed; it's there only to
5358 bypass the logic below when easily possible. */
5359 && t
->opcode_space
>= SPACE_0F
5360 && t
->opcode_space
<= SPACE_0F3A
5361 && !is_cpu (&i
.tm
, CpuSSE4a
)
5362 && !is_any_vex_encoding (t
))
5366 for (j
= 0; j
< t
->operands
; ++j
)
5368 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5370 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5374 if (j
>= t
->operands
&& simd
)
5375 (sse_check
== check_warning
5377 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5380 if (i
.tm
.opcode_modifier
.fwait
)
5381 if (!add_prefix (FWAIT_OPCODE
))
5384 /* Check if REP prefix is OK. */
5385 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5387 as_bad (_("invalid instruction `%s' after `%s'"),
5388 insn_name (&i
.tm
), i
.rep_prefix
);
5392 /* Check for lock without a lockable instruction. Destination operand
5393 must be memory unless it is xchg (0x86). */
5394 if (i
.prefix
[LOCK_PREFIX
])
5396 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5397 || i
.mem_operands
== 0
5398 || (i
.tm
.base_opcode
!= 0x86
5399 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5401 as_bad (_("expecting lockable instruction after `lock'"));
5405 /* Zap the redundant prefix from XCHG when optimizing. */
5406 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5407 i
.prefix
[LOCK_PREFIX
] = 0;
5410 if (is_any_vex_encoding (&i
.tm
)
5411 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5412 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5414 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5415 if (i
.prefix
[DATA_PREFIX
])
5417 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5421 /* Don't allow e.g. KMOV in TLS code sequences. */
5422 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5425 case BFD_RELOC_386_TLS_GOTIE
:
5426 case BFD_RELOC_386_TLS_LE_32
:
5427 case BFD_RELOC_X86_64_GOTTPOFF
:
5428 case BFD_RELOC_X86_64_TLSLD
:
5429 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5436 /* Check if HLE prefix is OK. */
5437 if (i
.hle_prefix
&& !check_hle ())
5440 /* Check BND prefix. */
5441 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5442 as_bad (_("expecting valid branch instruction after `bnd'"));
5444 /* Check NOTRACK prefix. */
5445 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5446 as_bad (_("expecting indirect branch instruction after `notrack'"));
5448 if (is_cpu (&i
.tm
, CpuMPX
))
5450 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5451 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5452 else if (flag_code
!= CODE_16BIT
5453 ? i
.prefix
[ADDR_PREFIX
]
5454 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5455 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5458 /* Insert BND prefix. */
5459 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5461 if (!i
.prefix
[BND_PREFIX
])
5462 add_prefix (BND_PREFIX_OPCODE
);
5463 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5465 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5466 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5470 /* Check string instruction segment overrides. */
5471 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5473 gas_assert (i
.mem_operands
);
5474 if (!check_string ())
5476 i
.disp_operands
= 0;
5479 /* The memory operand of (%dx) should be only used with input/output
5480 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5481 if (i
.input_output_operand
5482 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5483 || i
.tm
.opcode_space
!= SPACE_BASE
))
5485 as_bad (_("input/output port address isn't allowed with `%s'"),
5490 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5491 optimize_encoding ();
5493 /* Past optimization there's no need to distinguish vex_encoding_evex and
5494 vex_encoding_evex512 anymore. */
5495 if (i
.vec_encoding
== vex_encoding_evex512
)
5496 i
.vec_encoding
= vex_encoding_evex
;
5498 if (use_unaligned_vector_move
)
5499 encode_with_unaligned_vector_move ();
5501 if (!process_suffix ())
5504 /* Check if IP-relative addressing requirements can be satisfied. */
5505 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5506 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5507 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5509 /* Update operand types and check extended states. */
5510 for (j
= 0; j
< i
.operands
; j
++)
5512 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5513 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5518 i
.xstate
|= xstate_mmx
;
5521 i
.xstate
|= xstate_mask
;
5524 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5525 i
.xstate
|= xstate_tmm
;
5526 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5527 && !i
.tm
.opcode_modifier
.vex
5528 && vector_size
>= VSZ512
)
5529 i
.xstate
|= xstate_zmm
;
5530 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5531 && vector_size
>= VSZ256
)
5532 i
.xstate
|= xstate_ymm
;
5533 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5534 i
.xstate
|= xstate_xmm
;
5539 /* Make still unresolved immediate matches conform to size of immediate
5540 given in i.suffix. */
5541 if (!finalize_imm ())
5544 if (i
.types
[0].bitfield
.imm1
)
5545 i
.imm_operands
= 0; /* kludge for shift insns. */
5547 /* For insns with operands there are more diddles to do to the opcode. */
5550 if (!process_operands ())
5553 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5555 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5556 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5559 if (is_any_vex_encoding (&i
.tm
))
5561 if (!cpu_arch_flags
.bitfield
.cpui286
)
5563 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5568 /* Check for explicit REX prefix. */
5569 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5571 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5575 if (i
.tm
.opcode_modifier
.vex
)
5576 build_vex_prefix (t
);
5578 build_evex_prefix ();
5580 /* The individual REX.RXBW bits got consumed. */
5581 i
.rex
&= REX_OPCODE
;
5584 /* Handle conversion of 'int $3' --> special int3 insn. */
5585 if (i
.tm
.mnem_off
== MN_int
5586 && i
.op
[0].imms
->X_add_number
== 3)
5588 i
.tm
.base_opcode
= INT3_OPCODE
;
5592 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5593 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5594 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5595 && i
.op
[0].disps
->X_op
== O_constant
)
5597 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5598 the absolute address given by the constant. Since ix86 jumps and
5599 calls are pc relative, we need to generate a reloc. */
5600 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5601 i
.op
[0].disps
->X_op
= O_symbol
;
5604 /* For 8 bit registers we need an empty rex prefix. Also if the
5605 instruction already has a prefix, we need to convert old
5606 registers to new ones. */
5608 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5609 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5610 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5611 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5612 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5613 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5618 i
.rex
|= REX_OPCODE
;
5619 for (x
= 0; x
< 2; x
++)
5621 /* Look for 8 bit operand that uses old registers. */
5622 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5623 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5625 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5626 /* In case it is "hi" register, give up. */
5627 if (i
.op
[x
].regs
->reg_num
> 3)
5628 as_bad (_("can't encode register '%s%s' in an "
5629 "instruction requiring REX prefix."),
5630 register_prefix
, i
.op
[x
].regs
->reg_name
);
5632 /* Otherwise it is equivalent to the extended register.
5633 Since the encoding doesn't change this is merely
5634 cosmetic cleanup for debug output. */
5636 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5641 if (i
.rex
== 0 && i
.rex_encoding
)
5643 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5644 that uses legacy register. If it is "hi" register, don't add
5645 the REX_OPCODE byte. */
5647 for (x
= 0; x
< 2; x
++)
5648 if (i
.types
[x
].bitfield
.class == Reg
5649 && i
.types
[x
].bitfield
.byte
5650 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5651 && i
.op
[x
].regs
->reg_num
> 3)
5653 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5654 i
.rex_encoding
= false;
5663 add_prefix (REX_OPCODE
| i
.rex
);
5665 insert_lfence_before ();
5667 /* We are ready to output the insn. */
5670 insert_lfence_after ();
5672 last_insn
.seg
= now_seg
;
5674 if (i
.tm
.opcode_modifier
.isprefix
)
5676 last_insn
.kind
= last_insn_prefix
;
5677 last_insn
.name
= insn_name (&i
.tm
);
5678 last_insn
.file
= as_where (&last_insn
.line
);
5681 last_insn
.kind
= last_insn_other
;
5684 /* The Q suffix is generally valid only in 64-bit mode, with very few
5685 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5686 and fisttp only one of their two templates is matched below: That's
5687 sufficient since other relevant attributes are the same between both
5688 respective templates. */
5689 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5691 return flag_code
== CODE_64BIT
5692 || (t
->opcode_space
== SPACE_BASE
5693 && t
->base_opcode
== 0xdf
5694 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5695 || t
->mnem_off
== MN_cmpxchg8b
;
5699 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5701 const char *l
= line
, *token_start
= l
;
5703 bool pass1
= !current_templates
;
5705 const insn_template
*t
;
5711 /* Pseudo-prefixes start with an opening figure brace. */
5712 if ((*mnem_p
= *l
) == '{')
5717 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5722 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5725 as_bad (_("no such instruction: `%s'"), token_start
);
5730 /* Pseudo-prefixes end with a closing figure brace. */
5731 if (*mnemonic
== '{' && *l
== '}')
5734 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5738 /* Point l at the closing brace if there's no other separator. */
5739 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5740 && *l
!= PREFIX_SEPARATOR
)
5743 else if (!is_space_char (*l
)
5744 && *l
!= END_OF_INSN
5746 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5750 as_bad (_("invalid character %s in mnemonic"),
5751 output_invalid (*l
));
5754 if (token_start
== l
)
5756 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5757 as_bad (_("expecting prefix; got nothing"));
5759 as_bad (_("expecting mnemonic; got nothing"));
5763 /* Look up instruction (or prefix) via hash table. */
5764 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5766 if (*l
!= END_OF_INSN
5767 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5768 && current_templates
5769 && current_templates
->start
->opcode_modifier
.isprefix
)
5771 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5773 as_bad ((flag_code
!= CODE_64BIT
5774 ? _("`%s' is only supported in 64-bit mode")
5775 : _("`%s' is not supported in 64-bit mode")),
5776 insn_name (current_templates
->start
));
5779 /* If we are in 16-bit mode, do not allow addr16 or data16.
5780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5781 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5782 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5783 && flag_code
!= CODE_64BIT
5784 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5785 ^ (flag_code
== CODE_16BIT
)))
5787 as_bad (_("redundant %s prefix"),
5788 insn_name (current_templates
->start
));
5792 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5794 /* Handle pseudo prefixes. */
5795 switch (current_templates
->start
->extension_opcode
)
5799 i
.disp_encoding
= disp_encoding_8bit
;
5803 i
.disp_encoding
= disp_encoding_16bit
;
5807 i
.disp_encoding
= disp_encoding_32bit
;
5811 i
.dir_encoding
= dir_encoding_load
;
5815 i
.dir_encoding
= dir_encoding_store
;
5819 i
.vec_encoding
= vex_encoding_vex
;
5823 i
.vec_encoding
= vex_encoding_vex3
;
5827 i
.vec_encoding
= vex_encoding_evex
;
5831 i
.rex_encoding
= true;
5833 case Prefix_NoOptimize
:
5835 i
.no_optimize
= true;
5843 /* Add prefix, checking for repeated prefixes. */
5844 switch (add_prefix (current_templates
->start
->base_opcode
))
5849 if (is_cpu (current_templates
->start
, CpuIBT
))
5850 i
.notrack_prefix
= insn_name (current_templates
->start
);
5853 if (is_cpu (current_templates
->start
, CpuHLE
))
5854 i
.hle_prefix
= insn_name (current_templates
->start
);
5855 else if (is_cpu (current_templates
->start
, CpuMPX
))
5856 i
.bnd_prefix
= insn_name (current_templates
->start
);
5858 i
.rep_prefix
= insn_name (current_templates
->start
);
5864 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5874 if (!current_templates
)
5876 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5877 Check if we should swap operand or force 32bit displacement in
5879 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5880 i
.dir_encoding
= dir_encoding_swap
;
5881 else if (mnem_p
- 3 == dot_p
5884 i
.disp_encoding
= disp_encoding_8bit
;
5885 else if (mnem_p
- 4 == dot_p
5889 i
.disp_encoding
= disp_encoding_32bit
;
5894 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5897 if (!current_templates
|| !pass1
)
5899 current_templates
= NULL
;
5902 if (mnem_p
> mnemonic
)
5904 /* See if we can get a match by trimming off a suffix. */
5907 case WORD_MNEM_SUFFIX
:
5908 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5909 i
.suffix
= SHORT_MNEM_SUFFIX
;
5912 case BYTE_MNEM_SUFFIX
:
5913 case QWORD_MNEM_SUFFIX
:
5914 i
.suffix
= mnem_p
[-1];
5917 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5919 case SHORT_MNEM_SUFFIX
:
5920 case LONG_MNEM_SUFFIX
:
5923 i
.suffix
= mnem_p
[-1];
5926 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5934 if (intel_float_operand (mnemonic
) == 1)
5935 i
.suffix
= SHORT_MNEM_SUFFIX
;
5937 i
.suffix
= LONG_MNEM_SUFFIX
;
5940 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5942 /* For compatibility reasons accept MOVSD and CMPSD without
5943 operands even in AT&T mode. */
5944 else if (*l
== END_OF_INSN
5945 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5949 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5950 if (current_templates
!= NULL
5952 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5953 && current_templates
->start
->opcode_space
5955 && mnem_p
[-2] == 's')
5957 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5958 mnemonic
, mnemonic
);
5959 i
.suffix
= LONG_MNEM_SUFFIX
;
5963 current_templates
= NULL
;
5971 if (!current_templates
)
5974 as_bad (_("no such instruction: `%s'"), token_start
);
5979 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5980 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5982 /* Check for a branch hint. We allow ",pt" and ",pn" for
5983 predict taken and predict not taken respectively.
5984 I'm not sure that branch hints actually do anything on loop
5985 and jcxz insns (JumpByte) for current Pentium4 chips. They
5986 may work in the future and it doesn't hurt to accept them
5988 if (l
[0] == ',' && l
[1] == 'p')
5992 if (!add_prefix (DS_PREFIX_OPCODE
))
5996 else if (l
[2] == 'n')
5998 if (!add_prefix (CS_PREFIX_OPCODE
))
6004 /* Any other comma loses. */
6007 as_bad (_("invalid character %s in mnemonic"),
6008 output_invalid (*l
));
6012 /* Check if instruction is supported on specified architecture. */
6014 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6016 supported
|= cpu_flags_match (t
);
6018 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6019 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6021 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6027 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6028 i
.error
= unsupported_on_arch
;
6030 i
.error
= unsupported_64bit
;
6037 parse_operands (char *l
, const char *mnemonic
)
6041 /* 1 if operand is pending after ','. */
6042 unsigned int expecting_operand
= 0;
6044 while (*l
!= END_OF_INSN
)
6046 /* Non-zero if operand parens not balanced. */
6047 unsigned int paren_not_balanced
= 0;
6048 /* True if inside double quotes. */
6049 bool in_quotes
= false;
6051 /* Skip optional white space before operand. */
6052 if (is_space_char (*l
))
6054 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6056 as_bad (_("invalid character %s before operand %d"),
6057 output_invalid (*l
),
6061 token_start
= l
; /* After white space. */
6062 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6064 if (*l
== END_OF_INSN
)
6068 as_bad (_("unbalanced double quotes in operand %d."),
6072 if (paren_not_balanced
)
6074 know (!intel_syntax
);
6075 as_bad (_("unbalanced parenthesis in operand %d."),
6080 break; /* we are done */
6082 else if (*l
== '\\' && l
[1] == '"')
6085 in_quotes
= !in_quotes
;
6086 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6088 as_bad (_("invalid character %s in operand %d"),
6089 output_invalid (*l
),
6093 if (!intel_syntax
&& !in_quotes
)
6096 ++paren_not_balanced
;
6098 --paren_not_balanced
;
6102 if (l
!= token_start
)
6103 { /* Yes, we've read in another operand. */
6104 unsigned int operand_ok
;
6105 this_operand
= i
.operands
++;
6106 if (i
.operands
> MAX_OPERANDS
)
6108 as_bad (_("spurious operands; (%d operands/instruction max)"),
6112 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6113 /* Now parse operand adding info to 'i' as we go along. */
6114 END_STRING_AND_SAVE (l
);
6116 if (i
.mem_operands
> 1)
6118 as_bad (_("too many memory references for `%s'"),
6125 i386_intel_operand (token_start
,
6126 intel_float_operand (mnemonic
));
6128 operand_ok
= i386_att_operand (token_start
);
6130 RESTORE_END_STRING (l
);
6136 if (expecting_operand
)
6138 expecting_operand_after_comma
:
6139 as_bad (_("expecting operand after ','; got nothing"));
6144 as_bad (_("expecting operand before ','; got nothing"));
6149 /* Now *l must be either ',' or END_OF_INSN. */
6152 if (*++l
== END_OF_INSN
)
6154 /* Just skip it, if it's \n complain. */
6155 goto expecting_operand_after_comma
;
6157 expecting_operand
= 1;
6164 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6166 union i386_op temp_op
;
6167 i386_operand_type temp_type
;
6168 unsigned int temp_flags
;
6169 enum bfd_reloc_code_real temp_reloc
;
6171 temp_type
= i
.types
[xchg2
];
6172 i
.types
[xchg2
] = i
.types
[xchg1
];
6173 i
.types
[xchg1
] = temp_type
;
6175 temp_flags
= i
.flags
[xchg2
];
6176 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6177 i
.flags
[xchg1
] = temp_flags
;
6179 temp_op
= i
.op
[xchg2
];
6180 i
.op
[xchg2
] = i
.op
[xchg1
];
6181 i
.op
[xchg1
] = temp_op
;
6183 temp_reloc
= i
.reloc
[xchg2
];
6184 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6185 i
.reloc
[xchg1
] = temp_reloc
;
6187 temp_flags
= i
.imm_bits
[xchg2
];
6188 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6189 i
.imm_bits
[xchg1
] = temp_flags
;
6193 if (i
.mask
.operand
== xchg1
)
6194 i
.mask
.operand
= xchg2
;
6195 else if (i
.mask
.operand
== xchg2
)
6196 i
.mask
.operand
= xchg1
;
6198 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6200 if (i
.broadcast
.operand
== xchg1
)
6201 i
.broadcast
.operand
= xchg2
;
6202 else if (i
.broadcast
.operand
== xchg2
)
6203 i
.broadcast
.operand
= xchg1
;
6208 swap_operands (void)
6214 swap_2_operands (1, i
.operands
- 2);
6218 swap_2_operands (0, i
.operands
- 1);
6224 if (i
.mem_operands
== 2)
6226 const reg_entry
*temp_seg
;
6227 temp_seg
= i
.seg
[0];
6228 i
.seg
[0] = i
.seg
[1];
6229 i
.seg
[1] = temp_seg
;
6233 /* Try to ensure constant immediates are represented in the smallest
6238 char guess_suffix
= 0;
6242 guess_suffix
= i
.suffix
;
6243 else if (i
.reg_operands
)
6245 /* Figure out a suffix from the last register operand specified.
6246 We can't do this properly yet, i.e. excluding special register
6247 instances, but the following works for instructions with
6248 immediates. In any case, we can't set i.suffix yet. */
6249 for (op
= i
.operands
; --op
>= 0;)
6250 if (i
.types
[op
].bitfield
.class != Reg
)
6252 else if (i
.types
[op
].bitfield
.byte
)
6254 guess_suffix
= BYTE_MNEM_SUFFIX
;
6257 else if (i
.types
[op
].bitfield
.word
)
6259 guess_suffix
= WORD_MNEM_SUFFIX
;
6262 else if (i
.types
[op
].bitfield
.dword
)
6264 guess_suffix
= LONG_MNEM_SUFFIX
;
6267 else if (i
.types
[op
].bitfield
.qword
)
6269 guess_suffix
= QWORD_MNEM_SUFFIX
;
6273 else if ((flag_code
== CODE_16BIT
)
6274 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6275 guess_suffix
= WORD_MNEM_SUFFIX
;
6276 else if (flag_code
!= CODE_64BIT
6277 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6278 /* A more generic (but also more involved) way of dealing
6279 with the special case(s) would be to go look for
6280 DefaultSize attributes on any of the templates. */
6281 && current_templates
->start
->mnem_off
!= MN_push
))
6282 guess_suffix
= LONG_MNEM_SUFFIX
;
6284 for (op
= i
.operands
; --op
>= 0;)
6285 if (operand_type_check (i
.types
[op
], imm
))
6287 switch (i
.op
[op
].imms
->X_op
)
6290 /* If a suffix is given, this operand may be shortened. */
6291 switch (guess_suffix
)
6293 case LONG_MNEM_SUFFIX
:
6294 i
.types
[op
].bitfield
.imm32
= 1;
6295 i
.types
[op
].bitfield
.imm64
= 1;
6297 case WORD_MNEM_SUFFIX
:
6298 i
.types
[op
].bitfield
.imm16
= 1;
6299 i
.types
[op
].bitfield
.imm32
= 1;
6300 i
.types
[op
].bitfield
.imm32s
= 1;
6301 i
.types
[op
].bitfield
.imm64
= 1;
6303 case BYTE_MNEM_SUFFIX
:
6304 i
.types
[op
].bitfield
.imm8
= 1;
6305 i
.types
[op
].bitfield
.imm8s
= 1;
6306 i
.types
[op
].bitfield
.imm16
= 1;
6307 i
.types
[op
].bitfield
.imm32
= 1;
6308 i
.types
[op
].bitfield
.imm32s
= 1;
6309 i
.types
[op
].bitfield
.imm64
= 1;
6313 /* If this operand is at most 16 bits, convert it
6314 to a signed 16 bit number before trying to see
6315 whether it will fit in an even smaller size.
6316 This allows a 16-bit operand such as $0xffe0 to
6317 be recognised as within Imm8S range. */
6318 if ((i
.types
[op
].bitfield
.imm16
)
6319 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6321 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6322 ^ 0x8000) - 0x8000);
6325 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6326 if ((i
.types
[op
].bitfield
.imm32
)
6327 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6329 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6330 ^ ((offsetT
) 1 << 31))
6331 - ((offsetT
) 1 << 31));
6335 = operand_type_or (i
.types
[op
],
6336 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6338 /* We must avoid matching of Imm32 templates when 64bit
6339 only immediate is available. */
6340 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6341 i
.types
[op
].bitfield
.imm32
= 0;
6348 /* Symbols and expressions. */
6350 /* Convert symbolic operand to proper sizes for matching, but don't
6351 prevent matching a set of insns that only supports sizes other
6352 than those matching the insn suffix. */
6354 i386_operand_type mask
, allowed
;
6355 const insn_template
*t
= current_templates
->start
;
6357 operand_type_set (&mask
, 0);
6358 switch (guess_suffix
)
6360 case QWORD_MNEM_SUFFIX
:
6361 mask
.bitfield
.imm64
= 1;
6362 mask
.bitfield
.imm32s
= 1;
6364 case LONG_MNEM_SUFFIX
:
6365 mask
.bitfield
.imm32
= 1;
6367 case WORD_MNEM_SUFFIX
:
6368 mask
.bitfield
.imm16
= 1;
6370 case BYTE_MNEM_SUFFIX
:
6371 mask
.bitfield
.imm8
= 1;
6377 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6378 while (++t
< current_templates
->end
)
6380 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6381 allowed
= operand_type_and (allowed
, mask
);
6384 if (!operand_type_all_zero (&allowed
))
6385 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6392 /* Try to use the smallest displacement type too. */
6394 optimize_disp (const insn_template
*t
)
6398 if (!want_disp32 (t
)
6399 && (!t
->opcode_modifier
.jump
6400 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6402 for (op
= 0; op
< i
.operands
; ++op
)
6404 const expressionS
*exp
= i
.op
[op
].disps
;
6406 if (!operand_type_check (i
.types
[op
], disp
))
6409 if (exp
->X_op
!= O_constant
)
6412 /* Since displacement is signed extended to 64bit, don't allow
6413 disp32 if it is out of range. */
6414 if (fits_in_signed_long (exp
->X_add_number
))
6417 i
.types
[op
].bitfield
.disp32
= 0;
6418 if (i
.types
[op
].bitfield
.baseindex
)
6420 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6421 (uint64_t) exp
->X_add_number
);
6427 /* Don't optimize displacement for movabs since it only takes 64bit
6429 if (i
.disp_encoding
> disp_encoding_8bit
6430 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6433 for (op
= i
.operands
; op
-- > 0;)
6434 if (operand_type_check (i
.types
[op
], disp
))
6436 if (i
.op
[op
].disps
->X_op
== O_constant
)
6438 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6440 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6442 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6443 i
.op
[op
].disps
= NULL
;
6448 if (i
.types
[op
].bitfield
.disp16
6449 && fits_in_unsigned_word (op_disp
))
6451 /* If this operand is at most 16 bits, convert
6452 to a signed 16 bit number and don't use 64bit
6454 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6455 i
.types
[op
].bitfield
.disp64
= 0;
6459 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6460 if ((flag_code
!= CODE_64BIT
6461 ? i
.types
[op
].bitfield
.disp32
6463 && (!t
->opcode_modifier
.jump
6464 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6465 && fits_in_unsigned_long (op_disp
))
6467 /* If this operand is at most 32 bits, convert
6468 to a signed 32 bit number and don't use 64bit
6470 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6471 i
.types
[op
].bitfield
.disp64
= 0;
6472 i
.types
[op
].bitfield
.disp32
= 1;
6475 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6477 i
.types
[op
].bitfield
.disp64
= 0;
6478 i
.types
[op
].bitfield
.disp32
= 1;
6481 if ((i
.types
[op
].bitfield
.disp32
6482 || i
.types
[op
].bitfield
.disp16
)
6483 && fits_in_disp8 (op_disp
))
6484 i
.types
[op
].bitfield
.disp8
= 1;
6486 i
.op
[op
].disps
->X_add_number
= op_disp
;
6488 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6489 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6491 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6492 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6493 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6496 /* We only support 64bit displacement on constants. */
6497 i
.types
[op
].bitfield
.disp64
= 0;
6503 /* Return 1 if there is a match in broadcast bytes between operand
6504 GIVEN and instruction template T. */
6507 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6509 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6510 && i
.types
[given
].bitfield
.byte
)
6511 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6512 && i
.types
[given
].bitfield
.word
)
6513 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6514 && i
.types
[given
].bitfield
.dword
)
6515 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6516 && i
.types
[given
].bitfield
.qword
));
6519 /* Check if operands are valid for the instruction. */
6522 check_VecOperands (const insn_template
*t
)
6527 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6528 any one operand are implicity requiring AVX512VL support if the actual
6529 operand size is YMMword or XMMword. Since this function runs after
6530 template matching, there's no need to check for YMMword/XMMword in
6532 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6533 if (!cpu_flags_all_zero (&cpu
)
6534 && !is_cpu (t
, CpuAVX512VL
)
6535 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6536 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6538 for (op
= 0; op
< t
->operands
; ++op
)
6540 if (t
->operand_types
[op
].bitfield
.zmmword
6541 && (i
.types
[op
].bitfield
.ymmword
6542 || i
.types
[op
].bitfield
.xmmword
))
6544 i
.error
= unsupported
;
6550 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6551 requiring AVX2 support if the actual operand size is YMMword. */
6552 if (maybe_cpu (t
, CpuAVX
) && maybe_cpu (t
, CpuAVX2
)
6553 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6555 for (op
= 0; op
< t
->operands
; ++op
)
6557 if (t
->operand_types
[op
].bitfield
.xmmword
6558 && i
.types
[op
].bitfield
.ymmword
)
6560 i
.error
= unsupported
;
6566 /* Without VSIB byte, we can't have a vector register for index. */
6567 if (!t
->opcode_modifier
.sib
6569 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6570 || i
.index_reg
->reg_type
.bitfield
.ymmword
6571 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6573 i
.error
= unsupported_vector_index_register
;
6577 /* Check if default mask is allowed. */
6578 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6579 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6581 i
.error
= no_default_mask
;
6585 /* For VSIB byte, we need a vector register for index, and all vector
6586 registers must be distinct. */
6587 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6590 || !((t
->opcode_modifier
.sib
== VECSIB128
6591 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6592 || (t
->opcode_modifier
.sib
== VECSIB256
6593 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6594 || (t
->opcode_modifier
.sib
== VECSIB512
6595 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6597 i
.error
= invalid_vsib_address
;
6601 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6602 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6604 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6605 gas_assert (i
.types
[0].bitfield
.xmmword
6606 || i
.types
[0].bitfield
.ymmword
);
6607 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6608 gas_assert (i
.types
[2].bitfield
.xmmword
6609 || i
.types
[2].bitfield
.ymmword
);
6610 if (operand_check
== check_none
)
6612 if (register_number (i
.op
[0].regs
)
6613 != register_number (i
.index_reg
)
6614 && register_number (i
.op
[2].regs
)
6615 != register_number (i
.index_reg
)
6616 && register_number (i
.op
[0].regs
)
6617 != register_number (i
.op
[2].regs
))
6619 if (operand_check
== check_error
)
6621 i
.error
= invalid_vector_register_set
;
6624 as_warn (_("mask, index, and destination registers should be distinct"));
6626 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6628 if (i
.types
[1].bitfield
.class == RegSIMD
6629 && (i
.types
[1].bitfield
.xmmword
6630 || i
.types
[1].bitfield
.ymmword
6631 || i
.types
[1].bitfield
.zmmword
)
6632 && (register_number (i
.op
[1].regs
)
6633 == register_number (i
.index_reg
)))
6635 if (operand_check
== check_error
)
6637 i
.error
= invalid_vector_register_set
;
6640 if (operand_check
!= check_none
)
6641 as_warn (_("index and destination registers should be distinct"));
6646 /* For AMX instructions with 3 TMM register operands, all operands
6647 must be distinct. */
6648 if (i
.reg_operands
== 3
6649 && t
->operand_types
[0].bitfield
.tmmword
6650 && (i
.op
[0].regs
== i
.op
[1].regs
6651 || i
.op
[0].regs
== i
.op
[2].regs
6652 || i
.op
[1].regs
== i
.op
[2].regs
))
6654 i
.error
= invalid_tmm_register_set
;
6658 /* For some special instructions require that destination must be distinct
6659 from source registers. */
6660 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6662 unsigned int dest_reg
= i
.operands
- 1;
6664 know (i
.operands
>= 3);
6666 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6667 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6668 || (i
.reg_operands
> 2
6669 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6671 i
.error
= invalid_dest_and_src_register_set
;
6676 /* Check if broadcast is supported by the instruction and is applied
6677 to the memory operand. */
6678 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6680 i386_operand_type type
, overlap
;
6682 /* Check if specified broadcast is supported in this instruction,
6683 and its broadcast bytes match the memory operand. */
6684 op
= i
.broadcast
.operand
;
6685 if (!t
->opcode_modifier
.broadcast
6686 || !(i
.flags
[op
] & Operand_Mem
)
6687 || (!i
.types
[op
].bitfield
.unspecified
6688 && !match_broadcast_size (t
, op
)))
6691 i
.error
= unsupported_broadcast
;
6695 operand_type_set (&type
, 0);
6696 switch (get_broadcast_bytes (t
, false))
6699 type
.bitfield
.word
= 1;
6702 type
.bitfield
.dword
= 1;
6705 type
.bitfield
.qword
= 1;
6708 type
.bitfield
.xmmword
= 1;
6711 if (vector_size
< VSZ256
)
6713 type
.bitfield
.ymmword
= 1;
6716 if (vector_size
< VSZ512
)
6718 type
.bitfield
.zmmword
= 1;
6724 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6725 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6726 && t
->operand_types
[op
].bitfield
.byte
6727 + t
->operand_types
[op
].bitfield
.word
6728 + t
->operand_types
[op
].bitfield
.dword
6729 + t
->operand_types
[op
].bitfield
.qword
> 1)
6731 overlap
.bitfield
.xmmword
= 0;
6732 overlap
.bitfield
.ymmword
= 0;
6733 overlap
.bitfield
.zmmword
= 0;
6735 if (operand_type_all_zero (&overlap
))
6738 if (t
->opcode_modifier
.checkoperandsize
)
6742 type
.bitfield
.baseindex
= 1;
6743 for (j
= 0; j
< i
.operands
; ++j
)
6746 && !operand_type_register_match(i
.types
[j
],
6747 t
->operand_types
[j
],
6749 t
->operand_types
[op
]))
6754 /* If broadcast is supported in this instruction, we need to check if
6755 operand of one-element size isn't specified without broadcast. */
6756 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6758 /* Find memory operand. */
6759 for (op
= 0; op
< i
.operands
; op
++)
6760 if (i
.flags
[op
] & Operand_Mem
)
6762 gas_assert (op
< i
.operands
);
6763 /* Check size of the memory operand. */
6764 if (match_broadcast_size (t
, op
))
6766 i
.error
= broadcast_needed
;
6771 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6773 /* Check if requested masking is supported. */
6776 if (!t
->opcode_modifier
.masking
)
6778 i
.error
= unsupported_masking
;
6782 /* Common rules for masking:
6783 - mask register destinations permit only zeroing-masking, without
6784 that actually being expressed by a {z} operand suffix or EVEX.z,
6785 - memory destinations allow only merging-masking,
6786 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6789 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6790 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6791 || t
->opcode_modifier
.sib
))
6793 i
.error
= unsupported_masking
;
6798 /* Check if masking is applied to dest operand. */
6799 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6801 i
.error
= mask_not_on_destination
;
6806 if (i
.rounding
.type
!= rc_none
)
6808 if (!t
->opcode_modifier
.sae
6809 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6812 i
.error
= unsupported_rc_sae
;
6816 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6818 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6820 for (op
= 0; op
< t
->operands
; ++op
)
6821 if (i
.types
[op
].bitfield
.zmmword
)
6823 if (op
>= t
->operands
)
6825 i
.error
= operand_size_mismatch
;
6831 /* Check the special Imm4 cases; must be the first operand. */
6832 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6834 if (i
.op
[0].imms
->X_op
!= O_constant
6835 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6841 /* Turn off Imm<N> so that update_imm won't complain. */
6842 operand_type_set (&i
.types
[0], 0);
6845 /* Check vector Disp8 operand. */
6846 if (t
->opcode_modifier
.disp8memshift
6847 && (!t
->opcode_modifier
.vex
6848 || need_evex_encoding ())
6849 && i
.disp_encoding
<= disp_encoding_8bit
)
6851 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6852 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6853 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6854 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6857 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6860 for (op
= 0; op
< i
.operands
; op
++)
6861 if (i
.flags
[op
] & Operand_Mem
)
6863 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6864 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6865 else if (t
->operand_types
[op
].bitfield
.xmmword
6866 + t
->operand_types
[op
].bitfield
.ymmword
6867 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6868 type
= &t
->operand_types
[op
];
6869 else if (!i
.types
[op
].bitfield
.unspecified
)
6870 type
= &i
.types
[op
];
6871 else /* Ambiguities get resolved elsewhere. */
6872 fallback
= &t
->operand_types
[op
];
6874 else if (i
.types
[op
].bitfield
.class == RegSIMD
6875 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6877 if (i
.types
[op
].bitfield
.zmmword
)
6879 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6881 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6885 if (!type
&& !i
.memshift
)
6889 if (type
->bitfield
.zmmword
)
6891 else if (type
->bitfield
.ymmword
)
6893 else if (type
->bitfield
.xmmword
)
6897 /* For the check in fits_in_disp8(). */
6898 if (i
.memshift
== 0)
6902 for (op
= 0; op
< i
.operands
; op
++)
6903 if (operand_type_check (i
.types
[op
], disp
)
6904 && i
.op
[op
].disps
->X_op
== O_constant
)
6906 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6908 i
.types
[op
].bitfield
.disp8
= 1;
6911 i
.types
[op
].bitfield
.disp8
= 0;
6920 /* Check if encoding requirements are met by the instruction. */
6923 VEX_check_encoding (const insn_template
*t
)
6925 if (i
.vec_encoding
== vex_encoding_error
)
6927 i
.error
= unsupported
;
6931 /* Vector size restrictions. */
6932 if ((vector_size
< VSZ512
6933 && (t
->opcode_modifier
.evex
== EVEX512
6934 || t
->opcode_modifier
.vsz
>= VSZ512
))
6935 || (vector_size
< VSZ256
6936 && (t
->opcode_modifier
.evex
== EVEX256
6937 || t
->opcode_modifier
.vex
== VEX256
6938 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6940 i
.error
= unsupported
;
6944 if (i
.vec_encoding
== vex_encoding_evex
6945 || i
.vec_encoding
== vex_encoding_evex512
)
6947 /* This instruction must be encoded with EVEX prefix. */
6948 if (!t
->opcode_modifier
.evex
)
6950 i
.error
= unsupported
;
6956 if (!t
->opcode_modifier
.vex
)
6958 /* This instruction template doesn't have VEX prefix. */
6959 if (i
.vec_encoding
!= vex_encoding_default
)
6961 i
.error
= unsupported
;
6970 /* Helper function for the progress() macro in match_template(). */
6971 static INLINE
enum i386_error
progress (enum i386_error
new,
6972 enum i386_error last
,
6973 unsigned int line
, unsigned int *line_p
)
6975 if (line
<= *line_p
)
6981 static const insn_template
*
6982 match_template (char mnem_suffix
)
6984 /* Points to template once we've found it. */
6985 const insn_template
*t
;
6986 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6987 i386_operand_type overlap4
;
6988 unsigned int found_reverse_match
;
6989 i386_operand_type operand_types
[MAX_OPERANDS
];
6990 int addr_prefix_disp
;
6991 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6992 enum i386_error specific_error
= number_of_operands_mismatch
;
6993 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6995 #if MAX_OPERANDS != 5
6996 # error "MAX_OPERANDS must be 5."
6999 found_reverse_match
= 0;
7000 addr_prefix_disp
= -1;
7002 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7004 addr_prefix_disp
= -1;
7005 found_reverse_match
= 0;
7007 /* Must have right number of operands. */
7008 if (i
.operands
!= t
->operands
)
7011 /* Check processor support. */
7012 specific_error
= progress (unsupported
);
7013 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7016 /* Check AT&T mnemonic. */
7017 specific_error
= progress (unsupported_with_intel_mnemonic
);
7018 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7021 /* Check AT&T/Intel syntax. */
7022 specific_error
= progress (unsupported_syntax
);
7023 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7024 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7027 /* Check Intel64/AMD64 ISA. */
7031 /* Default: Don't accept Intel64. */
7032 if (t
->opcode_modifier
.isa64
== INTEL64
)
7036 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7037 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7041 /* -mintel64: Don't accept AMD64. */
7042 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7047 /* Check the suffix. */
7048 specific_error
= progress (invalid_instruction_suffix
);
7049 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7050 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7051 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7052 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7053 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7056 specific_error
= progress (operand_size_mismatch
);
7057 size_match
= operand_size_match (t
);
7061 /* This is intentionally not
7063 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7065 as the case of a missing * on the operand is accepted (perhaps with
7066 a warning, issued further down). */
7067 specific_error
= progress (operand_type_mismatch
);
7068 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7071 /* In Intel syntax, normally we can check for memory operand size when
7072 there is no mnemonic suffix. But jmp and call have 2 different
7073 encodings with Dword memory operand size. Skip the "near" one
7074 (permitting a register operand) when "far" was requested. */
7076 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7077 && t
->operand_types
[0].bitfield
.class == Reg
)
7080 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7081 operand_types
[j
] = t
->operand_types
[j
];
7083 /* In general, don't allow 32-bit operands on pre-386. */
7084 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7085 : operand_size_mismatch
);
7086 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7087 if (i
.suffix
== LONG_MNEM_SUFFIX
7088 && !cpu_arch_flags
.bitfield
.cpui386
7090 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7091 && !intel_float_operand (insn_name (t
)))
7092 : intel_float_operand (insn_name (t
)) != 2)
7093 && (t
->operands
== i
.imm_operands
7094 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7095 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7096 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7097 || (operand_types
[j
].bitfield
.class != RegMMX
7098 && operand_types
[j
].bitfield
.class != RegSIMD
7099 && operand_types
[j
].bitfield
.class != RegMask
))
7100 && !t
->opcode_modifier
.sib
)
7103 /* Do not verify operands when there are none. */
7106 if (VEX_check_encoding (t
))
7108 specific_error
= progress (i
.error
);
7112 /* We've found a match; break out of loop. */
7116 if (!t
->opcode_modifier
.jump
7117 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7119 /* There should be only one Disp operand. */
7120 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7121 if (operand_type_check (operand_types
[j
], disp
))
7123 if (j
< MAX_OPERANDS
)
7125 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7127 addr_prefix_disp
= j
;
7129 /* Address size prefix will turn Disp64 operand into Disp32 and
7130 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7134 override
= !override
;
7137 if (operand_types
[j
].bitfield
.disp32
7138 && operand_types
[j
].bitfield
.disp16
)
7140 operand_types
[j
].bitfield
.disp16
= override
;
7141 operand_types
[j
].bitfield
.disp32
= !override
;
7143 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7147 if (operand_types
[j
].bitfield
.disp64
)
7149 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7150 operand_types
[j
].bitfield
.disp32
= override
;
7151 operand_types
[j
].bitfield
.disp64
= !override
;
7153 operand_types
[j
].bitfield
.disp16
= 0;
7159 /* We check register size if needed. */
7160 if (t
->opcode_modifier
.checkoperandsize
)
7162 check_register
= (1 << t
->operands
) - 1;
7163 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7164 check_register
&= ~(1 << i
.broadcast
.operand
);
7169 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7170 switch (t
->operands
)
7173 if (!operand_type_match (overlap0
, i
.types
[0]))
7176 /* Allow the ModR/M encoding to be requested by using the {load} or
7177 {store} pseudo prefix on an applicable insn. */
7178 if (!t
->opcode_modifier
.modrm
7179 && i
.reg_operands
== 1
7180 && ((i
.dir_encoding
== dir_encoding_load
7181 && t
->mnem_off
!= MN_pop
)
7182 || (i
.dir_encoding
== dir_encoding_store
7183 && t
->mnem_off
!= MN_push
))
7185 && t
->mnem_off
!= MN_bswap
)
7190 /* xchg %eax, %eax is a special case. It is an alias for nop
7191 only in 32bit mode and we can use opcode 0x90. In 64bit
7192 mode, we can't use 0x90 for xchg %eax, %eax since it should
7193 zero-extend %eax to %rax. */
7194 if (t
->base_opcode
== 0x90
7195 && t
->opcode_space
== SPACE_BASE
)
7197 if (flag_code
== CODE_64BIT
7198 && i
.types
[0].bitfield
.instance
== Accum
7199 && i
.types
[0].bitfield
.dword
7200 && i
.types
[1].bitfield
.instance
== Accum
)
7203 /* Allow the ModR/M encoding to be requested by using the
7204 {load} or {store} pseudo prefix. */
7205 if (i
.dir_encoding
== dir_encoding_load
7206 || i
.dir_encoding
== dir_encoding_store
)
7210 if (t
->base_opcode
== MOV_AX_DISP32
7211 && t
->opcode_space
== SPACE_BASE
7212 && t
->mnem_off
!= MN_movabs
)
7214 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7215 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7218 /* xrelease mov %eax, <disp> is another special case. It must not
7219 match the accumulator-only encoding of mov. */
7223 /* Allow the ModR/M encoding to be requested by using a suitable
7224 {load} or {store} pseudo prefix. */
7225 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7226 ? dir_encoding_store
7227 : dir_encoding_load
)
7228 && !i
.types
[0].bitfield
.disp64
7229 && !i
.types
[1].bitfield
.disp64
)
7233 /* Allow the ModR/M encoding to be requested by using the {load} or
7234 {store} pseudo prefix on an applicable insn. */
7235 if (!t
->opcode_modifier
.modrm
7236 && i
.reg_operands
== 1
7237 && i
.imm_operands
== 1
7238 && (i
.dir_encoding
== dir_encoding_load
7239 || i
.dir_encoding
== dir_encoding_store
)
7240 && t
->opcode_space
== SPACE_BASE
)
7242 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7243 && i
.dir_encoding
== dir_encoding_store
)
7246 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7247 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7248 || i
.dir_encoding
== dir_encoding_load
))
7251 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7252 && i
.dir_encoding
== dir_encoding_load
)
7258 if (!(size_match
& MATCH_STRAIGHT
))
7260 /* Reverse direction of operands if swapping is possible in the first
7261 place (operands need to be symmetric) and
7262 - the load form is requested, and the template is a store form,
7263 - the store form is requested, and the template is a load form,
7264 - the non-default (swapped) form is requested. */
7265 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7266 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7267 && !operand_type_all_zero (&overlap1
))
7268 switch (i
.dir_encoding
)
7270 case dir_encoding_load
:
7271 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7272 || t
->opcode_modifier
.regmem
)
7276 case dir_encoding_store
:
7277 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7278 && !t
->opcode_modifier
.regmem
)
7282 case dir_encoding_swap
:
7285 case dir_encoding_default
:
7288 /* If we want store form, we skip the current load. */
7289 if ((i
.dir_encoding
== dir_encoding_store
7290 || i
.dir_encoding
== dir_encoding_swap
)
7291 && i
.mem_operands
== 0
7292 && t
->opcode_modifier
.load
)
7297 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7298 if (!operand_type_match (overlap0
, i
.types
[0])
7299 || !operand_type_match (overlap1
, i
.types
[1])
7300 || ((check_register
& 3) == 3
7301 && !operand_type_register_match (i
.types
[0],
7306 specific_error
= progress (i
.error
);
7308 /* Check if other direction is valid ... */
7309 if (!t
->opcode_modifier
.d
)
7313 if (!(size_match
& MATCH_REVERSE
))
7315 /* Try reversing direction of operands. */
7316 j
= is_cpu (t
, CpuFMA4
)
7317 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7318 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7319 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7320 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7321 gas_assert (t
->operands
!= 3 || !check_register
);
7322 if (!operand_type_match (overlap0
, i
.types
[0])
7323 || !operand_type_match (overlap1
, i
.types
[j
])
7324 || (t
->operands
== 3
7325 && !operand_type_match (overlap2
, i
.types
[1]))
7327 && !operand_type_register_match (i
.types
[0],
7332 /* Does not match either direction. */
7333 specific_error
= progress (i
.error
);
7336 /* found_reverse_match holds which variant of D
7338 if (!t
->opcode_modifier
.d
)
7339 found_reverse_match
= 0;
7340 else if (operand_types
[0].bitfield
.tbyte
)
7342 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7343 found_reverse_match
= Opcode_FloatD
;
7345 found_reverse_match
= ~0;
7346 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7347 if ((t
->extension_opcode
& 4)
7348 && (intel_syntax
|| intel_mnemonic
))
7349 found_reverse_match
|= Opcode_FloatR
;
7351 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7353 found_reverse_match
= Opcode_VexW
;
7354 goto check_operands_345
;
7356 else if (t
->opcode_space
!= SPACE_BASE
7357 && (t
->opcode_space
!= SPACE_0F
7358 /* MOV to/from CR/DR/TR, as an exception, follow
7359 the base opcode space encoding model. */
7360 || (t
->base_opcode
| 7) != 0x27))
7361 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7362 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7363 else if (!t
->opcode_modifier
.commutative
)
7364 found_reverse_match
= Opcode_D
;
7366 found_reverse_match
= ~0;
7370 /* Found a forward 2 operand match here. */
7372 switch (t
->operands
)
7375 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7376 if (!operand_type_match (overlap4
, i
.types
[4])
7377 || !operand_type_register_match (i
.types
[3],
7382 specific_error
= progress (i
.error
);
7387 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7388 if (!operand_type_match (overlap3
, i
.types
[3])
7389 || ((check_register
& 0xa) == 0xa
7390 && !operand_type_register_match (i
.types
[1],
7394 || ((check_register
& 0xc) == 0xc
7395 && !operand_type_register_match (i
.types
[2],
7400 specific_error
= progress (i
.error
);
7405 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7406 if (!operand_type_match (overlap2
, i
.types
[2])
7407 || ((check_register
& 5) == 5
7408 && !operand_type_register_match (i
.types
[0],
7412 || ((check_register
& 6) == 6
7413 && !operand_type_register_match (i
.types
[1],
7418 specific_error
= progress (i
.error
);
7424 /* Found either forward/reverse 2, 3 or 4 operand match here:
7425 slip through to break. */
7428 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7429 if (VEX_check_encoding (t
))
7431 specific_error
= progress (i
.error
);
7435 /* Check if vector operands are valid. */
7436 if (check_VecOperands (t
))
7438 specific_error
= progress (i
.error
);
7442 /* Check whether to use the shorter VEX encoding for certain insns where
7443 the EVEX enconding comes first in the table. This requires the respective
7444 AVX-* feature to be explicitly enabled. */
7445 if (t
== current_templates
->start
7446 && t
->opcode_modifier
.disp8memshift
7447 && !t
->opcode_modifier
.vex
7448 && !need_evex_encoding ()
7449 && t
+ 1 < current_templates
->end
7450 && t
[1].opcode_modifier
.vex
)
7453 unsigned int memshift
= i
.memshift
;
7456 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7457 if (!cpu_flags_all_zero (&cpu
)
7458 && (!i
.types
[0].bitfield
.disp8
7459 || !operand_type_check (i
.types
[0], disp
)
7460 || i
.op
[0].disps
->X_op
!= O_constant
7461 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7463 specific_error
= progress (internal_error
);
7466 i
.memshift
= memshift
;
7469 /* We've found a match; break out of loop. */
7475 if (t
== current_templates
->end
)
7477 /* We found no match. */
7478 i
.error
= specific_error
;
7482 if (!quiet_warnings
)
7485 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7486 as_warn (_("indirect %s without `*'"), insn_name (t
));
7488 if (t
->opcode_modifier
.isprefix
7489 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7491 /* Warn them that a data or address size prefix doesn't
7492 affect assembly of the next line of code. */
7493 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7497 /* Copy the template we found. */
7498 install_template (t
);
7500 if (addr_prefix_disp
!= -1)
7501 i
.tm
.operand_types
[addr_prefix_disp
]
7502 = operand_types
[addr_prefix_disp
];
7504 switch (found_reverse_match
)
7510 case Opcode_FloatR
| Opcode_FloatD
:
7511 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7512 found_reverse_match
&= Opcode_FloatD
;
7516 /* If we found a reverse match we must alter the opcode direction
7517 bit and clear/flip the regmem modifier one. found_reverse_match
7518 holds bits to change (different for int & float insns). */
7520 i
.tm
.base_opcode
^= found_reverse_match
;
7522 /* Certain SIMD insns have their load forms specified in the opcode
7523 table, and hence we need to _set_ RegMem instead of clearing it.
7524 We need to avoid setting the bit though on insns like KMOVW. */
7525 i
.tm
.opcode_modifier
.regmem
7526 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7527 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7528 && !i
.tm
.opcode_modifier
.regmem
;
7532 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7533 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7537 /* Only the first two register operands need reversing, alongside
7539 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7541 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7542 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7543 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7547 /* This pattern aims to put the unusually placed imm operand to a usual
7548 place. The constraints are currently only adapted to uwrmsr, and may
7549 need further tweaking when new similar instructions become available. */
7550 if (i
.imm_operands
&& i
.imm_operands
< i
.operands
7551 && operand_type_check (operand_types
[i
.operands
- 1], imm
))
7553 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7554 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7555 swap_2_operands(0, i
.operands
- 1);
7564 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7565 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7567 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7569 as_bad (_("`%s' operand %u must use `%ses' segment"),
7571 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7576 /* There's only ever one segment override allowed per instruction.
7577 This instruction possibly has a legal segment override on the
7578 second operand, so copy the segment to where non-string
7579 instructions store it, allowing common code. */
7580 i
.seg
[op
] = i
.seg
[1];
7586 process_suffix (void)
7588 bool is_movx
= false;
7590 /* If matched instruction specifies an explicit instruction mnemonic
7592 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7593 i
.suffix
= WORD_MNEM_SUFFIX
;
7594 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7595 i
.suffix
= LONG_MNEM_SUFFIX
;
7596 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7597 i
.suffix
= QWORD_MNEM_SUFFIX
;
7598 else if (i
.reg_operands
7599 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7600 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7602 unsigned int numop
= i
.operands
;
7605 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7606 && (i
.tm
.base_opcode
| 8) == 0xbe)
7607 || (i
.tm
.opcode_space
== SPACE_BASE
7608 && i
.tm
.base_opcode
== 0x63
7609 && is_cpu (&i
.tm
, Cpu64
));
7611 /* movsx/movzx want only their source operand considered here, for the
7612 ambiguity checking below. The suffix will be replaced afterwards
7613 to represent the destination (register). */
7614 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7617 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7618 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7621 /* If there's no instruction mnemonic suffix we try to invent one
7622 based on GPR operands. */
7625 /* We take i.suffix from the last register operand specified,
7626 Destination register type is more significant than source
7627 register type. crc32 in SSE4.2 prefers source register
7629 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7632 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7633 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7635 if (i
.types
[op
].bitfield
.class != Reg
)
7637 if (i
.types
[op
].bitfield
.byte
)
7638 i
.suffix
= BYTE_MNEM_SUFFIX
;
7639 else if (i
.types
[op
].bitfield
.word
)
7640 i
.suffix
= WORD_MNEM_SUFFIX
;
7641 else if (i
.types
[op
].bitfield
.dword
)
7642 i
.suffix
= LONG_MNEM_SUFFIX
;
7643 else if (i
.types
[op
].bitfield
.qword
)
7644 i
.suffix
= QWORD_MNEM_SUFFIX
;
7650 /* As an exception, movsx/movzx silently default to a byte source
7652 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7653 i
.suffix
= BYTE_MNEM_SUFFIX
;
7655 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7657 if (!check_byte_reg ())
7660 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7662 if (!check_long_reg ())
7665 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7667 if (!check_qword_reg ())
7670 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7672 if (!check_word_reg ())
7675 else if (intel_syntax
7676 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7677 /* Do nothing if the instruction is going to ignore the prefix. */
7682 /* Undo the movsx/movzx change done above. */
7685 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7688 i
.suffix
= stackop_size
;
7689 if (stackop_size
== LONG_MNEM_SUFFIX
)
7691 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7692 .code16gcc directive to support 16-bit mode with
7693 32-bit address. For IRET without a suffix, generate
7694 16-bit IRET (opcode 0xcf) to return from an interrupt
7696 if (i
.tm
.base_opcode
== 0xcf)
7698 i
.suffix
= WORD_MNEM_SUFFIX
;
7699 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7701 /* Warn about changed behavior for segment register push/pop. */
7702 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7703 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7708 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7709 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7710 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7711 || (i
.tm
.opcode_space
== SPACE_0F
7712 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7713 && i
.tm
.extension_opcode
<= 3)))
7718 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7720 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7721 || i
.tm
.opcode_modifier
.no_lsuf
)
7722 i
.suffix
= QWORD_MNEM_SUFFIX
;
7727 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7728 i
.suffix
= LONG_MNEM_SUFFIX
;
7731 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7732 i
.suffix
= WORD_MNEM_SUFFIX
;
7738 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7739 /* Also cover lret/retf/iret in 64-bit mode. */
7740 || (flag_code
== CODE_64BIT
7741 && !i
.tm
.opcode_modifier
.no_lsuf
7742 && !i
.tm
.opcode_modifier
.no_qsuf
))
7743 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7744 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7745 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7746 /* Accept FLDENV et al without suffix. */
7747 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7749 unsigned int suffixes
, evex
= 0;
7751 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7752 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7754 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7756 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7758 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7761 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7762 also suitable for AT&T syntax mode, it was requested that this be
7763 restricted to just Intel syntax. */
7764 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7765 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7769 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7771 if (vector_size
< VSZ512
)
7773 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7774 if (vector_size
< VSZ256
)
7776 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7777 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7778 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7779 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7781 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7782 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7783 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7784 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7786 else if (i
.tm
.opcode_modifier
.evex
7787 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7789 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7790 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7791 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7792 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7793 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7794 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7797 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7798 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7799 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7802 /* Any properly sized operand disambiguates the insn. */
7803 if (i
.types
[op
].bitfield
.xmmword
7804 || i
.types
[op
].bitfield
.ymmword
7805 || i
.types
[op
].bitfield
.zmmword
)
7807 suffixes
&= ~(7 << 6);
7812 if ((i
.flags
[op
] & Operand_Mem
)
7813 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7815 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7817 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7819 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7821 if (i
.tm
.opcode_modifier
.evex
)
7827 /* Are multiple suffixes / operand sizes allowed? */
7828 if (suffixes
& (suffixes
- 1))
7831 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7832 || operand_check
== check_error
))
7834 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7837 if (operand_check
== check_error
)
7839 as_bad (_("no instruction mnemonic suffix given and "
7840 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7843 if (operand_check
== check_warning
)
7844 as_warn (_("%s; using default for `%s'"),
7846 ? _("ambiguous operand size")
7847 : _("no instruction mnemonic suffix given and "
7848 "no register operands"),
7851 if (i
.tm
.opcode_modifier
.floatmf
)
7852 i
.suffix
= SHORT_MNEM_SUFFIX
;
7854 /* handled below */;
7856 i
.tm
.opcode_modifier
.evex
= evex
;
7857 else if (flag_code
== CODE_16BIT
)
7858 i
.suffix
= WORD_MNEM_SUFFIX
;
7859 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7860 i
.suffix
= LONG_MNEM_SUFFIX
;
7862 i
.suffix
= QWORD_MNEM_SUFFIX
;
7868 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7869 In AT&T syntax, if there is no suffix (warned about above), the default
7870 will be byte extension. */
7871 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7872 i
.tm
.base_opcode
|= 1;
7874 /* For further processing, the suffix should represent the destination
7875 (register). This is already the case when one was used with
7876 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7877 no suffix to begin with. */
7878 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7880 if (i
.types
[1].bitfield
.word
)
7881 i
.suffix
= WORD_MNEM_SUFFIX
;
7882 else if (i
.types
[1].bitfield
.qword
)
7883 i
.suffix
= QWORD_MNEM_SUFFIX
;
7885 i
.suffix
= LONG_MNEM_SUFFIX
;
7887 i
.tm
.opcode_modifier
.w
= 0;
7891 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7892 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7893 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7895 /* Change the opcode based on the operand size given by i.suffix. */
7898 /* Size floating point instruction. */
7899 case LONG_MNEM_SUFFIX
:
7900 if (i
.tm
.opcode_modifier
.floatmf
)
7902 i
.tm
.base_opcode
^= 4;
7906 case WORD_MNEM_SUFFIX
:
7907 case QWORD_MNEM_SUFFIX
:
7908 /* It's not a byte, select word/dword operation. */
7909 if (i
.tm
.opcode_modifier
.w
)
7912 i
.tm
.base_opcode
|= 8;
7914 i
.tm
.base_opcode
|= 1;
7917 case SHORT_MNEM_SUFFIX
:
7918 /* Now select between word & dword operations via the operand
7919 size prefix, except for instructions that will ignore this
7921 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7922 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7923 && !i
.tm
.opcode_modifier
.floatmf
7924 && !is_any_vex_encoding (&i
.tm
)
7925 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7926 || (flag_code
== CODE_64BIT
7927 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7929 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7931 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7932 prefix
= ADDR_PREFIX_OPCODE
;
7934 if (!add_prefix (prefix
))
7938 /* Set mode64 for an operand. */
7939 if (i
.suffix
== QWORD_MNEM_SUFFIX
7940 && flag_code
== CODE_64BIT
7941 && !i
.tm
.opcode_modifier
.norex64
7942 && !i
.tm
.opcode_modifier
.vexw
7943 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7945 && ! (i
.operands
== 2
7946 && i
.tm
.base_opcode
== 0x90
7947 && i
.tm
.opcode_space
== SPACE_BASE
7948 && i
.types
[0].bitfield
.instance
== Accum
7949 && i
.types
[0].bitfield
.qword
7950 && i
.types
[1].bitfield
.instance
== Accum
))
7956 /* Select word/dword/qword operation with explicit data sizing prefix
7957 when there are no suitable register operands. */
7958 if (i
.tm
.opcode_modifier
.w
7959 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7961 || (i
.reg_operands
== 1
7963 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7965 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7966 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7967 || i
.tm
.mnem_off
== MN_crc32
))))
7968 i
.tm
.base_opcode
|= 1;
7972 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7974 gas_assert (!i
.suffix
);
7975 gas_assert (i
.reg_operands
);
7977 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7980 /* The address size override prefix changes the size of the
7982 if (flag_code
== CODE_64BIT
7983 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7985 as_bad (_("16-bit addressing unavailable for `%s'"),
7990 if ((flag_code
== CODE_32BIT
7991 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7992 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7993 && !add_prefix (ADDR_PREFIX_OPCODE
))
7998 /* Check invalid register operand when the address size override
7999 prefix changes the size of register operands. */
8001 enum { need_word
, need_dword
, need_qword
} need
;
8003 /* Check the register operand for the address size prefix if
8004 the memory operand has no real registers, like symbol, DISP
8005 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8006 if (i
.mem_operands
== 1
8007 && i
.reg_operands
== 1
8009 && i
.types
[1].bitfield
.class == Reg
8010 && (flag_code
== CODE_32BIT
8011 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8012 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8013 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8014 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8015 || (x86_elf_abi
== X86_64_X32_ABI
8017 && i
.base_reg
->reg_num
== RegIP
8018 && i
.base_reg
->reg_type
.bitfield
.qword
))
8022 && !add_prefix (ADDR_PREFIX_OPCODE
))
8025 if (flag_code
== CODE_32BIT
)
8026 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8027 else if (i
.prefix
[ADDR_PREFIX
])
8030 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8032 for (op
= 0; op
< i
.operands
; op
++)
8034 if (i
.types
[op
].bitfield
.class != Reg
)
8040 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8044 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8048 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8053 as_bad (_("invalid register operand size for `%s'"),
8064 check_byte_reg (void)
8068 for (op
= i
.operands
; --op
>= 0;)
8070 /* Skip non-register operands. */
8071 if (i
.types
[op
].bitfield
.class != Reg
)
8074 /* If this is an eight bit register, it's OK. If it's the 16 or
8075 32 bit version of an eight bit register, we will just use the
8076 low portion, and that's OK too. */
8077 if (i
.types
[op
].bitfield
.byte
)
8080 /* I/O port address operands are OK too. */
8081 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8082 && i
.tm
.operand_types
[op
].bitfield
.word
)
8085 /* crc32 only wants its source operand checked here. */
8086 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8089 /* Any other register is bad. */
8090 as_bad (_("`%s%s' not allowed with `%s%c'"),
8091 register_prefix
, i
.op
[op
].regs
->reg_name
,
8092 insn_name (&i
.tm
), i
.suffix
);
8099 check_long_reg (void)
8103 for (op
= i
.operands
; --op
>= 0;)
8104 /* Skip non-register operands. */
8105 if (i
.types
[op
].bitfield
.class != Reg
)
8107 /* Reject eight bit registers, except where the template requires
8108 them. (eg. movzb) */
8109 else if (i
.types
[op
].bitfield
.byte
8110 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8111 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8112 && (i
.tm
.operand_types
[op
].bitfield
.word
8113 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8115 as_bad (_("`%s%s' not allowed with `%s%c'"),
8117 i
.op
[op
].regs
->reg_name
,
8122 /* Error if the e prefix on a general reg is missing. */
8123 else if (i
.types
[op
].bitfield
.word
8124 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8125 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8126 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8128 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8129 register_prefix
, i
.op
[op
].regs
->reg_name
,
8133 /* Warn if the r prefix on a general reg is present. */
8134 else if (i
.types
[op
].bitfield
.qword
8135 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8136 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8137 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8139 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8140 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8147 check_qword_reg (void)
8151 for (op
= i
.operands
; --op
>= 0; )
8152 /* Skip non-register operands. */
8153 if (i
.types
[op
].bitfield
.class != Reg
)
8155 /* Reject eight bit registers, except where the template requires
8156 them. (eg. movzb) */
8157 else if (i
.types
[op
].bitfield
.byte
8158 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8159 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8160 && (i
.tm
.operand_types
[op
].bitfield
.word
8161 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8163 as_bad (_("`%s%s' not allowed with `%s%c'"),
8165 i
.op
[op
].regs
->reg_name
,
8170 /* Warn if the r prefix on a general reg is missing. */
8171 else if ((i
.types
[op
].bitfield
.word
8172 || i
.types
[op
].bitfield
.dword
)
8173 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8174 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8175 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8177 /* Prohibit these changes in the 64bit mode, since the
8178 lowering is more complicated. */
8179 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8180 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8187 check_word_reg (void)
8190 for (op
= i
.operands
; --op
>= 0;)
8191 /* Skip non-register operands. */
8192 if (i
.types
[op
].bitfield
.class != Reg
)
8194 /* Reject eight bit registers, except where the template requires
8195 them. (eg. movzb) */
8196 else if (i
.types
[op
].bitfield
.byte
8197 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8198 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8199 && (i
.tm
.operand_types
[op
].bitfield
.word
8200 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8202 as_bad (_("`%s%s' not allowed with `%s%c'"),
8204 i
.op
[op
].regs
->reg_name
,
8209 /* Error if the e or r prefix on a general reg is present. */
8210 else if ((i
.types
[op
].bitfield
.dword
8211 || i
.types
[op
].bitfield
.qword
)
8212 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8213 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8214 && i
.tm
.operand_types
[op
].bitfield
.word
)
8216 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8217 register_prefix
, i
.op
[op
].regs
->reg_name
,
8225 update_imm (unsigned int j
)
8227 i386_operand_type overlap
= i
.types
[j
];
8229 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8230 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8231 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8233 /* This combination is used on 8-bit immediates where e.g. $~0 is
8234 desirable to permit. We're past operand type matching, so simply
8235 put things back in the shape they were before introducing the
8236 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8237 overlap
.bitfield
.imm8s
= 0;
8240 if (overlap
.bitfield
.imm8
8241 + overlap
.bitfield
.imm8s
8242 + overlap
.bitfield
.imm16
8243 + overlap
.bitfield
.imm32
8244 + overlap
.bitfield
.imm32s
8245 + overlap
.bitfield
.imm64
> 1)
8247 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8248 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8249 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8250 static const i386_operand_type imm16_32
= { .bitfield
=
8251 { .imm16
= 1, .imm32
= 1 }
8253 static const i386_operand_type imm16_32s
= { .bitfield
=
8254 { .imm16
= 1, .imm32s
= 1 }
8256 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8257 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8262 i386_operand_type temp
;
8264 operand_type_set (&temp
, 0);
8265 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8267 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8268 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8270 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8271 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8272 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8274 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8275 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8278 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8281 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8282 || operand_type_equal (&overlap
, &imm16_32
)
8283 || operand_type_equal (&overlap
, &imm16_32s
))
8285 if ((flag_code
== CODE_16BIT
)
8286 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8291 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8292 overlap
= operand_type_and (overlap
, imm32s
);
8293 else if (i
.prefix
[DATA_PREFIX
])
8294 overlap
= operand_type_and (overlap
,
8295 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8296 if (overlap
.bitfield
.imm8
8297 + overlap
.bitfield
.imm8s
8298 + overlap
.bitfield
.imm16
8299 + overlap
.bitfield
.imm32
8300 + overlap
.bitfield
.imm32s
8301 + overlap
.bitfield
.imm64
!= 1)
8303 as_bad (_("no instruction mnemonic suffix given; "
8304 "can't determine immediate size"));
8308 i
.types
[j
] = overlap
;
8318 /* Update the first 2 immediate operands. */
8319 n
= i
.operands
> 2 ? 2 : i
.operands
;
8322 for (j
= 0; j
< n
; j
++)
8323 if (update_imm (j
) == 0)
8326 /* The 3rd operand can't be immediate operand. */
8327 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8333 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8336 if (r
->reg_flags
& RegRex
)
8338 if (i
.rex
& rex_bit
)
8339 as_bad (_("same type of prefix used twice"));
8342 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8344 gas_assert (i
.vex
.register_specifier
== r
);
8345 i
.vex
.register_specifier
+= 8;
8348 if (r
->reg_flags
& RegVRex
)
8353 process_operands (void)
8355 /* Default segment register this instruction will use for memory
8356 accesses. 0 means unknown. This is only for optimizing out
8357 unnecessary segment overrides. */
8358 const reg_entry
*default_seg
= NULL
;
8360 /* We only need to check those implicit registers for instructions
8361 with 3 operands or less. */
8362 if (i
.operands
<= 3)
8363 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8364 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8367 if (i
.tm
.opcode_modifier
.sse2avx
)
8369 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8371 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8372 i
.prefix
[REX_PREFIX
] = 0;
8375 /* ImmExt should be processed after SSE2AVX. */
8376 else if (i
.tm
.opcode_modifier
.immext
)
8379 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8380 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8381 new destination operand here, while converting the source one to register
8383 if (i
.tm
.mnem_off
== MN_tilezero
)
8385 i
.op
[1].regs
= i
.op
[0].regs
;
8386 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8387 i
.types
[1] = i
.types
[0];
8388 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8389 i
.flags
[1] = i
.flags
[0];
8395 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8397 static const i386_operand_type regxmm
= {
8398 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8400 unsigned int dupl
= i
.operands
;
8401 unsigned int dest
= dupl
- 1;
8404 /* The destination must be an xmm register. */
8405 gas_assert (i
.reg_operands
8406 && MAX_OPERANDS
> dupl
8407 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8409 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8410 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8412 /* Keep xmm0 for instructions with VEX prefix and 3
8414 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8415 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8420 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8422 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8424 /* Add the implicit xmm0 for instructions with VEX prefix
8426 for (j
= i
.operands
; j
> 0; j
--)
8428 i
.op
[j
] = i
.op
[j
- 1];
8429 i
.types
[j
] = i
.types
[j
- 1];
8430 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8431 i
.flags
[j
] = i
.flags
[j
- 1];
8434 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8435 i
.types
[0] = regxmm
;
8436 i
.tm
.operand_types
[0] = regxmm
;
8439 i
.reg_operands
+= 2;
8444 i
.op
[dupl
] = i
.op
[dest
];
8445 i
.types
[dupl
] = i
.types
[dest
];
8446 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8447 i
.flags
[dupl
] = i
.flags
[dest
];
8456 i
.op
[dupl
] = i
.op
[dest
];
8457 i
.types
[dupl
] = i
.types
[dest
];
8458 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8459 i
.flags
[dupl
] = i
.flags
[dest
];
8462 if (i
.tm
.opcode_modifier
.immext
)
8465 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8466 && i
.tm
.opcode_modifier
.modrm
)
8470 for (j
= 1; j
< i
.operands
; j
++)
8472 i
.op
[j
- 1] = i
.op
[j
];
8473 i
.types
[j
- 1] = i
.types
[j
];
8475 /* We need to adjust fields in i.tm since they are used by
8476 build_modrm_byte. */
8477 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8479 i
.flags
[j
- 1] = i
.flags
[j
];
8482 /* No adjustment to i.reg_operands: This was already done at the top
8487 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8489 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8491 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8492 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8493 regnum
= register_number (i
.op
[1].regs
);
8494 first_reg_in_group
= regnum
& ~3;
8495 last_reg_in_group
= first_reg_in_group
+ 3;
8496 if (regnum
!= first_reg_in_group
)
8497 as_warn (_("source register `%s%s' implicitly denotes"
8498 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8499 register_prefix
, i
.op
[1].regs
->reg_name
,
8500 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8501 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8504 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8506 /* The imul $imm, %reg instruction is converted into
8507 imul $imm, %reg, %reg, and the clr %reg instruction
8508 is converted into xor %reg, %reg. */
8510 unsigned int first_reg_op
;
8512 if (operand_type_check (i
.types
[0], reg
))
8516 /* Pretend we saw the extra register operand. */
8517 gas_assert (i
.reg_operands
== 1
8518 && i
.op
[first_reg_op
+ 1].regs
== 0);
8519 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8520 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8525 if (i
.tm
.opcode_modifier
.modrm
)
8527 /* The opcode is completed (modulo i.tm.extension_opcode which
8528 must be put into the modrm byte). Now, we make the modrm and
8529 index base bytes based on all the info we've collected. */
8531 default_seg
= build_modrm_byte ();
8533 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8535 /* Warn about some common errors, but press on regardless. */
8536 if (i
.operands
== 2)
8538 /* Reversed arguments on faddp or fmulp. */
8539 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8540 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8541 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8543 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8545 /* Extraneous `l' suffix on fp insn. */
8546 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8547 register_prefix
, i
.op
[0].regs
->reg_name
);
8551 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8553 if (flag_code
!= CODE_64BIT
8554 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8555 && i
.op
[0].regs
->reg_num
== 1
8556 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8557 && i
.op
[0].regs
->reg_num
< 4)
8559 as_bad (_("you can't `%s %s%s'"),
8560 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8563 if (i
.op
[0].regs
->reg_num
> 3
8564 && i
.tm
.opcode_space
== SPACE_BASE
)
8566 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8567 i
.tm
.opcode_space
= SPACE_0F
;
8569 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8571 else if (i
.tm
.opcode_space
== SPACE_BASE
8572 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8574 default_seg
= reg_ds
;
8576 else if (i
.tm
.opcode_modifier
.isstring
)
8578 /* For the string instructions that allow a segment override
8579 on one of their operands, the default segment is ds. */
8580 default_seg
= reg_ds
;
8582 else if (i
.short_form
)
8584 /* The register operand is in the 1st or 2nd non-immediate operand. */
8585 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8588 && r
->reg_type
.bitfield
.instance
== Accum
8589 && i
.op
[i
.imm_operands
+ 1].regs
)
8590 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8591 /* Register goes in low 3 bits of opcode. */
8592 i
.tm
.base_opcode
|= r
->reg_num
;
8593 set_rex_vrex (r
, REX_B
, false);
8595 if (dot_insn () && i
.reg_operands
== 2)
8597 gas_assert (is_any_vex_encoding (&i
.tm
)
8598 || i
.vec_encoding
!= vex_encoding_default
);
8599 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8602 else if (i
.reg_operands
== 1
8603 && !i
.flags
[i
.operands
- 1]
8604 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8607 gas_assert (is_any_vex_encoding (&i
.tm
)
8608 || i
.vec_encoding
!= vex_encoding_default
);
8609 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8612 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8613 && i
.tm
.mnem_off
== MN_lea
)
8615 if (!quiet_warnings
)
8616 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8617 if (optimize
&& !i
.no_optimize
)
8620 i
.prefix
[SEG_PREFIX
] = 0;
8624 /* If a segment was explicitly specified, and the specified segment
8625 is neither the default nor the one already recorded from a prefix,
8626 use an opcode prefix to select it. If we never figured out what
8627 the default segment is, then default_seg will be zero at this
8628 point, and the specified segment prefix will always be used. */
8630 && i
.seg
[0] != default_seg
8631 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8633 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8639 static const reg_entry
*
8640 build_modrm_byte (void)
8642 const reg_entry
*default_seg
= NULL
;
8643 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8644 /* Compensate for kludge in md_assemble(). */
8645 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8646 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8647 unsigned int v
, op
, reg_slot
= ~0;
8649 /* Accumulator (in particular %st), shift count (%cl), and alike need
8650 to be skipped just like immediate operands do. */
8651 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8653 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8656 for (op
= source
; op
< i
.operands
; ++op
)
8657 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8660 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8664 /* There are 2 kinds of instructions:
8665 1. 5 operands: 4 register operands or 3 register operands
8666 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8667 VexW0 or VexW1. The destination must be either XMM, YMM or
8669 2. 4 operands: 4 register operands or 3 register operands
8670 plus 1 memory operand, with VexXDS.
8671 3. Other equivalent combinations when coming from s_insn(). */
8672 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8673 && i
.tm
.opcode_modifier
.vexw
);
8674 gas_assert (dot_insn ()
8675 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8677 /* Of the first two non-immediate operands the one with the template
8678 not allowing for a memory one is encoded in the immediate operand. */
8680 reg_slot
= source
+ 1;
8682 reg_slot
= source
++;
8686 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8687 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8690 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8692 if (i
.imm_operands
== 0)
8694 /* When there is no immediate operand, generate an 8bit
8695 immediate operand to encode the first operand. */
8696 exp
= &im_expressions
[i
.imm_operands
++];
8697 i
.op
[i
.operands
].imms
= exp
;
8698 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8701 exp
->X_op
= O_constant
;
8705 gas_assert (i
.imm_operands
== 1);
8706 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8707 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8709 /* Turn on Imm8 again so that output_imm will generate it. */
8710 i
.types
[0].bitfield
.imm8
= 1;
8714 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8715 << (3 + !(i
.tm
.opcode_modifier
.evex
8716 || i
.vec_encoding
== vex_encoding_evex
));
8719 for (v
= source
+ 1; v
< dest
; ++v
)
8724 if (i
.tm
.extension_opcode
!= None
)
8730 gas_assert (source
< dest
);
8731 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8734 unsigned int tmp
= source
;
8740 if (v
< MAX_OPERANDS
)
8742 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8743 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8746 if (op
< i
.operands
)
8750 unsigned int fake_zero_displacement
= 0;
8752 gas_assert (i
.flags
[op
] & Operand_Mem
);
8754 if (i
.tm
.opcode_modifier
.sib
)
8756 /* The index register of VSIB shouldn't be RegIZ. */
8757 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8758 && i
.index_reg
->reg_num
== RegIZ
)
8761 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8764 i
.sib
.base
= NO_BASE_REGISTER
;
8765 i
.sib
.scale
= i
.log2_scale_factor
;
8766 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8767 i
.types
[op
].bitfield
.disp32
= 1;
8770 /* Since the mandatory SIB always has index register, so
8771 the code logic remains unchanged. The non-mandatory SIB
8772 without index register is allowed and will be handled
8776 if (i
.index_reg
->reg_num
== RegIZ
)
8777 i
.sib
.index
= NO_INDEX_REGISTER
;
8779 i
.sib
.index
= i
.index_reg
->reg_num
;
8780 set_rex_vrex (i
.index_reg
, REX_X
, false);
8784 default_seg
= reg_ds
;
8786 if (i
.base_reg
== 0)
8789 if (!i
.disp_operands
)
8790 fake_zero_displacement
= 1;
8791 if (i
.index_reg
== 0)
8793 /* Both check for VSIB and mandatory non-vector SIB. */
8794 gas_assert (!i
.tm
.opcode_modifier
.sib
8795 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8796 /* Operand is just <disp> */
8797 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8798 if (flag_code
== CODE_64BIT
)
8800 /* 64bit mode overwrites the 32bit absolute
8801 addressing by RIP relative addressing and
8802 absolute addressing is encoded by one of the
8803 redundant SIB forms. */
8804 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8805 i
.sib
.base
= NO_BASE_REGISTER
;
8806 i
.sib
.index
= NO_INDEX_REGISTER
;
8807 i
.types
[op
].bitfield
.disp32
= 1;
8809 else if ((flag_code
== CODE_16BIT
)
8810 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8812 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8813 i
.types
[op
].bitfield
.disp16
= 1;
8817 i
.rm
.regmem
= NO_BASE_REGISTER
;
8818 i
.types
[op
].bitfield
.disp32
= 1;
8821 else if (!i
.tm
.opcode_modifier
.sib
)
8823 /* !i.base_reg && i.index_reg */
8824 if (i
.index_reg
->reg_num
== RegIZ
)
8825 i
.sib
.index
= NO_INDEX_REGISTER
;
8827 i
.sib
.index
= i
.index_reg
->reg_num
;
8828 i
.sib
.base
= NO_BASE_REGISTER
;
8829 i
.sib
.scale
= i
.log2_scale_factor
;
8830 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8831 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8832 i
.types
[op
].bitfield
.disp32
= 1;
8833 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8837 /* RIP addressing for 64bit mode. */
8838 else if (i
.base_reg
->reg_num
== RegIP
)
8840 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8841 i
.rm
.regmem
= NO_BASE_REGISTER
;
8842 i
.types
[op
].bitfield
.disp8
= 0;
8843 i
.types
[op
].bitfield
.disp16
= 0;
8844 i
.types
[op
].bitfield
.disp32
= 1;
8845 i
.types
[op
].bitfield
.disp64
= 0;
8846 i
.flags
[op
] |= Operand_PCrel
;
8847 if (! i
.disp_operands
)
8848 fake_zero_displacement
= 1;
8850 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8852 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8853 switch (i
.base_reg
->reg_num
)
8856 if (i
.index_reg
== 0)
8858 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8859 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8862 default_seg
= reg_ss
;
8863 if (i
.index_reg
== 0)
8866 if (operand_type_check (i
.types
[op
], disp
) == 0)
8868 /* fake (%bp) into 0(%bp) */
8869 if (i
.disp_encoding
== disp_encoding_16bit
)
8870 i
.types
[op
].bitfield
.disp16
= 1;
8872 i
.types
[op
].bitfield
.disp8
= 1;
8873 fake_zero_displacement
= 1;
8876 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8877 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8879 default: /* (%si) -> 4 or (%di) -> 5 */
8880 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8882 if (!fake_zero_displacement
8886 fake_zero_displacement
= 1;
8887 if (i
.disp_encoding
== disp_encoding_8bit
)
8888 i
.types
[op
].bitfield
.disp8
= 1;
8890 i
.types
[op
].bitfield
.disp16
= 1;
8892 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8894 else /* i.base_reg and 32/64 bit mode */
8896 if (operand_type_check (i
.types
[op
], disp
))
8898 i
.types
[op
].bitfield
.disp16
= 0;
8899 i
.types
[op
].bitfield
.disp64
= 0;
8900 i
.types
[op
].bitfield
.disp32
= 1;
8903 if (!i
.tm
.opcode_modifier
.sib
)
8904 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8905 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8907 i
.sib
.base
= i
.base_reg
->reg_num
;
8908 /* x86-64 ignores REX prefix bit here to avoid decoder
8910 if (!(i
.base_reg
->reg_flags
& RegRex
)
8911 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8912 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8913 default_seg
= reg_ss
;
8914 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8916 fake_zero_displacement
= 1;
8917 if (i
.disp_encoding
== disp_encoding_32bit
)
8918 i
.types
[op
].bitfield
.disp32
= 1;
8920 i
.types
[op
].bitfield
.disp8
= 1;
8922 i
.sib
.scale
= i
.log2_scale_factor
;
8923 if (i
.index_reg
== 0)
8925 /* Only check for VSIB. */
8926 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8927 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8928 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8930 /* <disp>(%esp) becomes two byte modrm with no index
8931 register. We've already stored the code for esp
8932 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8933 Any base register besides %esp will not use the
8934 extra modrm byte. */
8935 i
.sib
.index
= NO_INDEX_REGISTER
;
8937 else if (!i
.tm
.opcode_modifier
.sib
)
8939 if (i
.index_reg
->reg_num
== RegIZ
)
8940 i
.sib
.index
= NO_INDEX_REGISTER
;
8942 i
.sib
.index
= i
.index_reg
->reg_num
;
8943 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8944 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8949 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8950 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8954 if (!fake_zero_displacement
8958 fake_zero_displacement
= 1;
8959 if (i
.disp_encoding
== disp_encoding_8bit
)
8960 i
.types
[op
].bitfield
.disp8
= 1;
8962 i
.types
[op
].bitfield
.disp32
= 1;
8964 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8968 if (fake_zero_displacement
)
8970 /* Fakes a zero displacement assuming that i.types[op]
8971 holds the correct displacement size. */
8974 gas_assert (i
.op
[op
].disps
== 0);
8975 exp
= &disp_expressions
[i
.disp_operands
++];
8976 i
.op
[op
].disps
= exp
;
8977 exp
->X_op
= O_constant
;
8978 exp
->X_add_number
= 0;
8979 exp
->X_add_symbol
= (symbolS
*) 0;
8980 exp
->X_op_symbol
= (symbolS
*) 0;
8986 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8987 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8998 if (!i
.tm
.opcode_modifier
.regmem
)
9000 gas_assert (source
< MAX_OPERANDS
);
9001 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9002 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9003 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9008 gas_assert (dest
< MAX_OPERANDS
);
9009 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9010 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9015 /* Fill in i.rm.reg field with extension opcode (if any) or the
9016 appropriate register. */
9017 if (i
.tm
.extension_opcode
!= None
)
9018 i
.rm
.reg
= i
.tm
.extension_opcode
;
9019 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9021 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9022 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9026 gas_assert (source
< MAX_OPERANDS
);
9027 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9028 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9031 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9033 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9035 add_prefix (LOCK_PREFIX_OPCODE
);
9042 frag_opcode_byte (unsigned char byte
)
9044 if (now_seg
!= absolute_section
)
9045 FRAG_APPEND_1_CHAR (byte
);
9047 ++abs_section_offset
;
9051 flip_code16 (unsigned int code16
)
9053 gas_assert (i
.tm
.operands
== 1);
9055 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9056 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9057 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9062 output_branch (void)
9068 relax_substateT subtype
;
9072 if (now_seg
== absolute_section
)
9074 as_bad (_("relaxable branches not supported in absolute section"));
9078 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9079 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9082 if (i
.prefix
[DATA_PREFIX
] != 0)
9086 code16
^= flip_code16(code16
);
9088 /* Pentium4 branch hints. */
9089 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9090 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9095 if (i
.prefix
[REX_PREFIX
] != 0)
9101 /* BND prefixed jump. */
9102 if (i
.prefix
[BND_PREFIX
] != 0)
9108 if (i
.prefixes
!= 0)
9109 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9111 /* It's always a symbol; End frag & setup for relax.
9112 Make sure there is enough room in this frag for the largest
9113 instruction we may generate in md_convert_frag. This is 2
9114 bytes for the opcode and room for the prefix and largest
9116 frag_grow (prefix
+ 2 + 4);
9117 /* Prefix and 1 opcode byte go in fr_fix. */
9118 p
= frag_more (prefix
+ 1);
9119 if (i
.prefix
[DATA_PREFIX
] != 0)
9120 *p
++ = DATA_PREFIX_OPCODE
;
9121 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9122 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9123 *p
++ = i
.prefix
[SEG_PREFIX
];
9124 if (i
.prefix
[BND_PREFIX
] != 0)
9125 *p
++ = BND_PREFIX_OPCODE
;
9126 if (i
.prefix
[REX_PREFIX
] != 0)
9127 *p
++ = i
.prefix
[REX_PREFIX
];
9128 *p
= i
.tm
.base_opcode
;
9130 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9131 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9132 else if (cpu_arch_flags
.bitfield
.cpui386
)
9133 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9135 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9138 sym
= i
.op
[0].disps
->X_add_symbol
;
9139 off
= i
.op
[0].disps
->X_add_number
;
9141 if (i
.op
[0].disps
->X_op
!= O_constant
9142 && i
.op
[0].disps
->X_op
!= O_symbol
)
9144 /* Handle complex expressions. */
9145 sym
= make_expr_symbol (i
.op
[0].disps
);
9149 /* 1 possible extra opcode + 4 byte displacement go in var part.
9150 Pass reloc in fr_var. */
9151 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9155 /* Return TRUE iff PLT32 relocation should be used for branching to
9159 need_plt32_p (symbolS
*s
)
9161 /* PLT32 relocation is ELF only. */
9166 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9167 krtld support it. */
9171 /* Since there is no need to prepare for PLT branch on x86-64, we
9172 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9173 be used as a marker for 32-bit PC-relative branches. */
9180 /* Weak or undefined symbol need PLT32 relocation. */
9181 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9184 /* Non-global symbol doesn't need PLT32 relocation. */
9185 if (! S_IS_EXTERNAL (s
))
9188 /* Other global symbols need PLT32 relocation. NB: Symbol with
9189 non-default visibilities are treated as normal global symbol
9190 so that PLT32 relocation can be used as a marker for 32-bit
9191 PC-relative branches. It is useful for linker relaxation. */
9202 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9204 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9206 /* This is a loop or jecxz type instruction. */
9208 if (i
.prefix
[ADDR_PREFIX
] != 0)
9210 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9213 /* Pentium4 branch hints. */
9214 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9215 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9217 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9226 if (flag_code
== CODE_16BIT
)
9229 if (i
.prefix
[DATA_PREFIX
] != 0)
9231 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9233 code16
^= flip_code16(code16
);
9241 /* BND prefixed jump. */
9242 if (i
.prefix
[BND_PREFIX
] != 0)
9244 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9248 if (i
.prefix
[REX_PREFIX
] != 0)
9250 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9254 if (i
.prefixes
!= 0)
9255 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9257 if (now_seg
== absolute_section
)
9259 abs_section_offset
+= i
.opcode_length
+ size
;
9263 p
= frag_more (i
.opcode_length
+ size
);
9264 switch (i
.opcode_length
)
9267 *p
++ = i
.tm
.base_opcode
>> 8;
9270 *p
++ = i
.tm
.base_opcode
;
9276 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9277 if (flag_code
== CODE_64BIT
&& size
== 4
9278 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9279 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9280 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9283 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9285 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9286 i
.op
[0].disps
, 1, jump_reloc
);
9288 /* All jumps handled here are signed, but don't unconditionally use a
9289 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9290 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9295 fixP
->fx_signed
= 1;
9299 if (i
.tm
.mnem_off
== MN_xbegin
)
9300 fixP
->fx_signed
= 1;
9304 if (flag_code
== CODE_64BIT
)
9305 fixP
->fx_signed
= 1;
9311 output_interseg_jump (void)
9319 if (flag_code
== CODE_16BIT
)
9323 if (i
.prefix
[DATA_PREFIX
] != 0)
9330 gas_assert (!i
.prefix
[REX_PREFIX
]);
9336 if (i
.prefixes
!= 0)
9337 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9339 if (now_seg
== absolute_section
)
9341 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9345 /* 1 opcode; 2 segment; offset */
9346 p
= frag_more (prefix
+ 1 + 2 + size
);
9348 if (i
.prefix
[DATA_PREFIX
] != 0)
9349 *p
++ = DATA_PREFIX_OPCODE
;
9351 if (i
.prefix
[REX_PREFIX
] != 0)
9352 *p
++ = i
.prefix
[REX_PREFIX
];
9354 *p
++ = i
.tm
.base_opcode
;
9355 if (i
.op
[1].imms
->X_op
== O_constant
)
9357 offsetT n
= i
.op
[1].imms
->X_add_number
;
9360 && !fits_in_unsigned_word (n
)
9361 && !fits_in_signed_word (n
))
9363 as_bad (_("16-bit jump out of range"));
9366 md_number_to_chars (p
, n
, size
);
9369 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9370 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9373 if (i
.op
[0].imms
->X_op
== O_constant
)
9374 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9376 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9377 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9380 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9385 asection
*seg
= now_seg
;
9386 subsegT subseg
= now_subseg
;
9388 unsigned int alignment
, align_size_1
;
9389 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9390 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9391 unsigned int padding
;
9393 if (!IS_ELF
|| !x86_used_note
)
9396 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9398 /* The .note.gnu.property section layout:
9400 Field Length Contents
9403 n_descsz 4 The note descriptor size
9404 n_type 4 NT_GNU_PROPERTY_TYPE_0
9406 n_desc n_descsz The program property array
9410 /* Create the .note.gnu.property section. */
9411 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9412 bfd_set_section_flags (sec
,
9419 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9430 bfd_set_section_alignment (sec
, alignment
);
9431 elf_section_type (sec
) = SHT_NOTE
;
9433 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9435 isa_1_descsz_raw
= 4 + 4 + 4;
9436 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9437 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9439 feature_2_descsz_raw
= isa_1_descsz
;
9440 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9442 feature_2_descsz_raw
+= 4 + 4 + 4;
9443 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9444 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9447 descsz
= feature_2_descsz
;
9448 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9449 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9451 /* Write n_namsz. */
9452 md_number_to_chars (p
, (valueT
) 4, 4);
9454 /* Write n_descsz. */
9455 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9458 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9461 memcpy (p
+ 4 * 3, "GNU", 4);
9463 /* Write 4-byte type. */
9464 md_number_to_chars (p
+ 4 * 4,
9465 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9467 /* Write 4-byte data size. */
9468 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9470 /* Write 4-byte data. */
9471 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9473 /* Zero out paddings. */
9474 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9476 memset (p
+ 4 * 7, 0, padding
);
9478 /* Write 4-byte type. */
9479 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9480 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9482 /* Write 4-byte data size. */
9483 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9485 /* Write 4-byte data. */
9486 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9487 (valueT
) x86_feature_2_used
, 4);
9489 /* Zero out paddings. */
9490 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9492 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9494 /* We probably can't restore the current segment, for there likely
9497 subseg_set (seg
, subseg
);
9501 x86_support_sframe_p (void)
9503 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9504 return (x86_elf_abi
== X86_64_ABI
);
9508 x86_sframe_ra_tracking_p (void)
9510 /* In AMD64, return address is always stored on the stack at a fixed offset
9511 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9512 Do not track explicitly via an SFrame Frame Row Entry. */
9517 x86_sframe_cfa_ra_offset (void)
9519 gas_assert (x86_elf_abi
== X86_64_ABI
);
9520 return (offsetT
) -8;
9524 x86_sframe_get_abi_arch (void)
9526 unsigned char sframe_abi_arch
= 0;
9528 if (x86_support_sframe_p ())
9530 gas_assert (!target_big_endian
);
9531 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9534 return sframe_abi_arch
;
9540 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9541 const char *frag_now_ptr
)
9543 unsigned int len
= 0;
9545 if (start_frag
!= frag_now
)
9547 const fragS
*fr
= start_frag
;
9552 } while (fr
&& fr
!= frag_now
);
9555 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9558 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9559 be macro-fused with conditional jumps.
9560 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9561 or is one of the following format:
9574 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9576 /* No RIP address. */
9577 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9580 /* No opcodes outside of base encoding space. */
9581 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9584 /* add, sub without add/sub m, imm. */
9585 if (i
.tm
.base_opcode
<= 5
9586 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9587 || ((i
.tm
.base_opcode
| 3) == 0x83
9588 && (i
.tm
.extension_opcode
== 0x5
9589 || i
.tm
.extension_opcode
== 0x0)))
9591 *mf_cmp_p
= mf_cmp_alu_cmp
;
9592 return !(i
.mem_operands
&& i
.imm_operands
);
9595 /* and without and m, imm. */
9596 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9597 || ((i
.tm
.base_opcode
| 3) == 0x83
9598 && i
.tm
.extension_opcode
== 0x4))
9600 *mf_cmp_p
= mf_cmp_test_and
;
9601 return !(i
.mem_operands
&& i
.imm_operands
);
9604 /* test without test m imm. */
9605 if ((i
.tm
.base_opcode
| 1) == 0x85
9606 || (i
.tm
.base_opcode
| 1) == 0xa9
9607 || ((i
.tm
.base_opcode
| 1) == 0xf7
9608 && i
.tm
.extension_opcode
== 0))
9610 *mf_cmp_p
= mf_cmp_test_and
;
9611 return !(i
.mem_operands
&& i
.imm_operands
);
9614 /* cmp without cmp m, imm. */
9615 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9616 || ((i
.tm
.base_opcode
| 3) == 0x83
9617 && (i
.tm
.extension_opcode
== 0x7)))
9619 *mf_cmp_p
= mf_cmp_alu_cmp
;
9620 return !(i
.mem_operands
&& i
.imm_operands
);
9623 /* inc, dec without inc/dec m. */
9624 if ((is_cpu (&i
.tm
, CpuNo64
)
9625 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9626 || ((i
.tm
.base_opcode
| 1) == 0xff
9627 && i
.tm
.extension_opcode
<= 0x1))
9629 *mf_cmp_p
= mf_cmp_incdec
;
9630 return !i
.mem_operands
;
9636 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9639 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9641 /* NB: Don't work with COND_JUMP86 without i386. */
9642 if (!align_branch_power
9643 || now_seg
== absolute_section
9644 || !cpu_arch_flags
.bitfield
.cpui386
9645 || !(align_branch
& align_branch_fused_bit
))
9648 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9650 if (last_insn
.kind
== last_insn_other
9651 || last_insn
.seg
!= now_seg
)
9654 as_warn_where (last_insn
.file
, last_insn
.line
,
9655 _("`%s` skips -malign-branch-boundary on `%s`"),
9656 last_insn
.name
, insn_name (&i
.tm
));
9662 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9665 add_branch_prefix_frag_p (void)
9667 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9668 to PadLock instructions since they include prefixes in opcode. */
9669 if (!align_branch_power
9670 || !align_branch_prefix_size
9671 || now_seg
== absolute_section
9672 || is_cpu (&i
.tm
, CpuPadLock
)
9673 || !cpu_arch_flags
.bitfield
.cpui386
)
9676 /* Don't add prefix if it is a prefix or there is no operand in case
9677 that segment prefix is special. */
9678 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9681 if (last_insn
.kind
== last_insn_other
9682 || last_insn
.seg
!= now_seg
)
9686 as_warn_where (last_insn
.file
, last_insn
.line
,
9687 _("`%s` skips -malign-branch-boundary on `%s`"),
9688 last_insn
.name
, insn_name (&i
.tm
));
9693 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9696 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9697 enum mf_jcc_kind
*mf_jcc_p
)
9701 /* NB: Don't work with COND_JUMP86 without i386. */
9702 if (!align_branch_power
9703 || now_seg
== absolute_section
9704 || !cpu_arch_flags
.bitfield
.cpui386
9705 || i
.tm
.opcode_space
!= SPACE_BASE
)
9710 /* Check for jcc and direct jmp. */
9711 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9713 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9715 *branch_p
= align_branch_jmp
;
9716 add_padding
= align_branch
& align_branch_jmp_bit
;
9720 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9721 igore the lowest bit. */
9722 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9723 *branch_p
= align_branch_jcc
;
9724 if ((align_branch
& align_branch_jcc_bit
))
9728 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9731 *branch_p
= align_branch_ret
;
9732 if ((align_branch
& align_branch_ret_bit
))
9737 /* Check for indirect jmp, direct and indirect calls. */
9738 if (i
.tm
.base_opcode
== 0xe8)
9741 *branch_p
= align_branch_call
;
9742 if ((align_branch
& align_branch_call_bit
))
9745 else if (i
.tm
.base_opcode
== 0xff
9746 && (i
.tm
.extension_opcode
== 2
9747 || i
.tm
.extension_opcode
== 4))
9749 /* Indirect call and jmp. */
9750 *branch_p
= align_branch_indirect
;
9751 if ((align_branch
& align_branch_indirect_bit
))
9758 && (i
.op
[0].disps
->X_op
== O_symbol
9759 || (i
.op
[0].disps
->X_op
== O_subtract
9760 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9762 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9763 /* No padding to call to global or undefined tls_get_addr. */
9764 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9765 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9771 && last_insn
.kind
!= last_insn_other
9772 && last_insn
.seg
== now_seg
)
9775 as_warn_where (last_insn
.file
, last_insn
.line
,
9776 _("`%s` skips -malign-branch-boundary on `%s`"),
9777 last_insn
.name
, insn_name (&i
.tm
));
9787 fragS
*insn_start_frag
;
9788 offsetT insn_start_off
;
9789 fragS
*fragP
= NULL
;
9790 enum align_branch_kind branch
= align_branch_none
;
9791 /* The initializer is arbitrary just to avoid uninitialized error.
9792 it's actually either assigned in add_branch_padding_frag_p
9793 or never be used. */
9794 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9797 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9799 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9800 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9801 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9803 if (is_cpu (&i
.tm
, Cpu8087
)
9804 || is_cpu (&i
.tm
, Cpu287
)
9805 || is_cpu (&i
.tm
, Cpu387
)
9806 || is_cpu (&i
.tm
, Cpu687
)
9807 || is_cpu (&i
.tm
, CpuFISTTP
))
9808 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9810 if ((i
.xstate
& xstate_mmx
)
9811 || i
.tm
.mnem_off
== MN_emms
9812 || i
.tm
.mnem_off
== MN_femms
)
9813 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9817 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9818 i
.xstate
|= xstate_zmm
;
9819 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9820 i
.xstate
|= xstate_ymm
;
9821 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9822 i
.xstate
|= xstate_xmm
;
9825 /* vzeroall / vzeroupper */
9826 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9827 i
.xstate
|= xstate_ymm
;
9829 if ((i
.xstate
& xstate_xmm
)
9830 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9831 || (i
.tm
.base_opcode
== 0xae
9832 && (is_cpu (&i
.tm
, CpuSSE
)
9833 || is_cpu (&i
.tm
, CpuAVX
)))
9834 || is_cpu (&i
.tm
, CpuWideKL
)
9835 || is_cpu (&i
.tm
, CpuKL
))
9836 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9838 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9839 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9840 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9841 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9842 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9843 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9844 if (is_cpu (&i
.tm
, CpuFXSR
))
9845 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9846 if (is_cpu (&i
.tm
, CpuXsave
))
9847 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9848 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9849 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9850 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9851 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9853 if (x86_feature_2_used
9854 || is_cpu (&i
.tm
, CpuCMOV
)
9855 || is_cpu (&i
.tm
, CpuSYSCALL
)
9856 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9857 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9858 if (is_cpu (&i
.tm
, CpuSSE3
)
9859 || is_cpu (&i
.tm
, CpuSSSE3
)
9860 || is_cpu (&i
.tm
, CpuSSE4_1
)
9861 || is_cpu (&i
.tm
, CpuSSE4_2
)
9862 || is_cpu (&i
.tm
, CpuCX16
)
9863 || is_cpu (&i
.tm
, CpuPOPCNT
)
9864 /* LAHF-SAHF insns in 64-bit mode. */
9865 || (flag_code
== CODE_64BIT
9866 && (i
.tm
.base_opcode
| 1) == 0x9f
9867 && i
.tm
.opcode_space
== SPACE_BASE
))
9868 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9869 if (is_cpu (&i
.tm
, CpuAVX
)
9870 || is_cpu (&i
.tm
, CpuAVX2
)
9871 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9872 XOP, FMA4, LPW, TBM, and AMX. */
9873 || (i
.tm
.opcode_modifier
.vex
9874 && !is_cpu (&i
.tm
, CpuAVX512F
)
9875 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9876 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9877 && !is_cpu (&i
.tm
, CpuXOP
)
9878 && !is_cpu (&i
.tm
, CpuFMA4
)
9879 && !is_cpu (&i
.tm
, CpuLWP
)
9880 && !is_cpu (&i
.tm
, CpuTBM
)
9881 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9882 || is_cpu (&i
.tm
, CpuF16C
)
9883 || is_cpu (&i
.tm
, CpuFMA
)
9884 || is_cpu (&i
.tm
, CpuLZCNT
)
9885 || is_cpu (&i
.tm
, CpuMovbe
)
9886 || is_cpu (&i
.tm
, CpuXSAVES
)
9887 || (x86_feature_2_used
9888 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9889 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9890 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9891 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9892 if (is_cpu (&i
.tm
, CpuAVX512F
)
9893 || is_cpu (&i
.tm
, CpuAVX512BW
)
9894 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9895 || is_cpu (&i
.tm
, CpuAVX512VL
)
9896 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9897 AVX512-4FMAPS, and AVX512-4VNNIW. */
9898 || (i
.tm
.opcode_modifier
.evex
9899 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9900 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9901 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9902 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9903 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9907 /* Tie dwarf2 debug info to the address at the start of the insn.
9908 We can't do this after the insn has been output as the current
9909 frag may have been closed off. eg. by frag_var. */
9910 dwarf2_emit_insn (0);
9912 insn_start_frag
= frag_now
;
9913 insn_start_off
= frag_now_fix ();
9915 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9918 /* Branch can be 8 bytes. Leave some room for prefixes. */
9919 unsigned int max_branch_padding_size
= 14;
9921 /* Align section to boundary. */
9922 record_alignment (now_seg
, align_branch_power
);
9924 /* Make room for padding. */
9925 frag_grow (max_branch_padding_size
);
9927 /* Start of the padding. */
9932 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9933 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9936 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9937 fragP
->tc_frag_data
.branch_type
= branch
;
9938 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9941 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9942 && !pre_386_16bit_warned
)
9944 as_warn (_("use .code16 to ensure correct addressing mode"));
9945 pre_386_16bit_warned
= true;
9949 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9951 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9952 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9954 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9955 output_interseg_jump ();
9958 /* Output normal instructions here. */
9962 enum mf_cmp_kind mf_cmp
;
9965 && (i
.tm
.base_opcode
== 0xaee8
9966 || i
.tm
.base_opcode
== 0xaef0
9967 || i
.tm
.base_opcode
== 0xaef8))
9969 /* Encode lfence, mfence, and sfence as
9970 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9971 if (flag_code
== CODE_16BIT
)
9972 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9973 else if (omit_lock_prefix
)
9974 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9976 else if (now_seg
!= absolute_section
)
9978 offsetT val
= 0x240483f0ULL
;
9981 md_number_to_chars (p
, val
, 5);
9984 abs_section_offset
+= 5;
9988 /* Some processors fail on LOCK prefix. This options makes
9989 assembler ignore LOCK prefix and serves as a workaround. */
9990 if (omit_lock_prefix
)
9992 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9993 && i
.tm
.opcode_modifier
.isprefix
)
9995 i
.prefix
[LOCK_PREFIX
] = 0;
9999 /* Skip if this is a branch. */
10001 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10003 /* Make room for padding. */
10004 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10009 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10010 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10013 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10014 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10015 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10017 else if (add_branch_prefix_frag_p ())
10019 unsigned int max_prefix_size
= align_branch_prefix_size
;
10021 /* Make room for padding. */
10022 frag_grow (max_prefix_size
);
10027 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10028 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10031 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10034 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10035 don't need the explicit prefix. */
10036 if (!is_any_vex_encoding (&i
.tm
))
10038 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10047 if (!is_cpu (&i
.tm
, CpuPadLock
)
10048 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10052 switch (i
.opcode_length
)
10057 /* Check for pseudo prefixes. */
10058 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10060 as_bad_where (insn_start_frag
->fr_file
,
10061 insn_start_frag
->fr_line
,
10062 _("pseudo prefix without instruction"));
10072 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10073 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10074 R_X86_64_GOTTPOFF relocation so that linker can safely
10075 perform IE->LE optimization. A dummy REX_OPCODE prefix
10076 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10077 relocation for GDesc -> IE/LE optimization. */
10078 if (x86_elf_abi
== X86_64_X32_ABI
10080 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10081 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10082 && i
.prefix
[REX_PREFIX
] == 0)
10083 add_prefix (REX_OPCODE
);
10086 /* The prefix bytes. */
10087 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10089 frag_opcode_byte (*q
);
10093 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10099 frag_opcode_byte (*q
);
10102 /* There should be no other prefixes for instructions
10103 with VEX prefix. */
10107 /* For EVEX instructions i.vrex should become 0 after
10108 build_evex_prefix. For VEX instructions upper 16 registers
10109 aren't available, so VREX should be 0. */
10112 /* Now the VEX prefix. */
10113 if (now_seg
!= absolute_section
)
10115 p
= frag_more (i
.vex
.length
);
10116 for (j
= 0; j
< i
.vex
.length
; j
++)
10117 p
[j
] = i
.vex
.bytes
[j
];
10120 abs_section_offset
+= i
.vex
.length
;
10123 /* Now the opcode; be careful about word order here! */
10124 j
= i
.opcode_length
;
10126 switch (i
.tm
.opcode_space
)
10141 if (now_seg
== absolute_section
)
10142 abs_section_offset
+= j
;
10145 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10151 && i
.tm
.opcode_space
!= SPACE_BASE
)
10154 if (i
.tm
.opcode_space
!= SPACE_0F
)
10155 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10159 switch (i
.opcode_length
)
10162 /* Put out high byte first: can't use md_number_to_chars! */
10163 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10164 /* Fall through. */
10166 *p
= i
.tm
.base_opcode
& 0xff;
10175 /* Now the modrm byte and sib byte (if present). */
10176 if (i
.tm
.opcode_modifier
.modrm
)
10178 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10180 | (i
.rm
.mode
<< 6));
10181 /* If i.rm.regmem == ESP (4)
10182 && i.rm.mode != (Register mode)
10184 ==> need second modrm byte. */
10185 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10187 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10188 frag_opcode_byte ((i
.sib
.base
<< 0)
10189 | (i
.sib
.index
<< 3)
10190 | (i
.sib
.scale
<< 6));
10193 if (i
.disp_operands
)
10194 output_disp (insn_start_frag
, insn_start_off
);
10196 if (i
.imm_operands
)
10197 output_imm (insn_start_frag
, insn_start_off
);
10200 * frag_now_fix () returning plain abs_section_offset when we're in the
10201 * absolute section, and abs_section_offset not getting updated as data
10202 * gets added to the frag breaks the logic below.
10204 if (now_seg
!= absolute_section
)
10206 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10208 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10212 /* NB: Don't add prefix with GOTPC relocation since
10213 output_disp() above depends on the fixed encoding
10214 length. Can't add prefix with TLS relocation since
10215 it breaks TLS linker optimization. */
10216 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10217 /* Prefix count on the current instruction. */
10218 unsigned int count
= i
.vex
.length
;
10220 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10221 /* REX byte is encoded in VEX/EVEX prefix. */
10222 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10225 /* Count prefixes for extended opcode maps. */
10227 switch (i
.tm
.opcode_space
)
10242 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10245 /* Set the maximum prefix size in BRANCH_PREFIX
10247 if (fragP
->tc_frag_data
.max_bytes
> max
)
10248 fragP
->tc_frag_data
.max_bytes
= max
;
10249 if (fragP
->tc_frag_data
.max_bytes
> count
)
10250 fragP
->tc_frag_data
.max_bytes
-= count
;
10252 fragP
->tc_frag_data
.max_bytes
= 0;
10256 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10258 unsigned int max_prefix_size
;
10259 if (align_branch_prefix_size
> max
)
10260 max_prefix_size
= max
;
10262 max_prefix_size
= align_branch_prefix_size
;
10263 if (max_prefix_size
> count
)
10264 fragP
->tc_frag_data
.max_prefix_length
10265 = max_prefix_size
- count
;
10268 /* Use existing segment prefix if possible. Use CS
10269 segment prefix in 64-bit mode. In 32-bit mode, use SS
10270 segment prefix with ESP/EBP base register and use DS
10271 segment prefix without ESP/EBP base register. */
10272 if (i
.prefix
[SEG_PREFIX
])
10273 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10274 else if (flag_code
== CODE_64BIT
)
10275 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10276 else if (i
.base_reg
10277 && (i
.base_reg
->reg_num
== 4
10278 || i
.base_reg
->reg_num
== 5))
10279 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10281 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10286 /* NB: Don't work with COND_JUMP86 without i386. */
10287 if (align_branch_power
10288 && now_seg
!= absolute_section
10289 && cpu_arch_flags
.bitfield
.cpui386
)
10291 /* Terminate each frag so that we can add prefix and check for
10293 frag_wane (frag_now
);
10300 pi ("" /*line*/, &i
);
10302 #endif /* DEBUG386 */
10305 /* Return the size of the displacement operand N. */
10308 disp_size (unsigned int n
)
10312 if (i
.types
[n
].bitfield
.disp64
)
10314 else if (i
.types
[n
].bitfield
.disp8
)
10316 else if (i
.types
[n
].bitfield
.disp16
)
10321 /* Return the size of the immediate operand N. */
10324 imm_size (unsigned int n
)
10327 if (i
.types
[n
].bitfield
.imm64
)
10329 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10331 else if (i
.types
[n
].bitfield
.imm16
)
10337 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10342 for (n
= 0; n
< i
.operands
; n
++)
10344 if (operand_type_check (i
.types
[n
], disp
))
10346 int size
= disp_size (n
);
10348 if (now_seg
== absolute_section
)
10349 abs_section_offset
+= size
;
10350 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10352 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10354 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10356 p
= frag_more (size
);
10357 md_number_to_chars (p
, val
, size
);
10361 enum bfd_reloc_code_real reloc_type
;
10362 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10363 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10364 && (!want_disp32 (&i
.tm
)
10365 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10366 && !i
.types
[n
].bitfield
.baseindex
)))
10370 /* We can't have 8 bit displacement here. */
10371 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10373 /* The PC relative address is computed relative
10374 to the instruction boundary, so in case immediate
10375 fields follows, we need to adjust the value. */
10376 if (pcrel
&& i
.imm_operands
)
10381 for (n1
= 0; n1
< i
.operands
; n1
++)
10382 if (operand_type_check (i
.types
[n1
], imm
))
10384 /* Only one immediate is allowed for PC
10385 relative address, except with .insn. */
10386 gas_assert (sz
== 0 || dot_insn ());
10387 sz
+= imm_size (n1
);
10389 /* We should find at least one immediate. */
10390 gas_assert (sz
!= 0);
10391 i
.op
[n
].disps
->X_add_number
-= sz
;
10394 p
= frag_more (size
);
10395 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10397 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10398 && (((reloc_type
== BFD_RELOC_32
10399 || reloc_type
== BFD_RELOC_X86_64_32S
10400 || (reloc_type
== BFD_RELOC_64
10402 && (i
.op
[n
].disps
->X_op
== O_symbol
10403 || (i
.op
[n
].disps
->X_op
== O_add
10404 && ((symbol_get_value_expression
10405 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10407 || reloc_type
== BFD_RELOC_32_PCREL
))
10411 reloc_type
= BFD_RELOC_386_GOTPC
;
10412 i
.has_gotpc_tls_reloc
= true;
10413 i
.op
[n
].disps
->X_add_number
+=
10414 encoding_length (insn_start_frag
, insn_start_off
, p
);
10416 else if (reloc_type
== BFD_RELOC_64
)
10417 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10419 /* Don't do the adjustment for x86-64, as there
10420 the pcrel addressing is relative to the _next_
10421 insn, and that is taken care of in other code. */
10422 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10424 else if (align_branch_power
)
10426 switch (reloc_type
)
10428 case BFD_RELOC_386_TLS_GD
:
10429 case BFD_RELOC_386_TLS_LDM
:
10430 case BFD_RELOC_386_TLS_IE
:
10431 case BFD_RELOC_386_TLS_IE_32
:
10432 case BFD_RELOC_386_TLS_GOTIE
:
10433 case BFD_RELOC_386_TLS_GOTDESC
:
10434 case BFD_RELOC_386_TLS_DESC_CALL
:
10435 case BFD_RELOC_X86_64_TLSGD
:
10436 case BFD_RELOC_X86_64_TLSLD
:
10437 case BFD_RELOC_X86_64_GOTTPOFF
:
10438 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10439 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10440 i
.has_gotpc_tls_reloc
= true;
10445 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10446 size
, i
.op
[n
].disps
, pcrel
,
10449 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10450 && !i
.prefix
[ADDR_PREFIX
])
10451 fixP
->fx_signed
= 1;
10453 /* Check for "call/jmp *mem", "mov mem, %reg",
10454 "test %reg, mem" and "binop mem, %reg" where binop
10455 is one of adc, add, and, cmp, or, sbb, sub, xor
10456 instructions without data prefix. Always generate
10457 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10458 if (i
.prefix
[DATA_PREFIX
] == 0
10459 && (generate_relax_relocations
10462 && i
.rm
.regmem
== 5))
10464 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10465 && i
.tm
.opcode_space
== SPACE_BASE
10466 && ((i
.operands
== 1
10467 && i
.tm
.base_opcode
== 0xff
10468 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10469 || (i
.operands
== 2
10470 && (i
.tm
.base_opcode
== 0x8b
10471 || i
.tm
.base_opcode
== 0x85
10472 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10476 fixP
->fx_tcbit
= i
.rex
!= 0;
10478 && (i
.base_reg
->reg_num
== RegIP
))
10479 fixP
->fx_tcbit2
= 1;
10482 fixP
->fx_tcbit2
= 1;
10490 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10495 for (n
= 0; n
< i
.operands
; n
++)
10497 if (operand_type_check (i
.types
[n
], imm
))
10499 int size
= imm_size (n
);
10501 if (now_seg
== absolute_section
)
10502 abs_section_offset
+= size
;
10503 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10507 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10509 p
= frag_more (size
);
10510 md_number_to_chars (p
, val
, size
);
10514 /* Not absolute_section.
10515 Need a 32-bit fixup (don't support 8bit
10516 non-absolute imms). Try to support other
10518 enum bfd_reloc_code_real reloc_type
;
10521 if (i
.types
[n
].bitfield
.imm32s
10522 && (i
.suffix
== QWORD_MNEM_SUFFIX
10523 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10524 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10530 p
= frag_more (size
);
10531 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10533 /* This is tough to explain. We end up with this one if we
10534 * have operands that look like
10535 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10536 * obtain the absolute address of the GOT, and it is strongly
10537 * preferable from a performance point of view to avoid using
10538 * a runtime relocation for this. The actual sequence of
10539 * instructions often look something like:
10544 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10546 * The call and pop essentially return the absolute address
10547 * of the label .L66 and store it in %ebx. The linker itself
10548 * will ultimately change the first operand of the addl so
10549 * that %ebx points to the GOT, but to keep things simple, the
10550 * .o file must have this operand set so that it generates not
10551 * the absolute address of .L66, but the absolute address of
10552 * itself. This allows the linker itself simply treat a GOTPC
10553 * relocation as asking for a pcrel offset to the GOT to be
10554 * added in, and the addend of the relocation is stored in the
10555 * operand field for the instruction itself.
10557 * Our job here is to fix the operand so that it would add
10558 * the correct offset so that %ebx would point to itself. The
10559 * thing that is tricky is that .-.L66 will point to the
10560 * beginning of the instruction, so we need to further modify
10561 * the operand so that it will point to itself. There are
10562 * other cases where you have something like:
10564 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10566 * and here no correction would be required. Internally in
10567 * the assembler we treat operands of this form as not being
10568 * pcrel since the '.' is explicitly mentioned, and I wonder
10569 * whether it would simplify matters to do it this way. Who
10570 * knows. In earlier versions of the PIC patches, the
10571 * pcrel_adjust field was used to store the correction, but
10572 * since the expression is not pcrel, I felt it would be
10573 * confusing to do it this way. */
10575 if ((reloc_type
== BFD_RELOC_32
10576 || reloc_type
== BFD_RELOC_X86_64_32S
10577 || reloc_type
== BFD_RELOC_64
)
10579 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10580 && (i
.op
[n
].imms
->X_op
== O_symbol
10581 || (i
.op
[n
].imms
->X_op
== O_add
10582 && ((symbol_get_value_expression
10583 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10587 reloc_type
= BFD_RELOC_386_GOTPC
;
10588 else if (size
== 4)
10589 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10590 else if (size
== 8)
10591 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10592 i
.has_gotpc_tls_reloc
= true;
10593 i
.op
[n
].imms
->X_add_number
+=
10594 encoding_length (insn_start_frag
, insn_start_off
, p
);
10596 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10597 i
.op
[n
].imms
, 0, reloc_type
);
10603 /* x86_cons_fix_new is called via the expression parsing code when a
10604 reloc is needed. We use this hook to get the correct .got reloc. */
10605 static int cons_sign
= -1;
10608 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10609 expressionS
*exp
, bfd_reloc_code_real_type r
)
10611 r
= reloc (len
, 0, cons_sign
, r
);
10614 if (exp
->X_op
== O_secrel
)
10616 exp
->X_op
= O_symbol
;
10617 r
= BFD_RELOC_32_SECREL
;
10619 else if (exp
->X_op
== O_secidx
)
10620 r
= BFD_RELOC_16_SECIDX
;
10623 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10626 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10627 purpose of the `.dc.a' internal pseudo-op. */
10630 x86_address_bytes (void)
10632 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10634 return stdoutput
->arch_info
->bits_per_address
/ 8;
10637 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10638 || defined (LEX_AT)) && !defined (TE_PE)
10639 # define lex_got(reloc, adjust, types) NULL
10641 /* Parse operands of the form
10642 <symbol>@GOTOFF+<nnn>
10643 and similar .plt or .got references.
10645 If we find one, set up the correct relocation in RELOC and copy the
10646 input string, minus the `@GOTOFF' into a malloc'd buffer for
10647 parsing by the calling routine. Return this buffer, and if ADJUST
10648 is non-null set it to the length of the string we removed from the
10649 input line. Otherwise return NULL. */
10651 lex_got (enum bfd_reloc_code_real
*rel
,
10653 i386_operand_type
*types
)
10655 /* Some of the relocations depend on the size of what field is to
10656 be relocated. But in our callers i386_immediate and i386_displacement
10657 we don't yet know the operand size (this will be set by insn
10658 matching). Hence we record the word32 relocation here,
10659 and adjust the reloc according to the real size in reloc(). */
10660 static const struct
10664 const enum bfd_reloc_code_real rel
[2];
10665 const i386_operand_type types64
;
10666 bool need_GOT_symbol
;
10671 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10672 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10673 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10674 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10675 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10676 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10677 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10678 { .imm64 = 1, .disp64 = 1 } }
10681 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10682 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10683 BFD_RELOC_SIZE32
},
10684 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10686 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10687 BFD_RELOC_X86_64_PLTOFF64
},
10688 { .bitfield
= { .imm64
= 1 } }, true },
10689 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10690 BFD_RELOC_X86_64_PLT32
},
10691 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10692 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10693 BFD_RELOC_X86_64_GOTPLT64
},
10694 OPERAND_TYPE_IMM64_DISP64
, true },
10695 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10696 BFD_RELOC_X86_64_GOTOFF64
},
10697 OPERAND_TYPE_IMM64_DISP64
, true },
10698 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10699 BFD_RELOC_X86_64_GOTPCREL
},
10700 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10701 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10702 BFD_RELOC_X86_64_TLSGD
},
10703 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10704 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10705 _dummy_first_bfd_reloc_code_real
},
10706 OPERAND_TYPE_NONE
, true },
10707 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10708 BFD_RELOC_X86_64_TLSLD
},
10709 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10710 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10711 BFD_RELOC_X86_64_GOTTPOFF
},
10712 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10713 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10714 BFD_RELOC_X86_64_TPOFF32
},
10715 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10716 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10717 _dummy_first_bfd_reloc_code_real
},
10718 OPERAND_TYPE_NONE
, true },
10719 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10720 BFD_RELOC_X86_64_DTPOFF32
},
10721 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10722 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10723 _dummy_first_bfd_reloc_code_real
},
10724 OPERAND_TYPE_NONE
, true },
10725 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10726 _dummy_first_bfd_reloc_code_real
},
10727 OPERAND_TYPE_NONE
, true },
10728 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10729 BFD_RELOC_X86_64_GOT32
},
10730 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10731 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10732 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10733 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10734 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10735 BFD_RELOC_X86_64_TLSDESC_CALL
},
10736 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10738 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10739 BFD_RELOC_32_SECREL
},
10740 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10743 #undef OPERAND_TYPE_IMM32_32S_DISP32
10744 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10745 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10746 #undef OPERAND_TYPE_IMM64_DISP64
10752 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10757 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10758 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10761 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10763 int len
= gotrel
[j
].len
;
10764 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10766 if (gotrel
[j
].rel
[object_64bit
] != 0)
10769 char *tmpbuf
, *past_reloc
;
10771 *rel
= gotrel
[j
].rel
[object_64bit
];
10775 if (flag_code
!= CODE_64BIT
)
10777 types
->bitfield
.imm32
= 1;
10778 types
->bitfield
.disp32
= 1;
10781 *types
= gotrel
[j
].types64
;
10784 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10785 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10787 /* The length of the first part of our input line. */
10788 first
= cp
- input_line_pointer
;
10790 /* The second part goes from after the reloc token until
10791 (and including) an end_of_line char or comma. */
10792 past_reloc
= cp
+ 1 + len
;
10794 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10796 second
= cp
+ 1 - past_reloc
;
10798 /* Allocate and copy string. The trailing NUL shouldn't
10799 be necessary, but be safe. */
10800 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10801 memcpy (tmpbuf
, input_line_pointer
, first
);
10802 if (second
!= 0 && *past_reloc
!= ' ')
10803 /* Replace the relocation token with ' ', so that
10804 errors like foo@GOTOFF1 will be detected. */
10805 tmpbuf
[first
++] = ' ';
10807 /* Increment length by 1 if the relocation token is
10812 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10813 tmpbuf
[first
+ second
] = '\0';
10817 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10818 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10823 /* Might be a symbol version string. Don't as_bad here. */
10828 bfd_reloc_code_real_type
10829 x86_cons (expressionS
*exp
, int size
)
10831 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10833 intel_syntax
= -intel_syntax
;
10835 expr_mode
= expr_operator_none
;
10837 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10838 && !defined (LEX_AT)) \
10840 if (size
== 4 || (object_64bit
&& size
== 8))
10842 /* Handle @GOTOFF and the like in an expression. */
10844 char *gotfree_input_line
;
10847 save
= input_line_pointer
;
10848 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10849 if (gotfree_input_line
)
10850 input_line_pointer
= gotfree_input_line
;
10854 if (gotfree_input_line
)
10856 /* expression () has merrily parsed up to the end of line,
10857 or a comma - in the wrong buffer. Transfer how far
10858 input_line_pointer has moved to the right buffer. */
10859 input_line_pointer
= (save
10860 + (input_line_pointer
- gotfree_input_line
)
10862 free (gotfree_input_line
);
10863 if (exp
->X_op
== O_constant
10864 || exp
->X_op
== O_absent
10865 || exp
->X_op
== O_illegal
10866 || exp
->X_op
== O_register
10867 || exp
->X_op
== O_big
)
10869 char c
= *input_line_pointer
;
10870 *input_line_pointer
= 0;
10871 as_bad (_("missing or invalid expression `%s'"), save
);
10872 *input_line_pointer
= c
;
10874 else if ((got_reloc
== BFD_RELOC_386_PLT32
10875 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10876 && exp
->X_op
!= O_symbol
)
10878 char c
= *input_line_pointer
;
10879 *input_line_pointer
= 0;
10880 as_bad (_("invalid PLT expression `%s'"), save
);
10881 *input_line_pointer
= c
;
10889 intel_syntax
= -intel_syntax
;
10892 i386_intel_simplify (exp
);
10894 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10895 if (size
<= 4 && expr_mode
== expr_operator_present
10896 && exp
->X_op
== O_constant
&& !object_64bit
)
10897 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10903 signed_cons (int size
)
10912 s_insn (int dummy ATTRIBUTE_UNUSED
)
10914 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10915 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10919 bool vex
= false, xop
= false, evex
= false;
10920 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10924 saved_char
= *saved_ilp
;
10927 end
= parse_insn (line
, mnemonic
, true);
10931 *saved_ilp
= saved_char
;
10932 ignore_rest_of_line ();
10936 line
+= end
- line
;
10938 current_templates
= &tt
;
10939 i
.tm
.mnem_off
= MN__insn
;
10940 i
.tm
.extension_opcode
= None
;
10942 if (startswith (line
, "VEX")
10943 && (line
[3] == '.' || is_space_char (line
[3])))
10948 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10951 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10953 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10954 && (*e
== '.' || is_space_char (*e
)))
10957 /* Arrange for build_vex_prefix() to emit 0x8f. */
10958 i
.tm
.opcode_space
= SPACE_XOP08
;
10959 i
.insn_opcode_space
= n
;
10963 else if (startswith (line
, "EVEX")
10964 && (line
[4] == '.' || is_space_char (line
[4])))
10971 ? i
.vec_encoding
== vex_encoding_evex
10973 ? i
.vec_encoding
== vex_encoding_vex
10974 || i
.vec_encoding
== vex_encoding_vex3
10975 : i
.vec_encoding
!= vex_encoding_default
)
10977 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10981 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10982 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10984 if (i
.vec_encoding
!= vex_encoding_default
)
10986 /* Only address size and segment override prefixes are permitted with
10987 VEX/XOP/EVEX encodings. */
10988 const unsigned char *p
= i
.prefix
;
10990 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11001 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11007 if (line
> end
&& *line
== '.')
11009 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11017 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11019 i
.tm
.opcode_modifier
.vex
= VEX128
;
11024 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11026 i
.tm
.opcode_modifier
.vex
= VEX256
;
11031 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11036 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11040 if (line
[3] == 'G')
11043 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11045 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11051 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11056 if (line
[2] == '2' && line
[3] == '8')
11059 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11061 i
.tm
.opcode_modifier
.vex
= VEX128
;
11067 if (line
[2] == '5' && line
[3] == '6')
11070 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11072 i
.tm
.opcode_modifier
.vex
= VEX256
;
11078 if (evex
&& line
[2] == '1' && line
[3] == '2')
11080 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11087 if (line
> end
&& *line
== '.')
11089 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11093 if (line
[2] == 'P')
11098 if (line
[2] == '6')
11100 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11105 case 'F': case 'f':
11106 if (line
[2] == '3')
11108 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11111 else if (line
[2] == '2')
11113 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11120 if (line
> end
&& !xop
&& *line
== '.')
11122 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11126 if (TOUPPER (line
[2]) != 'F')
11128 if (line
[3] == '.' || is_space_char (line
[3]))
11130 i
.insn_opcode_space
= SPACE_0F
;
11133 else if (line
[3] == '3'
11134 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11135 && (line
[5] == '.' || is_space_char (line
[5])))
11137 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11143 if (ISDIGIT (line
[2]) && line
[2] != '0')
11146 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11148 if (n
<= (evex
? 15 : 31)
11149 && (*e
== '.' || is_space_char (*e
)))
11151 i
.insn_opcode_space
= n
;
11159 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11161 /* VEX.W, XOP.W, EVEX.W */
11165 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11169 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11173 if (line
[3] == 'G')
11175 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11181 if (i
.tm
.opcode_modifier
.vexw
)
11185 if (line
> end
&& *line
&& !is_space_char (*line
))
11187 /* Improve diagnostic a little. */
11188 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11193 /* Before processing the opcode expression, find trailing "+r" or
11194 "/<digit>" specifiers. */
11195 for (ptr
= line
; ; ++ptr
)
11200 ptr
= strpbrk (ptr
, "+/,");
11201 if (ptr
== NULL
|| *ptr
== ',')
11204 if (*ptr
== '+' && ptr
[1] == 'r'
11205 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11209 i
.short_form
= true;
11213 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11214 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11216 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11220 i
.tm
.extension_opcode
= n
;
11221 i
.tm
.opcode_modifier
.modrm
= 1;
11226 input_line_pointer
= line
;
11227 val
= get_absolute_expression ();
11228 line
= input_line_pointer
;
11230 if (i
.short_form
&& (val
& 7))
11231 as_warn ("`+r' assumes low three opcode bits to be clear");
11233 for (j
= 1; j
< sizeof(val
); ++j
)
11234 if (!(val
>> (j
* 8)))
11237 /* Trim off a prefix if present. */
11238 if (j
> 1 && !vex
&& !xop
&& !evex
)
11240 uint8_t byte
= val
>> ((j
- 1) * 8);
11244 case DATA_PREFIX_OPCODE
:
11245 case REPE_PREFIX_OPCODE
:
11246 case REPNE_PREFIX_OPCODE
:
11247 if (!add_prefix (byte
))
11249 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11254 /* Trim off encoding space. */
11255 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11257 uint8_t byte
= val
>> ((--j
- 1) * 8);
11259 i
.insn_opcode_space
= SPACE_0F
;
11260 switch (byte
& -(j
> 1))
11263 i
.insn_opcode_space
= SPACE_0F38
;
11267 i
.insn_opcode_space
= SPACE_0F3A
;
11271 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11272 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11274 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11275 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11276 Also avoid hitting abort() there or in build_evex_prefix(). */
11277 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11282 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11285 i
.opcode_length
= j
;
11287 /* Handle operands, if any. */
11290 i386_operand_type combined
;
11291 expressionS
*disp_exp
= NULL
;
11296 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11304 as_bad (_("expecting operand after ','; got nothing"));
11308 if (i
.mem_operands
> 1)
11310 as_bad (_("too many memory references for `%s'"),
11311 &i386_mnemonics
[MN__insn
]);
11315 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11316 if (i
.vec_encoding
== vex_encoding_evex512
)
11317 i
.vec_encoding
= vex_encoding_evex
;
11319 /* Are we to emit ModR/M encoding? */
11322 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11323 || i
.tm
.extension_opcode
!= None
))
11324 i
.tm
.opcode_modifier
.modrm
= 1;
11326 if (!i
.tm
.opcode_modifier
.modrm
11328 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11329 || i
.mem_operands
))
11331 as_bad (_("too many register/memory operands"));
11335 /* Enforce certain constraints on operands. */
11336 switch (i
.reg_operands
+ i
.mem_operands
11337 + (i
.tm
.extension_opcode
!= None
))
11342 as_bad (_("too few register/memory operands"));
11345 /* Fall through. */
11347 if (i
.tm
.opcode_modifier
.modrm
)
11349 as_bad (_("too few register/memory operands"));
11359 && (i
.op
[0].imms
->X_op
!= O_constant
11360 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11362 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11365 /* Fall through. */
11367 if (i
.vec_encoding
!= vex_encoding_default
)
11369 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11372 /* Fall through. */
11374 as_bad (_("too many register/memory operands"));
11378 /* Bring operands into canonical order (imm, mem, reg). */
11383 for (j
= 1; j
< i
.operands
; ++j
)
11385 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11386 && operand_type_check (i
.types
[j
], imm
))
11387 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11388 && i
.types
[j
].bitfield
.class == ClassNone
))
11390 swap_2_operands (j
- 1, j
);
11397 /* For Intel syntax swap the order of register operands. */
11399 switch (i
.reg_operands
)
11406 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11407 /* Fall through. */
11410 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11417 /* Enforce constraints when using VSIB. */
11419 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11420 || i
.index_reg
->reg_type
.bitfield
.ymmword
11421 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11423 if (i
.vec_encoding
== vex_encoding_default
)
11425 as_bad (_("VSIB unavailable with legacy encoding"));
11429 if (i
.vec_encoding
== vex_encoding_evex
11430 && i
.reg_operands
> 1)
11432 /* We could allow two register operands, encoding the 2nd one in
11433 an 8-bit immediate like for 4-register-operand insns, but that
11434 would require ugly fiddling with process_operands() and/or
11435 build_modrm_byte(). */
11436 as_bad (_("too many register operands with VSIB"));
11440 i
.tm
.opcode_modifier
.sib
= 1;
11443 /* Establish operand size encoding. */
11444 operand_type_set (&combined
, 0);
11446 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11448 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11450 if (operand_type_check (i
.types
[j
], disp
))
11452 i
.types
[j
].bitfield
.baseindex
= 1;
11453 disp_exp
= i
.op
[j
].disps
;
11456 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11458 unsigned int n
= i
.memshift
;
11460 if (i
.types
[j
].bitfield
.byte
)
11462 else if (i
.types
[j
].bitfield
.word
)
11464 else if (i
.types
[j
].bitfield
.dword
)
11466 else if (i
.types
[j
].bitfield
.qword
)
11468 else if (i
.types
[j
].bitfield
.xmmword
)
11470 else if (i
.types
[j
].bitfield
.ymmword
)
11472 else if (i
.types
[j
].bitfield
.zmmword
)
11475 if (i
.memshift
< 32 && n
!= i
.memshift
)
11476 as_warn ("conflicting memory operand size specifiers");
11480 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11481 && j
== i
.broadcast
.operand
)
11484 combined
= operand_type_or (combined
, i
.types
[j
]);
11485 combined
.bitfield
.class = ClassNone
;
11488 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11489 << (i
.memshift
< 32 ? i
.memshift
: 0))
11491 case 64: combined
.bitfield
.zmmword
= 1; break;
11492 case 32: combined
.bitfield
.ymmword
= 1; break;
11493 case 16: combined
.bitfield
.xmmword
= 1; break;
11494 case 8: combined
.bitfield
.qword
= 1; break;
11495 case 4: combined
.bitfield
.dword
= 1; break;
11498 if (i
.vec_encoding
== vex_encoding_default
)
11500 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11502 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11503 : combined
.bitfield
.word
)
11504 && !add_prefix (DATA_PREFIX_OPCODE
))
11507 else if (!i
.tm
.opcode_modifier
.vexw
)
11509 if (flag_code
== CODE_64BIT
)
11511 if (combined
.bitfield
.qword
)
11512 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11513 else if (combined
.bitfield
.dword
)
11514 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11517 if (!i
.tm
.opcode_modifier
.vexw
)
11518 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11523 if (!i
.tm
.opcode_modifier
.vex
)
11525 if (combined
.bitfield
.ymmword
)
11526 i
.tm
.opcode_modifier
.vex
= VEX256
;
11527 else if (combined
.bitfield
.xmmword
)
11528 i
.tm
.opcode_modifier
.vex
= VEX128
;
11533 if (!i
.tm
.opcode_modifier
.evex
)
11535 /* Do _not_ consider AVX512VL here. */
11536 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11537 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11538 else if (combined
.bitfield
.ymmword
)
11539 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11540 else if (combined
.bitfield
.xmmword
)
11541 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11544 if (i
.memshift
>= 32)
11546 unsigned int n
= 0;
11548 switch (i
.tm
.opcode_modifier
.evex
)
11550 case EVEX512
: n
= 64; break;
11551 case EVEX256
: n
= 32; break;
11552 case EVEX128
: n
= 16; break;
11555 if (i
.broadcast
.type
)
11556 n
/= i
.broadcast
.type
;
11559 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11561 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11562 && disp_exp
->X_add_number
!= 0
11563 && i
.disp_encoding
!= disp_encoding_32bit
)
11565 if (!quiet_warnings
)
11566 as_warn ("cannot determine memory operand size");
11567 i
.disp_encoding
= disp_encoding_32bit
;
11572 if (i
.memshift
>= 32)
11575 i
.vec_encoding
= vex_encoding_error
;
11577 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11580 /* Establish size for immediate operands. */
11581 for (j
= 0; j
< i
.imm_operands
; ++j
)
11583 expressionS
*expP
= i
.op
[j
].imms
;
11585 gas_assert (operand_type_check (i
.types
[j
], imm
));
11586 operand_type_set (&i
.types
[j
], 0);
11588 if (i
.imm_bits
[j
] > 32)
11589 i
.types
[j
].bitfield
.imm64
= 1;
11590 else if (i
.imm_bits
[j
] > 16)
11592 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11593 i
.types
[j
].bitfield
.imm32s
= 1;
11595 i
.types
[j
].bitfield
.imm32
= 1;
11597 else if (i
.imm_bits
[j
] > 8)
11598 i
.types
[j
].bitfield
.imm16
= 1;
11599 else if (i
.imm_bits
[j
] > 0)
11601 if (i
.flags
[j
] & Operand_Signed
)
11602 i
.types
[j
].bitfield
.imm8s
= 1;
11604 i
.types
[j
].bitfield
.imm8
= 1;
11606 else if (expP
->X_op
== O_constant
)
11608 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11609 i
.types
[j
].bitfield
.imm1
= 0;
11610 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11611 zapping since smallest_imm_type() sets it unconditionally. */
11612 if (flag_code
!= CODE_64BIT
)
11614 i
.types
[j
].bitfield
.imm64
= 0;
11615 i
.types
[j
].bitfield
.imm32s
= 0;
11616 i
.types
[j
].bitfield
.imm32
= 1;
11618 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11619 i
.types
[j
].bitfield
.imm64
= 0;
11622 /* Non-constant expressions are sized heuristically. */
11625 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11626 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11627 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11631 for (j
= 0; j
< i
.operands
; ++j
)
11632 i
.tm
.operand_types
[j
] = i
.types
[j
];
11634 process_operands ();
11637 /* Don't set opcode until after processing operands, to avoid any
11638 potential special casing there. */
11639 i
.tm
.base_opcode
|= val
;
11641 if (i
.vec_encoding
== vex_encoding_error
11642 || (i
.vec_encoding
!= vex_encoding_evex
11643 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11644 || i
.rounding
.type
!= rc_none
11646 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11647 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11648 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11650 as_bad (_("conflicting .insn operands"));
11656 if (!i
.tm
.opcode_modifier
.vex
)
11657 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11659 build_vex_prefix (NULL
);
11660 i
.rex
&= REX_OPCODE
;
11664 if (!i
.tm
.opcode_modifier
.evex
)
11665 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11667 build_evex_prefix ();
11668 i
.rex
&= REX_OPCODE
;
11670 else if (i
.rex
!= 0)
11671 add_prefix (REX_OPCODE
| i
.rex
);
11676 *saved_ilp
= saved_char
;
11677 input_line_pointer
= line
;
11679 demand_empty_rest_of_line ();
11681 /* Make sure dot_insn() won't yield "true" anymore. */
11687 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11694 if (exp
.X_op
== O_symbol
)
11695 exp
.X_op
= O_secrel
;
11697 emit_expr (&exp
, 4);
11699 while (*input_line_pointer
++ == ',');
11701 input_line_pointer
--;
11702 demand_empty_rest_of_line ();
11706 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11713 if (exp
.X_op
== O_symbol
)
11714 exp
.X_op
= O_secidx
;
11716 emit_expr (&exp
, 2);
11718 while (*input_line_pointer
++ == ',');
11720 input_line_pointer
--;
11721 demand_empty_rest_of_line ();
11725 /* Handle Rounding Control / SAE specifiers. */
11728 RC_SAE_specifier (const char *pstr
)
11732 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11734 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11736 if (i
.rounding
.type
!= rc_none
)
11738 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11742 if (i
.vec_encoding
== vex_encoding_default
)
11743 i
.vec_encoding
= vex_encoding_evex512
;
11744 else if (i
.vec_encoding
!= vex_encoding_evex
11745 && i
.vec_encoding
!= vex_encoding_evex512
)
11748 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11750 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11757 /* Handle Vector operations. */
11760 check_VecOperations (char *op_string
)
11762 const reg_entry
*mask
;
11769 if (*op_string
== '{')
11773 /* Check broadcasts. */
11774 if (startswith (op_string
, "1to"))
11776 unsigned int bcst_type
;
11778 if (i
.broadcast
.type
)
11779 goto duplicated_vec_op
;
11782 if (*op_string
== '8')
11784 else if (*op_string
== '4')
11786 else if (*op_string
== '2')
11788 else if (*op_string
== '1'
11789 && *(op_string
+1) == '6')
11794 else if (*op_string
== '3'
11795 && *(op_string
+1) == '2')
11802 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11807 if (i
.vec_encoding
== vex_encoding_default
)
11808 i
.vec_encoding
= vex_encoding_evex
;
11809 else if (i
.vec_encoding
!= vex_encoding_evex
11810 && i
.vec_encoding
!= vex_encoding_evex512
)
11811 goto unknown_vec_op
;
11813 i
.broadcast
.type
= bcst_type
;
11814 i
.broadcast
.operand
= this_operand
;
11816 /* For .insn a data size specifier may be appended. */
11817 if (dot_insn () && *op_string
== ':')
11818 goto dot_insn_modifier
;
11820 /* Check .insn special cases. */
11821 else if (dot_insn () && *op_string
== ':')
11824 switch (op_string
[1])
11829 if (i
.memshift
< 32)
11830 goto duplicated_vec_op
;
11832 n
= strtoul (op_string
+ 2, &end_op
, 0);
11834 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11836 if (i
.memshift
< 32 && n
== 1)
11837 op_string
= end_op
;
11840 case 's': case 'u':
11841 /* This isn't really a "vector" operation, but a sign/size
11842 specifier for immediate operands of .insn. Note that AT&T
11843 syntax handles the same in i386_immediate(). */
11847 if (i
.imm_bits
[this_operand
])
11848 goto duplicated_vec_op
;
11850 n
= strtoul (op_string
+ 2, &end_op
, 0);
11851 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11853 i
.imm_bits
[this_operand
] = n
;
11854 if (op_string
[1] == 's')
11855 i
.flags
[this_operand
] |= Operand_Signed
;
11856 op_string
= end_op
;
11861 /* Check masking operation. */
11862 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11864 if (mask
== &bad_reg
)
11867 /* k0 can't be used for write mask. */
11868 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11870 as_bad (_("`%s%s' can't be used for write mask"),
11871 register_prefix
, mask
->reg_name
);
11878 i
.mask
.operand
= this_operand
;
11880 else if (i
.mask
.reg
->reg_num
)
11881 goto duplicated_vec_op
;
11886 /* Only "{z}" is allowed here. No need to check
11887 zeroing mask explicitly. */
11888 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11890 as_bad (_("invalid write mask `%s'"), saved
);
11895 op_string
= end_op
;
11897 /* Check zeroing-flag for masking operation. */
11898 else if (*op_string
== 'z')
11902 i
.mask
.reg
= reg_k0
;
11903 i
.mask
.zeroing
= 1;
11904 i
.mask
.operand
= this_operand
;
11908 if (i
.mask
.zeroing
)
11911 as_bad (_("duplicated `%s'"), saved
);
11915 i
.mask
.zeroing
= 1;
11917 /* Only "{%k}" is allowed here. No need to check mask
11918 register explicitly. */
11919 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11921 as_bad (_("invalid zeroing-masking `%s'"),
11929 else if (intel_syntax
11930 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11931 i
.rounding
.modifier
= true;
11933 goto unknown_vec_op
;
11935 if (*op_string
!= '}')
11937 as_bad (_("missing `}' in `%s'"), saved
);
11942 /* Strip whitespace since the addition of pseudo prefixes
11943 changed how the scrubber treats '{'. */
11944 if (is_space_char (*op_string
))
11950 /* We don't know this one. */
11951 as_bad (_("unknown vector operation: `%s'"), saved
);
11955 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11957 as_bad (_("zeroing-masking only allowed with write mask"));
11965 i386_immediate (char *imm_start
)
11967 char *save_input_line_pointer
;
11968 char *gotfree_input_line
;
11971 i386_operand_type types
;
11973 operand_type_set (&types
, ~0);
11975 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11977 as_bad (_("at most %d immediate operands are allowed"),
11978 MAX_IMMEDIATE_OPERANDS
);
11982 exp
= &im_expressions
[i
.imm_operands
++];
11983 i
.op
[this_operand
].imms
= exp
;
11985 if (is_space_char (*imm_start
))
11988 save_input_line_pointer
= input_line_pointer
;
11989 input_line_pointer
= imm_start
;
11991 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11992 if (gotfree_input_line
)
11993 input_line_pointer
= gotfree_input_line
;
11995 expr_mode
= expr_operator_none
;
11996 exp_seg
= expression (exp
);
11998 /* For .insn immediates there may be a size specifier. */
11999 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12000 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12003 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12005 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12007 i
.imm_bits
[this_operand
] = n
;
12008 if (input_line_pointer
[2] == 's')
12009 i
.flags
[this_operand
] |= Operand_Signed
;
12010 input_line_pointer
= e
+ 1;
12014 SKIP_WHITESPACE ();
12015 if (*input_line_pointer
)
12016 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12018 input_line_pointer
= save_input_line_pointer
;
12019 if (gotfree_input_line
)
12021 free (gotfree_input_line
);
12023 if (exp
->X_op
== O_constant
)
12024 exp
->X_op
= O_illegal
;
12027 if (exp_seg
== reg_section
)
12029 as_bad (_("illegal immediate register operand %s"), imm_start
);
12033 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12037 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12038 i386_operand_type types
, const char *imm_start
)
12040 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12043 as_bad (_("missing or invalid immediate expression `%s'"),
12047 else if (exp
->X_op
== O_constant
)
12049 /* Size it properly later. */
12050 i
.types
[this_operand
].bitfield
.imm64
= 1;
12052 /* If not 64bit, sign/zero extend val, to account for wraparound
12054 if (expr_mode
== expr_operator_present
12055 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12056 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12058 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12059 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12060 && exp_seg
!= absolute_section
12061 && exp_seg
!= text_section
12062 && exp_seg
!= data_section
12063 && exp_seg
!= bss_section
12064 && exp_seg
!= undefined_section
12065 && !bfd_is_com_section (exp_seg
))
12067 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12073 /* This is an address. The size of the address will be
12074 determined later, depending on destination register,
12075 suffix, or the default for the section. */
12076 i
.types
[this_operand
].bitfield
.imm8
= 1;
12077 i
.types
[this_operand
].bitfield
.imm16
= 1;
12078 i
.types
[this_operand
].bitfield
.imm32
= 1;
12079 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12080 i
.types
[this_operand
].bitfield
.imm64
= 1;
12081 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12089 i386_scale (char *scale
)
12092 char *save
= input_line_pointer
;
12094 input_line_pointer
= scale
;
12095 val
= get_absolute_expression ();
12100 i
.log2_scale_factor
= 0;
12103 i
.log2_scale_factor
= 1;
12106 i
.log2_scale_factor
= 2;
12109 i
.log2_scale_factor
= 3;
12113 char sep
= *input_line_pointer
;
12115 *input_line_pointer
= '\0';
12116 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12118 *input_line_pointer
= sep
;
12119 input_line_pointer
= save
;
12123 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12125 as_warn (_("scale factor of %d without an index register"),
12126 1 << i
.log2_scale_factor
);
12127 i
.log2_scale_factor
= 0;
12129 scale
= input_line_pointer
;
12130 input_line_pointer
= save
;
12135 i386_displacement (char *disp_start
, char *disp_end
)
12139 char *save_input_line_pointer
;
12140 char *gotfree_input_line
;
12142 i386_operand_type bigdisp
, types
= anydisp
;
12145 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12147 as_bad (_("at most %d displacement operands are allowed"),
12148 MAX_MEMORY_OPERANDS
);
12152 operand_type_set (&bigdisp
, 0);
12154 || i
.types
[this_operand
].bitfield
.baseindex
12155 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12156 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12158 i386_addressing_mode ();
12159 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12160 if (flag_code
== CODE_64BIT
)
12162 bigdisp
.bitfield
.disp32
= 1;
12164 bigdisp
.bitfield
.disp64
= 1;
12166 else if ((flag_code
== CODE_16BIT
) ^ override
)
12167 bigdisp
.bitfield
.disp16
= 1;
12169 bigdisp
.bitfield
.disp32
= 1;
12173 /* For PC-relative branches, the width of the displacement may be
12174 dependent upon data size, but is never dependent upon address size.
12175 Also make sure to not unintentionally match against a non-PC-relative
12176 branch template. */
12177 static templates aux_templates
;
12178 const insn_template
*t
= current_templates
->start
;
12179 bool has_intel64
= false;
12181 aux_templates
.start
= t
;
12182 while (++t
< current_templates
->end
)
12184 if (t
->opcode_modifier
.jump
12185 != current_templates
->start
->opcode_modifier
.jump
)
12187 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12188 has_intel64
= true;
12190 if (t
< current_templates
->end
)
12192 aux_templates
.end
= t
;
12193 current_templates
= &aux_templates
;
12196 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12197 if (flag_code
== CODE_64BIT
)
12199 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12200 && (!intel64
|| !has_intel64
))
12201 bigdisp
.bitfield
.disp16
= 1;
12203 bigdisp
.bitfield
.disp32
= 1;
12208 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12210 : LONG_MNEM_SUFFIX
));
12211 bigdisp
.bitfield
.disp32
= 1;
12212 if ((flag_code
== CODE_16BIT
) ^ override
)
12214 bigdisp
.bitfield
.disp32
= 0;
12215 bigdisp
.bitfield
.disp16
= 1;
12219 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12222 exp
= &disp_expressions
[i
.disp_operands
];
12223 i
.op
[this_operand
].disps
= exp
;
12225 save_input_line_pointer
= input_line_pointer
;
12226 input_line_pointer
= disp_start
;
12227 END_STRING_AND_SAVE (disp_end
);
12229 #ifndef GCC_ASM_O_HACK
12230 #define GCC_ASM_O_HACK 0
12233 END_STRING_AND_SAVE (disp_end
+ 1);
12234 if (i
.types
[this_operand
].bitfield
.baseIndex
12235 && displacement_string_end
[-1] == '+')
12237 /* This hack is to avoid a warning when using the "o"
12238 constraint within gcc asm statements.
12241 #define _set_tssldt_desc(n,addr,limit,type) \
12242 __asm__ __volatile__ ( \
12243 "movw %w2,%0\n\t" \
12244 "movw %w1,2+%0\n\t" \
12245 "rorl $16,%1\n\t" \
12246 "movb %b1,4+%0\n\t" \
12247 "movb %4,5+%0\n\t" \
12248 "movb $0,6+%0\n\t" \
12249 "movb %h1,7+%0\n\t" \
12251 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12253 This works great except that the output assembler ends
12254 up looking a bit weird if it turns out that there is
12255 no offset. You end up producing code that looks like:
12268 So here we provide the missing zero. */
12270 *displacement_string_end
= '0';
12273 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12274 if (gotfree_input_line
)
12275 input_line_pointer
= gotfree_input_line
;
12277 expr_mode
= expr_operator_none
;
12278 exp_seg
= expression (exp
);
12280 SKIP_WHITESPACE ();
12281 if (*input_line_pointer
)
12282 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12284 RESTORE_END_STRING (disp_end
+ 1);
12286 input_line_pointer
= save_input_line_pointer
;
12287 if (gotfree_input_line
)
12289 free (gotfree_input_line
);
12291 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12292 exp
->X_op
= O_illegal
;
12295 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12297 RESTORE_END_STRING (disp_end
);
12303 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12304 i386_operand_type types
, const char *disp_start
)
12308 /* We do this to make sure that the section symbol is in
12309 the symbol table. We will ultimately change the relocation
12310 to be relative to the beginning of the section. */
12311 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12312 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12313 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12315 if (exp
->X_op
!= O_symbol
)
12318 if (S_IS_LOCAL (exp
->X_add_symbol
)
12319 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12320 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12321 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12322 exp
->X_op
= O_subtract
;
12323 exp
->X_op_symbol
= GOT_symbol
;
12324 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12325 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12326 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12327 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12329 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12332 else if (exp
->X_op
== O_absent
12333 || exp
->X_op
== O_illegal
12334 || exp
->X_op
== O_big
)
12337 as_bad (_("missing or invalid displacement expression `%s'"),
12342 else if (exp
->X_op
== O_constant
)
12344 /* Sizing gets taken care of by optimize_disp().
12346 If not 64bit, sign/zero extend val, to account for wraparound
12348 if (expr_mode
== expr_operator_present
12349 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12350 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12353 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12354 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12355 && exp_seg
!= absolute_section
12356 && exp_seg
!= text_section
12357 && exp_seg
!= data_section
12358 && exp_seg
!= bss_section
12359 && exp_seg
!= undefined_section
12360 && !bfd_is_com_section (exp_seg
))
12362 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12367 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12368 i
.types
[this_operand
].bitfield
.disp8
= 1;
12370 /* Check if this is a displacement only operand. */
12371 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12372 i
.types
[this_operand
] =
12373 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12374 operand_type_and (i
.types
[this_operand
], types
));
12379 /* Return the active addressing mode, taking address override and
12380 registers forming the address into consideration. Update the
12381 address override prefix if necessary. */
12383 static enum flag_code
12384 i386_addressing_mode (void)
12386 enum flag_code addr_mode
;
12388 if (i
.prefix
[ADDR_PREFIX
])
12389 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12390 else if (flag_code
== CODE_16BIT
12391 && is_cpu (current_templates
->start
, CpuMPX
)
12392 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12393 from md_assemble() by "is not a valid base/index expression"
12394 when there is a base and/or index. */
12395 && !i
.types
[this_operand
].bitfield
.baseindex
)
12397 /* MPX insn memory operands with neither base nor index must be forced
12398 to use 32-bit addressing in 16-bit mode. */
12399 addr_mode
= CODE_32BIT
;
12400 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12402 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12403 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12407 addr_mode
= flag_code
;
12409 #if INFER_ADDR_PREFIX
12410 if (i
.mem_operands
== 0)
12412 /* Infer address prefix from the first memory operand. */
12413 const reg_entry
*addr_reg
= i
.base_reg
;
12415 if (addr_reg
== NULL
)
12416 addr_reg
= i
.index_reg
;
12420 if (addr_reg
->reg_type
.bitfield
.dword
)
12421 addr_mode
= CODE_32BIT
;
12422 else if (flag_code
!= CODE_64BIT
12423 && addr_reg
->reg_type
.bitfield
.word
)
12424 addr_mode
= CODE_16BIT
;
12426 if (addr_mode
!= flag_code
)
12428 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12430 /* Change the size of any displacement too. At most one
12431 of Disp16 or Disp32 is set.
12432 FIXME. There doesn't seem to be any real need for
12433 separate Disp16 and Disp32 flags. The same goes for
12434 Imm16 and Imm32. Removing them would probably clean
12435 up the code quite a lot. */
12436 if (flag_code
!= CODE_64BIT
12437 && (i
.types
[this_operand
].bitfield
.disp16
12438 || i
.types
[this_operand
].bitfield
.disp32
))
12440 static const i386_operand_type disp16_32
= {
12441 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12444 i
.types
[this_operand
]
12445 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12456 /* Make sure the memory operand we've been dealt is valid.
12457 Return 1 on success, 0 on a failure. */
12460 i386_index_check (const char *operand_string
)
12462 const char *kind
= "base/index";
12463 enum flag_code addr_mode
= i386_addressing_mode ();
12464 const insn_template
*t
= current_templates
->end
- 1;
12466 if (t
->opcode_modifier
.isstring
)
12468 /* Memory operands of string insns are special in that they only allow
12469 a single register (rDI, rSI, or rBX) as their memory address. */
12470 const reg_entry
*expected_reg
;
12471 static const char di_si
[][2][4] =
12477 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12479 kind
= "string address";
12481 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12483 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12486 if (!t
->operand_types
[0].bitfield
.baseindex
12487 || ((!i
.mem_operands
!= !intel_syntax
)
12488 && t
->operand_types
[1].bitfield
.baseindex
))
12491 = (const reg_entry
*) str_hash_find (reg_hash
,
12492 di_si
[addr_mode
][op
== es_op
]);
12496 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12498 if (i
.base_reg
!= expected_reg
12500 || operand_type_check (i
.types
[this_operand
], disp
))
12502 /* The second memory operand must have the same size as
12506 && !((addr_mode
== CODE_64BIT
12507 && i
.base_reg
->reg_type
.bitfield
.qword
)
12508 || (addr_mode
== CODE_32BIT
12509 ? i
.base_reg
->reg_type
.bitfield
.dword
12510 : i
.base_reg
->reg_type
.bitfield
.word
)))
12513 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12515 intel_syntax
? '[' : '(',
12517 expected_reg
->reg_name
,
12518 intel_syntax
? ']' : ')');
12525 as_bad (_("`%s' is not a valid %s expression"),
12526 operand_string
, kind
);
12531 t
= current_templates
->start
;
12533 if (addr_mode
!= CODE_16BIT
)
12535 /* 32-bit/64-bit checks. */
12536 if (i
.disp_encoding
== disp_encoding_16bit
)
12539 as_bad (_("invalid `%s' prefix"),
12540 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12545 && ((addr_mode
== CODE_64BIT
12546 ? !i
.base_reg
->reg_type
.bitfield
.qword
12547 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12548 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12549 || i
.base_reg
->reg_num
== RegIZ
))
12551 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12552 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12553 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12554 && ((addr_mode
== CODE_64BIT
12555 ? !i
.index_reg
->reg_type
.bitfield
.qword
12556 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12557 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12560 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12561 if (t
->mnem_off
== MN_bndmk
12562 || t
->mnem_off
== MN_bndldx
12563 || t
->mnem_off
== MN_bndstx
12564 || t
->opcode_modifier
.sib
== SIBMEM
)
12566 /* They cannot use RIP-relative addressing. */
12567 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12569 as_bad (_("`%s' cannot be used here"), operand_string
);
12573 /* bndldx and bndstx ignore their scale factor. */
12574 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12575 && i
.log2_scale_factor
)
12576 as_warn (_("register scaling is being ignored here"));
12581 /* 16-bit checks. */
12582 if (i
.disp_encoding
== disp_encoding_32bit
)
12586 && (!i
.base_reg
->reg_type
.bitfield
.word
12587 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12589 && (!i
.index_reg
->reg_type
.bitfield
.word
12590 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12592 && i
.base_reg
->reg_num
< 6
12593 && i
.index_reg
->reg_num
>= 6
12594 && i
.log2_scale_factor
== 0))))
12601 /* Handle vector immediates. */
12604 RC_SAE_immediate (const char *imm_start
)
12606 const char *pstr
= imm_start
;
12611 pstr
= RC_SAE_specifier (pstr
+ 1);
12615 if (*pstr
++ != '}')
12617 as_bad (_("Missing '}': '%s'"), imm_start
);
12620 /* RC/SAE immediate string should contain nothing more. */;
12623 as_bad (_("Junk after '}': '%s'"), imm_start
);
12627 /* Internally this doesn't count as an operand. */
12633 static INLINE
bool starts_memory_operand (char c
)
12636 || is_name_beginner (c
)
12637 || strchr ("([\"+-!~", c
);
12640 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12644 i386_att_operand (char *operand_string
)
12646 const reg_entry
*r
;
12648 char *op_string
= operand_string
;
12650 if (is_space_char (*op_string
))
12653 /* We check for an absolute prefix (differentiating,
12654 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12655 if (*op_string
== ABSOLUTE_PREFIX
12656 && current_templates
->start
->opcode_modifier
.jump
)
12659 if (is_space_char (*op_string
))
12661 i
.jumpabsolute
= true;
12664 /* Check if operand is a register. */
12665 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12667 i386_operand_type temp
;
12672 /* Check for a segment override by searching for ':' after a
12673 segment register. */
12674 op_string
= end_op
;
12675 if (is_space_char (*op_string
))
12677 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12679 i
.seg
[i
.mem_operands
] = r
;
12681 /* Skip the ':' and whitespace. */
12683 if (is_space_char (*op_string
))
12686 /* Handle case of %es:*foo. */
12687 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12688 && current_templates
->start
->opcode_modifier
.jump
)
12691 if (is_space_char (*op_string
))
12693 i
.jumpabsolute
= true;
12696 if (!starts_memory_operand (*op_string
))
12698 as_bad (_("bad memory operand `%s'"), op_string
);
12701 goto do_memory_reference
;
12704 /* Handle vector operations. */
12705 if (*op_string
== '{')
12707 op_string
= check_VecOperations (op_string
);
12708 if (op_string
== NULL
)
12714 as_bad (_("junk `%s' after register"), op_string
);
12718 /* Reject pseudo registers for .insn. */
12719 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12721 as_bad (_("`%s%s' cannot be used here"),
12722 register_prefix
, r
->reg_name
);
12726 temp
= r
->reg_type
;
12727 temp
.bitfield
.baseindex
= 0;
12728 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12730 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12731 i
.op
[this_operand
].regs
= r
;
12734 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12735 operand was also present earlier on. */
12736 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12737 && i
.reg_operands
== 1)
12741 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12742 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12744 as_bad (_("`%s': misplaced `{%s}'"),
12745 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12749 else if (*op_string
== REGISTER_PREFIX
)
12751 as_bad (_("bad register name `%s'"), op_string
);
12754 else if (*op_string
== IMMEDIATE_PREFIX
)
12757 if (i
.jumpabsolute
)
12759 as_bad (_("immediate operand illegal with absolute jump"));
12762 if (!i386_immediate (op_string
))
12764 if (i
.rounding
.type
!= rc_none
)
12766 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12767 insn_name (current_templates
->start
));
12771 else if (RC_SAE_immediate (operand_string
))
12773 /* If it is a RC or SAE immediate, do the necessary placement check:
12774 Only another immediate or a GPR may precede it. */
12775 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12776 || (i
.reg_operands
== 1
12777 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12779 as_bad (_("`%s': misplaced `%s'"),
12780 insn_name (current_templates
->start
), operand_string
);
12784 else if (starts_memory_operand (*op_string
))
12786 /* This is a memory reference of some sort. */
12789 /* Start and end of displacement string expression (if found). */
12790 char *displacement_string_start
;
12791 char *displacement_string_end
;
12793 do_memory_reference
:
12794 /* Check for base index form. We detect the base index form by
12795 looking for an ')' at the end of the operand, searching
12796 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12798 base_string
= op_string
+ strlen (op_string
);
12800 /* Handle vector operations. */
12802 if (is_space_char (*base_string
))
12805 if (*base_string
== '}')
12807 char *vop_start
= NULL
;
12809 while (base_string
-- > op_string
)
12811 if (*base_string
== '"')
12813 if (*base_string
!= '{')
12816 vop_start
= base_string
;
12819 if (is_space_char (*base_string
))
12822 if (*base_string
!= '}')
12830 as_bad (_("unbalanced figure braces"));
12834 if (check_VecOperations (vop_start
) == NULL
)
12838 /* If we only have a displacement, set-up for it to be parsed later. */
12839 displacement_string_start
= op_string
;
12840 displacement_string_end
= base_string
+ 1;
12842 if (*base_string
== ')')
12845 unsigned int parens_not_balanced
= 0;
12846 bool in_quotes
= false;
12848 /* We've already checked that the number of left & right ()'s are
12849 equal, and that there's a matching set of double quotes. */
12850 end_op
= base_string
;
12851 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12853 if (*temp_string
== '\\' && temp_string
[1] == '"')
12855 else if (*temp_string
== '"')
12856 in_quotes
= !in_quotes
;
12857 else if (!in_quotes
)
12859 if (*temp_string
== '(' && !parens_not_balanced
++)
12860 base_string
= temp_string
;
12861 if (*temp_string
== ')')
12862 --parens_not_balanced
;
12866 temp_string
= base_string
;
12868 /* Skip past '(' and whitespace. */
12869 gas_assert (*base_string
== '(');
12871 if (is_space_char (*base_string
))
12874 if (*base_string
== ','
12875 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12878 displacement_string_end
= temp_string
;
12880 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12884 if (i
.base_reg
== &bad_reg
)
12886 base_string
= end_op
;
12887 if (is_space_char (*base_string
))
12891 /* There may be an index reg or scale factor here. */
12892 if (*base_string
== ',')
12895 if (is_space_char (*base_string
))
12898 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12901 if (i
.index_reg
== &bad_reg
)
12903 base_string
= end_op
;
12904 if (is_space_char (*base_string
))
12906 if (*base_string
== ',')
12909 if (is_space_char (*base_string
))
12912 else if (*base_string
!= ')')
12914 as_bad (_("expecting `,' or `)' "
12915 "after index register in `%s'"),
12920 else if (*base_string
== REGISTER_PREFIX
)
12922 end_op
= strchr (base_string
, ',');
12925 as_bad (_("bad register name `%s'"), base_string
);
12929 /* Check for scale factor. */
12930 if (*base_string
!= ')')
12932 char *end_scale
= i386_scale (base_string
);
12937 base_string
= end_scale
;
12938 if (is_space_char (*base_string
))
12940 if (*base_string
!= ')')
12942 as_bad (_("expecting `)' "
12943 "after scale factor in `%s'"),
12948 else if (!i
.index_reg
)
12950 as_bad (_("expecting index register or scale factor "
12951 "after `,'; got '%c'"),
12956 else if (*base_string
!= ')')
12958 as_bad (_("expecting `,' or `)' "
12959 "after base register in `%s'"),
12964 else if (*base_string
== REGISTER_PREFIX
)
12966 end_op
= strchr (base_string
, ',');
12969 as_bad (_("bad register name `%s'"), base_string
);
12974 /* If there's an expression beginning the operand, parse it,
12975 assuming displacement_string_start and
12976 displacement_string_end are meaningful. */
12977 if (displacement_string_start
!= displacement_string_end
)
12979 if (!i386_displacement (displacement_string_start
,
12980 displacement_string_end
))
12984 /* Special case for (%dx) while doing input/output op. */
12986 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12987 && i
.base_reg
->reg_type
.bitfield
.word
12988 && i
.index_reg
== 0
12989 && i
.log2_scale_factor
== 0
12990 && i
.seg
[i
.mem_operands
] == 0
12991 && !operand_type_check (i
.types
[this_operand
], disp
))
12993 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12994 i
.input_output_operand
= true;
12998 if (i386_index_check (operand_string
) == 0)
13000 i
.flags
[this_operand
] |= Operand_Mem
;
13005 /* It's not a memory operand; argh! */
13006 as_bad (_("invalid char %s beginning operand %d `%s'"),
13007 output_invalid (*op_string
),
13012 return 1; /* Normal return. */
13015 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13016 that an rs_machine_dependent frag may reach. */
13019 i386_frag_max_var (fragS
*frag
)
13021 /* The only relaxable frags are for jumps.
13022 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13023 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13024 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13029 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13031 /* STT_GNU_IFUNC symbol must go through PLT. */
13032 if ((symbol_get_bfdsym (fr_symbol
)->flags
13033 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13036 if (!S_IS_EXTERNAL (fr_symbol
))
13037 /* Symbol may be weak or local. */
13038 return !S_IS_WEAK (fr_symbol
);
13040 /* Global symbols with non-default visibility can't be preempted. */
13041 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13044 if (fr_var
!= NO_RELOC
)
13045 switch ((enum bfd_reloc_code_real
) fr_var
)
13047 case BFD_RELOC_386_PLT32
:
13048 case BFD_RELOC_X86_64_PLT32
:
13049 /* Symbol with PLT relocation may be preempted. */
13055 /* Global symbols with default visibility in a shared library may be
13056 preempted by another definition. */
13061 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13062 Note also work for Skylake and Cascadelake.
13063 ---------------------------------------------------------------------
13064 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13065 | ------ | ----------- | ------- | -------- |
13067 | Jno | N | N | Y |
13068 | Jc/Jb | Y | N | Y |
13069 | Jae/Jnb | Y | N | Y |
13070 | Je/Jz | Y | Y | Y |
13071 | Jne/Jnz | Y | Y | Y |
13072 | Jna/Jbe | Y | N | Y |
13073 | Ja/Jnbe | Y | N | Y |
13075 | Jns | N | N | Y |
13076 | Jp/Jpe | N | N | Y |
13077 | Jnp/Jpo | N | N | Y |
13078 | Jl/Jnge | Y | Y | Y |
13079 | Jge/Jnl | Y | Y | Y |
13080 | Jle/Jng | Y | Y | Y |
13081 | Jg/Jnle | Y | Y | Y |
13082 --------------------------------------------------------------------- */
13084 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13086 if (mf_cmp
== mf_cmp_alu_cmp
)
13087 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13088 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13089 if (mf_cmp
== mf_cmp_incdec
)
13090 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13091 || mf_jcc
== mf_jcc_jle
);
13092 if (mf_cmp
== mf_cmp_test_and
)
13097 /* Return the next non-empty frag. */
13100 i386_next_non_empty_frag (fragS
*fragP
)
13102 /* There may be a frag with a ".fill 0" when there is no room in
13103 the current frag for frag_grow in output_insn. */
13104 for (fragP
= fragP
->fr_next
;
13106 && fragP
->fr_type
== rs_fill
13107 && fragP
->fr_fix
== 0);
13108 fragP
= fragP
->fr_next
)
13113 /* Return the next jcc frag after BRANCH_PADDING. */
13116 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13118 fragS
*branch_fragP
;
13122 if (pad_fragP
->fr_type
== rs_machine_dependent
13123 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13124 == BRANCH_PADDING
))
13126 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13127 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13129 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13130 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13131 pad_fragP
->tc_frag_data
.mf_type
))
13132 return branch_fragP
;
13138 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13141 i386_classify_machine_dependent_frag (fragS
*fragP
)
13145 fragS
*branch_fragP
;
13147 unsigned int max_prefix_length
;
13149 if (fragP
->tc_frag_data
.classified
)
13152 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13153 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13154 for (next_fragP
= fragP
;
13155 next_fragP
!= NULL
;
13156 next_fragP
= next_fragP
->fr_next
)
13158 next_fragP
->tc_frag_data
.classified
= 1;
13159 if (next_fragP
->fr_type
== rs_machine_dependent
)
13160 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13162 case BRANCH_PADDING
:
13163 /* The BRANCH_PADDING frag must be followed by a branch
13165 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13166 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13168 case FUSED_JCC_PADDING
:
13169 /* Check if this is a fused jcc:
13171 CMP like instruction
13175 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13176 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13177 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13180 /* The BRANCH_PADDING frag is merged with the
13181 FUSED_JCC_PADDING frag. */
13182 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13183 /* CMP like instruction size. */
13184 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13185 frag_wane (pad_fragP
);
13186 /* Skip to branch_fragP. */
13187 next_fragP
= branch_fragP
;
13189 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13191 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13193 next_fragP
->fr_subtype
13194 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13195 next_fragP
->tc_frag_data
.max_bytes
13196 = next_fragP
->tc_frag_data
.max_prefix_length
;
13197 /* This will be updated in the BRANCH_PREFIX scan. */
13198 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13201 frag_wane (next_fragP
);
13206 /* Stop if there is no BRANCH_PREFIX. */
13207 if (!align_branch_prefix_size
)
13210 /* Scan for BRANCH_PREFIX. */
13211 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13213 if (fragP
->fr_type
!= rs_machine_dependent
13214 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13218 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13219 COND_JUMP_PREFIX. */
13220 max_prefix_length
= 0;
13221 for (next_fragP
= fragP
;
13222 next_fragP
!= NULL
;
13223 next_fragP
= next_fragP
->fr_next
)
13225 if (next_fragP
->fr_type
== rs_fill
)
13226 /* Skip rs_fill frags. */
13228 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13229 /* Stop for all other frags. */
13232 /* rs_machine_dependent frags. */
13233 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13236 /* Count BRANCH_PREFIX frags. */
13237 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13239 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13240 frag_wane (next_fragP
);
13244 += next_fragP
->tc_frag_data
.max_bytes
;
13246 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13248 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13249 == FUSED_JCC_PADDING
))
13251 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13252 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13256 /* Stop for other rs_machine_dependent frags. */
13260 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13262 /* Skip to the next frag. */
13263 fragP
= next_fragP
;
13267 /* Compute padding size for
13270 CMP like instruction
13272 COND_JUMP/UNCOND_JUMP
13277 COND_JUMP/UNCOND_JUMP
13281 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13283 unsigned int offset
, size
, padding_size
;
13284 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13286 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13288 address
= fragP
->fr_address
;
13289 address
+= fragP
->fr_fix
;
13291 /* CMP like instrunction size. */
13292 size
= fragP
->tc_frag_data
.cmp_size
;
13294 /* The base size of the branch frag. */
13295 size
+= branch_fragP
->fr_fix
;
13297 /* Add opcode and displacement bytes for the rs_machine_dependent
13299 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13300 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13302 /* Check if branch is within boundary and doesn't end at the last
13304 offset
= address
& ((1U << align_branch_power
) - 1);
13305 if ((offset
+ size
) >= (1U << align_branch_power
))
13306 /* Padding needed to avoid crossing boundary. */
13307 padding_size
= (1U << align_branch_power
) - offset
;
13309 /* No padding needed. */
13312 /* The return value may be saved in tc_frag_data.length which is
13314 if (!fits_in_unsigned_byte (padding_size
))
13317 return padding_size
;
13320 /* i386_generic_table_relax_frag()
13322 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13323 grow/shrink padding to align branch frags. Hand others to
13327 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13329 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13330 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13332 long padding_size
= i386_branch_padding_size (fragP
, 0);
13333 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13335 /* When the BRANCH_PREFIX frag is used, the computed address
13336 must match the actual address and there should be no padding. */
13337 if (fragP
->tc_frag_data
.padding_address
13338 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13342 /* Update the padding size. */
13344 fragP
->tc_frag_data
.length
= padding_size
;
13348 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13350 fragS
*padding_fragP
, *next_fragP
;
13351 long padding_size
, left_size
, last_size
;
13353 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13354 if (!padding_fragP
)
13355 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13356 return (fragP
->tc_frag_data
.length
13357 - fragP
->tc_frag_data
.last_length
);
13359 /* Compute the relative address of the padding frag in the very
13360 first time where the BRANCH_PREFIX frag sizes are zero. */
13361 if (!fragP
->tc_frag_data
.padding_address
)
13362 fragP
->tc_frag_data
.padding_address
13363 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13365 /* First update the last length from the previous interation. */
13366 left_size
= fragP
->tc_frag_data
.prefix_length
;
13367 for (next_fragP
= fragP
;
13368 next_fragP
!= padding_fragP
;
13369 next_fragP
= next_fragP
->fr_next
)
13370 if (next_fragP
->fr_type
== rs_machine_dependent
13371 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13376 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13380 if (max
> left_size
)
13385 next_fragP
->tc_frag_data
.last_length
= size
;
13389 next_fragP
->tc_frag_data
.last_length
= 0;
13392 /* Check the padding size for the padding frag. */
13393 padding_size
= i386_branch_padding_size
13394 (padding_fragP
, (fragP
->fr_address
13395 + fragP
->tc_frag_data
.padding_address
));
13397 last_size
= fragP
->tc_frag_data
.prefix_length
;
13398 /* Check if there is change from the last interation. */
13399 if (padding_size
== last_size
)
13401 /* Update the expected address of the padding frag. */
13402 padding_fragP
->tc_frag_data
.padding_address
13403 = (fragP
->fr_address
+ padding_size
13404 + fragP
->tc_frag_data
.padding_address
);
13408 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13410 /* No padding if there is no sufficient room. Clear the
13411 expected address of the padding frag. */
13412 padding_fragP
->tc_frag_data
.padding_address
= 0;
13416 /* Store the expected address of the padding frag. */
13417 padding_fragP
->tc_frag_data
.padding_address
13418 = (fragP
->fr_address
+ padding_size
13419 + fragP
->tc_frag_data
.padding_address
);
13421 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13423 /* Update the length for the current interation. */
13424 left_size
= padding_size
;
13425 for (next_fragP
= fragP
;
13426 next_fragP
!= padding_fragP
;
13427 next_fragP
= next_fragP
->fr_next
)
13428 if (next_fragP
->fr_type
== rs_machine_dependent
13429 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13434 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13438 if (max
> left_size
)
13443 next_fragP
->tc_frag_data
.length
= size
;
13447 next_fragP
->tc_frag_data
.length
= 0;
13450 return (fragP
->tc_frag_data
.length
13451 - fragP
->tc_frag_data
.last_length
);
13453 return relax_frag (segment
, fragP
, stretch
);
13456 /* md_estimate_size_before_relax()
13458 Called just before relax() for rs_machine_dependent frags. The x86
13459 assembler uses these frags to handle variable size jump
13462 Any symbol that is now undefined will not become defined.
13463 Return the correct fr_subtype in the frag.
13464 Return the initial "guess for variable size of frag" to caller.
13465 The guess is actually the growth beyond the fixed part. Whatever
13466 we do to grow the fixed or variable part contributes to our
13470 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13472 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13473 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13474 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13476 i386_classify_machine_dependent_frag (fragP
);
13477 return fragP
->tc_frag_data
.length
;
13480 /* We've already got fragP->fr_subtype right; all we have to do is
13481 check for un-relaxable symbols. On an ELF system, we can't relax
13482 an externally visible symbol, because it may be overridden by a
13484 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13485 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13487 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13490 #if defined (OBJ_COFF) && defined (TE_PE)
13491 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13492 && S_IS_WEAK (fragP
->fr_symbol
))
13496 /* Symbol is undefined in this segment, or we need to keep a
13497 reloc so that weak symbols can be overridden. */
13498 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13499 enum bfd_reloc_code_real reloc_type
;
13500 unsigned char *opcode
;
13504 if (fragP
->fr_var
!= NO_RELOC
)
13505 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13506 else if (size
== 2)
13507 reloc_type
= BFD_RELOC_16_PCREL
;
13508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13509 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13510 && fragP
->fr_offset
== 0
13511 && need_plt32_p (fragP
->fr_symbol
))
13512 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13515 reloc_type
= BFD_RELOC_32_PCREL
;
13517 old_fr_fix
= fragP
->fr_fix
;
13518 opcode
= (unsigned char *) fragP
->fr_opcode
;
13520 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13523 /* Make jmp (0xeb) a (d)word displacement jump. */
13525 fragP
->fr_fix
+= size
;
13526 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13528 fragP
->fr_offset
, 1,
13534 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13536 /* Negate the condition, and branch past an
13537 unconditional jump. */
13540 /* Insert an unconditional jump. */
13542 /* We added two extra opcode bytes, and have a two byte
13544 fragP
->fr_fix
+= 2 + 2;
13545 fix_new (fragP
, old_fr_fix
+ 2, 2,
13547 fragP
->fr_offset
, 1,
13551 /* Fall through. */
13554 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13556 fragP
->fr_fix
+= 1;
13557 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13559 fragP
->fr_offset
, 1,
13560 BFD_RELOC_8_PCREL
);
13561 fixP
->fx_signed
= 1;
13565 /* This changes the byte-displacement jump 0x7N
13566 to the (d)word-displacement jump 0x0f,0x8N. */
13567 opcode
[1] = opcode
[0] + 0x10;
13568 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13569 /* We've added an opcode byte. */
13570 fragP
->fr_fix
+= 1 + size
;
13571 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13573 fragP
->fr_offset
, 1,
13578 BAD_CASE (fragP
->fr_subtype
);
13582 /* All jumps handled here are signed, but don't unconditionally use a
13583 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13584 around at 4G (outside of 64-bit mode) and 64k. */
13585 if (size
== 4 && flag_code
== CODE_64BIT
)
13586 fixP
->fx_signed
= 1;
13589 return fragP
->fr_fix
- old_fr_fix
;
13592 /* Guess size depending on current relax state. Initially the relax
13593 state will correspond to a short jump and we return 1, because
13594 the variable part of the frag (the branch offset) is one byte
13595 long. However, we can relax a section more than once and in that
13596 case we must either set fr_subtype back to the unrelaxed state,
13597 or return the value for the appropriate branch. */
13598 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13601 /* Called after relax() is finished.
13603 In: Address of frag.
13604 fr_type == rs_machine_dependent.
13605 fr_subtype is what the address relaxed to.
13607 Out: Any fixSs and constants are set up.
13608 Caller will turn frag into a ".space 0". */
13611 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13614 unsigned char *opcode
;
13615 unsigned char *where_to_put_displacement
= NULL
;
13616 offsetT target_address
;
13617 offsetT opcode_address
;
13618 unsigned int extension
= 0;
13619 offsetT displacement_from_opcode_start
;
13621 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13622 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13623 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13625 /* Generate nop padding. */
13626 unsigned int size
= fragP
->tc_frag_data
.length
;
13629 if (size
> fragP
->tc_frag_data
.max_bytes
)
13635 const char *branch
= "branch";
13636 const char *prefix
= "";
13637 fragS
*padding_fragP
;
13638 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13641 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13642 switch (fragP
->tc_frag_data
.default_prefix
)
13647 case CS_PREFIX_OPCODE
:
13650 case DS_PREFIX_OPCODE
:
13653 case ES_PREFIX_OPCODE
:
13656 case FS_PREFIX_OPCODE
:
13659 case GS_PREFIX_OPCODE
:
13662 case SS_PREFIX_OPCODE
:
13667 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13668 "%s within %d-byte boundary\n");
13670 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13671 "align %s within %d-byte boundary\n");
13675 padding_fragP
= fragP
;
13676 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13677 "%s within %d-byte boundary\n");
13681 switch (padding_fragP
->tc_frag_data
.branch_type
)
13683 case align_branch_jcc
:
13686 case align_branch_fused
:
13687 branch
= "fused jcc";
13689 case align_branch_jmp
:
13692 case align_branch_call
:
13695 case align_branch_indirect
:
13696 branch
= "indiret branch";
13698 case align_branch_ret
:
13705 fprintf (stdout
, msg
,
13706 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13707 (long long) fragP
->fr_address
, branch
,
13708 1 << align_branch_power
);
13710 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13711 memset (fragP
->fr_opcode
,
13712 fragP
->tc_frag_data
.default_prefix
, size
);
13714 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13716 fragP
->fr_fix
+= size
;
13721 opcode
= (unsigned char *) fragP
->fr_opcode
;
13723 /* Address we want to reach in file space. */
13724 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13726 /* Address opcode resides at in file space. */
13727 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13729 /* Displacement from opcode start to fill into instruction. */
13730 displacement_from_opcode_start
= target_address
- opcode_address
;
13732 if ((fragP
->fr_subtype
& BIG
) == 0)
13734 /* Don't have to change opcode. */
13735 extension
= 1; /* 1 opcode + 1 displacement */
13736 where_to_put_displacement
= &opcode
[1];
13740 if (no_cond_jump_promotion
13741 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13742 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13743 _("long jump required"));
13745 switch (fragP
->fr_subtype
)
13747 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13748 extension
= 4; /* 1 opcode + 4 displacement */
13750 where_to_put_displacement
= &opcode
[1];
13753 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13754 extension
= 2; /* 1 opcode + 2 displacement */
13756 where_to_put_displacement
= &opcode
[1];
13759 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13760 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13761 extension
= 5; /* 2 opcode + 4 displacement */
13762 opcode
[1] = opcode
[0] + 0x10;
13763 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13764 where_to_put_displacement
= &opcode
[2];
13767 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13768 extension
= 3; /* 2 opcode + 2 displacement */
13769 opcode
[1] = opcode
[0] + 0x10;
13770 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13771 where_to_put_displacement
= &opcode
[2];
13774 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13779 where_to_put_displacement
= &opcode
[3];
13783 BAD_CASE (fragP
->fr_subtype
);
13788 /* If size if less then four we are sure that the operand fits,
13789 but if it's 4, then it could be that the displacement is larger
13791 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13793 && ((addressT
) (displacement_from_opcode_start
- extension
13794 + ((addressT
) 1 << 31))
13795 > (((addressT
) 2 << 31) - 1)))
13797 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13798 _("jump target out of range"));
13799 /* Make us emit 0. */
13800 displacement_from_opcode_start
= extension
;
13802 /* Now put displacement after opcode. */
13803 md_number_to_chars ((char *) where_to_put_displacement
,
13804 (valueT
) (displacement_from_opcode_start
- extension
),
13805 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13806 fragP
->fr_fix
+= extension
;
13809 /* Apply a fixup (fixP) to segment data, once it has been determined
13810 by our caller that we have all the info we need to fix it up.
13812 Parameter valP is the pointer to the value of the bits.
13814 On the 386, immediates, displacements, and data pointers are all in
13815 the same (little-endian) format, so we don't need to care about which
13816 we are handling. */
13819 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13821 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13822 valueT value
= *valP
;
13824 #if !defined (TE_Mach)
13825 if (fixP
->fx_pcrel
)
13827 switch (fixP
->fx_r_type
)
13833 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13836 case BFD_RELOC_X86_64_32S
:
13837 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13840 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13843 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13848 if (fixP
->fx_addsy
!= NULL
13849 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13850 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13851 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13852 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13853 && !use_rela_relocations
)
13855 /* This is a hack. There should be a better way to handle this.
13856 This covers for the fact that bfd_install_relocation will
13857 subtract the current location (for partial_inplace, PC relative
13858 relocations); see more below. */
13862 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13865 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13870 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13872 if ((sym_seg
== seg
13873 || (symbol_section_p (fixP
->fx_addsy
)
13874 && sym_seg
!= absolute_section
))
13875 && !generic_force_reloc (fixP
))
13877 /* Yes, we add the values in twice. This is because
13878 bfd_install_relocation subtracts them out again. I think
13879 bfd_install_relocation is broken, but I don't dare change
13881 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13885 #if defined (OBJ_COFF) && defined (TE_PE)
13886 /* For some reason, the PE format does not store a
13887 section address offset for a PC relative symbol. */
13888 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13889 || S_IS_WEAK (fixP
->fx_addsy
))
13890 value
+= md_pcrel_from (fixP
);
13893 #if defined (OBJ_COFF) && defined (TE_PE)
13894 if (fixP
->fx_addsy
!= NULL
13895 && S_IS_WEAK (fixP
->fx_addsy
)
13896 /* PR 16858: Do not modify weak function references. */
13897 && ! fixP
->fx_pcrel
)
13899 #if !defined (TE_PEP)
13900 /* For x86 PE weak function symbols are neither PC-relative
13901 nor do they set S_IS_FUNCTION. So the only reliable way
13902 to detect them is to check the flags of their containing
13904 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13905 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13909 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13913 /* Fix a few things - the dynamic linker expects certain values here,
13914 and we must not disappoint it. */
13915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13916 if (IS_ELF
&& fixP
->fx_addsy
)
13917 switch (fixP
->fx_r_type
)
13919 case BFD_RELOC_386_PLT32
:
13920 case BFD_RELOC_X86_64_PLT32
:
13921 /* Make the jump instruction point to the address of the operand.
13922 At runtime we merely add the offset to the actual PLT entry.
13923 NB: Subtract the offset size only for jump instructions. */
13924 if (fixP
->fx_pcrel
)
13928 case BFD_RELOC_386_TLS_GD
:
13929 case BFD_RELOC_386_TLS_LDM
:
13930 case BFD_RELOC_386_TLS_IE_32
:
13931 case BFD_RELOC_386_TLS_IE
:
13932 case BFD_RELOC_386_TLS_GOTIE
:
13933 case BFD_RELOC_386_TLS_GOTDESC
:
13934 case BFD_RELOC_X86_64_TLSGD
:
13935 case BFD_RELOC_X86_64_TLSLD
:
13936 case BFD_RELOC_X86_64_GOTTPOFF
:
13937 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13938 value
= 0; /* Fully resolved at runtime. No addend. */
13940 case BFD_RELOC_386_TLS_LE
:
13941 case BFD_RELOC_386_TLS_LDO_32
:
13942 case BFD_RELOC_386_TLS_LE_32
:
13943 case BFD_RELOC_X86_64_DTPOFF32
:
13944 case BFD_RELOC_X86_64_DTPOFF64
:
13945 case BFD_RELOC_X86_64_TPOFF32
:
13946 case BFD_RELOC_X86_64_TPOFF64
:
13947 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13950 case BFD_RELOC_386_TLS_DESC_CALL
:
13951 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13952 value
= 0; /* Fully resolved at runtime. No addend. */
13953 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13957 case BFD_RELOC_VTABLE_INHERIT
:
13958 case BFD_RELOC_VTABLE_ENTRY
:
13965 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13967 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13969 value
= extend_to_32bit_address (value
);
13972 #endif /* !defined (TE_Mach) */
13974 /* Are we finished with this relocation now? */
13975 if (fixP
->fx_addsy
== NULL
)
13978 switch (fixP
->fx_r_type
)
13980 case BFD_RELOC_X86_64_32S
:
13981 fixP
->fx_signed
= 1;
13988 #if defined (OBJ_COFF) && defined (TE_PE)
13989 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13992 /* Remember value for tc_gen_reloc. */
13993 fixP
->fx_addnumber
= value
;
13994 /* Clear out the frag for now. */
13998 else if (use_rela_relocations
)
14000 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14001 fixP
->fx_no_overflow
= 1;
14002 /* Remember value for tc_gen_reloc. */
14003 fixP
->fx_addnumber
= value
;
14007 md_number_to_chars (p
, value
, fixP
->fx_size
);
14011 md_atof (int type
, char *litP
, int *sizeP
)
14013 /* This outputs the LITTLENUMs in REVERSE order;
14014 in accord with the bigendian 386. */
14015 return ieee_md_atof (type
, litP
, sizeP
, false);
14018 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14021 output_invalid (int c
)
14024 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14027 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14028 "(0x%x)", (unsigned char) c
);
14029 return output_invalid_buf
;
14032 /* Verify that @r can be used in the current context. */
14034 static bool check_register (const reg_entry
*r
)
14036 if (allow_pseudo_reg
)
14039 if (operand_type_all_zero (&r
->reg_type
))
14042 if ((r
->reg_type
.bitfield
.dword
14043 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14044 || r
->reg_type
.bitfield
.class == RegCR
14045 || r
->reg_type
.bitfield
.class == RegDR
)
14046 && !cpu_arch_flags
.bitfield
.cpui386
)
14049 if (r
->reg_type
.bitfield
.class == RegTR
14050 && (flag_code
== CODE_64BIT
14051 || !cpu_arch_flags
.bitfield
.cpui386
14052 || cpu_arch_isa_flags
.bitfield
.cpui586
14053 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14056 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14059 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14061 if (r
->reg_type
.bitfield
.zmmword
14062 || r
->reg_type
.bitfield
.class == RegMask
)
14065 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14067 if (r
->reg_type
.bitfield
.ymmword
)
14070 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14075 if (r
->reg_type
.bitfield
.zmmword
)
14077 if (vector_size
< VSZ512
)
14080 if (i
.vec_encoding
== vex_encoding_default
)
14081 i
.vec_encoding
= vex_encoding_evex512
;
14082 else if (i
.vec_encoding
!= vex_encoding_evex
14083 && i
.vec_encoding
!= vex_encoding_evex512
)
14084 i
.vec_encoding
= vex_encoding_error
;
14087 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14090 if (r
->reg_type
.bitfield
.tmmword
14091 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14092 || flag_code
!= CODE_64BIT
))
14095 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14098 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14099 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14102 /* Upper 16 vector registers are only available with VREX in 64bit
14103 mode, and require EVEX encoding. */
14104 if (r
->reg_flags
& RegVRex
)
14106 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14107 || flag_code
!= CODE_64BIT
)
14110 if (i
.vec_encoding
== vex_encoding_default
14111 || i
.vec_encoding
== vex_encoding_evex512
)
14112 i
.vec_encoding
= vex_encoding_evex
;
14113 else if (i
.vec_encoding
!= vex_encoding_evex
)
14114 i
.vec_encoding
= vex_encoding_error
;
14117 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14118 && (!cpu_arch_flags
.bitfield
.cpu64
14119 || r
->reg_type
.bitfield
.class != RegCR
14121 && flag_code
!= CODE_64BIT
)
14124 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14131 /* REG_STRING starts *before* REGISTER_PREFIX. */
14133 static const reg_entry
*
14134 parse_real_register (const char *reg_string
, char **end_op
)
14136 const char *s
= reg_string
;
14138 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14139 const reg_entry
*r
;
14141 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14142 if (*s
== REGISTER_PREFIX
)
14145 if (is_space_char (*s
))
14148 p
= reg_name_given
;
14149 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14151 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14152 return (const reg_entry
*) NULL
;
14156 if (is_part_of_name (*s
))
14157 return (const reg_entry
*) NULL
;
14159 *end_op
= (char *) s
;
14161 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14163 /* Handle floating point regs, allowing spaces in the (i) part. */
14166 if (!cpu_arch_flags
.bitfield
.cpu8087
14167 && !cpu_arch_flags
.bitfield
.cpu287
14168 && !cpu_arch_flags
.bitfield
.cpu387
14169 && !allow_pseudo_reg
)
14170 return (const reg_entry
*) NULL
;
14172 if (is_space_char (*s
))
14177 if (is_space_char (*s
))
14179 if (*s
>= '0' && *s
<= '7')
14181 int fpr
= *s
- '0';
14183 if (is_space_char (*s
))
14187 *end_op
= (char *) s
+ 1;
14188 know (r
[fpr
].reg_num
== fpr
);
14192 /* We have "%st(" then garbage. */
14193 return (const reg_entry
*) NULL
;
14197 return r
&& check_register (r
) ? r
: NULL
;
14200 /* REG_STRING starts *before* REGISTER_PREFIX. */
14202 static const reg_entry
*
14203 parse_register (const char *reg_string
, char **end_op
)
14205 const reg_entry
*r
;
14207 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14208 r
= parse_real_register (reg_string
, end_op
);
14213 char *save
= input_line_pointer
;
14214 char *buf
= xstrdup (reg_string
), *name
;
14217 input_line_pointer
= buf
;
14218 get_symbol_name (&name
);
14219 symbolP
= symbol_find (name
);
14220 while (symbolP
&& symbol_equated_p (symbolP
))
14222 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14224 if (e
->X_add_number
)
14226 symbolP
= e
->X_add_symbol
;
14228 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14230 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14232 if (e
->X_op
== O_register
)
14234 know (e
->X_add_number
>= 0
14235 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14236 r
= i386_regtab
+ e
->X_add_number
;
14237 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14239 if (r
&& !check_register (r
))
14241 as_bad (_("register '%s%s' cannot be used here"),
14242 register_prefix
, r
->reg_name
);
14246 input_line_pointer
= save
;
14253 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14255 const reg_entry
*r
= NULL
;
14256 char *end
= input_line_pointer
;
14258 /* We only know the terminating character here. It being double quote could
14259 be the closing one of a quoted symbol name, or an opening one from a
14260 following string (or another quoted symbol name). Since the latter can't
14261 be valid syntax for anything, bailing in either case is good enough. */
14262 if (*nextcharP
== '"')
14266 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14267 r
= parse_real_register (name
, &input_line_pointer
);
14268 if (r
&& end
<= input_line_pointer
)
14270 *nextcharP
= *input_line_pointer
;
14271 *input_line_pointer
= 0;
14272 e
->X_op
= O_register
;
14273 e
->X_add_number
= r
- i386_regtab
;
14276 input_line_pointer
= end
;
14278 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14282 md_operand (expressionS
*e
)
14285 const reg_entry
*r
;
14287 switch (*input_line_pointer
)
14289 case REGISTER_PREFIX
:
14290 r
= parse_real_register (input_line_pointer
, &end
);
14293 e
->X_op
= O_register
;
14294 e
->X_add_number
= r
- i386_regtab
;
14295 input_line_pointer
= end
;
14300 gas_assert (intel_syntax
);
14301 end
= input_line_pointer
++;
14303 if (*input_line_pointer
== ']')
14305 ++input_line_pointer
;
14306 e
->X_op_symbol
= make_expr_symbol (e
);
14307 e
->X_add_symbol
= NULL
;
14308 e
->X_add_number
= 0;
14313 e
->X_op
= O_absent
;
14314 input_line_pointer
= end
;
14321 /* To maintain consistency with !BFD64 builds of gas record, whether any
14322 (binary) operator was involved in an expression. As expressions are
14323 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14324 truncate results. */
14325 bool i386_record_operator (operatorT op
,
14326 const expressionS
*left
,
14327 const expressionS
*right
)
14329 if (op
== O_absent
)
14334 /* Since the expression parser applies unary operators fine to bignum
14335 operands, we don't need to be concerned of respective operands not
14336 fitting in 32 bits. */
14337 if (right
->X_op
== O_constant
&& right
->X_unsigned
14338 && !fits_in_unsigned_long (right
->X_add_number
))
14341 /* This isn't entirely right: The pattern can also result when constant
14342 expressions are folded (e.g. 0xffffffff + 1). */
14343 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14344 && !fits_in_unsigned_long (left
->X_add_number
))
14345 || (right
->X_op
== O_constant
&& right
->X_unsigned
14346 && !fits_in_unsigned_long (right
->X_add_number
)))
14347 expr_mode
= expr_large_value
;
14349 if (expr_mode
!= expr_large_value
)
14350 expr_mode
= expr_operator_present
;
14356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14357 const char *md_shortopts
= "kVQ:sqnO::";
14359 const char *md_shortopts
= "qnO::";
14362 #define OPTION_32 (OPTION_MD_BASE + 0)
14363 #define OPTION_64 (OPTION_MD_BASE + 1)
14364 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14365 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14366 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14367 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14368 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14369 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14370 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14371 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14372 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14373 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14374 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14375 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14376 #define OPTION_X32 (OPTION_MD_BASE + 14)
14377 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14378 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14379 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14380 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14381 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14382 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14383 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14384 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14385 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14386 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14387 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14388 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14389 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14390 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14391 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14392 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14393 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14394 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14395 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14396 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14398 struct option md_longopts
[] =
14400 {"32", no_argument
, NULL
, OPTION_32
},
14401 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14402 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14403 {"64", no_argument
, NULL
, OPTION_64
},
14405 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14406 {"x32", no_argument
, NULL
, OPTION_X32
},
14407 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14408 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14410 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14411 {"march", required_argument
, NULL
, OPTION_MARCH
},
14412 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14413 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14414 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14415 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14416 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14417 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14418 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14419 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14420 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14421 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14422 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14423 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14424 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14425 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14426 # if defined (TE_PE) || defined (TE_PEP)
14427 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14429 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14430 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14431 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14432 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14433 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14434 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14435 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14436 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14437 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14438 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14439 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14440 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14441 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14442 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14443 {NULL
, no_argument
, NULL
, 0}
14445 size_t md_longopts_size
= sizeof (md_longopts
);
14448 md_parse_option (int c
, const char *arg
)
14451 char *arch
, *next
, *saved
, *type
;
14456 optimize_align_code
= 0;
14460 quiet_warnings
= 1;
14463 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14464 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14465 should be emitted or not. FIXME: Not implemented. */
14467 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14471 /* -V: SVR4 argument to print version ID. */
14473 print_version_id ();
14476 /* -k: Ignore for FreeBSD compatibility. */
14481 /* -s: On i386 Solaris, this tells the native assembler to use
14482 .stab instead of .stab.excl. We always use .stab anyhow. */
14485 case OPTION_MSHARED
:
14489 case OPTION_X86_USED_NOTE
:
14490 if (strcasecmp (arg
, "yes") == 0)
14492 else if (strcasecmp (arg
, "no") == 0)
14495 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14500 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14501 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14504 const char **list
, **l
;
14506 list
= bfd_target_list ();
14507 for (l
= list
; *l
!= NULL
; l
++)
14508 if (startswith (*l
, "elf64-x86-64")
14509 || strcmp (*l
, "coff-x86-64") == 0
14510 || strcmp (*l
, "pe-x86-64") == 0
14511 || strcmp (*l
, "pei-x86-64") == 0
14512 || strcmp (*l
, "mach-o-x86-64") == 0)
14514 default_arch
= "x86_64";
14518 as_fatal (_("no compiled in support for x86_64"));
14524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14528 const char **list
, **l
;
14530 list
= bfd_target_list ();
14531 for (l
= list
; *l
!= NULL
; l
++)
14532 if (startswith (*l
, "elf32-x86-64"))
14534 default_arch
= "x86_64:32";
14538 as_fatal (_("no compiled in support for 32bit x86_64"));
14542 as_fatal (_("32bit x86_64 is only supported for ELF"));
14548 const char **list
, **l
;
14550 list
= bfd_target_list ();
14551 for (l
= list
; *l
!= NULL
; l
++)
14552 if (strstr (*l
, "-i386")
14553 || strstr (*l
, "-go32"))
14555 default_arch
= "i386";
14559 as_fatal (_("no compiled in support for ix86"));
14564 case OPTION_DIVIDE
:
14565 #ifdef SVR4_COMMENT_CHARS
14570 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14572 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14576 i386_comment_chars
= n
;
14582 saved
= xstrdup (arg
);
14584 /* Allow -march=+nosse. */
14592 as_fatal (_("invalid -march= option: `%s'"), arg
);
14593 next
= strchr (arch
, '+');
14596 vsz
= strchr (arch
, '/');
14599 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14601 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14604 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14605 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14608 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14611 cpu_arch_name
= cpu_arch
[j
].name
;
14612 free (cpu_sub_arch_name
);
14613 cpu_sub_arch_name
= NULL
;
14614 cpu_arch_flags
= cpu_arch
[j
].enable
;
14615 cpu_arch_isa
= cpu_arch
[j
].type
;
14616 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14617 if (!cpu_arch_tune_set
)
14618 cpu_arch_tune
= cpu_arch_isa
;
14619 vector_size
= VSZ_DEFAULT
;
14622 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14623 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14624 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14626 /* ISA extension. */
14629 switch (cpu_arch
[j
].vsz
)
14638 unsigned long val
= strtoul (vsz
, &end
, 0);
14644 case 512: vector_size
= VSZ512
; break;
14645 case 256: vector_size
= VSZ256
; break;
14646 case 128: vector_size
= VSZ128
; break;
14648 as_warn (_("Unrecognized vector size specifier ignored"));
14653 /* Fall through. */
14655 vector_size
= VSZ_DEFAULT
;
14663 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14665 /* Disable an ISA extension. */
14666 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14667 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14668 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14671 if (cpu_arch
[j
].vsz
== vsz_set
)
14672 vector_size
= VSZ_DEFAULT
;
14677 if (j
>= ARRAY_SIZE (cpu_arch
))
14678 as_fatal (_("invalid -march= option: `%s'"), arg
);
14682 while (next
!= NULL
);
14688 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14689 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14691 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14692 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14694 cpu_arch_tune_set
= 1;
14695 cpu_arch_tune
= cpu_arch
[j
].type
;
14699 if (j
>= ARRAY_SIZE (cpu_arch
))
14700 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14703 case OPTION_MMNEMONIC
:
14704 if (strcasecmp (arg
, "att") == 0)
14705 intel_mnemonic
= 0;
14706 else if (strcasecmp (arg
, "intel") == 0)
14707 intel_mnemonic
= 1;
14709 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14712 case OPTION_MSYNTAX
:
14713 if (strcasecmp (arg
, "att") == 0)
14715 else if (strcasecmp (arg
, "intel") == 0)
14718 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14721 case OPTION_MINDEX_REG
:
14722 allow_index_reg
= 1;
14725 case OPTION_MNAKED_REG
:
14726 allow_naked_reg
= 1;
14729 case OPTION_MSSE2AVX
:
14733 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14734 use_unaligned_vector_move
= 1;
14737 case OPTION_MSSE_CHECK
:
14738 if (strcasecmp (arg
, "error") == 0)
14739 sse_check
= check_error
;
14740 else if (strcasecmp (arg
, "warning") == 0)
14741 sse_check
= check_warning
;
14742 else if (strcasecmp (arg
, "none") == 0)
14743 sse_check
= check_none
;
14745 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14748 case OPTION_MOPERAND_CHECK
:
14749 if (strcasecmp (arg
, "error") == 0)
14750 operand_check
= check_error
;
14751 else if (strcasecmp (arg
, "warning") == 0)
14752 operand_check
= check_warning
;
14753 else if (strcasecmp (arg
, "none") == 0)
14754 operand_check
= check_none
;
14756 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14759 case OPTION_MAVXSCALAR
:
14760 if (strcasecmp (arg
, "128") == 0)
14761 avxscalar
= vex128
;
14762 else if (strcasecmp (arg
, "256") == 0)
14763 avxscalar
= vex256
;
14765 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14768 case OPTION_MVEXWIG
:
14769 if (strcmp (arg
, "0") == 0)
14771 else if (strcmp (arg
, "1") == 0)
14774 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14777 case OPTION_MADD_BND_PREFIX
:
14778 add_bnd_prefix
= 1;
14781 case OPTION_MEVEXLIG
:
14782 if (strcmp (arg
, "128") == 0)
14783 evexlig
= evexl128
;
14784 else if (strcmp (arg
, "256") == 0)
14785 evexlig
= evexl256
;
14786 else if (strcmp (arg
, "512") == 0)
14787 evexlig
= evexl512
;
14789 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14792 case OPTION_MEVEXRCIG
:
14793 if (strcmp (arg
, "rne") == 0)
14795 else if (strcmp (arg
, "rd") == 0)
14797 else if (strcmp (arg
, "ru") == 0)
14799 else if (strcmp (arg
, "rz") == 0)
14802 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14805 case OPTION_MEVEXWIG
:
14806 if (strcmp (arg
, "0") == 0)
14808 else if (strcmp (arg
, "1") == 0)
14811 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14814 # if defined (TE_PE) || defined (TE_PEP)
14815 case OPTION_MBIG_OBJ
:
14820 case OPTION_MOMIT_LOCK_PREFIX
:
14821 if (strcasecmp (arg
, "yes") == 0)
14822 omit_lock_prefix
= 1;
14823 else if (strcasecmp (arg
, "no") == 0)
14824 omit_lock_prefix
= 0;
14826 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14829 case OPTION_MFENCE_AS_LOCK_ADD
:
14830 if (strcasecmp (arg
, "yes") == 0)
14832 else if (strcasecmp (arg
, "no") == 0)
14835 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14838 case OPTION_MLFENCE_AFTER_LOAD
:
14839 if (strcasecmp (arg
, "yes") == 0)
14840 lfence_after_load
= 1;
14841 else if (strcasecmp (arg
, "no") == 0)
14842 lfence_after_load
= 0;
14844 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14847 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14848 if (strcasecmp (arg
, "all") == 0)
14850 lfence_before_indirect_branch
= lfence_branch_all
;
14851 if (lfence_before_ret
== lfence_before_ret_none
)
14852 lfence_before_ret
= lfence_before_ret_shl
;
14854 else if (strcasecmp (arg
, "memory") == 0)
14855 lfence_before_indirect_branch
= lfence_branch_memory
;
14856 else if (strcasecmp (arg
, "register") == 0)
14857 lfence_before_indirect_branch
= lfence_branch_register
;
14858 else if (strcasecmp (arg
, "none") == 0)
14859 lfence_before_indirect_branch
= lfence_branch_none
;
14861 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14865 case OPTION_MLFENCE_BEFORE_RET
:
14866 if (strcasecmp (arg
, "or") == 0)
14867 lfence_before_ret
= lfence_before_ret_or
;
14868 else if (strcasecmp (arg
, "not") == 0)
14869 lfence_before_ret
= lfence_before_ret_not
;
14870 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14871 lfence_before_ret
= lfence_before_ret_shl
;
14872 else if (strcasecmp (arg
, "none") == 0)
14873 lfence_before_ret
= lfence_before_ret_none
;
14875 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14879 case OPTION_MRELAX_RELOCATIONS
:
14880 if (strcasecmp (arg
, "yes") == 0)
14881 generate_relax_relocations
= 1;
14882 else if (strcasecmp (arg
, "no") == 0)
14883 generate_relax_relocations
= 0;
14885 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14888 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14891 long int align
= strtoul (arg
, &end
, 0);
14896 align_branch_power
= 0;
14899 else if (align
>= 16)
14902 for (align_power
= 0;
14904 align
>>= 1, align_power
++)
14906 /* Limit alignment power to 31. */
14907 if (align
== 1 && align_power
< 32)
14909 align_branch_power
= align_power
;
14914 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14918 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14921 int align
= strtoul (arg
, &end
, 0);
14922 /* Some processors only support 5 prefixes. */
14923 if (*end
== '\0' && align
>= 0 && align
< 6)
14925 align_branch_prefix_size
= align
;
14928 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14933 case OPTION_MALIGN_BRANCH
:
14935 saved
= xstrdup (arg
);
14939 next
= strchr (type
, '+');
14942 if (strcasecmp (type
, "jcc") == 0)
14943 align_branch
|= align_branch_jcc_bit
;
14944 else if (strcasecmp (type
, "fused") == 0)
14945 align_branch
|= align_branch_fused_bit
;
14946 else if (strcasecmp (type
, "jmp") == 0)
14947 align_branch
|= align_branch_jmp_bit
;
14948 else if (strcasecmp (type
, "call") == 0)
14949 align_branch
|= align_branch_call_bit
;
14950 else if (strcasecmp (type
, "ret") == 0)
14951 align_branch
|= align_branch_ret_bit
;
14952 else if (strcasecmp (type
, "indirect") == 0)
14953 align_branch
|= align_branch_indirect_bit
;
14955 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14958 while (next
!= NULL
);
14962 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14963 align_branch_power
= 5;
14964 align_branch_prefix_size
= 5;
14965 align_branch
= (align_branch_jcc_bit
14966 | align_branch_fused_bit
14967 | align_branch_jmp_bit
);
14970 case OPTION_MAMD64
:
14974 case OPTION_MINTEL64
:
14982 /* Turn off -Os. */
14983 optimize_for_space
= 0;
14985 else if (*arg
== 's')
14987 optimize_for_space
= 1;
14988 /* Turn on all encoding optimizations. */
14989 optimize
= INT_MAX
;
14993 optimize
= atoi (arg
);
14994 /* Turn off -Os. */
14995 optimize_for_space
= 0;
15005 #define MESSAGE_TEMPLATE \
15009 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15010 int *left_p
, const char *name
, int len
)
15012 int size
= sizeof (MESSAGE_TEMPLATE
);
15013 int left
= *left_p
;
15015 /* Reserve 2 spaces for ", " or ",\0" */
15018 /* Check if there is any room. */
15026 p
= mempcpy (p
, name
, len
);
15030 /* Output the current message now and start a new one. */
15033 fprintf (stream
, "%s\n", message
);
15035 left
= size
- (start
- message
) - len
- 2;
15037 gas_assert (left
>= 0);
15039 p
= mempcpy (p
, name
, len
);
15047 show_arch (FILE *stream
, int ext
, int check
)
15049 static char message
[] = MESSAGE_TEMPLATE
;
15050 char *start
= message
+ 27;
15052 int size
= sizeof (MESSAGE_TEMPLATE
);
15059 left
= size
- (start
- message
);
15063 p
= output_message (stream
, p
, message
, start
, &left
,
15064 STRING_COMMA_LEN ("default"));
15065 p
= output_message (stream
, p
, message
, start
, &left
,
15066 STRING_COMMA_LEN ("push"));
15067 p
= output_message (stream
, p
, message
, start
, &left
,
15068 STRING_COMMA_LEN ("pop"));
15071 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15073 /* Should it be skipped? */
15074 if (cpu_arch
[j
].skip
)
15077 name
= cpu_arch
[j
].name
;
15078 len
= cpu_arch
[j
].len
;
15079 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15081 /* It is an extension. Skip if we aren't asked to show it. */
15082 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15087 /* It is an processor. Skip if we show only extension. */
15090 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15092 /* It is an impossible processor - skip. */
15096 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15099 /* Display disabled extensions. */
15101 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15105 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15106 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15108 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15109 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15115 fprintf (stream
, "%s\n", message
);
15119 md_show_usage (FILE *stream
)
15121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15122 fprintf (stream
, _("\
15123 -Qy, -Qn ignored\n\
15124 -V print assembler version number\n\
15127 fprintf (stream
, _("\
15128 -n do not optimize code alignment\n\
15129 -O{012s} attempt some code optimizations\n\
15130 -q quieten some warnings\n"));
15131 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15132 fprintf (stream
, _("\
15136 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15137 fprintf (stream
, _("\
15138 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15139 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15140 fprintf (stream
, _("\
15141 --32/--64 generate 32bit/64bit object\n"));
15144 #ifdef SVR4_COMMENT_CHARS
15145 fprintf (stream
, _("\
15146 --divide do not treat `/' as a comment character\n"));
15148 fprintf (stream
, _("\
15149 --divide ignored\n"));
15151 fprintf (stream
, _("\
15152 -march=CPU[,+EXTENSION...]\n\
15153 generate code for CPU and EXTENSION, CPU is one of:\n"));
15154 show_arch (stream
, 0, 1);
15155 fprintf (stream
, _("\
15156 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15157 show_arch (stream
, 1, 0);
15158 fprintf (stream
, _("\
15159 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15160 show_arch (stream
, 0, 0);
15161 fprintf (stream
, _("\
15162 -msse2avx encode SSE instructions with VEX prefix\n"));
15163 fprintf (stream
, _("\
15164 -muse-unaligned-vector-move\n\
15165 encode aligned vector move as unaligned vector move\n"));
15166 fprintf (stream
, _("\
15167 -msse-check=[none|error|warning] (default: warning)\n\
15168 check SSE instructions\n"));
15169 fprintf (stream
, _("\
15170 -moperand-check=[none|error|warning] (default: warning)\n\
15171 check operand combinations for validity\n"));
15172 fprintf (stream
, _("\
15173 -mavxscalar=[128|256] (default: 128)\n\
15174 encode scalar AVX instructions with specific vector\n\
15176 fprintf (stream
, _("\
15177 -mvexwig=[0|1] (default: 0)\n\
15178 encode VEX instructions with specific VEX.W value\n\
15179 for VEX.W bit ignored instructions\n"));
15180 fprintf (stream
, _("\
15181 -mevexlig=[128|256|512] (default: 128)\n\
15182 encode scalar EVEX instructions with specific vector\n\
15184 fprintf (stream
, _("\
15185 -mevexwig=[0|1] (default: 0)\n\
15186 encode EVEX instructions with specific EVEX.W value\n\
15187 for EVEX.W bit ignored instructions\n"));
15188 fprintf (stream
, _("\
15189 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15190 encode EVEX instructions with specific EVEX.RC value\n\
15191 for SAE-only ignored instructions\n"));
15192 fprintf (stream
, _("\
15193 -mmnemonic=[att|intel] "));
15194 if (SYSV386_COMPAT
)
15195 fprintf (stream
, _("(default: att)\n"));
15197 fprintf (stream
, _("(default: intel)\n"));
15198 fprintf (stream
, _("\
15199 use AT&T/Intel mnemonic\n"));
15200 fprintf (stream
, _("\
15201 -msyntax=[att|intel] (default: att)\n\
15202 use AT&T/Intel syntax\n"));
15203 fprintf (stream
, _("\
15204 -mindex-reg support pseudo index registers\n"));
15205 fprintf (stream
, _("\
15206 -mnaked-reg don't require `%%' prefix for registers\n"));
15207 fprintf (stream
, _("\
15208 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15210 fprintf (stream
, _("\
15211 -mshared disable branch optimization for shared code\n"));
15212 fprintf (stream
, _("\
15213 -mx86-used-note=[no|yes] "));
15214 if (DEFAULT_X86_USED_NOTE
)
15215 fprintf (stream
, _("(default: yes)\n"));
15217 fprintf (stream
, _("(default: no)\n"));
15218 fprintf (stream
, _("\
15219 generate x86 used ISA and feature properties\n"));
15221 #if defined (TE_PE) || defined (TE_PEP)
15222 fprintf (stream
, _("\
15223 -mbig-obj generate big object files\n"));
15225 fprintf (stream
, _("\
15226 -momit-lock-prefix=[no|yes] (default: no)\n\
15227 strip all lock prefixes\n"));
15228 fprintf (stream
, _("\
15229 -mfence-as-lock-add=[no|yes] (default: no)\n\
15230 encode lfence, mfence and sfence as\n\
15231 lock addl $0x0, (%%{re}sp)\n"));
15232 fprintf (stream
, _("\
15233 -mrelax-relocations=[no|yes] "));
15234 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15235 fprintf (stream
, _("(default: yes)\n"));
15237 fprintf (stream
, _("(default: no)\n"));
15238 fprintf (stream
, _("\
15239 generate relax relocations\n"));
15240 fprintf (stream
, _("\
15241 -malign-branch-boundary=NUM (default: 0)\n\
15242 align branches within NUM byte boundary\n"));
15243 fprintf (stream
, _("\
15244 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15245 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15247 specify types of branches to align\n"));
15248 fprintf (stream
, _("\
15249 -malign-branch-prefix-size=NUM (default: 5)\n\
15250 align branches with NUM prefixes per instruction\n"));
15251 fprintf (stream
, _("\
15252 -mbranches-within-32B-boundaries\n\
15253 align branches within 32 byte boundary\n"));
15254 fprintf (stream
, _("\
15255 -mlfence-after-load=[no|yes] (default: no)\n\
15256 generate lfence after load\n"));
15257 fprintf (stream
, _("\
15258 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15259 generate lfence before indirect near branch\n"));
15260 fprintf (stream
, _("\
15261 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15262 generate lfence before ret\n"));
15263 fprintf (stream
, _("\
15264 -mamd64 accept only AMD64 ISA [default]\n"));
15265 fprintf (stream
, _("\
15266 -mintel64 accept only Intel64 ISA\n"));
15269 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15270 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15271 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15273 /* Pick the target format to use. */
15276 i386_target_format (void)
15278 if (startswith (default_arch
, "x86_64"))
15280 update_code_flag (CODE_64BIT
, 1);
15281 if (default_arch
[6] == '\0')
15282 x86_elf_abi
= X86_64_ABI
;
15284 x86_elf_abi
= X86_64_X32_ABI
;
15286 else if (!strcmp (default_arch
, "i386"))
15287 update_code_flag (CODE_32BIT
, 1);
15288 else if (!strcmp (default_arch
, "iamcu"))
15290 update_code_flag (CODE_32BIT
, 1);
15291 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15293 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15294 cpu_arch_name
= "iamcu";
15295 free (cpu_sub_arch_name
);
15296 cpu_sub_arch_name
= NULL
;
15297 cpu_arch_flags
= iamcu_flags
;
15298 cpu_arch_isa
= PROCESSOR_IAMCU
;
15299 cpu_arch_isa_flags
= iamcu_flags
;
15300 if (!cpu_arch_tune_set
)
15301 cpu_arch_tune
= PROCESSOR_IAMCU
;
15303 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15304 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15308 as_fatal (_("unknown architecture"));
15310 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15311 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15313 switch (OUTPUT_FLAVOR
)
15315 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15316 case bfd_target_aout_flavour
:
15317 return AOUT_TARGET_FORMAT
;
15319 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15320 # if defined (TE_PE) || defined (TE_PEP)
15321 case bfd_target_coff_flavour
:
15322 if (flag_code
== CODE_64BIT
)
15325 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15327 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15328 # elif defined (TE_GO32)
15329 case bfd_target_coff_flavour
:
15330 return "coff-go32";
15332 case bfd_target_coff_flavour
:
15333 return "coff-i386";
15336 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15337 case bfd_target_elf_flavour
:
15339 const char *format
;
15341 switch (x86_elf_abi
)
15344 format
= ELF_TARGET_FORMAT
;
15346 tls_get_addr
= "___tls_get_addr";
15350 use_rela_relocations
= 1;
15353 tls_get_addr
= "__tls_get_addr";
15355 format
= ELF_TARGET_FORMAT64
;
15357 case X86_64_X32_ABI
:
15358 use_rela_relocations
= 1;
15361 tls_get_addr
= "__tls_get_addr";
15363 disallow_64bit_reloc
= 1;
15364 format
= ELF_TARGET_FORMAT32
;
15367 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15369 if (x86_elf_abi
!= I386_ABI
)
15370 as_fatal (_("Intel MCU is 32bit only"));
15371 return ELF_TARGET_IAMCU_FORMAT
;
15377 #if defined (OBJ_MACH_O)
15378 case bfd_target_mach_o_flavour
:
15379 if (flag_code
== CODE_64BIT
)
15381 use_rela_relocations
= 1;
15383 return "mach-o-x86-64";
15386 return "mach-o-i386";
15394 #endif /* OBJ_MAYBE_ more than one */
15397 md_undefined_symbol (char *name
)
15399 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15400 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15401 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15402 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15406 if (symbol_find (name
))
15407 as_bad (_("GOT already in symbol table"));
15408 GOT_symbol
= symbol_new (name
, undefined_section
,
15409 &zero_address_frag
, 0);
15416 /* Round up a section size to the appropriate boundary. */
15419 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15421 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15422 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15424 /* For a.out, force the section size to be aligned. If we don't do
15425 this, BFD will align it for us, but it will not write out the
15426 final bytes of the section. This may be a bug in BFD, but it is
15427 easier to fix it here since that is how the other a.out targets
15431 align
= bfd_section_alignment (segment
);
15432 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15439 /* On the i386, PC-relative offsets are relative to the start of the
15440 next instruction. That is, the address of the offset, plus its
15441 size, since the offset is always the last part of the insn. */
15444 md_pcrel_from (fixS
*fixP
)
15446 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15452 s_bss (int ignore ATTRIBUTE_UNUSED
)
15456 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15458 obj_elf_section_change_hook ();
15460 temp
= get_absolute_expression ();
15461 subseg_set (bss_section
, (subsegT
) temp
);
15462 demand_empty_rest_of_line ();
15467 /* Remember constant directive. */
15470 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15472 if (last_insn
.kind
!= last_insn_directive
15473 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15475 last_insn
.seg
= now_seg
;
15476 last_insn
.kind
= last_insn_directive
;
15477 last_insn
.name
= "constant directive";
15478 last_insn
.file
= as_where (&last_insn
.line
);
15479 if (lfence_before_ret
!= lfence_before_ret_none
)
15481 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15482 as_warn (_("constant directive skips -mlfence-before-ret "
15483 "and -mlfence-before-indirect-branch"));
15485 as_warn (_("constant directive skips -mlfence-before-ret"));
15487 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15488 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15493 i386_validate_fix (fixS
*fixp
)
15495 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15497 reloc_howto_type
*howto
;
15499 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15501 _("invalid %s relocation against register"),
15502 howto
? howto
->name
: "<unknown>");
15506 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15507 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15508 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15509 return IS_ELF
&& fixp
->fx_addsy
15510 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15511 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15514 if (fixp
->fx_subsy
)
15516 if (fixp
->fx_subsy
== GOT_symbol
)
15518 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15523 if (fixp
->fx_tcbit2
)
15524 fixp
->fx_r_type
= (fixp
->fx_tcbit
15525 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15526 : BFD_RELOC_X86_64_GOTPCRELX
);
15529 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15534 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15536 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15538 fixp
->fx_subsy
= 0;
15541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15544 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15545 to section. Since PLT32 relocation must be against symbols,
15546 turn such PLT32 relocation into PC32 relocation. */
15548 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15549 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15550 && symbol_section_p (fixp
->fx_addsy
))
15551 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15554 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15555 && fixp
->fx_tcbit2
)
15556 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15565 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15568 bfd_reloc_code_real_type code
;
15570 switch (fixp
->fx_r_type
)
15572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15575 case BFD_RELOC_SIZE32
:
15576 case BFD_RELOC_SIZE64
:
15578 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15579 && (!fixp
->fx_subsy
15580 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15581 sym
= fixp
->fx_addsy
;
15582 else if (fixp
->fx_subsy
15583 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15584 && (!fixp
->fx_addsy
15585 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15586 sym
= fixp
->fx_subsy
;
15589 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15591 /* Resolve size relocation against local symbol to size of
15592 the symbol plus addend. */
15593 valueT value
= S_GET_SIZE (sym
);
15595 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15596 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15597 if (sym
== fixp
->fx_subsy
)
15600 if (fixp
->fx_addsy
)
15601 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15603 else if (fixp
->fx_subsy
)
15604 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15605 value
+= fixp
->fx_offset
;
15606 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15608 && !fits_in_unsigned_long (value
))
15609 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15610 _("symbol size computation overflow"));
15611 fixp
->fx_addsy
= NULL
;
15612 fixp
->fx_subsy
= NULL
;
15613 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15616 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15618 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15619 "unsupported expression involving @size");
15623 /* Fall through. */
15625 case BFD_RELOC_X86_64_PLT32
:
15626 case BFD_RELOC_X86_64_GOT32
:
15627 case BFD_RELOC_X86_64_GOTPCREL
:
15628 case BFD_RELOC_X86_64_GOTPCRELX
:
15629 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15630 case BFD_RELOC_386_PLT32
:
15631 case BFD_RELOC_386_GOT32
:
15632 case BFD_RELOC_386_GOT32X
:
15633 case BFD_RELOC_386_GOTOFF
:
15634 case BFD_RELOC_386_GOTPC
:
15635 case BFD_RELOC_386_TLS_GD
:
15636 case BFD_RELOC_386_TLS_LDM
:
15637 case BFD_RELOC_386_TLS_LDO_32
:
15638 case BFD_RELOC_386_TLS_IE_32
:
15639 case BFD_RELOC_386_TLS_IE
:
15640 case BFD_RELOC_386_TLS_GOTIE
:
15641 case BFD_RELOC_386_TLS_LE_32
:
15642 case BFD_RELOC_386_TLS_LE
:
15643 case BFD_RELOC_386_TLS_GOTDESC
:
15644 case BFD_RELOC_386_TLS_DESC_CALL
:
15645 case BFD_RELOC_X86_64_TLSGD
:
15646 case BFD_RELOC_X86_64_TLSLD
:
15647 case BFD_RELOC_X86_64_DTPOFF32
:
15648 case BFD_RELOC_X86_64_DTPOFF64
:
15649 case BFD_RELOC_X86_64_GOTTPOFF
:
15650 case BFD_RELOC_X86_64_TPOFF32
:
15651 case BFD_RELOC_X86_64_TPOFF64
:
15652 case BFD_RELOC_X86_64_GOTOFF64
:
15653 case BFD_RELOC_X86_64_GOTPC32
:
15654 case BFD_RELOC_X86_64_GOT64
:
15655 case BFD_RELOC_X86_64_GOTPCREL64
:
15656 case BFD_RELOC_X86_64_GOTPC64
:
15657 case BFD_RELOC_X86_64_GOTPLT64
:
15658 case BFD_RELOC_X86_64_PLTOFF64
:
15659 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15660 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15661 case BFD_RELOC_RVA
:
15662 case BFD_RELOC_VTABLE_ENTRY
:
15663 case BFD_RELOC_VTABLE_INHERIT
:
15665 case BFD_RELOC_32_SECREL
:
15666 case BFD_RELOC_16_SECIDX
:
15668 code
= fixp
->fx_r_type
;
15670 case BFD_RELOC_X86_64_32S
:
15671 if (!fixp
->fx_pcrel
)
15673 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15674 code
= fixp
->fx_r_type
;
15677 /* Fall through. */
15679 if (fixp
->fx_pcrel
)
15681 switch (fixp
->fx_size
)
15684 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15685 _("can not do %d byte pc-relative relocation"),
15687 code
= BFD_RELOC_32_PCREL
;
15689 case 1: code
= BFD_RELOC_8_PCREL
; break;
15690 case 2: code
= BFD_RELOC_16_PCREL
; break;
15691 case 4: code
= BFD_RELOC_32_PCREL
; break;
15693 case 8: code
= BFD_RELOC_64_PCREL
; break;
15699 switch (fixp
->fx_size
)
15702 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15703 _("can not do %d byte relocation"),
15705 code
= BFD_RELOC_32
;
15707 case 1: code
= BFD_RELOC_8
; break;
15708 case 2: code
= BFD_RELOC_16
; break;
15709 case 4: code
= BFD_RELOC_32
; break;
15711 case 8: code
= BFD_RELOC_64
; break;
15718 if ((code
== BFD_RELOC_32
15719 || code
== BFD_RELOC_32_PCREL
15720 || code
== BFD_RELOC_X86_64_32S
)
15722 && fixp
->fx_addsy
== GOT_symbol
)
15725 code
= BFD_RELOC_386_GOTPC
;
15727 code
= BFD_RELOC_X86_64_GOTPC32
;
15729 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15731 && fixp
->fx_addsy
== GOT_symbol
)
15733 code
= BFD_RELOC_X86_64_GOTPC64
;
15736 rel
= XNEW (arelent
);
15737 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15738 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15740 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15742 if (!use_rela_relocations
)
15744 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15745 vtable entry to be used in the relocation's section offset. */
15746 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15747 rel
->address
= fixp
->fx_offset
;
15748 #if defined (OBJ_COFF) && defined (TE_PE)
15749 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15750 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15755 /* Use the rela in 64bit mode. */
15758 if (disallow_64bit_reloc
)
15761 case BFD_RELOC_X86_64_DTPOFF64
:
15762 case BFD_RELOC_X86_64_TPOFF64
:
15763 case BFD_RELOC_64_PCREL
:
15764 case BFD_RELOC_X86_64_GOTOFF64
:
15765 case BFD_RELOC_X86_64_GOT64
:
15766 case BFD_RELOC_X86_64_GOTPCREL64
:
15767 case BFD_RELOC_X86_64_GOTPC64
:
15768 case BFD_RELOC_X86_64_GOTPLT64
:
15769 case BFD_RELOC_X86_64_PLTOFF64
:
15770 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15771 _("cannot represent relocation type %s in x32 mode"),
15772 bfd_get_reloc_code_name (code
));
15778 if (!fixp
->fx_pcrel
)
15779 rel
->addend
= fixp
->fx_offset
;
15783 case BFD_RELOC_X86_64_PLT32
:
15784 case BFD_RELOC_X86_64_GOT32
:
15785 case BFD_RELOC_X86_64_GOTPCREL
:
15786 case BFD_RELOC_X86_64_GOTPCRELX
:
15787 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15788 case BFD_RELOC_X86_64_TLSGD
:
15789 case BFD_RELOC_X86_64_TLSLD
:
15790 case BFD_RELOC_X86_64_GOTTPOFF
:
15791 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15792 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15793 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15796 rel
->addend
= (section
->vma
15798 + fixp
->fx_addnumber
15799 + md_pcrel_from (fixp
));
15804 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15805 if (rel
->howto
== NULL
)
15807 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15808 _("cannot represent relocation type %s"),
15809 bfd_get_reloc_code_name (code
));
15810 /* Set howto to a garbage value so that we can keep going. */
15811 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15812 gas_assert (rel
->howto
!= NULL
);
15818 #include "tc-i386-intel.c"
15821 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15823 int saved_naked_reg
;
15824 char saved_register_dot
;
15826 saved_naked_reg
= allow_naked_reg
;
15827 allow_naked_reg
= 1;
15828 saved_register_dot
= register_chars
['.'];
15829 register_chars
['.'] = '.';
15830 allow_pseudo_reg
= 1;
15831 expression_and_evaluate (exp
);
15832 allow_pseudo_reg
= 0;
15833 register_chars
['.'] = saved_register_dot
;
15834 allow_naked_reg
= saved_naked_reg
;
15836 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15838 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15840 exp
->X_op
= O_constant
;
15841 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15842 .dw2_regnum
[flag_code
>> 1];
15845 exp
->X_op
= O_illegal
;
15850 tc_x86_frame_initial_instructions (void)
15852 static unsigned int sp_regno
[2];
15854 if (!sp_regno
[flag_code
>> 1])
15856 char *saved_input
= input_line_pointer
;
15857 char sp
[][4] = {"esp", "rsp"};
15860 input_line_pointer
= sp
[flag_code
>> 1];
15861 tc_x86_parse_to_dw2regnum (&exp
);
15862 gas_assert (exp
.X_op
== O_constant
);
15863 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15864 input_line_pointer
= saved_input
;
15867 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15868 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15872 x86_dwarf2_addr_size (void)
15874 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15875 if (x86_elf_abi
== X86_64_X32_ABI
)
15878 return bfd_arch_bits_per_address (stdoutput
) / 8;
15882 i386_elf_section_type (const char *str
, size_t len
)
15884 if (flag_code
== CODE_64BIT
15885 && len
== sizeof ("unwind") - 1
15886 && startswith (str
, "unwind"))
15887 return SHT_X86_64_UNWIND
;
15894 i386_solaris_fix_up_eh_frame (segT sec
)
15896 if (flag_code
== CODE_64BIT
)
15897 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15903 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15907 exp
.X_op
= O_secrel
;
15908 exp
.X_add_symbol
= symbol
;
15909 exp
.X_add_number
= 0;
15910 emit_expr (&exp
, size
);
15914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15915 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15918 x86_64_section_letter (int letter
, const char **ptr_msg
)
15920 if (flag_code
== CODE_64BIT
)
15923 return SHF_X86_64_LARGE
;
15925 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15928 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15933 handle_large_common (int small ATTRIBUTE_UNUSED
)
15935 if (flag_code
!= CODE_64BIT
)
15937 s_comm_internal (0, elf_common_parse
);
15938 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15942 static segT lbss_section
;
15943 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15944 asection
*saved_bss_section
= bss_section
;
15946 if (lbss_section
== NULL
)
15948 flagword applicable
;
15949 segT seg
= now_seg
;
15950 subsegT subseg
= now_subseg
;
15952 /* The .lbss section is for local .largecomm symbols. */
15953 lbss_section
= subseg_new (".lbss", 0);
15954 applicable
= bfd_applicable_section_flags (stdoutput
);
15955 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15956 seg_info (lbss_section
)->bss
= 1;
15958 subseg_set (seg
, subseg
);
15961 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15962 bss_section
= lbss_section
;
15964 s_comm_internal (0, elf_common_parse
);
15966 elf_com_section_ptr
= saved_com_section_ptr
;
15967 bss_section
= saved_bss_section
;
15970 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */