1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* ISA extensions available in 64-bit mode only. */
808 static const i386_cpu_flags cpu_64_flags
= CPU_ANY_64_FLAGS
;
810 /* If we have selected a cpu we are generating instructions for. */
811 static int cpu_arch_tune_set
= 0;
813 /* Cpu we are generating instructions for. */
814 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
816 /* CPU instruction set architecture used. */
817 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of instruction set architecture used. */
820 i386_cpu_flags cpu_arch_isa_flags
;
822 /* If set, conditional jumps are not automatically promoted to handle
823 larger than a byte offset. */
824 static bool no_cond_jump_promotion
= false;
826 /* This will be set from an expression parser hook if there's any
827 applicable operator involved in an expression. */
830 expr_operator_present
,
834 /* Encode SSE instructions with VEX prefix. */
835 static unsigned int sse2avx
;
837 /* Encode aligned vector move as unaligned vector move. */
838 static unsigned int use_unaligned_vector_move
;
840 /* Maximum permitted vector size. */
841 #define VSZ_DEFAULT VSZ512
842 static unsigned int vector_size
= VSZ_DEFAULT
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
977 #define VECARCH(n, e, d, v) \
978 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
979 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
981 static const arch_entry cpu_arch
[] =
983 /* Do not replace the first two entries - i386_target_format() and
984 set_cpu_arch() rely on them being there in this order. */
985 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
986 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
987 ARCH (i8086
, UNKNOWN
, NONE
, false),
988 ARCH (i186
, UNKNOWN
, 186, false),
989 ARCH (i286
, UNKNOWN
, 286, false),
990 ARCH (i386
, I386
, 386, false),
991 ARCH (i486
, I486
, 486, false),
992 ARCH (i586
, PENTIUM
, 586, false),
993 ARCH (pentium
, PENTIUM
, 586, false),
994 ARCH (i686
, I686
, 686, false),
995 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
996 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
997 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
998 ARCH (pentium4
, PENTIUM4
, P4
, false),
999 ARCH (prescott
, NOCONA
, CORE
, false),
1000 ARCH (nocona
, NOCONA
, NOCONA
, false),
1001 ARCH (yonah
, CORE
, CORE
, true),
1002 ARCH (core
, CORE
, CORE
, false),
1003 ARCH (merom
, CORE2
, CORE2
, true),
1004 ARCH (core2
, CORE2
, CORE2
, false),
1005 ARCH (corei7
, COREI7
, COREI7
, false),
1006 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1007 ARCH (k6
, K6
, K6
, false),
1008 ARCH (k6_2
, K6
, K6_2
, false),
1009 ARCH (athlon
, ATHLON
, ATHLON
, false),
1010 ARCH (sledgehammer
, K8
, K8
, true),
1011 ARCH (opteron
, K8
, K8
, false),
1012 ARCH (k8
, K8
, K8
, false),
1013 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1014 ARCH (bdver1
, BD
, BDVER1
, false),
1015 ARCH (bdver2
, BD
, BDVER2
, false),
1016 ARCH (bdver3
, BD
, BDVER3
, false),
1017 ARCH (bdver4
, BD
, BDVER4
, false),
1018 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1019 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1020 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1021 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1022 ARCH (btver1
, BT
, BTVER1
, false),
1023 ARCH (btver2
, BT
, BTVER2
, false),
1025 SUBARCH (8087, 8087, ANY_8087
, false),
1026 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1027 SUBARCH (287, 287, ANY_287
, false),
1028 SUBARCH (387, 387, ANY_387
, false),
1029 SUBARCH (687, 687, ANY_687
, false),
1030 SUBARCH (cmov
, CMOV
, CMOV
, false),
1031 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1032 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1033 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1034 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1035 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1036 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1037 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1038 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1039 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1040 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1041 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1042 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1043 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1044 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1045 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1046 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1047 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1048 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1049 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1050 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1051 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1052 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1053 SUBARCH (smx
, SMX
, SMX
, false),
1054 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1055 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1056 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1057 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1058 SUBARCH (aes
, AES
, ANY_AES
, false),
1059 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1060 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1061 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1062 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1063 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1064 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1065 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1066 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1067 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1068 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1069 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1070 SUBARCH (cx16
, CX16
, CX16
, false),
1071 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1072 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1073 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1074 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1075 SUBARCH (hle
, HLE
, HLE
, false),
1076 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1077 SUBARCH (tsx
, TSX
, TSX
, false),
1078 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1079 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1080 SUBARCH (nop
, NOP
, NOP
, false),
1081 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1082 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1083 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1084 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1085 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1086 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1087 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1088 SUBARCH (abm
, ABM
, ABM
, false),
1089 SUBARCH (bmi
, BMI
, BMI
, false),
1090 SUBARCH (tbm
, TBM
, TBM
, false),
1091 SUBARCH (adx
, ADX
, ADX
, false),
1092 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1093 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1094 SUBARCH (smap
, SMAP
, SMAP
, false),
1095 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1096 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1097 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1098 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1099 SUBARCH (se1
, SE1
, SE1
, false),
1100 SUBARCH (clwb
, CLWB
, CLWB
, false),
1101 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1102 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1103 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1104 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1105 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1106 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1107 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1108 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1109 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1110 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1111 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1112 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1113 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1114 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1115 SUBARCH (ibt
, IBT
, IBT
, false),
1116 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1117 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1118 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1119 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1120 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1121 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1122 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1123 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1124 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1125 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1126 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1127 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1128 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1129 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1130 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1131 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1132 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1133 ANY_AVX512_VP2INTERSECT
, reset
),
1134 SUBARCH (tdx
, TDX
, TDX
, false),
1135 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1136 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1137 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1138 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1139 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1140 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1141 SUBARCH (kl
, KL
, ANY_KL
, false),
1142 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1143 SUBARCH (uintr
, UINTR
, UINTR
, false),
1144 SUBARCH (hreset
, HRESET
, HRESET
, false),
1145 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1146 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1147 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1148 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1149 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1150 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1151 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1152 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1153 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1154 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1155 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1156 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1157 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1158 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1159 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1160 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1161 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1162 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1163 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1170 /* Like s_lcomm_internal in gas/read.c but the alignment string
1171 is allowed to be optional. */
1174 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1181 && *input_line_pointer
== ',')
1183 align
= parse_align (needs_align
- 1);
1185 if (align
== (addressT
) -1)
1200 bss_alloc (symbolP
, size
, align
);
1205 pe_lcomm (int needs_align
)
1207 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1211 const pseudo_typeS md_pseudo_table
[] =
1213 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1214 {"align", s_align_bytes
, 0},
1216 {"align", s_align_ptwo
, 0},
1218 {"arch", set_cpu_arch
, 0},
1222 {"lcomm", pe_lcomm
, 1},
1224 {"ffloat", float_cons
, 'f'},
1225 {"dfloat", float_cons
, 'd'},
1226 {"tfloat", float_cons
, 'x'},
1227 {"hfloat", float_cons
, 'h'},
1228 {"bfloat16", float_cons
, 'b'},
1230 {"slong", signed_cons
, 4},
1231 {"insn", s_insn
, 0},
1232 {"noopt", s_ignore
, 0},
1233 {"optim", s_ignore
, 0},
1234 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1235 {"code16", set_code_flag
, CODE_16BIT
},
1236 {"code32", set_code_flag
, CODE_32BIT
},
1238 {"code64", set_code_flag
, CODE_64BIT
},
1240 {"intel_syntax", set_intel_syntax
, 1},
1241 {"att_syntax", set_intel_syntax
, 0},
1242 {"intel_mnemonic", set_intel_mnemonic
, 1},
1243 {"att_mnemonic", set_intel_mnemonic
, 0},
1244 {"allow_index_reg", set_allow_index_reg
, 1},
1245 {"disallow_index_reg", set_allow_index_reg
, 0},
1246 {"sse_check", set_check
, 0},
1247 {"operand_check", set_check
, 1},
1248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1249 {"largecomm", handle_large_common
, 0},
1251 {"file", dwarf2_directive_file
, 0},
1252 {"loc", dwarf2_directive_loc
, 0},
1253 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1256 {"secrel32", pe_directive_secrel
, 0},
1257 {"secidx", pe_directive_secidx
, 0},
1262 /* For interface with expression (). */
1263 extern char *input_line_pointer
;
1265 /* Hash table for instruction mnemonic lookup. */
1266 static htab_t op_hash
;
1268 /* Hash table for register lookup. */
1269 static htab_t reg_hash
;
1271 /* Various efficient no-op patterns for aligning code labels.
1272 Note: Don't try to assemble the instructions in the comments.
1273 0L and 0w are not legal. */
1274 static const unsigned char f32_1
[] =
1276 static const unsigned char f32_2
[] =
1277 {0x66,0x90}; /* xchg %ax,%ax */
1278 static const unsigned char f32_3
[] =
1279 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1280 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1281 static const unsigned char f32_5
[] =
1282 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1283 static const unsigned char f32_6
[] =
1284 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1285 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1286 static const unsigned char f32_8
[] =
1287 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1288 static const unsigned char f64_3
[] =
1289 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1290 static const unsigned char f64_4
[] =
1291 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1292 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1293 static const unsigned char f64_6
[] =
1294 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1295 static const unsigned char f64_7
[] =
1296 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1297 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1298 static const unsigned char f64_9
[] =
1299 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1300 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1301 static const unsigned char f16_3
[] =
1302 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1303 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1304 static const unsigned char f16_5
[] =
1305 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1306 static const unsigned char jump_disp8
[] =
1307 {0xeb}; /* jmp disp8 */
1308 static const unsigned char jump32_disp32
[] =
1309 {0xe9}; /* jmp disp32 */
1310 static const unsigned char jump16_disp32
[] =
1311 {0x66,0xe9}; /* jmp disp32 */
1312 /* 32-bit NOPs patterns. */
1313 static const unsigned char *const f32_patt
[] = {
1314 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1316 /* 64-bit NOPs patterns. */
1317 static const unsigned char *const f64_patt
[] = {
1318 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1320 /* 16-bit NOPs patterns. */
1321 static const unsigned char *const f16_patt
[] = {
1322 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1324 /* nopl (%[re]ax) */
1325 static const unsigned char alt_3
[] =
1327 /* nopl 0(%[re]ax) */
1328 static const unsigned char alt_4
[] =
1329 {0x0f,0x1f,0x40,0x00};
1330 /* nopl 0(%[re]ax,%[re]ax,1) */
1331 #define alt_5 (alt_6 + 1)
1332 /* nopw 0(%[re]ax,%[re]ax,1) */
1333 static const unsigned char alt_6
[] =
1334 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1335 /* nopl 0L(%[re]ax) */
1336 static const unsigned char alt_7
[] =
1337 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1338 /* nopl 0L(%[re]ax,%[re]ax,1) */
1339 #define alt_8 (alt_9 + 1)
1340 /* nopw 0L(%[re]ax,%[re]ax,1) */
1341 static const unsigned char alt_9
[] =
1342 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1343 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1344 #define alt_10 (alt_11 + 1)
1345 /* data16 nopw %cs:0L(%eax,%eax,1) */
1346 static const unsigned char alt_11
[] =
1347 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1348 /* 32-bit and 64-bit NOPs patterns. */
1349 static const unsigned char *const alt_patt
[] = {
1350 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1351 alt_9
, alt_10
, alt_11
1354 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1355 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1358 i386_output_nops (char *where
, const unsigned char *const *patt
,
1359 int count
, int max_single_nop_size
)
1362 /* Place the longer NOP first. */
1365 const unsigned char *nops
;
1367 if (max_single_nop_size
< 1)
1369 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1370 max_single_nop_size
);
1374 nops
= patt
[max_single_nop_size
- 1];
1375 last
= count
% max_single_nop_size
;
1378 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1379 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1383 nops
= patt
[last
- 1];
1384 memcpy (where
+ offset
, nops
, last
);
1389 fits_in_imm7 (offsetT num
)
1391 return (num
& 0x7f) == num
;
1395 fits_in_imm31 (offsetT num
)
1397 return (num
& 0x7fffffff) == num
;
1400 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1401 single NOP instruction LIMIT. */
1404 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1406 const unsigned char *const *patt
= NULL
;
1407 int max_single_nop_size
;
1408 /* Maximum number of NOPs before switching to jump over NOPs. */
1409 int max_number_of_nops
;
1411 switch (fragP
->fr_type
)
1416 case rs_machine_dependent
:
1417 /* Allow NOP padding for jumps and calls. */
1418 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1419 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1426 /* We need to decide which NOP sequence to use for 32bit and
1427 64bit. When -mtune= is used:
1429 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1430 PROCESSOR_GENERIC32, f32_patt will be used.
1431 2. For the rest, alt_patt will be used.
1433 When -mtune= isn't used, alt_patt will be used if
1434 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1437 When -march= or .arch is used, we can't use anything beyond
1438 cpu_arch_isa_flags. */
1440 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1443 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1444 /* Limit number of NOPs to 2 in 16-bit mode. */
1445 max_number_of_nops
= 2;
1449 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1450 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1452 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1453 explicitly disabled. */
1454 switch (fragP
->tc_frag_data
.tune
)
1456 case PROCESSOR_UNKNOWN
:
1457 /* We use cpu_arch_isa_flags to check if we SHOULD
1458 optimize with nops. */
1459 if (fragP
->tc_frag_data
.isanop
)
1463 case PROCESSOR_PENTIUMPRO
:
1464 case PROCESSOR_PENTIUM4
:
1465 case PROCESSOR_NOCONA
:
1466 case PROCESSOR_CORE
:
1467 case PROCESSOR_CORE2
:
1468 case PROCESSOR_COREI7
:
1469 case PROCESSOR_GENERIC64
:
1471 case PROCESSOR_ATHLON
:
1473 case PROCESSOR_AMDFAM10
:
1475 case PROCESSOR_ZNVER
:
1477 if (fragP
->tc_frag_data
.cpunop
)
1481 case PROCESSOR_I386
:
1482 case PROCESSOR_I486
:
1483 case PROCESSOR_PENTIUM
:
1484 case PROCESSOR_I686
:
1485 case PROCESSOR_IAMCU
:
1486 case PROCESSOR_GENERIC32
:
1488 case PROCESSOR_NONE
:
1494 switch (fragP
->tc_frag_data
.tune
)
1496 case PROCESSOR_UNKNOWN
:
1497 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1498 PROCESSOR_UNKNOWN. */
1503 /* We use cpu_arch_isa_flags to check if we CAN optimize
1505 if (fragP
->tc_frag_data
.isanop
)
1509 case PROCESSOR_NONE
:
1514 if (patt
!= alt_patt
)
1516 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1517 : ARRAY_SIZE (f64_patt
);
1518 /* Limit number of NOPs to 2 for older processors. */
1519 max_number_of_nops
= 2;
1523 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1524 /* Limit number of NOPs to 7 for newer processors. */
1525 max_number_of_nops
= 7;
1530 limit
= max_single_nop_size
;
1532 if (fragP
->fr_type
== rs_fill_nop
)
1534 /* Output NOPs for .nop directive. */
1535 if (limit
> max_single_nop_size
)
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("invalid single nop size: %d "
1539 "(expect within [0, %d])"),
1540 limit
, max_single_nop_size
);
1544 else if (fragP
->fr_type
!= rs_machine_dependent
)
1545 fragP
->fr_var
= count
;
1547 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1549 /* Generate jump over NOPs. */
1550 offsetT disp
= count
- 2;
1551 if (fits_in_imm7 (disp
))
1553 /* Use "jmp disp8" if possible. */
1555 where
[0] = jump_disp8
[0];
1561 unsigned int size_of_jump
;
1563 if (flag_code
== CODE_16BIT
)
1565 where
[0] = jump16_disp32
[0];
1566 where
[1] = jump16_disp32
[1];
1571 where
[0] = jump32_disp32
[0];
1575 count
-= size_of_jump
+ 4;
1576 if (!fits_in_imm31 (count
))
1578 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1579 _("jump over nop padding out of range"));
1583 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1584 where
+= size_of_jump
+ 4;
1588 /* Generate multiple NOPs. */
1589 i386_output_nops (where
, patt
, count
, limit
);
1593 operand_type_all_zero (const union i386_operand_type
*x
)
1595 switch (ARRAY_SIZE(x
->array
))
1606 return !x
->array
[0];
1613 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1615 switch (ARRAY_SIZE(x
->array
))
1631 x
->bitfield
.class = ClassNone
;
1632 x
->bitfield
.instance
= InstanceNone
;
1636 operand_type_equal (const union i386_operand_type
*x
,
1637 const union i386_operand_type
*y
)
1639 switch (ARRAY_SIZE(x
->array
))
1642 if (x
->array
[2] != y
->array
[2])
1646 if (x
->array
[1] != y
->array
[1])
1650 return x
->array
[0] == y
->array
[0];
1658 _is_cpu (const i386_cpu_attr
*a
, enum i386_cpu cpu
)
1662 case Cpu287
: return a
->bitfield
.cpu287
;
1663 case Cpu387
: return a
->bitfield
.cpu387
;
1664 case Cpu3dnow
: return a
->bitfield
.cpu3dnow
;
1665 case Cpu3dnowA
: return a
->bitfield
.cpu3dnowa
;
1666 case CpuAVX
: return a
->bitfield
.cpuavx
;
1667 case CpuHLE
: return a
->bitfield
.cpuhle
;
1668 case CpuAVX512F
: return a
->bitfield
.cpuavx512f
;
1669 case CpuAVX512VL
: return a
->bitfield
.cpuavx512vl
;
1670 case Cpu64
: return a
->bitfield
.cpu64
;
1671 case CpuNo64
: return a
->bitfield
.cpuno64
;
1673 gas_assert (cpu
< CpuAttrEnums
);
1675 return a
->bitfield
.isa
== cpu
+ 1u;
1679 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1681 return _is_cpu(&t
->cpu
, cpu
);
1685 maybe_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1687 return _is_cpu(&t
->cpu_any
, cpu
);
1690 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1692 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1693 i386_cpu_flags f
= { .array
[0] = 0 };
1695 switch (ARRAY_SIZE(a
.array
))
1698 f
.array
[CpuAttrEnums
/ bps
]
1699 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1700 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1701 f
.array
[CpuAttrEnums
/ bps
+ 1]
1702 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1709 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1715 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1717 switch (ARRAY_SIZE(x
->array
))
1736 return !x
->array
[0];
1743 cpu_flags_equal (const union i386_cpu_flags
*x
,
1744 const union i386_cpu_flags
*y
)
1746 switch (ARRAY_SIZE(x
->array
))
1749 if (x
->array
[4] != y
->array
[4])
1753 if (x
->array
[3] != y
->array
[3])
1757 if (x
->array
[2] != y
->array
[2])
1761 if (x
->array
[1] != y
->array
[1])
1765 return x
->array
[0] == y
->array
[0];
1773 cpu_flags_check_cpu64 (const insn_template
*t
)
1775 return flag_code
== CODE_64BIT
1776 ? !t
->cpu
.bitfield
.cpuno64
1777 : !t
->cpu
.bitfield
.cpu64
;
1780 static INLINE i386_cpu_flags
1781 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1783 switch (ARRAY_SIZE (x
.array
))
1786 x
.array
[4] &= y
.array
[4];
1789 x
.array
[3] &= y
.array
[3];
1792 x
.array
[2] &= y
.array
[2];
1795 x
.array
[1] &= y
.array
[1];
1798 x
.array
[0] &= y
.array
[0];
1806 static INLINE i386_cpu_flags
1807 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1809 switch (ARRAY_SIZE (x
.array
))
1812 x
.array
[4] |= y
.array
[4];
1815 x
.array
[3] |= y
.array
[3];
1818 x
.array
[2] |= y
.array
[2];
1821 x
.array
[1] |= y
.array
[1];
1824 x
.array
[0] |= y
.array
[0];
1832 static INLINE i386_cpu_flags
1833 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1835 switch (ARRAY_SIZE (x
.array
))
1838 x
.array
[4] &= ~y
.array
[4];
1841 x
.array
[3] &= ~y
.array
[3];
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1860 static INLINE
bool need_evex_encoding (void)
1862 return i
.vec_encoding
== vex_encoding_evex
1863 || i
.vec_encoding
== vex_encoding_evex512
1867 #define CPU_FLAGS_ARCH_MATCH 0x1
1868 #define CPU_FLAGS_64BIT_MATCH 0x2
1870 #define CPU_FLAGS_PERFECT_MATCH \
1871 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1873 /* Return CPU flags match bits. */
1876 cpu_flags_match (const insn_template
*t
)
1878 i386_cpu_flags cpu
, active
, all
= cpu_flags_from_attr (t
->cpu
);
1879 i386_cpu_flags any
= cpu_flags_from_attr (t
->cpu_any
);
1880 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1882 all
.bitfield
.cpu64
= 0;
1883 all
.bitfield
.cpuno64
= 0;
1884 gas_assert (!any
.bitfield
.cpu64
);
1885 gas_assert (!any
.bitfield
.cpuno64
);
1887 if (cpu_flags_all_zero (&all
) && cpu_flags_all_zero (&any
))
1889 /* This instruction is available on all archs. */
1890 return match
| CPU_FLAGS_ARCH_MATCH
;
1893 /* This instruction is available only on some archs. */
1895 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1896 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1898 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1899 know that EVEX encoding will be needed. */
1900 if ((any
.bitfield
.cpuavx
|| any
.bitfield
.cpuavx2
|| any
.bitfield
.cpufma
)
1901 && (any
.bitfield
.cpuavx512f
|| any
.bitfield
.cpuavx512vl
))
1903 if (need_evex_encoding ())
1905 any
.bitfield
.cpuavx
= 0;
1906 any
.bitfield
.cpuavx2
= 0;
1907 any
.bitfield
.cpufma
= 0;
1909 /* need_evex_encoding() isn't reliable before operands were
1911 else if (i
.operands
)
1913 any
.bitfield
.cpuavx512f
= 0;
1914 any
.bitfield
.cpuavx512vl
= 0;
1919 if (flag_code
!= CODE_64BIT
)
1920 active
= cpu_flags_and_not (cpu_arch_flags
, cpu_64_flags
);
1922 active
= cpu_arch_flags
;
1923 cpu
= cpu_flags_and (all
, active
);
1924 if (cpu_flags_equal (&cpu
, &all
))
1926 /* AVX and AVX2 present at the same time express an operand size
1927 dependency - strip AVX2 for the purposes here. The operand size
1928 dependent check occurs in check_vecOperands(). */
1929 if (any
.bitfield
.cpuavx
&& any
.bitfield
.cpuavx2
)
1930 any
.bitfield
.cpuavx2
= 0;
1932 cpu
= cpu_flags_and (any
, active
);
1933 if (cpu_flags_all_zero (&any
) || !cpu_flags_all_zero (&cpu
))
1935 if (all
.bitfield
.cpuavx
)
1937 /* We need to check SSE2AVX with AVX. */
1938 if (!t
->opcode_modifier
.sse2avx
1939 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1940 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 match
|= CPU_FLAGS_ARCH_MATCH
;
1949 static INLINE i386_operand_type
1950 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1952 if (x
.bitfield
.class != y
.bitfield
.class)
1953 x
.bitfield
.class = ClassNone
;
1954 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1955 x
.bitfield
.instance
= InstanceNone
;
1957 switch (ARRAY_SIZE (x
.array
))
1960 x
.array
[2] &= y
.array
[2];
1963 x
.array
[1] &= y
.array
[1];
1966 x
.array
[0] &= y
.array
[0];
1974 static INLINE i386_operand_type
1975 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1977 gas_assert (y
.bitfield
.class == ClassNone
);
1978 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1980 switch (ARRAY_SIZE (x
.array
))
1983 x
.array
[2] &= ~y
.array
[2];
1986 x
.array
[1] &= ~y
.array
[1];
1989 x
.array
[0] &= ~y
.array
[0];
1997 static INLINE i386_operand_type
1998 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2000 gas_assert (x
.bitfield
.class == ClassNone
||
2001 y
.bitfield
.class == ClassNone
||
2002 x
.bitfield
.class == y
.bitfield
.class);
2003 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2004 y
.bitfield
.instance
== InstanceNone
||
2005 x
.bitfield
.instance
== y
.bitfield
.instance
);
2007 switch (ARRAY_SIZE (x
.array
))
2010 x
.array
[2] |= y
.array
[2];
2013 x
.array
[1] |= y
.array
[1];
2016 x
.array
[0] |= y
.array
[0];
2024 static INLINE i386_operand_type
2025 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2027 gas_assert (y
.bitfield
.class == ClassNone
);
2028 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2030 switch (ARRAY_SIZE (x
.array
))
2033 x
.array
[2] ^= y
.array
[2];
2036 x
.array
[1] ^= y
.array
[1];
2039 x
.array
[0] ^= y
.array
[0];
2047 static const i386_operand_type anydisp
= {
2048 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2060 operand_type_check (i386_operand_type t
, enum operand_type c
)
2065 return t
.bitfield
.class == Reg
;
2068 return (t
.bitfield
.imm8
2072 || t
.bitfield
.imm32s
2073 || t
.bitfield
.imm64
);
2076 return (t
.bitfield
.disp8
2077 || t
.bitfield
.disp16
2078 || t
.bitfield
.disp32
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp64
2086 || t
.bitfield
.baseindex
);
2095 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2096 between operand GIVEN and opeand WANTED for instruction template T. */
2099 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2102 return !((i
.types
[given
].bitfield
.byte
2103 && !t
->operand_types
[wanted
].bitfield
.byte
)
2104 || (i
.types
[given
].bitfield
.word
2105 && !t
->operand_types
[wanted
].bitfield
.word
)
2106 || (i
.types
[given
].bitfield
.dword
2107 && !t
->operand_types
[wanted
].bitfield
.dword
)
2108 || (i
.types
[given
].bitfield
.qword
2109 && (!t
->operand_types
[wanted
].bitfield
.qword
2110 /* Don't allow 64-bit (memory) operands outside of 64-bit
2111 mode, when they're used where a 64-bit GPR could also
2112 be used. Checking is needed for Intel Syntax only. */
2114 && flag_code
!= CODE_64BIT
2115 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2116 || t
->operand_types
[wanted
].bitfield
.class == Accum
2117 || t
->opcode_modifier
.isstring
))))
2118 || (i
.types
[given
].bitfield
.tbyte
2119 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2122 /* Return 1 if there is no conflict in SIMD register between operand
2123 GIVEN and opeand WANTED for instruction template T. */
2126 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2129 return !((i
.types
[given
].bitfield
.xmmword
2130 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2131 || (i
.types
[given
].bitfield
.ymmword
2132 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2133 || (i
.types
[given
].bitfield
.zmmword
2134 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2135 || (i
.types
[given
].bitfield
.tmmword
2136 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2139 /* Return 1 if there is no conflict in any size between operand GIVEN
2140 and opeand WANTED for instruction template T. */
2143 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2146 return (match_operand_size (t
, wanted
, given
)
2147 && !((i
.types
[given
].bitfield
.unspecified
2148 && !i
.broadcast
.type
2149 && !i
.broadcast
.bytes
2150 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2151 || (i
.types
[given
].bitfield
.fword
2152 && !t
->operand_types
[wanted
].bitfield
.fword
)
2153 /* For scalar opcode templates to allow register and memory
2154 operands at the same time, some special casing is needed
2155 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2156 down-conversion vpmov*. */
2157 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2158 && t
->operand_types
[wanted
].bitfield
.byte
2159 + t
->operand_types
[wanted
].bitfield
.word
2160 + t
->operand_types
[wanted
].bitfield
.dword
2161 + t
->operand_types
[wanted
].bitfield
.qword
2162 > !!t
->opcode_modifier
.broadcast
)
2163 ? (i
.types
[given
].bitfield
.xmmword
2164 || i
.types
[given
].bitfield
.ymmword
2165 || i
.types
[given
].bitfield
.zmmword
)
2166 : !match_simd_size(t
, wanted
, given
))));
2169 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2170 operands for instruction template T, and it has MATCH_REVERSE set if there
2171 is no size conflict on any operands for the template with operands reversed
2172 (and the template allows for reversing in the first place). */
2174 #define MATCH_STRAIGHT 1
2175 #define MATCH_REVERSE 2
2177 static INLINE
unsigned int
2178 operand_size_match (const insn_template
*t
)
2180 unsigned int j
, match
= MATCH_STRAIGHT
;
2182 /* Don't check non-absolute jump instructions. */
2183 if (t
->opcode_modifier
.jump
2184 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2187 /* Check memory and accumulator operand size. */
2188 for (j
= 0; j
< i
.operands
; j
++)
2190 if (i
.types
[j
].bitfield
.class != Reg
2191 && i
.types
[j
].bitfield
.class != RegSIMD
2192 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2195 if (t
->operand_types
[j
].bitfield
.class == Reg
2196 && !match_operand_size (t
, j
, j
))
2202 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2203 && !match_simd_size (t
, j
, j
))
2209 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2210 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2216 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2223 if (!t
->opcode_modifier
.d
)
2226 /* Check reverse. */
2227 gas_assert (i
.operands
>= 2);
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 unsigned int given
= i
.operands
- j
- 1;
2233 /* For FMA4 and XOP insns VEX.W controls just the first two
2234 register operands. */
2235 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2236 given
= j
< 2 ? 1 - j
: j
;
2238 if (t
->operand_types
[j
].bitfield
.class == Reg
2239 && !match_operand_size (t
, j
, given
))
2242 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2243 && !match_simd_size (t
, j
, given
))
2246 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2247 && (!match_operand_size (t
, j
, given
)
2248 || !match_simd_size (t
, j
, given
)))
2251 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2255 return match
| MATCH_REVERSE
;
2259 operand_type_match (i386_operand_type overlap
,
2260 i386_operand_type given
)
2262 i386_operand_type temp
= overlap
;
2264 temp
.bitfield
.unspecified
= 0;
2265 temp
.bitfield
.byte
= 0;
2266 temp
.bitfield
.word
= 0;
2267 temp
.bitfield
.dword
= 0;
2268 temp
.bitfield
.fword
= 0;
2269 temp
.bitfield
.qword
= 0;
2270 temp
.bitfield
.tbyte
= 0;
2271 temp
.bitfield
.xmmword
= 0;
2272 temp
.bitfield
.ymmword
= 0;
2273 temp
.bitfield
.zmmword
= 0;
2274 temp
.bitfield
.tmmword
= 0;
2275 if (operand_type_all_zero (&temp
))
2278 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2282 i
.error
= operand_type_mismatch
;
2286 /* If given types g0 and g1 are registers they must be of the same type
2287 unless the expected operand type register overlap is null.
2288 Intel syntax sized memory operands are also checked here. */
2291 operand_type_register_match (i386_operand_type g0
,
2292 i386_operand_type t0
,
2293 i386_operand_type g1
,
2294 i386_operand_type t1
)
2296 if (g0
.bitfield
.class != Reg
2297 && g0
.bitfield
.class != RegSIMD
2298 && (g0
.bitfield
.unspecified
2299 || !operand_type_check (g0
, anymem
)))
2302 if (g1
.bitfield
.class != Reg
2303 && g1
.bitfield
.class != RegSIMD
2304 && (g1
.bitfield
.unspecified
2305 || !operand_type_check (g1
, anymem
)))
2308 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2309 && g0
.bitfield
.word
== g1
.bitfield
.word
2310 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2311 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2312 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2313 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2314 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2317 /* If expectations overlap in no more than a single size, all is fine. */
2318 g0
= operand_type_and (t0
, t1
);
2319 if (g0
.bitfield
.byte
2323 + g0
.bitfield
.xmmword
2324 + g0
.bitfield
.ymmword
2325 + g0
.bitfield
.zmmword
<= 1)
2328 i
.error
= register_type_mismatch
;
2333 static INLINE
unsigned int
2334 register_number (const reg_entry
*r
)
2336 unsigned int nr
= r
->reg_num
;
2338 if (r
->reg_flags
& RegRex
)
2341 if (r
->reg_flags
& RegVRex
)
2347 static INLINE
unsigned int
2348 mode_from_disp_size (i386_operand_type t
)
2350 if (t
.bitfield
.disp8
)
2352 else if (t
.bitfield
.disp16
2353 || t
.bitfield
.disp32
)
2360 fits_in_signed_byte (addressT num
)
2362 return num
+ 0x80 <= 0xff;
2366 fits_in_unsigned_byte (addressT num
)
2372 fits_in_unsigned_word (addressT num
)
2374 return num
<= 0xffff;
2378 fits_in_signed_word (addressT num
)
2380 return num
+ 0x8000 <= 0xffff;
2384 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2389 return num
+ 0x80000000 <= 0xffffffff;
2391 } /* fits_in_signed_long() */
2394 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2399 return num
<= 0xffffffff;
2401 } /* fits_in_unsigned_long() */
2403 static INLINE valueT
extend_to_32bit_address (addressT num
)
2406 if (fits_in_unsigned_long(num
))
2407 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2409 if (!fits_in_signed_long (num
))
2410 return num
& 0xffffffff;
2417 fits_in_disp8 (offsetT num
)
2419 int shift
= i
.memshift
;
2425 mask
= (1 << shift
) - 1;
2427 /* Return 0 if NUM isn't properly aligned. */
2431 /* Check if NUM will fit in 8bit after shift. */
2432 return fits_in_signed_byte (num
>> shift
);
2436 fits_in_imm4 (offsetT num
)
2438 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2439 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2442 static i386_operand_type
2443 smallest_imm_type (offsetT num
)
2445 i386_operand_type t
;
2447 operand_type_set (&t
, 0);
2448 t
.bitfield
.imm64
= 1;
2450 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2452 /* This code is disabled on the 486 because all the Imm1 forms
2453 in the opcode table are slower on the i486. They're the
2454 versions with the implicitly specified single-position
2455 displacement, which has another syntax if you really want to
2457 t
.bitfield
.imm1
= 1;
2458 t
.bitfield
.imm8
= 1;
2459 t
.bitfield
.imm8s
= 1;
2460 t
.bitfield
.imm16
= 1;
2461 t
.bitfield
.imm32
= 1;
2462 t
.bitfield
.imm32s
= 1;
2464 else if (fits_in_signed_byte (num
))
2466 if (fits_in_unsigned_byte (num
))
2467 t
.bitfield
.imm8
= 1;
2468 t
.bitfield
.imm8s
= 1;
2469 t
.bitfield
.imm16
= 1;
2470 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2471 t
.bitfield
.imm32
= 1;
2472 t
.bitfield
.imm32s
= 1;
2474 else if (fits_in_unsigned_byte (num
))
2476 t
.bitfield
.imm8
= 1;
2477 t
.bitfield
.imm16
= 1;
2478 t
.bitfield
.imm32
= 1;
2479 t
.bitfield
.imm32s
= 1;
2481 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2483 t
.bitfield
.imm16
= 1;
2484 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2485 t
.bitfield
.imm32
= 1;
2486 t
.bitfield
.imm32s
= 1;
2488 else if (fits_in_signed_long (num
))
2490 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_unsigned_long (num
))
2495 t
.bitfield
.imm32
= 1;
2501 offset_in_range (offsetT val
, int size
)
2507 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2508 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2510 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2512 case sizeof (val
): return val
;
2516 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2517 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2518 (uint64_t) val
, (uint64_t) (val
& mask
));
2523 static INLINE
const char *insn_name (const insn_template
*t
)
2525 return &i386_mnemonics
[t
->mnem_off
];
2538 a. PREFIX_EXIST if attempting to add a prefix where one from the
2539 same class already exists.
2540 b. PREFIX_LOCK if lock prefix is added.
2541 c. PREFIX_REP if rep/repne prefix is added.
2542 d. PREFIX_DS if ds prefix is added.
2543 e. PREFIX_OTHER if other prefix is added.
2546 static enum PREFIX_GROUP
2547 add_prefix (unsigned int prefix
)
2549 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2552 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2553 && flag_code
== CODE_64BIT
)
2555 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2556 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2557 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2558 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2569 case DS_PREFIX_OPCODE
:
2572 case CS_PREFIX_OPCODE
:
2573 case ES_PREFIX_OPCODE
:
2574 case FS_PREFIX_OPCODE
:
2575 case GS_PREFIX_OPCODE
:
2576 case SS_PREFIX_OPCODE
:
2580 case REPNE_PREFIX_OPCODE
:
2581 case REPE_PREFIX_OPCODE
:
2586 case LOCK_PREFIX_OPCODE
:
2595 case ADDR_PREFIX_OPCODE
:
2599 case DATA_PREFIX_OPCODE
:
2603 if (i
.prefix
[q
] != 0)
2611 i
.prefix
[q
] |= prefix
;
2614 as_bad (_("same type of prefix used twice"));
2620 update_code_flag (int value
, int check
)
2622 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2624 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2626 as_error (_("64bit mode not supported on `%s'."),
2627 cpu_arch_name
? cpu_arch_name
: default_arch
);
2631 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2633 as_error (_("32bit mode not supported on `%s'."),
2634 cpu_arch_name
? cpu_arch_name
: default_arch
);
2638 flag_code
= (enum flag_code
) value
;
2640 stackop_size
= '\0';
2644 set_code_flag (int value
)
2646 update_code_flag (value
, 0);
2650 set_16bit_gcc_code_flag (int new_code_flag
)
2652 flag_code
= (enum flag_code
) new_code_flag
;
2653 if (flag_code
!= CODE_16BIT
)
2655 stackop_size
= LONG_MNEM_SUFFIX
;
2659 set_intel_syntax (int syntax_flag
)
2661 /* Find out if register prefixing is specified. */
2662 int ask_naked_reg
= 0;
2665 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2668 int e
= get_symbol_name (&string
);
2670 if (strcmp (string
, "prefix") == 0)
2672 else if (strcmp (string
, "noprefix") == 0)
2675 as_bad (_("bad argument to syntax directive."));
2676 (void) restore_line_pointer (e
);
2678 demand_empty_rest_of_line ();
2680 intel_syntax
= syntax_flag
;
2682 if (ask_naked_reg
== 0)
2683 allow_naked_reg
= (intel_syntax
2684 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2686 allow_naked_reg
= (ask_naked_reg
< 0);
2688 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2690 register_prefix
= allow_naked_reg
? "" : "%";
2694 set_intel_mnemonic (int mnemonic_flag
)
2696 intel_mnemonic
= mnemonic_flag
;
2700 set_allow_index_reg (int flag
)
2702 allow_index_reg
= flag
;
2706 set_check (int what
)
2708 enum check_kind
*kind
;
2713 kind
= &operand_check
;
2724 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2727 int e
= get_symbol_name (&string
);
2729 if (strcmp (string
, "none") == 0)
2731 else if (strcmp (string
, "warning") == 0)
2732 *kind
= check_warning
;
2733 else if (strcmp (string
, "error") == 0)
2734 *kind
= check_error
;
2736 as_bad (_("bad argument to %s_check directive."), str
);
2737 (void) restore_line_pointer (e
);
2740 as_bad (_("missing argument for %s_check directive"), str
);
2742 demand_empty_rest_of_line ();
2746 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2747 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2750 static const char *arch
;
2752 /* Intel MCU is only supported on ELF. */
2758 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2759 use default_arch. */
2760 arch
= cpu_arch_name
;
2762 arch
= default_arch
;
2765 /* If we are targeting Intel MCU, we must enable it. */
2766 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2767 == new_flag
.bitfield
.cpuiamcu
)
2770 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2775 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2777 if (cpu_sub_arch_name
)
2778 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2779 pfx
, name
, (const char *) NULL
);
2781 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2784 static void isa_enable (unsigned int idx
)
2786 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2788 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2790 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2791 cpu_arch_flags
= flags
;
2794 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2797 static void isa_disable (unsigned int idx
)
2799 i386_cpu_flags flags
2800 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2802 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2804 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2805 cpu_arch_flags
= flags
;
2809 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2813 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2815 typedef struct arch_stack_entry
2817 const struct arch_stack_entry
*prev
;
2820 i386_cpu_flags flags
;
2821 i386_cpu_flags isa_flags
;
2822 enum processor_type isa
;
2823 enum flag_code flag_code
;
2824 unsigned int vector_size
;
2826 bool no_cond_jump_promotion
;
2828 static const arch_stack_entry
*arch_stack_top
;
2836 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2838 as_bad (_("missing cpu architecture"));
2839 input_line_pointer
++;
2843 e
= get_symbol_name (&s
);
2846 if (strcmp (string
, "push") == 0)
2848 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2850 top
->name
= cpu_arch_name
;
2851 if (cpu_sub_arch_name
)
2852 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2854 top
->sub_name
= NULL
;
2855 top
->flags
= cpu_arch_flags
;
2856 top
->isa
= cpu_arch_isa
;
2857 top
->isa_flags
= cpu_arch_isa_flags
;
2858 top
->flag_code
= flag_code
;
2859 top
->vector_size
= vector_size
;
2860 top
->stackop_size
= stackop_size
;
2861 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2863 top
->prev
= arch_stack_top
;
2864 arch_stack_top
= top
;
2866 (void) restore_line_pointer (e
);
2867 demand_empty_rest_of_line ();
2871 if (strcmp (string
, "pop") == 0)
2873 const arch_stack_entry
*top
= arch_stack_top
;
2876 as_bad (_(".arch stack is empty"));
2877 else if (top
->flag_code
!= flag_code
2878 || top
->stackop_size
!= stackop_size
)
2880 static const unsigned int bits
[] = {
2886 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2887 bits
[top
->flag_code
],
2888 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2892 arch_stack_top
= top
->prev
;
2894 cpu_arch_name
= top
->name
;
2895 free (cpu_sub_arch_name
);
2896 cpu_sub_arch_name
= top
->sub_name
;
2897 cpu_arch_flags
= top
->flags
;
2898 cpu_arch_isa
= top
->isa
;
2899 cpu_arch_isa_flags
= top
->isa_flags
;
2900 vector_size
= top
->vector_size
;
2901 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2906 (void) restore_line_pointer (e
);
2907 demand_empty_rest_of_line ();
2911 if (strcmp (string
, "default") == 0)
2913 if (strcmp (default_arch
, "iamcu") == 0)
2914 string
= default_arch
;
2917 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2919 cpu_arch_name
= NULL
;
2920 free (cpu_sub_arch_name
);
2921 cpu_sub_arch_name
= NULL
;
2922 cpu_arch_flags
= cpu_unknown_flags
;
2923 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2924 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2925 if (!cpu_arch_tune_set
)
2926 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2928 vector_size
= VSZ_DEFAULT
;
2930 j
= ARRAY_SIZE (cpu_arch
) + 1;
2934 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2936 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2937 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2941 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2943 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2945 as_bad (_("64bit mode not supported on `%s'."),
2947 (void) restore_line_pointer (e
);
2948 ignore_rest_of_line ();
2952 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2954 as_bad (_("32bit mode not supported on `%s'."),
2956 (void) restore_line_pointer (e
);
2957 ignore_rest_of_line ();
2961 cpu_arch_name
= cpu_arch
[j
].name
;
2962 free (cpu_sub_arch_name
);
2963 cpu_sub_arch_name
= NULL
;
2964 cpu_arch_flags
= cpu_arch
[j
].enable
;
2965 cpu_arch_isa
= cpu_arch
[j
].type
;
2966 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2967 if (!cpu_arch_tune_set
)
2968 cpu_arch_tune
= cpu_arch_isa
;
2970 vector_size
= VSZ_DEFAULT
;
2972 pre_386_16bit_warned
= false;
2976 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2981 (void) restore_line_pointer (e
);
2983 switch (cpu_arch
[j
].vsz
)
2989 #ifdef SVR4_COMMENT_CHARS
2990 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2992 if (*input_line_pointer
== '/')
2995 ++input_line_pointer
;
2996 switch (get_absolute_expression ())
2998 case 512: vector_size
= VSZ512
; break;
2999 case 256: vector_size
= VSZ256
; break;
3000 case 128: vector_size
= VSZ128
; break;
3002 as_bad (_("Unrecognized vector size specifier"));
3003 ignore_rest_of_line ();
3010 vector_size
= VSZ_DEFAULT
;
3014 demand_empty_rest_of_line ();
3019 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3021 /* Disable an ISA extension. */
3022 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3023 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3024 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3028 if (cpu_arch
[j
].vsz
== vsz_set
)
3029 vector_size
= VSZ_DEFAULT
;
3031 (void) restore_line_pointer (e
);
3032 demand_empty_rest_of_line ();
3037 if (j
== ARRAY_SIZE (cpu_arch
))
3038 as_bad (_("no such architecture: `%s'"), string
);
3040 *input_line_pointer
= e
;
3042 no_cond_jump_promotion
= 0;
3043 if (*input_line_pointer
== ','
3044 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3046 ++input_line_pointer
;
3047 e
= get_symbol_name (&s
);
3050 if (strcmp (string
, "nojumps") == 0)
3051 no_cond_jump_promotion
= 1;
3052 else if (strcmp (string
, "jumps") == 0)
3055 as_bad (_("no such architecture modifier: `%s'"), string
);
3057 (void) restore_line_pointer (e
);
3060 demand_empty_rest_of_line ();
3063 enum bfd_architecture
3066 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3068 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3069 || flag_code
== CODE_64BIT
)
3070 as_fatal (_("Intel MCU is 32bit ELF only"));
3071 return bfd_arch_iamcu
;
3074 return bfd_arch_i386
;
3080 if (startswith (default_arch
, "x86_64"))
3082 if (default_arch
[6] == '\0')
3083 return bfd_mach_x86_64
;
3085 return bfd_mach_x64_32
;
3087 else if (!strcmp (default_arch
, "i386")
3088 || !strcmp (default_arch
, "iamcu"))
3090 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3093 as_fatal (_("Intel MCU is 32bit ELF only"));
3094 return bfd_mach_i386_iamcu
;
3097 return bfd_mach_i386_i386
;
3100 as_fatal (_("unknown architecture"));
3103 #include "opcodes/i386-tbl.h"
3108 /* Support pseudo prefixes like {disp32}. */
3109 lex_type
['{'] = LEX_BEGIN_NAME
;
3111 /* Initialize op_hash hash table. */
3112 op_hash
= str_htab_create ();
3115 const insn_template
*const *sets
= i386_op_sets
;
3116 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3118 /* Type checks to compensate for the conversion through void * which
3119 occurs during hash table insertion / lookup. */
3120 (void) sizeof (sets
== ¤t_templates
->start
);
3121 (void) sizeof (end
== ¤t_templates
->end
);
3122 for (; sets
< end
; ++sets
)
3123 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3124 as_fatal (_("duplicate %s"), insn_name (*sets
));
3127 /* Initialize reg_hash hash table. */
3128 reg_hash
= str_htab_create ();
3130 const reg_entry
*regtab
;
3131 unsigned int regtab_size
= i386_regtab_size
;
3133 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3135 switch (regtab
->reg_type
.bitfield
.class)
3138 if (regtab
->reg_type
.bitfield
.dword
)
3140 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3143 else if (regtab
->reg_type
.bitfield
.tbyte
)
3145 /* There's no point inserting st(<N>) in the hash table, as
3146 parentheses aren't included in register_chars[] anyway. */
3147 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3154 switch (regtab
->reg_num
)
3156 case 0: reg_es
= regtab
; break;
3157 case 2: reg_ss
= regtab
; break;
3158 case 3: reg_ds
= regtab
; break;
3163 if (!regtab
->reg_num
)
3168 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3169 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3173 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3178 for (c
= 0; c
< 256; c
++)
3180 if (ISDIGIT (c
) || ISLOWER (c
))
3182 mnemonic_chars
[c
] = c
;
3183 register_chars
[c
] = c
;
3184 operand_chars
[c
] = c
;
3186 else if (ISUPPER (c
))
3188 mnemonic_chars
[c
] = TOLOWER (c
);
3189 register_chars
[c
] = mnemonic_chars
[c
];
3190 operand_chars
[c
] = c
;
3192 #ifdef SVR4_COMMENT_CHARS
3193 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3194 operand_chars
[c
] = c
;
3198 operand_chars
[c
] = c
;
3201 mnemonic_chars
['_'] = '_';
3202 mnemonic_chars
['-'] = '-';
3203 mnemonic_chars
['.'] = '.';
3205 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3206 operand_chars
[(unsigned char) *p
] = *p
;
3207 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3208 operand_chars
[(unsigned char) *p
] = *p
;
3211 if (flag_code
== CODE_64BIT
)
3213 #if defined (OBJ_COFF) && defined (TE_PE)
3214 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3217 x86_dwarf2_return_column
= 16;
3219 x86_cie_data_alignment
= -8;
3220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3221 x86_sframe_cfa_sp_reg
= 7;
3222 x86_sframe_cfa_fp_reg
= 6;
3227 x86_dwarf2_return_column
= 8;
3228 x86_cie_data_alignment
= -4;
3231 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3232 can be turned into BRANCH_PREFIX frag. */
3233 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3238 i386_print_statistics (FILE *file
)
3240 htab_print_statistics (file
, "i386 opcode", op_hash
);
3241 htab_print_statistics (file
, "i386 register", reg_hash
);
3247 htab_delete (op_hash
);
3248 htab_delete (reg_hash
);
3253 /* Debugging routines for md_assemble. */
3254 static void pte (insn_template
*);
3255 static void pt (i386_operand_type
);
3256 static void pe (expressionS
*);
3257 static void ps (symbolS
*);
3260 pi (const char *line
, i386_insn
*x
)
3264 fprintf (stdout
, "%s: template ", line
);
3266 fprintf (stdout
, " address: base %s index %s scale %x\n",
3267 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3268 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3269 x
->log2_scale_factor
);
3270 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3271 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3272 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3273 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3274 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3275 (x
->rex
& REX_W
) != 0,
3276 (x
->rex
& REX_R
) != 0,
3277 (x
->rex
& REX_X
) != 0,
3278 (x
->rex
& REX_B
) != 0);
3279 for (j
= 0; j
< x
->operands
; j
++)
3281 fprintf (stdout
, " #%d: ", j
+ 1);
3283 fprintf (stdout
, "\n");
3284 if (x
->types
[j
].bitfield
.class == Reg
3285 || x
->types
[j
].bitfield
.class == RegMMX
3286 || x
->types
[j
].bitfield
.class == RegSIMD
3287 || x
->types
[j
].bitfield
.class == RegMask
3288 || x
->types
[j
].bitfield
.class == SReg
3289 || x
->types
[j
].bitfield
.class == RegCR
3290 || x
->types
[j
].bitfield
.class == RegDR
3291 || x
->types
[j
].bitfield
.class == RegTR
3292 || x
->types
[j
].bitfield
.class == RegBND
)
3293 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3294 if (operand_type_check (x
->types
[j
], imm
))
3296 if (operand_type_check (x
->types
[j
], disp
))
3297 pe (x
->op
[j
].disps
);
3302 pte (insn_template
*t
)
3304 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3305 static const char *const opc_spc
[] = {
3306 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3307 "XOP08", "XOP09", "XOP0A",
3311 fprintf (stdout
, " %d operands ", t
->operands
);
3312 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3313 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3314 if (opc_spc
[t
->opcode_space
])
3315 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3316 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3317 if (t
->extension_opcode
!= None
)
3318 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3319 if (t
->opcode_modifier
.d
)
3320 fprintf (stdout
, "D");
3321 if (t
->opcode_modifier
.w
)
3322 fprintf (stdout
, "W");
3323 fprintf (stdout
, "\n");
3324 for (j
= 0; j
< t
->operands
; j
++)
3326 fprintf (stdout
, " #%d type ", j
+ 1);
3327 pt (t
->operand_types
[j
]);
3328 fprintf (stdout
, "\n");
3335 fprintf (stdout
, " operation %d\n", e
->X_op
);
3336 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3337 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3338 if (e
->X_add_symbol
)
3340 fprintf (stdout
, " add_symbol ");
3341 ps (e
->X_add_symbol
);
3342 fprintf (stdout
, "\n");
3346 fprintf (stdout
, " op_symbol ");
3347 ps (e
->X_op_symbol
);
3348 fprintf (stdout
, "\n");
3355 fprintf (stdout
, "%s type %s%s",
3357 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3358 segment_name (S_GET_SEGMENT (s
)));
3361 static struct type_name
3363 i386_operand_type mask
;
3366 const type_names
[] =
3368 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3369 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3370 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3371 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3372 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3373 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3374 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3375 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3376 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3377 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3378 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3379 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3380 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3381 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3382 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3383 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3384 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3385 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3386 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3387 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3388 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3389 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3390 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3391 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3392 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3393 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3394 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3395 { { .bitfield
= { .class = SReg
} }, "SReg" },
3396 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3397 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3398 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3399 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3400 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3401 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3405 pt (i386_operand_type t
)
3408 i386_operand_type a
;
3410 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3412 a
= operand_type_and (t
, type_names
[j
].mask
);
3413 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3414 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3419 #endif /* DEBUG386 */
3421 static bfd_reloc_code_real_type
3422 reloc (unsigned int size
,
3425 bfd_reloc_code_real_type other
)
3427 if (other
!= NO_RELOC
)
3429 reloc_howto_type
*rel
;
3434 case BFD_RELOC_X86_64_GOT32
:
3435 return BFD_RELOC_X86_64_GOT64
;
3437 case BFD_RELOC_X86_64_GOTPLT64
:
3438 return BFD_RELOC_X86_64_GOTPLT64
;
3440 case BFD_RELOC_X86_64_PLTOFF64
:
3441 return BFD_RELOC_X86_64_PLTOFF64
;
3443 case BFD_RELOC_X86_64_GOTPC32
:
3444 other
= BFD_RELOC_X86_64_GOTPC64
;
3446 case BFD_RELOC_X86_64_GOTPCREL
:
3447 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3449 case BFD_RELOC_X86_64_TPOFF32
:
3450 other
= BFD_RELOC_X86_64_TPOFF64
;
3452 case BFD_RELOC_X86_64_DTPOFF32
:
3453 other
= BFD_RELOC_X86_64_DTPOFF64
;
3459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3460 if (other
== BFD_RELOC_SIZE32
)
3463 other
= BFD_RELOC_SIZE64
;
3466 as_bad (_("there are no pc-relative size relocations"));
3472 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3473 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3476 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3478 as_bad (_("unknown relocation (%u)"), other
);
3479 else if (size
!= bfd_get_reloc_size (rel
))
3480 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3481 bfd_get_reloc_size (rel
),
3483 else if (pcrel
&& !rel
->pc_relative
)
3484 as_bad (_("non-pc-relative relocation for pc-relative field"));
3485 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3487 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3489 as_bad (_("relocated field and relocation type differ in signedness"));
3498 as_bad (_("there are no unsigned pc-relative relocations"));
3501 case 1: return BFD_RELOC_8_PCREL
;
3502 case 2: return BFD_RELOC_16_PCREL
;
3503 case 4: return BFD_RELOC_32_PCREL
;
3504 case 8: return BFD_RELOC_64_PCREL
;
3506 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3513 case 4: return BFD_RELOC_X86_64_32S
;
3518 case 1: return BFD_RELOC_8
;
3519 case 2: return BFD_RELOC_16
;
3520 case 4: return BFD_RELOC_32
;
3521 case 8: return BFD_RELOC_64
;
3523 as_bad (_("cannot do %s %u byte relocation"),
3524 sign
> 0 ? "signed" : "unsigned", size
);
3530 /* Here we decide which fixups can be adjusted to make them relative to
3531 the beginning of the section instead of the symbol. Basically we need
3532 to make sure that the dynamic relocations are done correctly, so in
3533 some cases we force the original symbol to be used. */
3536 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3542 /* Don't adjust pc-relative references to merge sections in 64-bit
3544 if (use_rela_relocations
3545 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3549 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3550 and changed later by validate_fix. */
3551 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3552 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3555 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3556 for size relocations. */
3557 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3558 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3559 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3560 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3561 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3562 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3563 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3564 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3565 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3566 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3572 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3573 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3574 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3575 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3576 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3586 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3587 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3594 want_disp32 (const insn_template
*t
)
3596 return flag_code
!= CODE_64BIT
3597 || i
.prefix
[ADDR_PREFIX
]
3598 || (t
->mnem_off
== MN_lea
3599 && (!i
.types
[1].bitfield
.qword
3600 || t
->opcode_modifier
.size
== SIZE32
));
3604 intel_float_operand (const char *mnemonic
)
3606 /* Note that the value returned is meaningful only for opcodes with (memory)
3607 operands, hence the code here is free to improperly handle opcodes that
3608 have no operands (for better performance and smaller code). */
3610 if (mnemonic
[0] != 'f')
3611 return 0; /* non-math */
3613 switch (mnemonic
[1])
3615 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3616 the fs segment override prefix not currently handled because no
3617 call path can make opcodes without operands get here */
3619 return 2 /* integer op */;
3621 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3622 return 3; /* fldcw/fldenv */
3625 if (mnemonic
[2] != 'o' /* fnop */)
3626 return 3; /* non-waiting control op */
3629 if (mnemonic
[2] == 's')
3630 return 3; /* frstor/frstpm */
3633 if (mnemonic
[2] == 'a')
3634 return 3; /* fsave */
3635 if (mnemonic
[2] == 't')
3637 switch (mnemonic
[3])
3639 case 'c': /* fstcw */
3640 case 'd': /* fstdw */
3641 case 'e': /* fstenv */
3642 case 's': /* fsts[gw] */
3648 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3649 return 0; /* fxsave/fxrstor are not really math ops */
3657 install_template (const insn_template
*t
)
3663 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3664 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3666 if ((maybe_cpu (t
, CpuAVX
) || maybe_cpu (t
, CpuAVX2
)
3667 || maybe_cpu (t
, CpuFMA
))
3668 && (maybe_cpu (t
, CpuAVX512F
) || maybe_cpu (t
, CpuAVX512VL
)))
3670 if (need_evex_encoding ())
3672 i
.tm
.opcode_modifier
.vex
= 0;
3673 i
.tm
.cpu
.bitfield
.cpuavx512f
= i
.tm
.cpu_any
.bitfield
.cpuavx512f
;
3674 i
.tm
.cpu
.bitfield
.cpuavx512vl
= i
.tm
.cpu_any
.bitfield
.cpuavx512vl
;
3678 i
.tm
.opcode_modifier
.evex
= 0;
3679 if (i
.tm
.cpu_any
.bitfield
.cpuavx
)
3680 i
.tm
.cpu
.bitfield
.cpuavx
= 1;
3681 else if (!i
.tm
.cpu
.bitfield
.isa
)
3682 i
.tm
.cpu
.bitfield
.isa
= i
.tm
.cpu_any
.bitfield
.isa
;
3684 gas_assert (i
.tm
.cpu
.bitfield
.isa
== i
.tm
.cpu_any
.bitfield
.isa
);
3689 /* Note that for pseudo prefixes this produces a length of 1. But for them
3690 the length isn't interesting at all. */
3691 for (l
= 1; l
< 4; ++l
)
3692 if (!(t
->base_opcode
>> (8 * l
)))
3695 i
.opcode_length
= l
;
3698 /* Build the VEX prefix. */
3701 build_vex_prefix (const insn_template
*t
)
3703 unsigned int register_specifier
;
3704 unsigned int vector_length
;
3707 /* Check register specifier. */
3708 if (i
.vex
.register_specifier
)
3710 register_specifier
=
3711 ~register_number (i
.vex
.register_specifier
) & 0xf;
3712 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3715 register_specifier
= 0xf;
3717 /* Use 2-byte VEX prefix by swapping destination and source operand
3718 if there are more than 1 register operand. */
3719 if (i
.reg_operands
> 1
3720 && i
.vec_encoding
!= vex_encoding_vex3
3721 && i
.dir_encoding
== dir_encoding_default
3722 && i
.operands
== i
.reg_operands
3723 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3724 && i
.tm
.opcode_space
== SPACE_0F
3725 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3730 swap_2_operands (0, i
.operands
- 1);
3732 gas_assert (i
.rm
.mode
== 3);
3736 i
.rm
.regmem
= i
.rm
.reg
;
3739 if (i
.tm
.opcode_modifier
.d
)
3740 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3741 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3742 else /* Use the next insn. */
3743 install_template (&t
[1]);
3746 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3747 are no memory operands and at least 3 register ones. */
3748 if (i
.reg_operands
>= 3
3749 && i
.vec_encoding
!= vex_encoding_vex3
3750 && i
.reg_operands
== i
.operands
- i
.imm_operands
3751 && i
.tm
.opcode_modifier
.vex
3752 && i
.tm
.opcode_modifier
.commutative
3753 && (i
.tm
.opcode_modifier
.sse2avx
3754 || (optimize
> 1 && !i
.no_optimize
))
3756 && i
.vex
.register_specifier
3757 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3759 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3761 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3762 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3763 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3764 &i
.types
[i
.operands
- 3]));
3765 gas_assert (i
.rm
.mode
== 3);
3767 swap_2_operands (xchg
, xchg
+ 1);
3770 xchg
= i
.rm
.regmem
| 8;
3771 i
.rm
.regmem
= ~register_specifier
& 0xf;
3772 gas_assert (!(i
.rm
.regmem
& 8));
3773 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3774 register_specifier
= ~xchg
& 0xf;
3777 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3778 vector_length
= avxscalar
;
3779 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3781 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3787 /* Determine vector length from the last multi-length vector
3790 for (op
= t
->operands
; op
--;)
3791 if (t
->operand_types
[op
].bitfield
.xmmword
3792 && t
->operand_types
[op
].bitfield
.ymmword
3793 && i
.types
[op
].bitfield
.ymmword
)
3800 /* Check the REX.W bit and VEXW. */
3801 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3802 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3803 else if (i
.tm
.opcode_modifier
.vexw
)
3804 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3806 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3808 /* Use 2-byte VEX prefix if possible. */
3810 && i
.vec_encoding
!= vex_encoding_vex3
3811 && i
.tm
.opcode_space
== SPACE_0F
3812 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3814 /* 2-byte VEX prefix. */
3818 i
.vex
.bytes
[0] = 0xc5;
3820 /* Check the REX.R bit. */
3821 r
= (i
.rex
& REX_R
) ? 0 : 1;
3822 i
.vex
.bytes
[1] = (r
<< 7
3823 | register_specifier
<< 3
3824 | vector_length
<< 2
3825 | i
.tm
.opcode_modifier
.opcodeprefix
);
3829 /* 3-byte VEX prefix. */
3832 switch (i
.tm
.opcode_space
)
3838 i
.vex
.bytes
[0] = 0xc4;
3843 i
.vex
.bytes
[0] = 0x8f;
3849 /* The high 3 bits of the second VEX byte are 1's compliment
3850 of RXB bits from REX. */
3851 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3852 | (!dot_insn () ? i
.tm
.opcode_space
3853 : i
.insn_opcode_space
);
3855 i
.vex
.bytes
[2] = (w
<< 7
3856 | register_specifier
<< 3
3857 | vector_length
<< 2
3858 | i
.tm
.opcode_modifier
.opcodeprefix
);
3863 is_evex_encoding (const insn_template
*t
)
3865 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3866 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3867 || t
->opcode_modifier
.sae
;
3871 is_any_vex_encoding (const insn_template
*t
)
3873 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3877 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3879 unsigned int op
, bytes
;
3880 const i386_operand_type
*types
;
3882 if (i
.broadcast
.type
)
3883 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3885 gas_assert (intel_syntax
);
3887 for (op
= 0; op
< t
->operands
; ++op
)
3888 if (t
->operand_types
[op
].bitfield
.baseindex
)
3891 gas_assert (op
< t
->operands
);
3893 if (t
->opcode_modifier
.evex
3894 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3895 switch (i
.broadcast
.bytes
)
3898 if (t
->operand_types
[op
].bitfield
.word
)
3902 if (t
->operand_types
[op
].bitfield
.dword
)
3906 if (t
->operand_types
[op
].bitfield
.qword
)
3910 if (t
->operand_types
[op
].bitfield
.xmmword
)
3912 if (t
->operand_types
[op
].bitfield
.ymmword
)
3914 if (t
->operand_types
[op
].bitfield
.zmmword
)
3921 gas_assert (op
+ 1 < t
->operands
);
3923 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3924 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3925 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3927 types
= &i
.types
[op
+ 1];
3930 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3931 types
= &t
->operand_types
[op
];
3933 if (types
->bitfield
.zmmword
)
3935 else if (types
->bitfield
.ymmword
)
3941 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3942 insn_name (t
), bytes
* 8);
3947 /* Build the EVEX prefix. */
3950 build_evex_prefix (void)
3952 unsigned int register_specifier
, w
;
3953 rex_byte vrex_used
= 0;
3955 /* Check register specifier. */
3956 if (i
.vex
.register_specifier
)
3958 gas_assert ((i
.vrex
& REX_X
) == 0);
3960 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3961 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3962 register_specifier
+= 8;
3963 /* The upper 16 registers are encoded in the fourth byte of the
3965 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3966 i
.vex
.bytes
[3] = 0x8;
3967 register_specifier
= ~register_specifier
& 0xf;
3971 register_specifier
= 0xf;
3973 /* Encode upper 16 vector index register in the fourth byte of
3975 if (!(i
.vrex
& REX_X
))
3976 i
.vex
.bytes
[3] = 0x8;
3981 /* 4 byte EVEX prefix. */
3983 i
.vex
.bytes
[0] = 0x62;
3985 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3987 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3988 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3989 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3990 | (!dot_insn () ? i
.tm
.opcode_space
3991 : i
.insn_opcode_space
);
3993 /* The fifth bit of the second EVEX byte is 1's compliment of the
3994 REX_R bit in VREX. */
3995 if (!(i
.vrex
& REX_R
))
3996 i
.vex
.bytes
[1] |= 0x10;
4000 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4002 /* When all operands are registers, the REX_X bit in REX is not
4003 used. We reuse it to encode the upper 16 registers, which is
4004 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4005 as 1's compliment. */
4006 if ((i
.vrex
& REX_B
))
4009 i
.vex
.bytes
[1] &= ~0x40;
4013 /* EVEX instructions shouldn't need the REX prefix. */
4014 i
.vrex
&= ~vrex_used
;
4015 gas_assert (i
.vrex
== 0);
4017 /* Check the REX.W bit and VEXW. */
4018 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4019 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4020 else if (i
.tm
.opcode_modifier
.vexw
)
4021 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4023 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4025 /* The third byte of the EVEX prefix. */
4026 i
.vex
.bytes
[2] = ((w
<< 7)
4027 | (register_specifier
<< 3)
4028 | 4 /* Encode the U bit. */
4029 | i
.tm
.opcode_modifier
.opcodeprefix
);
4031 /* The fourth byte of the EVEX prefix. */
4032 /* The zeroing-masking bit. */
4033 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4034 i
.vex
.bytes
[3] |= 0x80;
4036 /* Don't always set the broadcast bit if there is no RC. */
4037 if (i
.rounding
.type
== rc_none
)
4039 /* Encode the vector length. */
4040 unsigned int vec_length
;
4042 if (!i
.tm
.opcode_modifier
.evex
4043 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4047 /* Determine vector length from the last multi-length vector
4049 for (op
= i
.operands
; op
--;)
4050 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4051 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4052 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4054 if (i
.types
[op
].bitfield
.zmmword
)
4056 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4059 else if (i
.types
[op
].bitfield
.ymmword
)
4061 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4064 else if (i
.types
[op
].bitfield
.xmmword
)
4066 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4069 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4070 && op
== i
.broadcast
.operand
)
4072 switch (get_broadcast_bytes (&i
.tm
, true))
4075 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4078 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4081 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4090 if (op
>= MAX_OPERANDS
)
4094 switch (i
.tm
.opcode_modifier
.evex
)
4096 case EVEXLIG
: /* LL' is ignored */
4097 vec_length
= evexlig
<< 5;
4100 vec_length
= 0 << 5;
4103 vec_length
= 1 << 5;
4106 vec_length
= 2 << 5;
4111 vec_length
= 3 << 5;
4119 i
.vex
.bytes
[3] |= vec_length
;
4120 /* Encode the broadcast bit. */
4121 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4122 i
.vex
.bytes
[3] |= 0x10;
4124 else if (i
.rounding
.type
!= saeonly
)
4125 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4127 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4130 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4134 process_immext (void)
4138 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4139 which is coded in the same place as an 8-bit immediate field
4140 would be. Here we fake an 8-bit immediate operand from the
4141 opcode suffix stored in tm.extension_opcode.
4143 AVX instructions also use this encoding, for some of
4144 3 argument instructions. */
4146 gas_assert (i
.imm_operands
<= 1
4148 || (is_any_vex_encoding (&i
.tm
)
4149 && i
.operands
<= 4)));
4151 exp
= &im_expressions
[i
.imm_operands
++];
4152 i
.op
[i
.operands
].imms
= exp
;
4153 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4155 exp
->X_op
= O_constant
;
4156 exp
->X_add_number
= i
.tm
.extension_opcode
;
4157 i
.tm
.extension_opcode
= None
;
4164 switch (i
.tm
.opcode_modifier
.prefixok
)
4172 as_bad (_("invalid instruction `%s' after `%s'"),
4173 insn_name (&i
.tm
), i
.hle_prefix
);
4176 if (i
.prefix
[LOCK_PREFIX
])
4178 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4182 case PrefixHLERelease
:
4183 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4185 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4189 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4191 as_bad (_("memory destination needed for instruction `%s'"
4192 " after `xrelease'"), insn_name (&i
.tm
));
4199 /* Encode aligned vector move as unaligned vector move. */
4202 encode_with_unaligned_vector_move (void)
4204 switch (i
.tm
.base_opcode
)
4206 case 0x28: /* Load instructions. */
4207 case 0x29: /* Store instructions. */
4208 /* movaps/movapd/vmovaps/vmovapd. */
4209 if (i
.tm
.opcode_space
== SPACE_0F
4210 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4211 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4213 case 0x6f: /* Load instructions. */
4214 case 0x7f: /* Store instructions. */
4215 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4216 if (i
.tm
.opcode_space
== SPACE_0F
4217 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4218 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4225 /* Try the shortest encoding by shortening operand size. */
4228 optimize_encoding (void)
4232 if (i
.tm
.mnem_off
== MN_lea
)
4235 lea symbol, %rN -> mov $symbol, %rN
4236 lea (%rM), %rN -> mov %rM, %rN
4237 lea (,%rM,1), %rN -> mov %rM, %rN
4239 and in 32-bit mode for 16-bit addressing
4241 lea (%rM), %rN -> movzx %rM, %rN
4243 and in 64-bit mode zap 32-bit addressing in favor of using a
4244 32-bit (or less) destination.
4246 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4248 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4249 i
.tm
.opcode_modifier
.size
= SIZE32
;
4250 i
.prefix
[ADDR_PREFIX
] = 0;
4253 if (!i
.index_reg
&& !i
.base_reg
)
4256 lea symbol, %rN -> mov $symbol, %rN
4258 if (flag_code
== CODE_64BIT
)
4260 /* Don't transform a relocation to a 16-bit one. */
4262 && i
.op
[0].disps
->X_op
!= O_constant
4263 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4266 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4267 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4269 i
.tm
.base_opcode
= 0xb8;
4270 i
.tm
.opcode_modifier
.modrm
= 0;
4271 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4272 i
.types
[0].bitfield
.imm32
= 1;
4275 i
.tm
.opcode_modifier
.size
= SIZE16
;
4276 i
.types
[0].bitfield
.imm16
= 1;
4281 /* Subject to further optimization below. */
4282 i
.tm
.base_opcode
= 0xc7;
4283 i
.tm
.extension_opcode
= 0;
4284 i
.types
[0].bitfield
.imm32s
= 1;
4285 i
.types
[0].bitfield
.baseindex
= 0;
4288 /* Outside of 64-bit mode address and operand sizes have to match if
4289 a relocation is involved, as otherwise we wouldn't (currently) or
4290 even couldn't express the relocation correctly. */
4291 else if (i
.op
[0].disps
4292 && i
.op
[0].disps
->X_op
!= O_constant
4293 && ((!i
.prefix
[ADDR_PREFIX
])
4294 != (flag_code
== CODE_32BIT
4295 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4296 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4298 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4299 destination is going to grow encoding size. */
4300 else if (flag_code
== CODE_16BIT
4301 && (optimize
<= 1 || optimize_for_space
)
4302 && !i
.prefix
[ADDR_PREFIX
]
4303 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4307 i
.tm
.base_opcode
= 0xb8;
4308 i
.tm
.opcode_modifier
.modrm
= 0;
4309 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4310 i
.types
[0].bitfield
.imm32
= 1;
4312 i
.types
[0].bitfield
.imm16
= 1;
4315 && i
.op
[0].disps
->X_op
== O_constant
4316 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4317 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4319 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4320 i
.op
[0].disps
->X_add_number
&= 0xffff;
4323 i
.tm
.operand_types
[0] = i
.types
[0];
4327 i
.op
[0].imms
= &im_expressions
[0];
4328 i
.op
[0].imms
->X_op
= O_absent
;
4331 else if (i
.op
[0].disps
4332 && (i
.op
[0].disps
->X_op
!= O_constant
4333 || i
.op
[0].disps
->X_add_number
))
4338 lea (%rM), %rN -> mov %rM, %rN
4339 lea (,%rM,1), %rN -> mov %rM, %rN
4340 lea (%rM), %rN -> movzx %rM, %rN
4342 const reg_entry
*addr_reg
;
4344 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4345 addr_reg
= i
.base_reg
;
4346 else if (!i
.base_reg
4347 && i
.index_reg
->reg_num
!= RegIZ
4348 && !i
.log2_scale_factor
)
4349 addr_reg
= i
.index_reg
;
4353 if (addr_reg
->reg_type
.bitfield
.word
4354 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4356 if (flag_code
!= CODE_32BIT
)
4358 i
.tm
.opcode_space
= SPACE_0F
;
4359 i
.tm
.base_opcode
= 0xb7;
4362 i
.tm
.base_opcode
= 0x8b;
4364 if (addr_reg
->reg_type
.bitfield
.dword
4365 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4366 i
.tm
.opcode_modifier
.size
= SIZE32
;
4368 i
.op
[0].regs
= addr_reg
;
4373 i
.disp_operands
= 0;
4374 i
.prefix
[ADDR_PREFIX
] = 0;
4375 i
.prefix
[SEG_PREFIX
] = 0;
4379 if (optimize_for_space
4380 && i
.tm
.mnem_off
== MN_test
4381 && i
.reg_operands
== 1
4382 && i
.imm_operands
== 1
4383 && !i
.types
[1].bitfield
.byte
4384 && i
.op
[0].imms
->X_op
== O_constant
4385 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4388 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4390 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4391 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4393 i
.types
[1].bitfield
.byte
= 1;
4394 /* Ignore the suffix. */
4396 /* Convert to byte registers. */
4397 if (i
.types
[1].bitfield
.word
)
4399 else if (i
.types
[1].bitfield
.dword
)
4403 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4408 else if (flag_code
== CODE_64BIT
4409 && i
.tm
.opcode_space
== SPACE_BASE
4410 && ((i
.types
[1].bitfield
.qword
4411 && i
.reg_operands
== 1
4412 && i
.imm_operands
== 1
4413 && i
.op
[0].imms
->X_op
== O_constant
4414 && ((i
.tm
.base_opcode
== 0xb8
4415 && i
.tm
.extension_opcode
== None
4416 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4417 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4418 && (i
.tm
.base_opcode
== 0x24
4419 || (i
.tm
.base_opcode
== 0x80
4420 && i
.tm
.extension_opcode
== 0x4)
4421 || i
.tm
.mnem_off
== MN_test
4422 || ((i
.tm
.base_opcode
| 1) == 0xc7
4423 && i
.tm
.extension_opcode
== 0x0)))
4424 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4425 && i
.tm
.base_opcode
== 0x83
4426 && i
.tm
.extension_opcode
== 0x4)))
4427 || (i
.types
[0].bitfield
.qword
4428 && ((i
.reg_operands
== 2
4429 && i
.op
[0].regs
== i
.op
[1].regs
4430 && (i
.tm
.mnem_off
== MN_xor
4431 || i
.tm
.mnem_off
== MN_sub
))
4432 || i
.tm
.mnem_off
== MN_clr
))))
4435 andq $imm31, %r64 -> andl $imm31, %r32
4436 andq $imm7, %r64 -> andl $imm7, %r32
4437 testq $imm31, %r64 -> testl $imm31, %r32
4438 xorq %r64, %r64 -> xorl %r32, %r32
4439 subq %r64, %r64 -> subl %r32, %r32
4440 movq $imm31, %r64 -> movl $imm31, %r32
4441 movq $imm32, %r64 -> movl $imm32, %r32
4443 i
.tm
.opcode_modifier
.size
= SIZE32
;
4446 i
.types
[0].bitfield
.imm32
= 1;
4447 i
.types
[0].bitfield
.imm32s
= 0;
4448 i
.types
[0].bitfield
.imm64
= 0;
4452 i
.types
[0].bitfield
.dword
= 1;
4453 i
.types
[0].bitfield
.qword
= 0;
4455 i
.types
[1].bitfield
.dword
= 1;
4456 i
.types
[1].bitfield
.qword
= 0;
4457 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4460 movq $imm31, %r64 -> movl $imm31, %r32
4461 movq $imm32, %r64 -> movl $imm32, %r32
4463 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4464 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4465 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4466 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4469 movq $imm31, %r64 -> movl $imm31, %r32
4471 i
.tm
.base_opcode
= 0xb8;
4472 i
.tm
.extension_opcode
= None
;
4473 i
.tm
.opcode_modifier
.w
= 0;
4474 i
.tm
.opcode_modifier
.modrm
= 0;
4478 else if (optimize
> 1
4479 && !optimize_for_space
4480 && i
.reg_operands
== 2
4481 && i
.op
[0].regs
== i
.op
[1].regs
4482 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4483 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4486 andb %rN, %rN -> testb %rN, %rN
4487 andw %rN, %rN -> testw %rN, %rN
4488 andq %rN, %rN -> testq %rN, %rN
4489 orb %rN, %rN -> testb %rN, %rN
4490 orw %rN, %rN -> testw %rN, %rN
4491 orq %rN, %rN -> testq %rN, %rN
4493 and outside of 64-bit mode
4495 andl %rN, %rN -> testl %rN, %rN
4496 orl %rN, %rN -> testl %rN, %rN
4498 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4500 else if (i
.tm
.base_opcode
== 0xba
4501 && i
.tm
.opcode_space
== SPACE_0F
4502 && i
.reg_operands
== 1
4503 && i
.op
[0].imms
->X_op
== O_constant
4504 && i
.op
[0].imms
->X_add_number
>= 0)
4507 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4508 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4509 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4511 With <BT> one of bts, btr, and bts also:
4512 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4513 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4518 if (i
.tm
.extension_opcode
!= 4)
4520 if (i
.types
[1].bitfield
.qword
4521 && i
.op
[0].imms
->X_add_number
< 32
4522 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4523 i
.tm
.opcode_modifier
.size
= SIZE32
;
4526 if (i
.types
[1].bitfield
.word
4527 && i
.op
[0].imms
->X_add_number
< 16)
4528 i
.tm
.opcode_modifier
.size
= SIZE32
;
4531 if (i
.op
[0].imms
->X_add_number
< 16)
4532 i
.tm
.opcode_modifier
.size
= SIZE16
;
4536 else if (i
.reg_operands
== 3
4537 && i
.op
[0].regs
== i
.op
[1].regs
4538 && !i
.types
[2].bitfield
.xmmword
4539 && (i
.tm
.opcode_modifier
.vex
4540 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4541 && is_evex_encoding (&i
.tm
)
4542 && (i
.vec_encoding
!= vex_encoding_evex
4543 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4544 || is_cpu (&i
.tm
, CpuAVX512VL
)
4545 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4546 && i
.types
[2].bitfield
.ymmword
))))
4547 && i
.tm
.opcode_space
== SPACE_0F
4548 && ((i
.tm
.base_opcode
| 2) == 0x57
4549 || i
.tm
.base_opcode
== 0xdf
4550 || i
.tm
.base_opcode
== 0xef
4551 || (i
.tm
.base_opcode
| 3) == 0xfb
4552 || i
.tm
.base_opcode
== 0x42
4553 || i
.tm
.base_opcode
== 0x47))
4556 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4558 EVEX VOP %zmmM, %zmmM, %zmmN
4559 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4560 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4561 EVEX VOP %ymmM, %ymmM, %ymmN
4562 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4563 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4564 VEX VOP %ymmM, %ymmM, %ymmN
4565 -> VEX VOP %xmmM, %xmmM, %xmmN
4566 VOP, one of vpandn and vpxor:
4567 VEX VOP %ymmM, %ymmM, %ymmN
4568 -> VEX VOP %xmmM, %xmmM, %xmmN
4569 VOP, one of vpandnd and vpandnq:
4570 EVEX VOP %zmmM, %zmmM, %zmmN
4571 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4572 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4573 EVEX VOP %ymmM, %ymmM, %ymmN
4574 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4575 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4576 VOP, one of vpxord and vpxorq:
4577 EVEX VOP %zmmM, %zmmM, %zmmN
4578 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4579 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4580 EVEX VOP %ymmM, %ymmM, %ymmN
4581 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4582 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4583 VOP, one of kxord and kxorq:
4584 VEX VOP %kM, %kM, %kN
4585 -> VEX kxorw %kM, %kM, %kN
4586 VOP, one of kandnd and kandnq:
4587 VEX VOP %kM, %kM, %kN
4588 -> VEX kandnw %kM, %kM, %kN
4590 if (is_evex_encoding (&i
.tm
))
4592 if (i
.vec_encoding
!= vex_encoding_evex
)
4594 i
.tm
.opcode_modifier
.vex
= VEX128
;
4595 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4596 i
.tm
.opcode_modifier
.evex
= 0;
4597 i
.vec_encoding
= vex_encoding_vex
;
4600 else if (optimize
> 1)
4601 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4605 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4607 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4608 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4611 i
.tm
.opcode_modifier
.vex
= VEX128
;
4613 if (i
.tm
.opcode_modifier
.vex
)
4614 for (j
= 0; j
< 3; j
++)
4616 i
.types
[j
].bitfield
.xmmword
= 1;
4617 i
.types
[j
].bitfield
.ymmword
= 0;
4620 else if (i
.vec_encoding
!= vex_encoding_evex
4621 && !i
.types
[0].bitfield
.zmmword
4622 && !i
.types
[1].bitfield
.zmmword
4624 && !i
.broadcast
.type
4625 && !i
.broadcast
.bytes
4626 && is_evex_encoding (&i
.tm
)
4627 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4628 || (i
.tm
.base_opcode
& ~4) == 0xdb
4629 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4630 && i
.tm
.extension_opcode
== None
)
4633 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4634 vmovdqu32 and vmovdqu64:
4635 EVEX VOP %xmmM, %xmmN
4636 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4637 EVEX VOP %ymmM, %ymmN
4638 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4640 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4642 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4644 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4646 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4647 VOP, one of vpand, vpandn, vpor, vpxor:
4648 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4649 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4650 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4651 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4652 EVEX VOP{d,q} mem, %xmmM, %xmmN
4653 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4654 EVEX VOP{d,q} mem, %ymmM, %ymmN
4655 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4657 for (j
= 0; j
< i
.operands
; j
++)
4658 if (operand_type_check (i
.types
[j
], disp
)
4659 && i
.op
[j
].disps
->X_op
== O_constant
)
4661 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4662 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4663 bytes, we choose EVEX Disp8 over VEX Disp32. */
4664 int evex_disp8
, vex_disp8
;
4665 unsigned int memshift
= i
.memshift
;
4666 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4668 evex_disp8
= fits_in_disp8 (n
);
4670 vex_disp8
= fits_in_disp8 (n
);
4671 if (evex_disp8
!= vex_disp8
)
4673 i
.memshift
= memshift
;
4677 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4680 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4681 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4682 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4683 i
.tm
.opcode_modifier
.vex
4684 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4685 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4686 /* VPAND, VPOR, and VPXOR are commutative. */
4687 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4688 i
.tm
.opcode_modifier
.commutative
= 1;
4689 i
.tm
.opcode_modifier
.evex
= 0;
4690 i
.tm
.opcode_modifier
.masking
= 0;
4691 i
.tm
.opcode_modifier
.broadcast
= 0;
4692 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4695 i
.types
[j
].bitfield
.disp8
4696 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4698 else if (optimize_for_space
4699 && i
.tm
.base_opcode
== 0x29
4700 && i
.tm
.opcode_space
== SPACE_0F38
4701 && i
.operands
== i
.reg_operands
4702 && i
.op
[0].regs
== i
.op
[1].regs
4703 && (!i
.tm
.opcode_modifier
.vex
4704 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4705 && !is_evex_encoding (&i
.tm
))
4708 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4709 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4710 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4712 i
.tm
.opcode_space
= SPACE_0F
;
4713 i
.tm
.base_opcode
= 0x76;
4715 else if (((i
.tm
.base_opcode
>= 0x64
4716 && i
.tm
.base_opcode
<= 0x66
4717 && i
.tm
.opcode_space
== SPACE_0F
)
4718 || (i
.tm
.base_opcode
== 0x37
4719 && i
.tm
.opcode_space
== SPACE_0F38
))
4720 && i
.operands
== i
.reg_operands
4721 && i
.op
[0].regs
== i
.op
[1].regs
4722 && !is_evex_encoding (&i
.tm
))
4725 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4726 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4727 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4728 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4729 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4730 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4732 i
.tm
.opcode_space
= SPACE_0F
;
4733 i
.tm
.base_opcode
= 0xef;
4734 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4736 if (i
.operands
== 2)
4738 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4744 i
.op
[2].regs
= i
.op
[0].regs
;
4745 i
.types
[2] = i
.types
[0];
4746 i
.flags
[2] = i
.flags
[0];
4747 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4749 i
.tm
.opcode_modifier
.sse2avx
= 0;
4751 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4752 i
.op
[1].regs
= i
.op
[0].regs
;
4755 else if (optimize_for_space
4756 && i
.tm
.base_opcode
== 0x59
4757 && i
.tm
.opcode_space
== SPACE_0F38
4758 && i
.operands
== i
.reg_operands
4759 && i
.tm
.opcode_modifier
.vex
4760 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4761 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4762 && i
.vec_encoding
!= vex_encoding_vex3
)
4765 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4767 i
.tm
.opcode_space
= SPACE_0F
;
4768 i
.tm
.base_opcode
= 0x6c;
4769 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4775 i
.op
[2].regs
= i
.op
[0].regs
;
4776 i
.types
[2] = i
.types
[0];
4777 i
.flags
[2] = i
.flags
[0];
4778 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4780 swap_2_operands (1, 2);
4784 /* Return non-zero for load instruction. */
4790 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4791 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4795 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4796 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4797 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4801 if (i
.tm
.mnem_off
== MN_pop
)
4805 if (i
.tm
.opcode_space
== SPACE_BASE
)
4808 if (i
.tm
.base_opcode
== 0x9d
4809 || i
.tm
.base_opcode
== 0x61)
4812 /* movs, cmps, lods, scas. */
4813 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4817 if (base_opcode
== 0x6f
4818 || i
.tm
.base_opcode
== 0xd7)
4820 /* NB: For AMD-specific insns with implicit memory operands,
4821 they're intentionally not covered. */
4824 /* No memory operand. */
4825 if (!i
.mem_operands
)
4830 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4833 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4835 /* test, not, neg, mul, imul, div, idiv. */
4836 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4840 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4843 /* add, or, adc, sbb, and, sub, xor, cmp. */
4844 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4847 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4848 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4849 && i
.tm
.extension_opcode
!= 6)
4852 /* Check for x87 instructions. */
4853 if ((base_opcode
| 6) == 0xdf)
4855 /* Skip fst, fstp, fstenv, fstcw. */
4856 if (i
.tm
.base_opcode
== 0xd9
4857 && (i
.tm
.extension_opcode
== 2
4858 || i
.tm
.extension_opcode
== 3
4859 || i
.tm
.extension_opcode
== 6
4860 || i
.tm
.extension_opcode
== 7))
4863 /* Skip fisttp, fist, fistp, fstp. */
4864 if (i
.tm
.base_opcode
== 0xdb
4865 && (i
.tm
.extension_opcode
== 1
4866 || i
.tm
.extension_opcode
== 2
4867 || i
.tm
.extension_opcode
== 3
4868 || i
.tm
.extension_opcode
== 7))
4871 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4872 if (i
.tm
.base_opcode
== 0xdd
4873 && (i
.tm
.extension_opcode
== 1
4874 || i
.tm
.extension_opcode
== 2
4875 || i
.tm
.extension_opcode
== 3
4876 || i
.tm
.extension_opcode
== 6
4877 || i
.tm
.extension_opcode
== 7))
4880 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4881 if (i
.tm
.base_opcode
== 0xdf
4882 && (i
.tm
.extension_opcode
== 1
4883 || i
.tm
.extension_opcode
== 2
4884 || i
.tm
.extension_opcode
== 3
4885 || i
.tm
.extension_opcode
== 6
4886 || i
.tm
.extension_opcode
== 7))
4892 else if (i
.tm
.opcode_space
== SPACE_0F
)
4894 /* bt, bts, btr, btc. */
4895 if (i
.tm
.base_opcode
== 0xba
4896 && (i
.tm
.extension_opcode
| 3) == 7)
4899 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4900 if (i
.tm
.base_opcode
== 0xc7
4901 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4902 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4903 || i
.tm
.extension_opcode
== 6))
4906 /* fxrstor, ldmxcsr, xrstor. */
4907 if (i
.tm
.base_opcode
== 0xae
4908 && (i
.tm
.extension_opcode
== 1
4909 || i
.tm
.extension_opcode
== 2
4910 || i
.tm
.extension_opcode
== 5))
4913 /* lgdt, lidt, lmsw. */
4914 if (i
.tm
.base_opcode
== 0x01
4915 && (i
.tm
.extension_opcode
== 2
4916 || i
.tm
.extension_opcode
== 3
4917 || i
.tm
.extension_opcode
== 6))
4921 dest
= i
.operands
- 1;
4923 /* Check fake imm8 operand and 3 source operands. */
4924 if ((i
.tm
.opcode_modifier
.immext
4925 || i
.reg_operands
+ i
.mem_operands
== 4)
4926 && i
.types
[dest
].bitfield
.imm8
)
4929 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4930 if (i
.tm
.opcode_space
== SPACE_BASE
4931 && ((base_opcode
| 0x38) == 0x39
4932 || (base_opcode
| 2) == 0x87))
4935 if (i
.tm
.mnem_off
== MN_xadd
)
4938 /* Check for load instruction. */
4939 return (i
.types
[dest
].bitfield
.class != ClassNone
4940 || i
.types
[dest
].bitfield
.instance
== Accum
);
4943 /* Output lfence, 0xfaee8, after instruction. */
4946 insert_lfence_after (void)
4948 if (lfence_after_load
&& load_insn_p ())
4950 /* There are also two REP string instructions that require
4951 special treatment. Specifically, the compare string (CMPS)
4952 and scan string (SCAS) instructions set EFLAGS in a manner
4953 that depends on the data being compared/scanned. When used
4954 with a REP prefix, the number of iterations may therefore
4955 vary depending on this data. If the data is a program secret
4956 chosen by the adversary using an LVI method,
4957 then this data-dependent behavior may leak some aspect
4959 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4960 && i
.prefix
[REP_PREFIX
])
4962 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4965 char *p
= frag_more (3);
4972 /* Output lfence, 0xfaee8, before instruction. */
4975 insert_lfence_before (void)
4979 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4982 if (i
.tm
.base_opcode
== 0xff
4983 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4985 /* Insert lfence before indirect branch if needed. */
4987 if (lfence_before_indirect_branch
== lfence_branch_none
)
4990 if (i
.operands
!= 1)
4993 if (i
.reg_operands
== 1)
4995 /* Indirect branch via register. Don't insert lfence with
4996 -mlfence-after-load=yes. */
4997 if (lfence_after_load
4998 || lfence_before_indirect_branch
== lfence_branch_memory
)
5001 else if (i
.mem_operands
== 1
5002 && lfence_before_indirect_branch
!= lfence_branch_register
)
5004 as_warn (_("indirect `%s` with memory operand should be avoided"),
5011 if (last_insn
.kind
!= last_insn_other
5012 && last_insn
.seg
== now_seg
)
5014 as_warn_where (last_insn
.file
, last_insn
.line
,
5015 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5016 last_insn
.name
, insn_name (&i
.tm
));
5027 /* Output or/not/shl and lfence before near ret. */
5028 if (lfence_before_ret
!= lfence_before_ret_none
5029 && (i
.tm
.base_opcode
| 1) == 0xc3)
5031 if (last_insn
.kind
!= last_insn_other
5032 && last_insn
.seg
== now_seg
)
5034 as_warn_where (last_insn
.file
, last_insn
.line
,
5035 _("`%s` skips -mlfence-before-ret on `%s`"),
5036 last_insn
.name
, insn_name (&i
.tm
));
5040 /* Near ret ingore operand size override under CPU64. */
5041 char prefix
= flag_code
== CODE_64BIT
5043 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5045 if (lfence_before_ret
== lfence_before_ret_not
)
5047 /* not: 0xf71424, may add prefix
5048 for operand size override or 64-bit code. */
5049 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5063 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5066 if (lfence_before_ret
== lfence_before_ret_or
)
5068 /* or: 0x830c2400, may add prefix
5069 for operand size override or 64-bit code. */
5075 /* shl: 0xc1242400, may add prefix
5076 for operand size override or 64-bit code. */
5091 /* Shared helper for md_assemble() and s_insn(). */
5092 static void init_globals (void)
5096 memset (&i
, '\0', sizeof (i
));
5097 i
.rounding
.type
= rc_none
;
5098 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5099 i
.reloc
[j
] = NO_RELOC
;
5100 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5101 memset (im_expressions
, '\0', sizeof (im_expressions
));
5102 save_stack_p
= save_stack
;
5105 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5106 parsing pass. Instead of introducing a rarely use new insn attribute this
5107 utilizes a common pattern between affected templates. It is deemed
5108 acceptable that this will lead to unnecessary pass 2 preparations in a
5109 limited set of cases. */
5110 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5112 return t
->opcode_modifier
.sse2avx
5113 /* Note that all SSE2AVX templates have at least one operand. */
5114 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5115 : (t
->opcode_space
== SPACE_0F
5116 && (t
->base_opcode
| 1) == 0xbf)
5117 || (t
->opcode_space
== SPACE_BASE
5118 && t
->base_opcode
== 0x63);
5121 /* This is the guts of the machine-dependent assembler. LINE points to a
5122 machine dependent instruction. This function is supposed to emit
5123 the frags/bytes it assembles to. */
5126 md_assemble (char *line
)
5129 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5130 const char *end
, *pass1_mnem
= NULL
;
5131 enum i386_error pass1_err
= 0;
5132 const insn_template
*t
;
5134 /* Initialize globals. */
5135 current_templates
= NULL
;
5139 /* First parse an instruction mnemonic & call i386_operand for the operands.
5140 We assume that the scrubber has arranged it so that line[0] is the valid
5141 start of a (possibly prefixed) mnemonic. */
5143 end
= parse_insn (line
, mnemonic
, false);
5146 if (pass1_mnem
!= NULL
)
5148 if (i
.error
!= no_error
)
5150 gas_assert (current_templates
!= NULL
);
5151 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5153 /* No point in trying a 2nd pass - it'll only find the same suffix
5155 mnem_suffix
= i
.suffix
;
5160 t
= current_templates
->start
;
5161 if (may_need_pass2 (t
))
5163 /* Make a copy of the full line in case we need to retry. */
5164 copy
= xstrdup (line
);
5167 mnem_suffix
= i
.suffix
;
5169 line
= parse_operands (line
, mnemonic
);
5177 /* Now we've parsed the mnemonic into a set of templates, and have the
5178 operands at hand. */
5180 /* All Intel opcodes have reversed operands except for "bound", "enter",
5181 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5182 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5183 intersegment "jmp" and "call" instructions with 2 immediate operands so
5184 that the immediate segment precedes the offset consistently in Intel and
5188 && (t
->mnem_off
!= MN_bound
)
5189 && !startswith (mnemonic
, "invlpg")
5190 && !startswith (mnemonic
, "monitor")
5191 && !startswith (mnemonic
, "mwait")
5192 && (t
->mnem_off
!= MN_pvalidate
)
5193 && !startswith (mnemonic
, "rmp")
5194 && (t
->mnem_off
!= MN_tpause
)
5195 && (t
->mnem_off
!= MN_umwait
)
5196 && !(i
.operands
== 2
5197 && operand_type_check (i
.types
[0], imm
)
5198 && operand_type_check (i
.types
[1], imm
)))
5201 /* The order of the immediates should be reversed
5202 for 2 immediates extrq and insertq instructions */
5203 if (i
.imm_operands
== 2
5204 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5205 swap_2_operands (0, 1);
5209 /* For USER_MSR instructions, imm32 stands for the name of an model specific
5210 register (MSR). That's an unsigned quantity, whereas all other insns with
5211 32-bit immediate and 64-bit operand size use sign-extended
5212 immediates (imm32s). Therefore these insns are special-cased, bypassing
5213 the normal handling of immediates here. */
5214 if (is_cpu(current_templates
->start
, CpuUSER_MSR
))
5216 for (j
= 0; j
< i
.operands
; j
++)
5218 if (operand_type_check(i
.types
[j
], imm
))
5219 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
5226 if (i
.disp_operands
&& !optimize_disp (t
))
5229 /* Next, we find a template that matches the given insn,
5230 making sure the overlap of the given operands types is consistent
5231 with the template operand types. */
5233 if (!(t
= match_template (mnem_suffix
)))
5235 const char *err_msg
;
5237 if (copy
&& !mnem_suffix
)
5242 pass1_err
= i
.error
;
5243 pass1_mnem
= insn_name (current_templates
->start
);
5247 /* If a non-/only-64bit template (group) was found in pass 1, and if
5248 _some_ template (group) was found in pass 2, squash pass 1's
5250 if (pass1_err
== unsupported_64bit
)
5256 switch (pass1_mnem
? pass1_err
: i
.error
)
5260 case operand_size_mismatch
:
5261 err_msg
= _("operand size mismatch");
5263 case operand_type_mismatch
:
5264 err_msg
= _("operand type mismatch");
5266 case register_type_mismatch
:
5267 err_msg
= _("register type mismatch");
5269 case number_of_operands_mismatch
:
5270 err_msg
= _("number of operands mismatch");
5272 case invalid_instruction_suffix
:
5273 err_msg
= _("invalid instruction suffix");
5276 err_msg
= _("constant doesn't fit in 4 bits");
5278 case unsupported_with_intel_mnemonic
:
5279 err_msg
= _("unsupported with Intel mnemonic");
5281 case unsupported_syntax
:
5282 err_msg
= _("unsupported syntax");
5285 as_bad (_("unsupported instruction `%s'"),
5286 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5288 case unsupported_on_arch
:
5289 as_bad (_("`%s' is not supported on `%s%s'"),
5290 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5291 cpu_arch_name
? cpu_arch_name
: default_arch
,
5292 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5294 case unsupported_64bit
:
5295 if (ISLOWER (mnem_suffix
))
5297 if (flag_code
== CODE_64BIT
)
5298 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5299 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5302 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5303 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5308 if (flag_code
== CODE_64BIT
)
5309 as_bad (_("`%s' is not supported in 64-bit mode"),
5310 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5312 as_bad (_("`%s' is only supported in 64-bit mode"),
5313 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5316 case invalid_sib_address
:
5317 err_msg
= _("invalid SIB address");
5319 case invalid_vsib_address
:
5320 err_msg
= _("invalid VSIB address");
5322 case invalid_vector_register_set
:
5323 err_msg
= _("mask, index, and destination registers must be distinct");
5325 case invalid_tmm_register_set
:
5326 err_msg
= _("all tmm registers must be distinct");
5328 case invalid_dest_and_src_register_set
:
5329 err_msg
= _("destination and source registers must be distinct");
5331 case unsupported_vector_index_register
:
5332 err_msg
= _("unsupported vector index register");
5334 case unsupported_broadcast
:
5335 err_msg
= _("unsupported broadcast");
5337 case broadcast_needed
:
5338 err_msg
= _("broadcast is needed for operand of such type");
5340 case unsupported_masking
:
5341 err_msg
= _("unsupported masking");
5343 case mask_not_on_destination
:
5344 err_msg
= _("mask not on destination operand");
5346 case no_default_mask
:
5347 err_msg
= _("default mask isn't allowed");
5349 case unsupported_rc_sae
:
5350 err_msg
= _("unsupported static rounding/sae");
5352 case invalid_register_operand
:
5353 err_msg
= _("invalid register operand");
5355 case internal_error
:
5356 err_msg
= _("internal error");
5359 as_bad (_("%s for `%s'"), err_msg
,
5360 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5366 if (sse_check
!= check_none
5367 /* The opcode space check isn't strictly needed; it's there only to
5368 bypass the logic below when easily possible. */
5369 && t
->opcode_space
>= SPACE_0F
5370 && t
->opcode_space
<= SPACE_0F3A
5371 && !is_cpu (&i
.tm
, CpuSSE4a
)
5372 && !is_any_vex_encoding (t
))
5376 for (j
= 0; j
< t
->operands
; ++j
)
5378 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5380 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5384 if (j
>= t
->operands
&& simd
)
5385 (sse_check
== check_warning
5387 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5390 if (i
.tm
.opcode_modifier
.fwait
)
5391 if (!add_prefix (FWAIT_OPCODE
))
5394 /* Check if REP prefix is OK. */
5395 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5397 as_bad (_("invalid instruction `%s' after `%s'"),
5398 insn_name (&i
.tm
), i
.rep_prefix
);
5402 /* Check for lock without a lockable instruction. Destination operand
5403 must be memory unless it is xchg (0x86). */
5404 if (i
.prefix
[LOCK_PREFIX
])
5406 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5407 || i
.mem_operands
== 0
5408 || (i
.tm
.base_opcode
!= 0x86
5409 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5411 as_bad (_("expecting lockable instruction after `lock'"));
5415 /* Zap the redundant prefix from XCHG when optimizing. */
5416 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5417 i
.prefix
[LOCK_PREFIX
] = 0;
5420 if (is_any_vex_encoding (&i
.tm
)
5421 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5422 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5424 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5425 if (i
.prefix
[DATA_PREFIX
])
5427 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5431 /* Don't allow e.g. KMOV in TLS code sequences. */
5432 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5435 case BFD_RELOC_386_TLS_GOTIE
:
5436 case BFD_RELOC_386_TLS_LE_32
:
5437 case BFD_RELOC_X86_64_GOTTPOFF
:
5438 case BFD_RELOC_X86_64_TLSLD
:
5439 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5446 /* Check if HLE prefix is OK. */
5447 if (i
.hle_prefix
&& !check_hle ())
5450 /* Check BND prefix. */
5451 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5452 as_bad (_("expecting valid branch instruction after `bnd'"));
5454 /* Check NOTRACK prefix. */
5455 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5456 as_bad (_("expecting indirect branch instruction after `notrack'"));
5458 if (is_cpu (&i
.tm
, CpuMPX
))
5460 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5461 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5462 else if (flag_code
!= CODE_16BIT
5463 ? i
.prefix
[ADDR_PREFIX
]
5464 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5465 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5468 /* Insert BND prefix. */
5469 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5471 if (!i
.prefix
[BND_PREFIX
])
5472 add_prefix (BND_PREFIX_OPCODE
);
5473 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5475 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5476 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5480 /* Check string instruction segment overrides. */
5481 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5483 gas_assert (i
.mem_operands
);
5484 if (!check_string ())
5486 i
.disp_operands
= 0;
5489 /* The memory operand of (%dx) should be only used with input/output
5490 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5491 if (i
.input_output_operand
5492 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5493 || i
.tm
.opcode_space
!= SPACE_BASE
))
5495 as_bad (_("input/output port address isn't allowed with `%s'"),
5500 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5501 optimize_encoding ();
5503 /* Past optimization there's no need to distinguish vex_encoding_evex and
5504 vex_encoding_evex512 anymore. */
5505 if (i
.vec_encoding
== vex_encoding_evex512
)
5506 i
.vec_encoding
= vex_encoding_evex
;
5508 if (use_unaligned_vector_move
)
5509 encode_with_unaligned_vector_move ();
5511 if (!process_suffix ())
5514 /* Check if IP-relative addressing requirements can be satisfied. */
5515 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5516 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5517 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5519 /* Update operand types and check extended states. */
5520 for (j
= 0; j
< i
.operands
; j
++)
5522 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5523 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5528 i
.xstate
|= xstate_mmx
;
5531 i
.xstate
|= xstate_mask
;
5534 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5535 i
.xstate
|= xstate_tmm
;
5536 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5537 && !i
.tm
.opcode_modifier
.vex
5538 && vector_size
>= VSZ512
)
5539 i
.xstate
|= xstate_zmm
;
5540 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5541 && vector_size
>= VSZ256
)
5542 i
.xstate
|= xstate_ymm
;
5543 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5544 i
.xstate
|= xstate_xmm
;
5549 /* Make still unresolved immediate matches conform to size of immediate
5550 given in i.suffix. */
5551 if (!finalize_imm ())
5554 if (i
.types
[0].bitfield
.imm1
)
5555 i
.imm_operands
= 0; /* kludge for shift insns. */
5557 /* For insns with operands there are more diddles to do to the opcode. */
5560 if (!process_operands ())
5563 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5565 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5566 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5569 if (is_any_vex_encoding (&i
.tm
))
5571 if (!cpu_arch_flags
.bitfield
.cpui286
)
5573 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5578 /* Check for explicit REX prefix. */
5579 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5581 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5585 if (i
.tm
.opcode_modifier
.vex
)
5586 build_vex_prefix (t
);
5588 build_evex_prefix ();
5590 /* The individual REX.RXBW bits got consumed. */
5591 i
.rex
&= REX_OPCODE
;
5594 /* Handle conversion of 'int $3' --> special int3 insn. */
5595 if (i
.tm
.mnem_off
== MN_int
5596 && i
.op
[0].imms
->X_add_number
== 3)
5598 i
.tm
.base_opcode
= INT3_OPCODE
;
5602 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5603 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5604 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5605 && i
.op
[0].disps
->X_op
== O_constant
)
5607 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5608 the absolute address given by the constant. Since ix86 jumps and
5609 calls are pc relative, we need to generate a reloc. */
5610 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5611 i
.op
[0].disps
->X_op
= O_symbol
;
5614 /* For 8 bit registers we need an empty rex prefix. Also if the
5615 instruction already has a prefix, we need to convert old
5616 registers to new ones. */
5618 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5619 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5620 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5621 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5622 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5623 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5628 i
.rex
|= REX_OPCODE
;
5629 for (x
= 0; x
< 2; x
++)
5631 /* Look for 8 bit operand that uses old registers. */
5632 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5633 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5635 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5636 /* In case it is "hi" register, give up. */
5637 if (i
.op
[x
].regs
->reg_num
> 3)
5638 as_bad (_("can't encode register '%s%s' in an "
5639 "instruction requiring REX prefix."),
5640 register_prefix
, i
.op
[x
].regs
->reg_name
);
5642 /* Otherwise it is equivalent to the extended register.
5643 Since the encoding doesn't change this is merely
5644 cosmetic cleanup for debug output. */
5646 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5651 if (i
.rex
== 0 && i
.rex_encoding
)
5653 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5654 that uses legacy register. If it is "hi" register, don't add
5655 the REX_OPCODE byte. */
5657 for (x
= 0; x
< 2; x
++)
5658 if (i
.types
[x
].bitfield
.class == Reg
5659 && i
.types
[x
].bitfield
.byte
5660 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5661 && i
.op
[x
].regs
->reg_num
> 3)
5663 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5664 i
.rex_encoding
= false;
5673 add_prefix (REX_OPCODE
| i
.rex
);
5675 insert_lfence_before ();
5677 /* We are ready to output the insn. */
5680 insert_lfence_after ();
5682 last_insn
.seg
= now_seg
;
5684 if (i
.tm
.opcode_modifier
.isprefix
)
5686 last_insn
.kind
= last_insn_prefix
;
5687 last_insn
.name
= insn_name (&i
.tm
);
5688 last_insn
.file
= as_where (&last_insn
.line
);
5691 last_insn
.kind
= last_insn_other
;
5694 /* The Q suffix is generally valid only in 64-bit mode, with very few
5695 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5696 and fisttp only one of their two templates is matched below: That's
5697 sufficient since other relevant attributes are the same between both
5698 respective templates. */
5699 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5701 return flag_code
== CODE_64BIT
5702 || (t
->opcode_space
== SPACE_BASE
5703 && t
->base_opcode
== 0xdf
5704 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5705 || t
->mnem_off
== MN_cmpxchg8b
;
5709 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5711 const char *l
= line
, *token_start
= l
;
5713 bool pass1
= !current_templates
;
5715 const insn_template
*t
;
5721 /* Pseudo-prefixes start with an opening figure brace. */
5722 if ((*mnem_p
= *l
) == '{')
5727 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5732 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5735 as_bad (_("no such instruction: `%s'"), token_start
);
5740 /* Pseudo-prefixes end with a closing figure brace. */
5741 if (*mnemonic
== '{' && *l
== '}')
5744 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5748 /* Point l at the closing brace if there's no other separator. */
5749 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5750 && *l
!= PREFIX_SEPARATOR
)
5753 else if (!is_space_char (*l
)
5754 && *l
!= END_OF_INSN
5756 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5760 as_bad (_("invalid character %s in mnemonic"),
5761 output_invalid (*l
));
5764 if (token_start
== l
)
5766 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5767 as_bad (_("expecting prefix; got nothing"));
5769 as_bad (_("expecting mnemonic; got nothing"));
5773 /* Look up instruction (or prefix) via hash table. */
5774 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5776 if (*l
!= END_OF_INSN
5777 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5778 && current_templates
5779 && current_templates
->start
->opcode_modifier
.isprefix
)
5781 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5783 as_bad ((flag_code
!= CODE_64BIT
5784 ? _("`%s' is only supported in 64-bit mode")
5785 : _("`%s' is not supported in 64-bit mode")),
5786 insn_name (current_templates
->start
));
5789 /* If we are in 16-bit mode, do not allow addr16 or data16.
5790 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5791 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5792 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5793 && flag_code
!= CODE_64BIT
5794 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5795 ^ (flag_code
== CODE_16BIT
)))
5797 as_bad (_("redundant %s prefix"),
5798 insn_name (current_templates
->start
));
5802 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5804 /* Handle pseudo prefixes. */
5805 switch (current_templates
->start
->extension_opcode
)
5809 i
.disp_encoding
= disp_encoding_8bit
;
5813 i
.disp_encoding
= disp_encoding_16bit
;
5817 i
.disp_encoding
= disp_encoding_32bit
;
5821 i
.dir_encoding
= dir_encoding_load
;
5825 i
.dir_encoding
= dir_encoding_store
;
5829 i
.vec_encoding
= vex_encoding_vex
;
5833 i
.vec_encoding
= vex_encoding_vex3
;
5837 i
.vec_encoding
= vex_encoding_evex
;
5841 i
.rex_encoding
= true;
5843 case Prefix_NoOptimize
:
5845 i
.no_optimize
= true;
5853 /* Add prefix, checking for repeated prefixes. */
5854 switch (add_prefix (current_templates
->start
->base_opcode
))
5859 if (is_cpu (current_templates
->start
, CpuIBT
))
5860 i
.notrack_prefix
= insn_name (current_templates
->start
);
5863 if (is_cpu (current_templates
->start
, CpuHLE
))
5864 i
.hle_prefix
= insn_name (current_templates
->start
);
5865 else if (is_cpu (current_templates
->start
, CpuMPX
))
5866 i
.bnd_prefix
= insn_name (current_templates
->start
);
5868 i
.rep_prefix
= insn_name (current_templates
->start
);
5874 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5884 if (!current_templates
)
5886 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5887 Check if we should swap operand or force 32bit displacement in
5889 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5890 i
.dir_encoding
= dir_encoding_swap
;
5891 else if (mnem_p
- 3 == dot_p
5894 i
.disp_encoding
= disp_encoding_8bit
;
5895 else if (mnem_p
- 4 == dot_p
5899 i
.disp_encoding
= disp_encoding_32bit
;
5904 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5907 if (!current_templates
|| !pass1
)
5909 current_templates
= NULL
;
5912 if (mnem_p
> mnemonic
)
5914 /* See if we can get a match by trimming off a suffix. */
5917 case WORD_MNEM_SUFFIX
:
5918 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5919 i
.suffix
= SHORT_MNEM_SUFFIX
;
5922 case BYTE_MNEM_SUFFIX
:
5923 case QWORD_MNEM_SUFFIX
:
5924 i
.suffix
= mnem_p
[-1];
5927 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5929 case SHORT_MNEM_SUFFIX
:
5930 case LONG_MNEM_SUFFIX
:
5933 i
.suffix
= mnem_p
[-1];
5936 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5944 if (intel_float_operand (mnemonic
) == 1)
5945 i
.suffix
= SHORT_MNEM_SUFFIX
;
5947 i
.suffix
= LONG_MNEM_SUFFIX
;
5950 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5952 /* For compatibility reasons accept MOVSD and CMPSD without
5953 operands even in AT&T mode. */
5954 else if (*l
== END_OF_INSN
5955 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5959 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5960 if (current_templates
!= NULL
5962 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5963 && current_templates
->start
->opcode_space
5965 && mnem_p
[-2] == 's')
5967 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5968 mnemonic
, mnemonic
);
5969 i
.suffix
= LONG_MNEM_SUFFIX
;
5973 current_templates
= NULL
;
5981 if (!current_templates
)
5984 as_bad (_("no such instruction: `%s'"), token_start
);
5989 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5990 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5992 /* Check for a branch hint. We allow ",pt" and ",pn" for
5993 predict taken and predict not taken respectively.
5994 I'm not sure that branch hints actually do anything on loop
5995 and jcxz insns (JumpByte) for current Pentium4 chips. They
5996 may work in the future and it doesn't hurt to accept them
5998 if (l
[0] == ',' && l
[1] == 'p')
6002 if (!add_prefix (DS_PREFIX_OPCODE
))
6006 else if (l
[2] == 'n')
6008 if (!add_prefix (CS_PREFIX_OPCODE
))
6014 /* Any other comma loses. */
6017 as_bad (_("invalid character %s in mnemonic"),
6018 output_invalid (*l
));
6022 /* Check if instruction is supported on specified architecture. */
6024 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6026 supported
|= cpu_flags_match (t
);
6028 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6029 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6031 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6037 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6038 i
.error
= unsupported_on_arch
;
6040 i
.error
= unsupported_64bit
;
6047 parse_operands (char *l
, const char *mnemonic
)
6051 /* 1 if operand is pending after ','. */
6052 unsigned int expecting_operand
= 0;
6054 while (*l
!= END_OF_INSN
)
6056 /* Non-zero if operand parens not balanced. */
6057 unsigned int paren_not_balanced
= 0;
6058 /* True if inside double quotes. */
6059 bool in_quotes
= false;
6061 /* Skip optional white space before operand. */
6062 if (is_space_char (*l
))
6064 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6066 as_bad (_("invalid character %s before operand %d"),
6067 output_invalid (*l
),
6071 token_start
= l
; /* After white space. */
6072 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6074 if (*l
== END_OF_INSN
)
6078 as_bad (_("unbalanced double quotes in operand %d."),
6082 if (paren_not_balanced
)
6084 know (!intel_syntax
);
6085 as_bad (_("unbalanced parenthesis in operand %d."),
6090 break; /* we are done */
6092 else if (*l
== '\\' && l
[1] == '"')
6095 in_quotes
= !in_quotes
;
6096 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6098 as_bad (_("invalid character %s in operand %d"),
6099 output_invalid (*l
),
6103 if (!intel_syntax
&& !in_quotes
)
6106 ++paren_not_balanced
;
6108 --paren_not_balanced
;
6112 if (l
!= token_start
)
6113 { /* Yes, we've read in another operand. */
6114 unsigned int operand_ok
;
6115 this_operand
= i
.operands
++;
6116 if (i
.operands
> MAX_OPERANDS
)
6118 as_bad (_("spurious operands; (%d operands/instruction max)"),
6122 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6123 /* Now parse operand adding info to 'i' as we go along. */
6124 END_STRING_AND_SAVE (l
);
6126 if (i
.mem_operands
> 1)
6128 as_bad (_("too many memory references for `%s'"),
6135 i386_intel_operand (token_start
,
6136 intel_float_operand (mnemonic
));
6138 operand_ok
= i386_att_operand (token_start
);
6140 RESTORE_END_STRING (l
);
6146 if (expecting_operand
)
6148 expecting_operand_after_comma
:
6149 as_bad (_("expecting operand after ','; got nothing"));
6154 as_bad (_("expecting operand before ','; got nothing"));
6159 /* Now *l must be either ',' or END_OF_INSN. */
6162 if (*++l
== END_OF_INSN
)
6164 /* Just skip it, if it's \n complain. */
6165 goto expecting_operand_after_comma
;
6167 expecting_operand
= 1;
6174 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6176 union i386_op temp_op
;
6177 i386_operand_type temp_type
;
6178 unsigned int temp_flags
;
6179 enum bfd_reloc_code_real temp_reloc
;
6181 temp_type
= i
.types
[xchg2
];
6182 i
.types
[xchg2
] = i
.types
[xchg1
];
6183 i
.types
[xchg1
] = temp_type
;
6185 temp_flags
= i
.flags
[xchg2
];
6186 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6187 i
.flags
[xchg1
] = temp_flags
;
6189 temp_op
= i
.op
[xchg2
];
6190 i
.op
[xchg2
] = i
.op
[xchg1
];
6191 i
.op
[xchg1
] = temp_op
;
6193 temp_reloc
= i
.reloc
[xchg2
];
6194 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6195 i
.reloc
[xchg1
] = temp_reloc
;
6197 temp_flags
= i
.imm_bits
[xchg2
];
6198 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6199 i
.imm_bits
[xchg1
] = temp_flags
;
6203 if (i
.mask
.operand
== xchg1
)
6204 i
.mask
.operand
= xchg2
;
6205 else if (i
.mask
.operand
== xchg2
)
6206 i
.mask
.operand
= xchg1
;
6208 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6210 if (i
.broadcast
.operand
== xchg1
)
6211 i
.broadcast
.operand
= xchg2
;
6212 else if (i
.broadcast
.operand
== xchg2
)
6213 i
.broadcast
.operand
= xchg1
;
6218 swap_operands (void)
6224 swap_2_operands (1, i
.operands
- 2);
6228 swap_2_operands (0, i
.operands
- 1);
6234 if (i
.mem_operands
== 2)
6236 const reg_entry
*temp_seg
;
6237 temp_seg
= i
.seg
[0];
6238 i
.seg
[0] = i
.seg
[1];
6239 i
.seg
[1] = temp_seg
;
6243 /* Try to ensure constant immediates are represented in the smallest
6248 char guess_suffix
= 0;
6252 guess_suffix
= i
.suffix
;
6253 else if (i
.reg_operands
)
6255 /* Figure out a suffix from the last register operand specified.
6256 We can't do this properly yet, i.e. excluding special register
6257 instances, but the following works for instructions with
6258 immediates. In any case, we can't set i.suffix yet. */
6259 for (op
= i
.operands
; --op
>= 0;)
6260 if (i
.types
[op
].bitfield
.class != Reg
)
6262 else if (i
.types
[op
].bitfield
.byte
)
6264 guess_suffix
= BYTE_MNEM_SUFFIX
;
6267 else if (i
.types
[op
].bitfield
.word
)
6269 guess_suffix
= WORD_MNEM_SUFFIX
;
6272 else if (i
.types
[op
].bitfield
.dword
)
6274 guess_suffix
= LONG_MNEM_SUFFIX
;
6277 else if (i
.types
[op
].bitfield
.qword
)
6279 guess_suffix
= QWORD_MNEM_SUFFIX
;
6283 else if ((flag_code
== CODE_16BIT
)
6284 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6285 guess_suffix
= WORD_MNEM_SUFFIX
;
6286 else if (flag_code
!= CODE_64BIT
6287 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6288 /* A more generic (but also more involved) way of dealing
6289 with the special case(s) would be to go look for
6290 DefaultSize attributes on any of the templates. */
6291 && current_templates
->start
->mnem_off
!= MN_push
))
6292 guess_suffix
= LONG_MNEM_SUFFIX
;
6294 for (op
= i
.operands
; --op
>= 0;)
6295 if (operand_type_check (i
.types
[op
], imm
))
6297 switch (i
.op
[op
].imms
->X_op
)
6300 /* If a suffix is given, this operand may be shortened. */
6301 switch (guess_suffix
)
6303 case LONG_MNEM_SUFFIX
:
6304 i
.types
[op
].bitfield
.imm32
= 1;
6305 i
.types
[op
].bitfield
.imm64
= 1;
6307 case WORD_MNEM_SUFFIX
:
6308 i
.types
[op
].bitfield
.imm16
= 1;
6309 i
.types
[op
].bitfield
.imm32
= 1;
6310 i
.types
[op
].bitfield
.imm32s
= 1;
6311 i
.types
[op
].bitfield
.imm64
= 1;
6313 case BYTE_MNEM_SUFFIX
:
6314 i
.types
[op
].bitfield
.imm8
= 1;
6315 i
.types
[op
].bitfield
.imm8s
= 1;
6316 i
.types
[op
].bitfield
.imm16
= 1;
6317 i
.types
[op
].bitfield
.imm32
= 1;
6318 i
.types
[op
].bitfield
.imm32s
= 1;
6319 i
.types
[op
].bitfield
.imm64
= 1;
6323 /* If this operand is at most 16 bits, convert it
6324 to a signed 16 bit number before trying to see
6325 whether it will fit in an even smaller size.
6326 This allows a 16-bit operand such as $0xffe0 to
6327 be recognised as within Imm8S range. */
6328 if ((i
.types
[op
].bitfield
.imm16
)
6329 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6331 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6332 ^ 0x8000) - 0x8000);
6335 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6336 if ((i
.types
[op
].bitfield
.imm32
)
6337 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6339 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6340 ^ ((offsetT
) 1 << 31))
6341 - ((offsetT
) 1 << 31));
6345 = operand_type_or (i
.types
[op
],
6346 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6348 /* We must avoid matching of Imm32 templates when 64bit
6349 only immediate is available. */
6350 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6351 i
.types
[op
].bitfield
.imm32
= 0;
6358 /* Symbols and expressions. */
6360 /* Convert symbolic operand to proper sizes for matching, but don't
6361 prevent matching a set of insns that only supports sizes other
6362 than those matching the insn suffix. */
6364 i386_operand_type mask
, allowed
;
6365 const insn_template
*t
= current_templates
->start
;
6367 operand_type_set (&mask
, 0);
6368 switch (guess_suffix
)
6370 case QWORD_MNEM_SUFFIX
:
6371 mask
.bitfield
.imm64
= 1;
6372 mask
.bitfield
.imm32s
= 1;
6374 case LONG_MNEM_SUFFIX
:
6375 mask
.bitfield
.imm32
= 1;
6377 case WORD_MNEM_SUFFIX
:
6378 mask
.bitfield
.imm16
= 1;
6380 case BYTE_MNEM_SUFFIX
:
6381 mask
.bitfield
.imm8
= 1;
6387 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6388 while (++t
< current_templates
->end
)
6390 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6391 allowed
= operand_type_and (allowed
, mask
);
6394 if (!operand_type_all_zero (&allowed
))
6395 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6402 /* Try to use the smallest displacement type too. */
6404 optimize_disp (const insn_template
*t
)
6408 if (!want_disp32 (t
)
6409 && (!t
->opcode_modifier
.jump
6410 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6412 for (op
= 0; op
< i
.operands
; ++op
)
6414 const expressionS
*exp
= i
.op
[op
].disps
;
6416 if (!operand_type_check (i
.types
[op
], disp
))
6419 if (exp
->X_op
!= O_constant
)
6422 /* Since displacement is signed extended to 64bit, don't allow
6423 disp32 if it is out of range. */
6424 if (fits_in_signed_long (exp
->X_add_number
))
6427 i
.types
[op
].bitfield
.disp32
= 0;
6428 if (i
.types
[op
].bitfield
.baseindex
)
6430 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6431 (uint64_t) exp
->X_add_number
);
6437 /* Don't optimize displacement for movabs since it only takes 64bit
6439 if (i
.disp_encoding
> disp_encoding_8bit
6440 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6443 for (op
= i
.operands
; op
-- > 0;)
6444 if (operand_type_check (i
.types
[op
], disp
))
6446 if (i
.op
[op
].disps
->X_op
== O_constant
)
6448 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6450 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6452 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6453 i
.op
[op
].disps
= NULL
;
6458 if (i
.types
[op
].bitfield
.disp16
6459 && fits_in_unsigned_word (op_disp
))
6461 /* If this operand is at most 16 bits, convert
6462 to a signed 16 bit number and don't use 64bit
6464 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6465 i
.types
[op
].bitfield
.disp64
= 0;
6469 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6470 if ((flag_code
!= CODE_64BIT
6471 ? i
.types
[op
].bitfield
.disp32
6473 && (!t
->opcode_modifier
.jump
6474 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6475 && fits_in_unsigned_long (op_disp
))
6477 /* If this operand is at most 32 bits, convert
6478 to a signed 32 bit number and don't use 64bit
6480 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6481 i
.types
[op
].bitfield
.disp64
= 0;
6482 i
.types
[op
].bitfield
.disp32
= 1;
6485 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6487 i
.types
[op
].bitfield
.disp64
= 0;
6488 i
.types
[op
].bitfield
.disp32
= 1;
6491 if ((i
.types
[op
].bitfield
.disp32
6492 || i
.types
[op
].bitfield
.disp16
)
6493 && fits_in_disp8 (op_disp
))
6494 i
.types
[op
].bitfield
.disp8
= 1;
6496 i
.op
[op
].disps
->X_add_number
= op_disp
;
6498 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6499 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6501 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6502 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6503 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6506 /* We only support 64bit displacement on constants. */
6507 i
.types
[op
].bitfield
.disp64
= 0;
6513 /* Return 1 if there is a match in broadcast bytes between operand
6514 GIVEN and instruction template T. */
6517 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6519 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6520 && i
.types
[given
].bitfield
.byte
)
6521 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6522 && i
.types
[given
].bitfield
.word
)
6523 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6524 && i
.types
[given
].bitfield
.dword
)
6525 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6526 && i
.types
[given
].bitfield
.qword
));
6529 /* Check if operands are valid for the instruction. */
6532 check_VecOperands (const insn_template
*t
)
6537 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6538 any one operand are implicity requiring AVX512VL support if the actual
6539 operand size is YMMword or XMMword. Since this function runs after
6540 template matching, there's no need to check for YMMword/XMMword in
6542 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6543 if (!cpu_flags_all_zero (&cpu
)
6544 && !is_cpu (t
, CpuAVX512VL
)
6545 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6546 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6548 for (op
= 0; op
< t
->operands
; ++op
)
6550 if (t
->operand_types
[op
].bitfield
.zmmword
6551 && (i
.types
[op
].bitfield
.ymmword
6552 || i
.types
[op
].bitfield
.xmmword
))
6554 i
.error
= unsupported
;
6560 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6561 requiring AVX2 support if the actual operand size is YMMword. */
6562 if (maybe_cpu (t
, CpuAVX
) && maybe_cpu (t
, CpuAVX2
)
6563 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6565 for (op
= 0; op
< t
->operands
; ++op
)
6567 if (t
->operand_types
[op
].bitfield
.xmmword
6568 && i
.types
[op
].bitfield
.ymmword
)
6570 i
.error
= unsupported
;
6576 /* Without VSIB byte, we can't have a vector register for index. */
6577 if (!t
->opcode_modifier
.sib
6579 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6580 || i
.index_reg
->reg_type
.bitfield
.ymmword
6581 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6583 i
.error
= unsupported_vector_index_register
;
6587 /* Check if default mask is allowed. */
6588 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6589 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6591 i
.error
= no_default_mask
;
6595 /* For VSIB byte, we need a vector register for index, and all vector
6596 registers must be distinct. */
6597 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6600 || !((t
->opcode_modifier
.sib
== VECSIB128
6601 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6602 || (t
->opcode_modifier
.sib
== VECSIB256
6603 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6604 || (t
->opcode_modifier
.sib
== VECSIB512
6605 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6607 i
.error
= invalid_vsib_address
;
6611 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6612 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6614 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6615 gas_assert (i
.types
[0].bitfield
.xmmword
6616 || i
.types
[0].bitfield
.ymmword
);
6617 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6618 gas_assert (i
.types
[2].bitfield
.xmmword
6619 || i
.types
[2].bitfield
.ymmword
);
6620 if (operand_check
== check_none
)
6622 if (register_number (i
.op
[0].regs
)
6623 != register_number (i
.index_reg
)
6624 && register_number (i
.op
[2].regs
)
6625 != register_number (i
.index_reg
)
6626 && register_number (i
.op
[0].regs
)
6627 != register_number (i
.op
[2].regs
))
6629 if (operand_check
== check_error
)
6631 i
.error
= invalid_vector_register_set
;
6634 as_warn (_("mask, index, and destination registers should be distinct"));
6636 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6638 if (i
.types
[1].bitfield
.class == RegSIMD
6639 && (i
.types
[1].bitfield
.xmmword
6640 || i
.types
[1].bitfield
.ymmword
6641 || i
.types
[1].bitfield
.zmmword
)
6642 && (register_number (i
.op
[1].regs
)
6643 == register_number (i
.index_reg
)))
6645 if (operand_check
== check_error
)
6647 i
.error
= invalid_vector_register_set
;
6650 if (operand_check
!= check_none
)
6651 as_warn (_("index and destination registers should be distinct"));
6656 /* For AMX instructions with 3 TMM register operands, all operands
6657 must be distinct. */
6658 if (i
.reg_operands
== 3
6659 && t
->operand_types
[0].bitfield
.tmmword
6660 && (i
.op
[0].regs
== i
.op
[1].regs
6661 || i
.op
[0].regs
== i
.op
[2].regs
6662 || i
.op
[1].regs
== i
.op
[2].regs
))
6664 i
.error
= invalid_tmm_register_set
;
6668 /* For some special instructions require that destination must be distinct
6669 from source registers. */
6670 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6672 unsigned int dest_reg
= i
.operands
- 1;
6674 know (i
.operands
>= 3);
6676 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6677 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6678 || (i
.reg_operands
> 2
6679 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6681 i
.error
= invalid_dest_and_src_register_set
;
6686 /* Check if broadcast is supported by the instruction and is applied
6687 to the memory operand. */
6688 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6690 i386_operand_type type
, overlap
;
6692 /* Check if specified broadcast is supported in this instruction,
6693 and its broadcast bytes match the memory operand. */
6694 op
= i
.broadcast
.operand
;
6695 if (!t
->opcode_modifier
.broadcast
6696 || !(i
.flags
[op
] & Operand_Mem
)
6697 || (!i
.types
[op
].bitfield
.unspecified
6698 && !match_broadcast_size (t
, op
)))
6701 i
.error
= unsupported_broadcast
;
6705 operand_type_set (&type
, 0);
6706 switch (get_broadcast_bytes (t
, false))
6709 type
.bitfield
.word
= 1;
6712 type
.bitfield
.dword
= 1;
6715 type
.bitfield
.qword
= 1;
6718 type
.bitfield
.xmmword
= 1;
6721 if (vector_size
< VSZ256
)
6723 type
.bitfield
.ymmword
= 1;
6726 if (vector_size
< VSZ512
)
6728 type
.bitfield
.zmmword
= 1;
6734 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6735 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6736 && t
->operand_types
[op
].bitfield
.byte
6737 + t
->operand_types
[op
].bitfield
.word
6738 + t
->operand_types
[op
].bitfield
.dword
6739 + t
->operand_types
[op
].bitfield
.qword
> 1)
6741 overlap
.bitfield
.xmmword
= 0;
6742 overlap
.bitfield
.ymmword
= 0;
6743 overlap
.bitfield
.zmmword
= 0;
6745 if (operand_type_all_zero (&overlap
))
6748 if (t
->opcode_modifier
.checkoperandsize
)
6752 type
.bitfield
.baseindex
= 1;
6753 for (j
= 0; j
< i
.operands
; ++j
)
6756 && !operand_type_register_match(i
.types
[j
],
6757 t
->operand_types
[j
],
6759 t
->operand_types
[op
]))
6764 /* If broadcast is supported in this instruction, we need to check if
6765 operand of one-element size isn't specified without broadcast. */
6766 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6768 /* Find memory operand. */
6769 for (op
= 0; op
< i
.operands
; op
++)
6770 if (i
.flags
[op
] & Operand_Mem
)
6772 gas_assert (op
< i
.operands
);
6773 /* Check size of the memory operand. */
6774 if (match_broadcast_size (t
, op
))
6776 i
.error
= broadcast_needed
;
6781 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6783 /* Check if requested masking is supported. */
6786 if (!t
->opcode_modifier
.masking
)
6788 i
.error
= unsupported_masking
;
6792 /* Common rules for masking:
6793 - mask register destinations permit only zeroing-masking, without
6794 that actually being expressed by a {z} operand suffix or EVEX.z,
6795 - memory destinations allow only merging-masking,
6796 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6799 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6800 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6801 || t
->opcode_modifier
.sib
))
6803 i
.error
= unsupported_masking
;
6808 /* Check if masking is applied to dest operand. */
6809 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6811 i
.error
= mask_not_on_destination
;
6816 if (i
.rounding
.type
!= rc_none
)
6818 if (!t
->opcode_modifier
.sae
6819 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6822 i
.error
= unsupported_rc_sae
;
6826 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6828 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6830 for (op
= 0; op
< t
->operands
; ++op
)
6831 if (i
.types
[op
].bitfield
.zmmword
)
6833 if (op
>= t
->operands
)
6835 i
.error
= operand_size_mismatch
;
6841 /* Check the special Imm4 cases; must be the first operand. */
6842 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6844 if (i
.op
[0].imms
->X_op
!= O_constant
6845 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6851 /* Turn off Imm<N> so that update_imm won't complain. */
6852 operand_type_set (&i
.types
[0], 0);
6855 /* Check vector Disp8 operand. */
6856 if (t
->opcode_modifier
.disp8memshift
6857 && (!t
->opcode_modifier
.vex
6858 || need_evex_encoding ())
6859 && i
.disp_encoding
<= disp_encoding_8bit
)
6861 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6862 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6863 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6864 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6867 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6870 for (op
= 0; op
< i
.operands
; op
++)
6871 if (i
.flags
[op
] & Operand_Mem
)
6873 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6874 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6875 else if (t
->operand_types
[op
].bitfield
.xmmword
6876 + t
->operand_types
[op
].bitfield
.ymmword
6877 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6878 type
= &t
->operand_types
[op
];
6879 else if (!i
.types
[op
].bitfield
.unspecified
)
6880 type
= &i
.types
[op
];
6881 else /* Ambiguities get resolved elsewhere. */
6882 fallback
= &t
->operand_types
[op
];
6884 else if (i
.types
[op
].bitfield
.class == RegSIMD
6885 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6887 if (i
.types
[op
].bitfield
.zmmword
)
6889 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6891 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6895 if (!type
&& !i
.memshift
)
6899 if (type
->bitfield
.zmmword
)
6901 else if (type
->bitfield
.ymmword
)
6903 else if (type
->bitfield
.xmmword
)
6907 /* For the check in fits_in_disp8(). */
6908 if (i
.memshift
== 0)
6912 for (op
= 0; op
< i
.operands
; op
++)
6913 if (operand_type_check (i
.types
[op
], disp
)
6914 && i
.op
[op
].disps
->X_op
== O_constant
)
6916 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6918 i
.types
[op
].bitfield
.disp8
= 1;
6921 i
.types
[op
].bitfield
.disp8
= 0;
6930 /* Check if encoding requirements are met by the instruction. */
6933 VEX_check_encoding (const insn_template
*t
)
6935 if (i
.vec_encoding
== vex_encoding_error
)
6937 i
.error
= unsupported
;
6941 /* Vector size restrictions. */
6942 if ((vector_size
< VSZ512
6943 && (t
->opcode_modifier
.evex
== EVEX512
6944 || t
->opcode_modifier
.vsz
>= VSZ512
))
6945 || (vector_size
< VSZ256
6946 && (t
->opcode_modifier
.evex
== EVEX256
6947 || t
->opcode_modifier
.vex
== VEX256
6948 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6950 i
.error
= unsupported
;
6954 if (i
.vec_encoding
== vex_encoding_evex
6955 || i
.vec_encoding
== vex_encoding_evex512
)
6957 /* This instruction must be encoded with EVEX prefix. */
6958 if (!is_evex_encoding (t
))
6960 i
.error
= unsupported
;
6966 if (!t
->opcode_modifier
.vex
)
6968 /* This instruction template doesn't have VEX prefix. */
6969 if (i
.vec_encoding
!= vex_encoding_default
)
6971 i
.error
= unsupported
;
6980 /* Helper function for the progress() macro in match_template(). */
6981 static INLINE
enum i386_error
progress (enum i386_error
new,
6982 enum i386_error last
,
6983 unsigned int line
, unsigned int *line_p
)
6985 if (line
<= *line_p
)
6991 static const insn_template
*
6992 match_template (char mnem_suffix
)
6994 /* Points to template once we've found it. */
6995 const insn_template
*t
;
6996 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6997 i386_operand_type overlap4
;
6998 unsigned int found_reverse_match
;
6999 i386_operand_type operand_types
[MAX_OPERANDS
];
7000 int addr_prefix_disp
;
7001 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7002 enum i386_error specific_error
= number_of_operands_mismatch
;
7003 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7005 #if MAX_OPERANDS != 5
7006 # error "MAX_OPERANDS must be 5."
7009 found_reverse_match
= 0;
7010 addr_prefix_disp
= -1;
7012 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7014 addr_prefix_disp
= -1;
7015 found_reverse_match
= 0;
7017 /* Must have right number of operands. */
7018 if (i
.operands
!= t
->operands
)
7021 /* Check processor support. */
7022 specific_error
= progress (unsupported
);
7023 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7026 /* Check AT&T mnemonic. */
7027 specific_error
= progress (unsupported_with_intel_mnemonic
);
7028 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7031 /* Check AT&T/Intel syntax. */
7032 specific_error
= progress (unsupported_syntax
);
7033 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7034 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7037 /* Check Intel64/AMD64 ISA. */
7041 /* Default: Don't accept Intel64. */
7042 if (t
->opcode_modifier
.isa64
== INTEL64
)
7046 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7047 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7051 /* -mintel64: Don't accept AMD64. */
7052 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7057 /* Check the suffix. */
7058 specific_error
= progress (invalid_instruction_suffix
);
7059 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7060 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7061 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7062 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7063 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7066 specific_error
= progress (operand_size_mismatch
);
7067 size_match
= operand_size_match (t
);
7071 /* This is intentionally not
7073 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7075 as the case of a missing * on the operand is accepted (perhaps with
7076 a warning, issued further down). */
7077 specific_error
= progress (operand_type_mismatch
);
7078 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7081 /* In Intel syntax, normally we can check for memory operand size when
7082 there is no mnemonic suffix. But jmp and call have 2 different
7083 encodings with Dword memory operand size. Skip the "near" one
7084 (permitting a register operand) when "far" was requested. */
7086 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7087 && t
->operand_types
[0].bitfield
.class == Reg
)
7090 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7091 operand_types
[j
] = t
->operand_types
[j
];
7093 /* In general, don't allow 32-bit operands on pre-386. */
7094 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7095 : operand_size_mismatch
);
7096 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7097 if (i
.suffix
== LONG_MNEM_SUFFIX
7098 && !cpu_arch_flags
.bitfield
.cpui386
7100 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7101 && !intel_float_operand (insn_name (t
)))
7102 : intel_float_operand (insn_name (t
)) != 2)
7103 && (t
->operands
== i
.imm_operands
7104 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7105 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7106 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7107 || (operand_types
[j
].bitfield
.class != RegMMX
7108 && operand_types
[j
].bitfield
.class != RegSIMD
7109 && operand_types
[j
].bitfield
.class != RegMask
))
7110 && !t
->opcode_modifier
.sib
)
7113 /* Do not verify operands when there are none. */
7116 if (VEX_check_encoding (t
))
7118 specific_error
= progress (i
.error
);
7122 /* We've found a match; break out of loop. */
7126 if (!t
->opcode_modifier
.jump
7127 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7129 /* There should be only one Disp operand. */
7130 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7131 if (operand_type_check (operand_types
[j
], disp
))
7133 if (j
< MAX_OPERANDS
)
7135 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7137 addr_prefix_disp
= j
;
7139 /* Address size prefix will turn Disp64 operand into Disp32 and
7140 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7144 override
= !override
;
7147 if (operand_types
[j
].bitfield
.disp32
7148 && operand_types
[j
].bitfield
.disp16
)
7150 operand_types
[j
].bitfield
.disp16
= override
;
7151 operand_types
[j
].bitfield
.disp32
= !override
;
7153 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7157 if (operand_types
[j
].bitfield
.disp64
)
7159 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7160 operand_types
[j
].bitfield
.disp32
= override
;
7161 operand_types
[j
].bitfield
.disp64
= !override
;
7163 operand_types
[j
].bitfield
.disp16
= 0;
7169 /* We check register size if needed. */
7170 if (t
->opcode_modifier
.checkoperandsize
)
7172 check_register
= (1 << t
->operands
) - 1;
7173 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7174 check_register
&= ~(1 << i
.broadcast
.operand
);
7179 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7180 switch (t
->operands
)
7183 if (!operand_type_match (overlap0
, i
.types
[0]))
7186 /* Allow the ModR/M encoding to be requested by using the {load} or
7187 {store} pseudo prefix on an applicable insn. */
7188 if (!t
->opcode_modifier
.modrm
7189 && i
.reg_operands
== 1
7190 && ((i
.dir_encoding
== dir_encoding_load
7191 && t
->mnem_off
!= MN_pop
)
7192 || (i
.dir_encoding
== dir_encoding_store
7193 && t
->mnem_off
!= MN_push
))
7195 && t
->mnem_off
!= MN_bswap
)
7200 /* xchg %eax, %eax is a special case. It is an alias for nop
7201 only in 32bit mode and we can use opcode 0x90. In 64bit
7202 mode, we can't use 0x90 for xchg %eax, %eax since it should
7203 zero-extend %eax to %rax. */
7204 if (t
->base_opcode
== 0x90
7205 && t
->opcode_space
== SPACE_BASE
)
7207 if (flag_code
== CODE_64BIT
7208 && i
.types
[0].bitfield
.instance
== Accum
7209 && i
.types
[0].bitfield
.dword
7210 && i
.types
[1].bitfield
.instance
== Accum
)
7213 /* Allow the ModR/M encoding to be requested by using the
7214 {load} or {store} pseudo prefix. */
7215 if (i
.dir_encoding
== dir_encoding_load
7216 || i
.dir_encoding
== dir_encoding_store
)
7220 if (t
->base_opcode
== MOV_AX_DISP32
7221 && t
->opcode_space
== SPACE_BASE
7222 && t
->mnem_off
!= MN_movabs
)
7224 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7225 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7228 /* xrelease mov %eax, <disp> is another special case. It must not
7229 match the accumulator-only encoding of mov. */
7233 /* Allow the ModR/M encoding to be requested by using a suitable
7234 {load} or {store} pseudo prefix. */
7235 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7236 ? dir_encoding_store
7237 : dir_encoding_load
)
7238 && !i
.types
[0].bitfield
.disp64
7239 && !i
.types
[1].bitfield
.disp64
)
7243 /* Allow the ModR/M encoding to be requested by using the {load} or
7244 {store} pseudo prefix on an applicable insn. */
7245 if (!t
->opcode_modifier
.modrm
7246 && i
.reg_operands
== 1
7247 && i
.imm_operands
== 1
7248 && (i
.dir_encoding
== dir_encoding_load
7249 || i
.dir_encoding
== dir_encoding_store
)
7250 && t
->opcode_space
== SPACE_BASE
)
7252 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7253 && i
.dir_encoding
== dir_encoding_store
)
7256 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7257 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7258 || i
.dir_encoding
== dir_encoding_load
))
7261 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7262 && i
.dir_encoding
== dir_encoding_load
)
7268 if (!(size_match
& MATCH_STRAIGHT
))
7270 /* Reverse direction of operands if swapping is possible in the first
7271 place (operands need to be symmetric) and
7272 - the load form is requested, and the template is a store form,
7273 - the store form is requested, and the template is a load form,
7274 - the non-default (swapped) form is requested. */
7275 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7276 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7277 && !operand_type_all_zero (&overlap1
))
7278 switch (i
.dir_encoding
)
7280 case dir_encoding_load
:
7281 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7282 || t
->opcode_modifier
.regmem
)
7286 case dir_encoding_store
:
7287 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7288 && !t
->opcode_modifier
.regmem
)
7292 case dir_encoding_swap
:
7295 case dir_encoding_default
:
7298 /* If we want store form, we skip the current load. */
7299 if ((i
.dir_encoding
== dir_encoding_store
7300 || i
.dir_encoding
== dir_encoding_swap
)
7301 && i
.mem_operands
== 0
7302 && t
->opcode_modifier
.load
)
7307 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7308 if (!operand_type_match (overlap0
, i
.types
[0])
7309 || !operand_type_match (overlap1
, i
.types
[1])
7310 || ((check_register
& 3) == 3
7311 && !operand_type_register_match (i
.types
[0],
7316 specific_error
= progress (i
.error
);
7318 /* Check if other direction is valid ... */
7319 if (!t
->opcode_modifier
.d
)
7323 if (!(size_match
& MATCH_REVERSE
))
7325 /* Try reversing direction of operands. */
7326 j
= is_cpu (t
, CpuFMA4
)
7327 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7328 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7329 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7330 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7331 gas_assert (t
->operands
!= 3 || !check_register
);
7332 if (!operand_type_match (overlap0
, i
.types
[0])
7333 || !operand_type_match (overlap1
, i
.types
[j
])
7334 || (t
->operands
== 3
7335 && !operand_type_match (overlap2
, i
.types
[1]))
7337 && !operand_type_register_match (i
.types
[0],
7342 /* Does not match either direction. */
7343 specific_error
= progress (i
.error
);
7346 /* found_reverse_match holds which variant of D
7348 if (!t
->opcode_modifier
.d
)
7349 found_reverse_match
= 0;
7350 else if (operand_types
[0].bitfield
.tbyte
)
7352 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7353 found_reverse_match
= Opcode_FloatD
;
7355 found_reverse_match
= ~0;
7356 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7357 if ((t
->extension_opcode
& 4)
7358 && (intel_syntax
|| intel_mnemonic
))
7359 found_reverse_match
|= Opcode_FloatR
;
7361 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7363 found_reverse_match
= Opcode_VexW
;
7364 goto check_operands_345
;
7366 else if (t
->opcode_space
!= SPACE_BASE
7367 && (t
->opcode_space
!= SPACE_0F
7368 /* MOV to/from CR/DR/TR, as an exception, follow
7369 the base opcode space encoding model. */
7370 || (t
->base_opcode
| 7) != 0x27))
7371 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7372 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7373 else if (!t
->opcode_modifier
.commutative
)
7374 found_reverse_match
= Opcode_D
;
7376 found_reverse_match
= ~0;
7380 /* Found a forward 2 operand match here. */
7382 switch (t
->operands
)
7385 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7386 if (!operand_type_match (overlap4
, i
.types
[4])
7387 || !operand_type_register_match (i
.types
[3],
7392 specific_error
= progress (i
.error
);
7397 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7398 if (!operand_type_match (overlap3
, i
.types
[3])
7399 || ((check_register
& 0xa) == 0xa
7400 && !operand_type_register_match (i
.types
[1],
7404 || ((check_register
& 0xc) == 0xc
7405 && !operand_type_register_match (i
.types
[2],
7410 specific_error
= progress (i
.error
);
7415 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7416 if (!operand_type_match (overlap2
, i
.types
[2])
7417 || ((check_register
& 5) == 5
7418 && !operand_type_register_match (i
.types
[0],
7422 || ((check_register
& 6) == 6
7423 && !operand_type_register_match (i
.types
[1],
7428 specific_error
= progress (i
.error
);
7434 /* Found either forward/reverse 2, 3 or 4 operand match here:
7435 slip through to break. */
7438 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7439 if (VEX_check_encoding (t
))
7441 specific_error
= progress (i
.error
);
7445 /* Check if vector operands are valid. */
7446 if (check_VecOperands (t
))
7448 specific_error
= progress (i
.error
);
7452 /* Check whether to use the shorter VEX encoding for certain insns where
7453 the EVEX enconding comes first in the table. This requires the respective
7454 AVX-* feature to be explicitly enabled. */
7455 if (t
== current_templates
->start
7456 && t
->opcode_modifier
.disp8memshift
7457 && !t
->opcode_modifier
.vex
7458 && !need_evex_encoding ()
7459 && t
+ 1 < current_templates
->end
7460 && t
[1].opcode_modifier
.vex
)
7463 unsigned int memshift
= i
.memshift
;
7466 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7467 if (!cpu_flags_all_zero (&cpu
)
7468 && (!i
.types
[0].bitfield
.disp8
7469 || !operand_type_check (i
.types
[0], disp
)
7470 || i
.op
[0].disps
->X_op
!= O_constant
7471 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7473 specific_error
= progress (internal_error
);
7476 i
.memshift
= memshift
;
7479 /* We've found a match; break out of loop. */
7485 if (t
== current_templates
->end
)
7487 /* We found no match. */
7488 i
.error
= specific_error
;
7492 if (!quiet_warnings
)
7495 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7496 as_warn (_("indirect %s without `*'"), insn_name (t
));
7498 if (t
->opcode_modifier
.isprefix
7499 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7501 /* Warn them that a data or address size prefix doesn't
7502 affect assembly of the next line of code. */
7503 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7507 /* Copy the template we found. */
7508 install_template (t
);
7510 if (addr_prefix_disp
!= -1)
7511 i
.tm
.operand_types
[addr_prefix_disp
]
7512 = operand_types
[addr_prefix_disp
];
7514 switch (found_reverse_match
)
7520 case Opcode_FloatR
| Opcode_FloatD
:
7521 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7522 found_reverse_match
&= Opcode_FloatD
;
7526 /* If we found a reverse match we must alter the opcode direction
7527 bit and clear/flip the regmem modifier one. found_reverse_match
7528 holds bits to change (different for int & float insns). */
7530 i
.tm
.base_opcode
^= found_reverse_match
;
7532 /* Certain SIMD insns have their load forms specified in the opcode
7533 table, and hence we need to _set_ RegMem instead of clearing it.
7534 We need to avoid setting the bit though on insns like KMOVW. */
7535 i
.tm
.opcode_modifier
.regmem
7536 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7537 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7538 && !i
.tm
.opcode_modifier
.regmem
;
7542 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7543 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7547 /* Only the first two register operands need reversing, alongside
7549 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7551 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7552 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7553 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7557 /* This pattern aims to put the unusually placed imm operand to a usual
7558 place. The constraints are currently only adapted to uwrmsr, and may
7559 need further tweaking when new similar instructions become available. */
7560 if (i
.imm_operands
&& i
.imm_operands
< i
.operands
7561 && operand_type_check (operand_types
[i
.operands
- 1], imm
))
7563 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7564 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7565 swap_2_operands(0, i
.operands
- 1);
7574 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7575 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7577 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7579 as_bad (_("`%s' operand %u must use `%ses' segment"),
7581 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7586 /* There's only ever one segment override allowed per instruction.
7587 This instruction possibly has a legal segment override on the
7588 second operand, so copy the segment to where non-string
7589 instructions store it, allowing common code. */
7590 i
.seg
[op
] = i
.seg
[1];
7596 process_suffix (void)
7598 bool is_movx
= false;
7600 /* If matched instruction specifies an explicit instruction mnemonic
7602 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7603 i
.suffix
= WORD_MNEM_SUFFIX
;
7604 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7605 i
.suffix
= LONG_MNEM_SUFFIX
;
7606 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7607 i
.suffix
= QWORD_MNEM_SUFFIX
;
7608 else if (i
.reg_operands
7609 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7610 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7612 unsigned int numop
= i
.operands
;
7615 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7616 && (i
.tm
.base_opcode
| 8) == 0xbe)
7617 || (i
.tm
.opcode_space
== SPACE_BASE
7618 && i
.tm
.base_opcode
== 0x63
7619 && is_cpu (&i
.tm
, Cpu64
));
7621 /* movsx/movzx want only their source operand considered here, for the
7622 ambiguity checking below. The suffix will be replaced afterwards
7623 to represent the destination (register). */
7624 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7627 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7628 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7631 /* If there's no instruction mnemonic suffix we try to invent one
7632 based on GPR operands. */
7635 /* We take i.suffix from the last register operand specified,
7636 Destination register type is more significant than source
7637 register type. crc32 in SSE4.2 prefers source register
7639 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7642 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7643 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7645 if (i
.types
[op
].bitfield
.class != Reg
)
7647 if (i
.types
[op
].bitfield
.byte
)
7648 i
.suffix
= BYTE_MNEM_SUFFIX
;
7649 else if (i
.types
[op
].bitfield
.word
)
7650 i
.suffix
= WORD_MNEM_SUFFIX
;
7651 else if (i
.types
[op
].bitfield
.dword
)
7652 i
.suffix
= LONG_MNEM_SUFFIX
;
7653 else if (i
.types
[op
].bitfield
.qword
)
7654 i
.suffix
= QWORD_MNEM_SUFFIX
;
7660 /* As an exception, movsx/movzx silently default to a byte source
7662 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7663 i
.suffix
= BYTE_MNEM_SUFFIX
;
7665 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7667 if (!check_byte_reg ())
7670 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7672 if (!check_long_reg ())
7675 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7677 if (!check_qword_reg ())
7680 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7682 if (!check_word_reg ())
7685 else if (intel_syntax
7686 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7687 /* Do nothing if the instruction is going to ignore the prefix. */
7692 /* Undo the movsx/movzx change done above. */
7695 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7698 i
.suffix
= stackop_size
;
7699 if (stackop_size
== LONG_MNEM_SUFFIX
)
7701 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7702 .code16gcc directive to support 16-bit mode with
7703 32-bit address. For IRET without a suffix, generate
7704 16-bit IRET (opcode 0xcf) to return from an interrupt
7706 if (i
.tm
.base_opcode
== 0xcf)
7708 i
.suffix
= WORD_MNEM_SUFFIX
;
7709 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7711 /* Warn about changed behavior for segment register push/pop. */
7712 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7713 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7718 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7719 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7720 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7721 || (i
.tm
.opcode_space
== SPACE_0F
7722 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7723 && i
.tm
.extension_opcode
<= 3)))
7728 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7730 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7731 || i
.tm
.opcode_modifier
.no_lsuf
)
7732 i
.suffix
= QWORD_MNEM_SUFFIX
;
7737 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7738 i
.suffix
= LONG_MNEM_SUFFIX
;
7741 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7742 i
.suffix
= WORD_MNEM_SUFFIX
;
7748 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7749 /* Also cover lret/retf/iret in 64-bit mode. */
7750 || (flag_code
== CODE_64BIT
7751 && !i
.tm
.opcode_modifier
.no_lsuf
7752 && !i
.tm
.opcode_modifier
.no_qsuf
))
7753 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7754 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7755 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7756 /* Accept FLDENV et al without suffix. */
7757 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7759 unsigned int suffixes
, evex
= 0;
7761 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7762 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7764 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7766 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7768 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7771 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7772 also suitable for AT&T syntax mode, it was requested that this be
7773 restricted to just Intel syntax. */
7774 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7775 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7779 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7781 if (vector_size
< VSZ512
)
7783 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7784 if (vector_size
< VSZ256
)
7786 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7787 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7788 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7789 || (!i
.tm
.opcode_modifier
.evex
7790 && is_evex_encoding (&i
.tm
))))
7791 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7793 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7794 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7795 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7796 || (!i
.tm
.opcode_modifier
.evex
7797 && is_evex_encoding (&i
.tm
))))
7798 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7800 else if (is_evex_encoding (&i
.tm
)
7801 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7803 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7804 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7805 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7806 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7807 if (!i
.tm
.opcode_modifier
.evex
7808 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7809 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7812 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7813 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7814 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7817 /* Any properly sized operand disambiguates the insn. */
7818 if (i
.types
[op
].bitfield
.xmmword
7819 || i
.types
[op
].bitfield
.ymmword
7820 || i
.types
[op
].bitfield
.zmmword
)
7822 suffixes
&= ~(7 << 6);
7827 if ((i
.flags
[op
] & Operand_Mem
)
7828 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7830 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7832 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7834 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7836 if (is_evex_encoding (&i
.tm
))
7842 /* Are multiple suffixes / operand sizes allowed? */
7843 if (suffixes
& (suffixes
- 1))
7846 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7847 || operand_check
== check_error
))
7849 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7852 if (operand_check
== check_error
)
7854 as_bad (_("no instruction mnemonic suffix given and "
7855 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7858 if (operand_check
== check_warning
)
7859 as_warn (_("%s; using default for `%s'"),
7861 ? _("ambiguous operand size")
7862 : _("no instruction mnemonic suffix given and "
7863 "no register operands"),
7866 if (i
.tm
.opcode_modifier
.floatmf
)
7867 i
.suffix
= SHORT_MNEM_SUFFIX
;
7869 /* handled below */;
7871 i
.tm
.opcode_modifier
.evex
= evex
;
7872 else if (flag_code
== CODE_16BIT
)
7873 i
.suffix
= WORD_MNEM_SUFFIX
;
7874 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7875 i
.suffix
= LONG_MNEM_SUFFIX
;
7877 i
.suffix
= QWORD_MNEM_SUFFIX
;
7883 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7884 In AT&T syntax, if there is no suffix (warned about above), the default
7885 will be byte extension. */
7886 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7887 i
.tm
.base_opcode
|= 1;
7889 /* For further processing, the suffix should represent the destination
7890 (register). This is already the case when one was used with
7891 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7892 no suffix to begin with. */
7893 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7895 if (i
.types
[1].bitfield
.word
)
7896 i
.suffix
= WORD_MNEM_SUFFIX
;
7897 else if (i
.types
[1].bitfield
.qword
)
7898 i
.suffix
= QWORD_MNEM_SUFFIX
;
7900 i
.suffix
= LONG_MNEM_SUFFIX
;
7902 i
.tm
.opcode_modifier
.w
= 0;
7906 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7907 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7908 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7910 /* Change the opcode based on the operand size given by i.suffix. */
7913 /* Size floating point instruction. */
7914 case LONG_MNEM_SUFFIX
:
7915 if (i
.tm
.opcode_modifier
.floatmf
)
7917 i
.tm
.base_opcode
^= 4;
7921 case WORD_MNEM_SUFFIX
:
7922 case QWORD_MNEM_SUFFIX
:
7923 /* It's not a byte, select word/dword operation. */
7924 if (i
.tm
.opcode_modifier
.w
)
7927 i
.tm
.base_opcode
|= 8;
7929 i
.tm
.base_opcode
|= 1;
7932 case SHORT_MNEM_SUFFIX
:
7933 /* Now select between word & dword operations via the operand
7934 size prefix, except for instructions that will ignore this
7936 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7937 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7938 && !i
.tm
.opcode_modifier
.floatmf
7939 && !is_any_vex_encoding (&i
.tm
)
7940 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7941 || (flag_code
== CODE_64BIT
7942 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7944 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7946 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7947 prefix
= ADDR_PREFIX_OPCODE
;
7949 if (!add_prefix (prefix
))
7953 /* Set mode64 for an operand. */
7954 if (i
.suffix
== QWORD_MNEM_SUFFIX
7955 && flag_code
== CODE_64BIT
7956 && !i
.tm
.opcode_modifier
.norex64
7957 && !i
.tm
.opcode_modifier
.vexw
7958 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7960 && ! (i
.operands
== 2
7961 && i
.tm
.base_opcode
== 0x90
7962 && i
.tm
.opcode_space
== SPACE_BASE
7963 && i
.types
[0].bitfield
.instance
== Accum
7964 && i
.types
[0].bitfield
.qword
7965 && i
.types
[1].bitfield
.instance
== Accum
))
7971 /* Select word/dword/qword operation with explicit data sizing prefix
7972 when there are no suitable register operands. */
7973 if (i
.tm
.opcode_modifier
.w
7974 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7976 || (i
.reg_operands
== 1
7978 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7980 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7981 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7982 || i
.tm
.mnem_off
== MN_crc32
))))
7983 i
.tm
.base_opcode
|= 1;
7987 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7989 gas_assert (!i
.suffix
);
7990 gas_assert (i
.reg_operands
);
7992 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7995 /* The address size override prefix changes the size of the
7997 if (flag_code
== CODE_64BIT
7998 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
8000 as_bad (_("16-bit addressing unavailable for `%s'"),
8005 if ((flag_code
== CODE_32BIT
8006 ? i
.op
[0].regs
->reg_type
.bitfield
.word
8007 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
8008 && !add_prefix (ADDR_PREFIX_OPCODE
))
8013 /* Check invalid register operand when the address size override
8014 prefix changes the size of register operands. */
8016 enum { need_word
, need_dword
, need_qword
} need
;
8018 /* Check the register operand for the address size prefix if
8019 the memory operand has no real registers, like symbol, DISP
8020 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8021 if (i
.mem_operands
== 1
8022 && i
.reg_operands
== 1
8024 && i
.types
[1].bitfield
.class == Reg
8025 && (flag_code
== CODE_32BIT
8026 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8027 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8028 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8029 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8030 || (x86_elf_abi
== X86_64_X32_ABI
8032 && i
.base_reg
->reg_num
== RegIP
8033 && i
.base_reg
->reg_type
.bitfield
.qword
))
8037 && !add_prefix (ADDR_PREFIX_OPCODE
))
8040 if (flag_code
== CODE_32BIT
)
8041 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8042 else if (i
.prefix
[ADDR_PREFIX
])
8045 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8047 for (op
= 0; op
< i
.operands
; op
++)
8049 if (i
.types
[op
].bitfield
.class != Reg
)
8055 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8059 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8063 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8068 as_bad (_("invalid register operand size for `%s'"),
8079 check_byte_reg (void)
8083 for (op
= i
.operands
; --op
>= 0;)
8085 /* Skip non-register operands. */
8086 if (i
.types
[op
].bitfield
.class != Reg
)
8089 /* If this is an eight bit register, it's OK. If it's the 16 or
8090 32 bit version of an eight bit register, we will just use the
8091 low portion, and that's OK too. */
8092 if (i
.types
[op
].bitfield
.byte
)
8095 /* I/O port address operands are OK too. */
8096 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8097 && i
.tm
.operand_types
[op
].bitfield
.word
)
8100 /* crc32 only wants its source operand checked here. */
8101 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8104 /* Any other register is bad. */
8105 as_bad (_("`%s%s' not allowed with `%s%c'"),
8106 register_prefix
, i
.op
[op
].regs
->reg_name
,
8107 insn_name (&i
.tm
), i
.suffix
);
8114 check_long_reg (void)
8118 for (op
= i
.operands
; --op
>= 0;)
8119 /* Skip non-register operands. */
8120 if (i
.types
[op
].bitfield
.class != Reg
)
8122 /* Reject eight bit registers, except where the template requires
8123 them. (eg. movzb) */
8124 else if (i
.types
[op
].bitfield
.byte
8125 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8126 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8127 && (i
.tm
.operand_types
[op
].bitfield
.word
8128 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8130 as_bad (_("`%s%s' not allowed with `%s%c'"),
8132 i
.op
[op
].regs
->reg_name
,
8137 /* Error if the e prefix on a general reg is missing. */
8138 else if (i
.types
[op
].bitfield
.word
8139 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8140 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8141 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8143 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8144 register_prefix
, i
.op
[op
].regs
->reg_name
,
8148 /* Warn if the r prefix on a general reg is present. */
8149 else if (i
.types
[op
].bitfield
.qword
8150 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8151 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8152 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8154 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8155 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8162 check_qword_reg (void)
8166 for (op
= i
.operands
; --op
>= 0; )
8167 /* Skip non-register operands. */
8168 if (i
.types
[op
].bitfield
.class != Reg
)
8170 /* Reject eight bit registers, except where the template requires
8171 them. (eg. movzb) */
8172 else if (i
.types
[op
].bitfield
.byte
8173 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8174 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8175 && (i
.tm
.operand_types
[op
].bitfield
.word
8176 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8178 as_bad (_("`%s%s' not allowed with `%s%c'"),
8180 i
.op
[op
].regs
->reg_name
,
8185 /* Warn if the r prefix on a general reg is missing. */
8186 else if ((i
.types
[op
].bitfield
.word
8187 || i
.types
[op
].bitfield
.dword
)
8188 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8189 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8190 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8192 /* Prohibit these changes in the 64bit mode, since the
8193 lowering is more complicated. */
8194 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8195 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8202 check_word_reg (void)
8205 for (op
= i
.operands
; --op
>= 0;)
8206 /* Skip non-register operands. */
8207 if (i
.types
[op
].bitfield
.class != Reg
)
8209 /* Reject eight bit registers, except where the template requires
8210 them. (eg. movzb) */
8211 else if (i
.types
[op
].bitfield
.byte
8212 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8213 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8214 && (i
.tm
.operand_types
[op
].bitfield
.word
8215 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8217 as_bad (_("`%s%s' not allowed with `%s%c'"),
8219 i
.op
[op
].regs
->reg_name
,
8224 /* Error if the e or r prefix on a general reg is present. */
8225 else if ((i
.types
[op
].bitfield
.dword
8226 || i
.types
[op
].bitfield
.qword
)
8227 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8228 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8229 && i
.tm
.operand_types
[op
].bitfield
.word
)
8231 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8232 register_prefix
, i
.op
[op
].regs
->reg_name
,
8240 update_imm (unsigned int j
)
8242 i386_operand_type overlap
= i
.types
[j
];
8244 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8245 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8246 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8248 /* This combination is used on 8-bit immediates where e.g. $~0 is
8249 desirable to permit. We're past operand type matching, so simply
8250 put things back in the shape they were before introducing the
8251 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8252 overlap
.bitfield
.imm8s
= 0;
8255 if (overlap
.bitfield
.imm8
8256 + overlap
.bitfield
.imm8s
8257 + overlap
.bitfield
.imm16
8258 + overlap
.bitfield
.imm32
8259 + overlap
.bitfield
.imm32s
8260 + overlap
.bitfield
.imm64
> 1)
8262 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8263 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8264 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8265 static const i386_operand_type imm16_32
= { .bitfield
=
8266 { .imm16
= 1, .imm32
= 1 }
8268 static const i386_operand_type imm16_32s
= { .bitfield
=
8269 { .imm16
= 1, .imm32s
= 1 }
8271 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8272 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8277 i386_operand_type temp
;
8279 operand_type_set (&temp
, 0);
8280 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8282 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8283 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8285 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8286 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8287 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8289 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8290 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8293 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8296 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8297 || operand_type_equal (&overlap
, &imm16_32
)
8298 || operand_type_equal (&overlap
, &imm16_32s
))
8300 if ((flag_code
== CODE_16BIT
)
8301 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8306 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8307 overlap
= operand_type_and (overlap
, imm32s
);
8308 else if (i
.prefix
[DATA_PREFIX
])
8309 overlap
= operand_type_and (overlap
,
8310 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8311 if (overlap
.bitfield
.imm8
8312 + overlap
.bitfield
.imm8s
8313 + overlap
.bitfield
.imm16
8314 + overlap
.bitfield
.imm32
8315 + overlap
.bitfield
.imm32s
8316 + overlap
.bitfield
.imm64
!= 1)
8318 as_bad (_("no instruction mnemonic suffix given; "
8319 "can't determine immediate size"));
8323 i
.types
[j
] = overlap
;
8333 /* Update the first 2 immediate operands. */
8334 n
= i
.operands
> 2 ? 2 : i
.operands
;
8337 for (j
= 0; j
< n
; j
++)
8338 if (update_imm (j
) == 0)
8341 /* The 3rd operand can't be immediate operand. */
8342 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8348 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8351 if (r
->reg_flags
& RegRex
)
8353 if (i
.rex
& rex_bit
)
8354 as_bad (_("same type of prefix used twice"));
8357 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8359 gas_assert (i
.vex
.register_specifier
== r
);
8360 i
.vex
.register_specifier
+= 8;
8363 if (r
->reg_flags
& RegVRex
)
8368 process_operands (void)
8370 /* Default segment register this instruction will use for memory
8371 accesses. 0 means unknown. This is only for optimizing out
8372 unnecessary segment overrides. */
8373 const reg_entry
*default_seg
= NULL
;
8375 /* We only need to check those implicit registers for instructions
8376 with 3 operands or less. */
8377 if (i
.operands
<= 3)
8378 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8379 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8382 if (i
.tm
.opcode_modifier
.sse2avx
)
8384 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8386 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8387 i
.prefix
[REX_PREFIX
] = 0;
8390 /* ImmExt should be processed after SSE2AVX. */
8391 else if (i
.tm
.opcode_modifier
.immext
)
8394 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8395 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8396 new destination operand here, while converting the source one to register
8398 if (i
.tm
.mnem_off
== MN_tilezero
)
8400 i
.op
[1].regs
= i
.op
[0].regs
;
8401 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8402 i
.types
[1] = i
.types
[0];
8403 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8404 i
.flags
[1] = i
.flags
[0];
8410 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8412 static const i386_operand_type regxmm
= {
8413 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8415 unsigned int dupl
= i
.operands
;
8416 unsigned int dest
= dupl
- 1;
8419 /* The destination must be an xmm register. */
8420 gas_assert (i
.reg_operands
8421 && MAX_OPERANDS
> dupl
8422 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8424 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8425 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8427 /* Keep xmm0 for instructions with VEX prefix and 3
8429 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8430 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8435 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8437 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8439 /* Add the implicit xmm0 for instructions with VEX prefix
8441 for (j
= i
.operands
; j
> 0; j
--)
8443 i
.op
[j
] = i
.op
[j
- 1];
8444 i
.types
[j
] = i
.types
[j
- 1];
8445 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8446 i
.flags
[j
] = i
.flags
[j
- 1];
8449 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8450 i
.types
[0] = regxmm
;
8451 i
.tm
.operand_types
[0] = regxmm
;
8454 i
.reg_operands
+= 2;
8459 i
.op
[dupl
] = i
.op
[dest
];
8460 i
.types
[dupl
] = i
.types
[dest
];
8461 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8462 i
.flags
[dupl
] = i
.flags
[dest
];
8471 i
.op
[dupl
] = i
.op
[dest
];
8472 i
.types
[dupl
] = i
.types
[dest
];
8473 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8474 i
.flags
[dupl
] = i
.flags
[dest
];
8477 if (i
.tm
.opcode_modifier
.immext
)
8480 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8481 && i
.tm
.opcode_modifier
.modrm
)
8485 for (j
= 1; j
< i
.operands
; j
++)
8487 i
.op
[j
- 1] = i
.op
[j
];
8488 i
.types
[j
- 1] = i
.types
[j
];
8490 /* We need to adjust fields in i.tm since they are used by
8491 build_modrm_byte. */
8492 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8494 i
.flags
[j
- 1] = i
.flags
[j
];
8497 /* No adjustment to i.reg_operands: This was already done at the top
8502 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8504 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8506 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8507 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8508 regnum
= register_number (i
.op
[1].regs
);
8509 first_reg_in_group
= regnum
& ~3;
8510 last_reg_in_group
= first_reg_in_group
+ 3;
8511 if (regnum
!= first_reg_in_group
)
8512 as_warn (_("source register `%s%s' implicitly denotes"
8513 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8514 register_prefix
, i
.op
[1].regs
->reg_name
,
8515 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8516 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8519 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8521 /* The imul $imm, %reg instruction is converted into
8522 imul $imm, %reg, %reg, and the clr %reg instruction
8523 is converted into xor %reg, %reg. */
8525 unsigned int first_reg_op
;
8527 if (operand_type_check (i
.types
[0], reg
))
8531 /* Pretend we saw the extra register operand. */
8532 gas_assert (i
.reg_operands
== 1
8533 && i
.op
[first_reg_op
+ 1].regs
== 0);
8534 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8535 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8540 if (i
.tm
.opcode_modifier
.modrm
)
8542 /* The opcode is completed (modulo i.tm.extension_opcode which
8543 must be put into the modrm byte). Now, we make the modrm and
8544 index base bytes based on all the info we've collected. */
8546 default_seg
= build_modrm_byte ();
8548 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8550 /* Warn about some common errors, but press on regardless. */
8551 if (i
.operands
== 2)
8553 /* Reversed arguments on faddp or fmulp. */
8554 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8555 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8556 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8558 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8560 /* Extraneous `l' suffix on fp insn. */
8561 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8562 register_prefix
, i
.op
[0].regs
->reg_name
);
8566 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8568 if (flag_code
!= CODE_64BIT
8569 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8570 && i
.op
[0].regs
->reg_num
== 1
8571 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8572 && i
.op
[0].regs
->reg_num
< 4)
8574 as_bad (_("you can't `%s %s%s'"),
8575 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8578 if (i
.op
[0].regs
->reg_num
> 3
8579 && i
.tm
.opcode_space
== SPACE_BASE
)
8581 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8582 i
.tm
.opcode_space
= SPACE_0F
;
8584 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8586 else if (i
.tm
.opcode_space
== SPACE_BASE
8587 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8589 default_seg
= reg_ds
;
8591 else if (i
.tm
.opcode_modifier
.isstring
)
8593 /* For the string instructions that allow a segment override
8594 on one of their operands, the default segment is ds. */
8595 default_seg
= reg_ds
;
8597 else if (i
.short_form
)
8599 /* The register operand is in the 1st or 2nd non-immediate operand. */
8600 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8603 && r
->reg_type
.bitfield
.instance
== Accum
8604 && i
.op
[i
.imm_operands
+ 1].regs
)
8605 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8606 /* Register goes in low 3 bits of opcode. */
8607 i
.tm
.base_opcode
|= r
->reg_num
;
8608 set_rex_vrex (r
, REX_B
, false);
8610 if (dot_insn () && i
.reg_operands
== 2)
8612 gas_assert (is_any_vex_encoding (&i
.tm
)
8613 || i
.vec_encoding
!= vex_encoding_default
);
8614 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8617 else if (i
.reg_operands
== 1
8618 && !i
.flags
[i
.operands
- 1]
8619 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8622 gas_assert (is_any_vex_encoding (&i
.tm
)
8623 || i
.vec_encoding
!= vex_encoding_default
);
8624 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8627 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8628 && i
.tm
.mnem_off
== MN_lea
)
8630 if (!quiet_warnings
)
8631 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8632 if (optimize
&& !i
.no_optimize
)
8635 i
.prefix
[SEG_PREFIX
] = 0;
8639 /* If a segment was explicitly specified, and the specified segment
8640 is neither the default nor the one already recorded from a prefix,
8641 use an opcode prefix to select it. If we never figured out what
8642 the default segment is, then default_seg will be zero at this
8643 point, and the specified segment prefix will always be used. */
8645 && i
.seg
[0] != default_seg
8646 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8648 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8654 static const reg_entry
*
8655 build_modrm_byte (void)
8657 const reg_entry
*default_seg
= NULL
;
8658 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8659 /* Compensate for kludge in md_assemble(). */
8660 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8661 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8662 unsigned int v
, op
, reg_slot
= ~0;
8664 /* Accumulator (in particular %st), shift count (%cl), and alike need
8665 to be skipped just like immediate operands do. */
8666 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8668 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8671 for (op
= source
; op
< i
.operands
; ++op
)
8672 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8675 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8679 /* There are 2 kinds of instructions:
8680 1. 5 operands: 4 register operands or 3 register operands
8681 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8682 VexW0 or VexW1. The destination must be either XMM, YMM or
8684 2. 4 operands: 4 register operands or 3 register operands
8685 plus 1 memory operand, with VexXDS.
8686 3. Other equivalent combinations when coming from s_insn(). */
8687 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8688 && i
.tm
.opcode_modifier
.vexw
);
8689 gas_assert (dot_insn ()
8690 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8692 /* Of the first two non-immediate operands the one with the template
8693 not allowing for a memory one is encoded in the immediate operand. */
8695 reg_slot
= source
+ 1;
8697 reg_slot
= source
++;
8701 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8702 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8705 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8707 if (i
.imm_operands
== 0)
8709 /* When there is no immediate operand, generate an 8bit
8710 immediate operand to encode the first operand. */
8711 exp
= &im_expressions
[i
.imm_operands
++];
8712 i
.op
[i
.operands
].imms
= exp
;
8713 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8716 exp
->X_op
= O_constant
;
8720 gas_assert (i
.imm_operands
== 1);
8721 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8722 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8724 /* Turn on Imm8 again so that output_imm will generate it. */
8725 i
.types
[0].bitfield
.imm8
= 1;
8729 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8730 << (3 + !(is_evex_encoding (&i
.tm
)
8731 || i
.vec_encoding
== vex_encoding_evex
));
8734 for (v
= source
+ 1; v
< dest
; ++v
)
8739 if (i
.tm
.extension_opcode
!= None
)
8745 gas_assert (source
< dest
);
8746 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8749 unsigned int tmp
= source
;
8755 if (v
< MAX_OPERANDS
)
8757 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8758 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8761 if (op
< i
.operands
)
8765 unsigned int fake_zero_displacement
= 0;
8767 gas_assert (i
.flags
[op
] & Operand_Mem
);
8769 if (i
.tm
.opcode_modifier
.sib
)
8771 /* The index register of VSIB shouldn't be RegIZ. */
8772 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8773 && i
.index_reg
->reg_num
== RegIZ
)
8776 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8779 i
.sib
.base
= NO_BASE_REGISTER
;
8780 i
.sib
.scale
= i
.log2_scale_factor
;
8781 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8782 i
.types
[op
].bitfield
.disp32
= 1;
8785 /* Since the mandatory SIB always has index register, so
8786 the code logic remains unchanged. The non-mandatory SIB
8787 without index register is allowed and will be handled
8791 if (i
.index_reg
->reg_num
== RegIZ
)
8792 i
.sib
.index
= NO_INDEX_REGISTER
;
8794 i
.sib
.index
= i
.index_reg
->reg_num
;
8795 set_rex_vrex (i
.index_reg
, REX_X
, false);
8799 default_seg
= reg_ds
;
8801 if (i
.base_reg
== 0)
8804 if (!i
.disp_operands
)
8805 fake_zero_displacement
= 1;
8806 if (i
.index_reg
== 0)
8808 /* Both check for VSIB and mandatory non-vector SIB. */
8809 gas_assert (!i
.tm
.opcode_modifier
.sib
8810 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8811 /* Operand is just <disp> */
8812 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8813 if (flag_code
== CODE_64BIT
)
8815 /* 64bit mode overwrites the 32bit absolute
8816 addressing by RIP relative addressing and
8817 absolute addressing is encoded by one of the
8818 redundant SIB forms. */
8819 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8820 i
.sib
.base
= NO_BASE_REGISTER
;
8821 i
.sib
.index
= NO_INDEX_REGISTER
;
8822 i
.types
[op
].bitfield
.disp32
= 1;
8824 else if ((flag_code
== CODE_16BIT
)
8825 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8827 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8828 i
.types
[op
].bitfield
.disp16
= 1;
8832 i
.rm
.regmem
= NO_BASE_REGISTER
;
8833 i
.types
[op
].bitfield
.disp32
= 1;
8836 else if (!i
.tm
.opcode_modifier
.sib
)
8838 /* !i.base_reg && i.index_reg */
8839 if (i
.index_reg
->reg_num
== RegIZ
)
8840 i
.sib
.index
= NO_INDEX_REGISTER
;
8842 i
.sib
.index
= i
.index_reg
->reg_num
;
8843 i
.sib
.base
= NO_BASE_REGISTER
;
8844 i
.sib
.scale
= i
.log2_scale_factor
;
8845 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8846 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8847 i
.types
[op
].bitfield
.disp32
= 1;
8848 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8852 /* RIP addressing for 64bit mode. */
8853 else if (i
.base_reg
->reg_num
== RegIP
)
8855 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8856 i
.rm
.regmem
= NO_BASE_REGISTER
;
8857 i
.types
[op
].bitfield
.disp8
= 0;
8858 i
.types
[op
].bitfield
.disp16
= 0;
8859 i
.types
[op
].bitfield
.disp32
= 1;
8860 i
.types
[op
].bitfield
.disp64
= 0;
8861 i
.flags
[op
] |= Operand_PCrel
;
8862 if (! i
.disp_operands
)
8863 fake_zero_displacement
= 1;
8865 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8867 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8868 switch (i
.base_reg
->reg_num
)
8871 if (i
.index_reg
== 0)
8873 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8874 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8877 default_seg
= reg_ss
;
8878 if (i
.index_reg
== 0)
8881 if (operand_type_check (i
.types
[op
], disp
) == 0)
8883 /* fake (%bp) into 0(%bp) */
8884 if (i
.disp_encoding
== disp_encoding_16bit
)
8885 i
.types
[op
].bitfield
.disp16
= 1;
8887 i
.types
[op
].bitfield
.disp8
= 1;
8888 fake_zero_displacement
= 1;
8891 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8892 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8894 default: /* (%si) -> 4 or (%di) -> 5 */
8895 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8897 if (!fake_zero_displacement
8901 fake_zero_displacement
= 1;
8902 if (i
.disp_encoding
== disp_encoding_8bit
)
8903 i
.types
[op
].bitfield
.disp8
= 1;
8905 i
.types
[op
].bitfield
.disp16
= 1;
8907 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8909 else /* i.base_reg and 32/64 bit mode */
8911 if (operand_type_check (i
.types
[op
], disp
))
8913 i
.types
[op
].bitfield
.disp16
= 0;
8914 i
.types
[op
].bitfield
.disp64
= 0;
8915 i
.types
[op
].bitfield
.disp32
= 1;
8918 if (!i
.tm
.opcode_modifier
.sib
)
8919 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8920 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8922 i
.sib
.base
= i
.base_reg
->reg_num
;
8923 /* x86-64 ignores REX prefix bit here to avoid decoder
8925 if (!(i
.base_reg
->reg_flags
& RegRex
)
8926 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8927 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8928 default_seg
= reg_ss
;
8929 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8931 fake_zero_displacement
= 1;
8932 if (i
.disp_encoding
== disp_encoding_32bit
)
8933 i
.types
[op
].bitfield
.disp32
= 1;
8935 i
.types
[op
].bitfield
.disp8
= 1;
8937 i
.sib
.scale
= i
.log2_scale_factor
;
8938 if (i
.index_reg
== 0)
8940 /* Only check for VSIB. */
8941 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8942 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8943 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8945 /* <disp>(%esp) becomes two byte modrm with no index
8946 register. We've already stored the code for esp
8947 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8948 Any base register besides %esp will not use the
8949 extra modrm byte. */
8950 i
.sib
.index
= NO_INDEX_REGISTER
;
8952 else if (!i
.tm
.opcode_modifier
.sib
)
8954 if (i
.index_reg
->reg_num
== RegIZ
)
8955 i
.sib
.index
= NO_INDEX_REGISTER
;
8957 i
.sib
.index
= i
.index_reg
->reg_num
;
8958 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8959 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8964 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8965 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8969 if (!fake_zero_displacement
8973 fake_zero_displacement
= 1;
8974 if (i
.disp_encoding
== disp_encoding_8bit
)
8975 i
.types
[op
].bitfield
.disp8
= 1;
8977 i
.types
[op
].bitfield
.disp32
= 1;
8979 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8983 if (fake_zero_displacement
)
8985 /* Fakes a zero displacement assuming that i.types[op]
8986 holds the correct displacement size. */
8989 gas_assert (i
.op
[op
].disps
== 0);
8990 exp
= &disp_expressions
[i
.disp_operands
++];
8991 i
.op
[op
].disps
= exp
;
8992 exp
->X_op
= O_constant
;
8993 exp
->X_add_number
= 0;
8994 exp
->X_add_symbol
= (symbolS
*) 0;
8995 exp
->X_op_symbol
= (symbolS
*) 0;
9001 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
9002 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
9013 if (!i
.tm
.opcode_modifier
.regmem
)
9015 gas_assert (source
< MAX_OPERANDS
);
9016 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9017 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9018 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9023 gas_assert (dest
< MAX_OPERANDS
);
9024 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9025 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9030 /* Fill in i.rm.reg field with extension opcode (if any) or the
9031 appropriate register. */
9032 if (i
.tm
.extension_opcode
!= None
)
9033 i
.rm
.reg
= i
.tm
.extension_opcode
;
9034 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9036 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9037 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9041 gas_assert (source
< MAX_OPERANDS
);
9042 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9043 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9046 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9048 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9050 add_prefix (LOCK_PREFIX_OPCODE
);
9057 frag_opcode_byte (unsigned char byte
)
9059 if (now_seg
!= absolute_section
)
9060 FRAG_APPEND_1_CHAR (byte
);
9062 ++abs_section_offset
;
9066 flip_code16 (unsigned int code16
)
9068 gas_assert (i
.tm
.operands
== 1);
9070 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9071 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9072 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9077 output_branch (void)
9083 relax_substateT subtype
;
9087 if (now_seg
== absolute_section
)
9089 as_bad (_("relaxable branches not supported in absolute section"));
9093 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9094 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9097 if (i
.prefix
[DATA_PREFIX
] != 0)
9101 code16
^= flip_code16(code16
);
9103 /* Pentium4 branch hints. */
9104 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9105 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9110 if (i
.prefix
[REX_PREFIX
] != 0)
9116 /* BND prefixed jump. */
9117 if (i
.prefix
[BND_PREFIX
] != 0)
9123 if (i
.prefixes
!= 0)
9124 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9126 /* It's always a symbol; End frag & setup for relax.
9127 Make sure there is enough room in this frag for the largest
9128 instruction we may generate in md_convert_frag. This is 2
9129 bytes for the opcode and room for the prefix and largest
9131 frag_grow (prefix
+ 2 + 4);
9132 /* Prefix and 1 opcode byte go in fr_fix. */
9133 p
= frag_more (prefix
+ 1);
9134 if (i
.prefix
[DATA_PREFIX
] != 0)
9135 *p
++ = DATA_PREFIX_OPCODE
;
9136 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9137 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9138 *p
++ = i
.prefix
[SEG_PREFIX
];
9139 if (i
.prefix
[BND_PREFIX
] != 0)
9140 *p
++ = BND_PREFIX_OPCODE
;
9141 if (i
.prefix
[REX_PREFIX
] != 0)
9142 *p
++ = i
.prefix
[REX_PREFIX
];
9143 *p
= i
.tm
.base_opcode
;
9145 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9146 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9147 else if (cpu_arch_flags
.bitfield
.cpui386
)
9148 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9150 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9153 sym
= i
.op
[0].disps
->X_add_symbol
;
9154 off
= i
.op
[0].disps
->X_add_number
;
9156 if (i
.op
[0].disps
->X_op
!= O_constant
9157 && i
.op
[0].disps
->X_op
!= O_symbol
)
9159 /* Handle complex expressions. */
9160 sym
= make_expr_symbol (i
.op
[0].disps
);
9164 /* 1 possible extra opcode + 4 byte displacement go in var part.
9165 Pass reloc in fr_var. */
9166 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9170 /* Return TRUE iff PLT32 relocation should be used for branching to
9174 need_plt32_p (symbolS
*s
)
9176 /* PLT32 relocation is ELF only. */
9181 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9182 krtld support it. */
9186 /* Since there is no need to prepare for PLT branch on x86-64, we
9187 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9188 be used as a marker for 32-bit PC-relative branches. */
9195 /* Weak or undefined symbol need PLT32 relocation. */
9196 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9199 /* Non-global symbol doesn't need PLT32 relocation. */
9200 if (! S_IS_EXTERNAL (s
))
9203 /* Other global symbols need PLT32 relocation. NB: Symbol with
9204 non-default visibilities are treated as normal global symbol
9205 so that PLT32 relocation can be used as a marker for 32-bit
9206 PC-relative branches. It is useful for linker relaxation. */
9217 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9219 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9221 /* This is a loop or jecxz type instruction. */
9223 if (i
.prefix
[ADDR_PREFIX
] != 0)
9225 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9228 /* Pentium4 branch hints. */
9229 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9230 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9232 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9241 if (flag_code
== CODE_16BIT
)
9244 if (i
.prefix
[DATA_PREFIX
] != 0)
9246 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9248 code16
^= flip_code16(code16
);
9256 /* BND prefixed jump. */
9257 if (i
.prefix
[BND_PREFIX
] != 0)
9259 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9263 if (i
.prefix
[REX_PREFIX
] != 0)
9265 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9269 if (i
.prefixes
!= 0)
9270 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9272 if (now_seg
== absolute_section
)
9274 abs_section_offset
+= i
.opcode_length
+ size
;
9278 p
= frag_more (i
.opcode_length
+ size
);
9279 switch (i
.opcode_length
)
9282 *p
++ = i
.tm
.base_opcode
>> 8;
9285 *p
++ = i
.tm
.base_opcode
;
9291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9292 if (flag_code
== CODE_64BIT
&& size
== 4
9293 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9294 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9295 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9298 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9300 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9301 i
.op
[0].disps
, 1, jump_reloc
);
9303 /* All jumps handled here are signed, but don't unconditionally use a
9304 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9305 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9310 fixP
->fx_signed
= 1;
9314 if (i
.tm
.mnem_off
== MN_xbegin
)
9315 fixP
->fx_signed
= 1;
9319 if (flag_code
== CODE_64BIT
)
9320 fixP
->fx_signed
= 1;
9326 output_interseg_jump (void)
9334 if (flag_code
== CODE_16BIT
)
9338 if (i
.prefix
[DATA_PREFIX
] != 0)
9345 gas_assert (!i
.prefix
[REX_PREFIX
]);
9351 if (i
.prefixes
!= 0)
9352 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9354 if (now_seg
== absolute_section
)
9356 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9360 /* 1 opcode; 2 segment; offset */
9361 p
= frag_more (prefix
+ 1 + 2 + size
);
9363 if (i
.prefix
[DATA_PREFIX
] != 0)
9364 *p
++ = DATA_PREFIX_OPCODE
;
9366 if (i
.prefix
[REX_PREFIX
] != 0)
9367 *p
++ = i
.prefix
[REX_PREFIX
];
9369 *p
++ = i
.tm
.base_opcode
;
9370 if (i
.op
[1].imms
->X_op
== O_constant
)
9372 offsetT n
= i
.op
[1].imms
->X_add_number
;
9375 && !fits_in_unsigned_word (n
)
9376 && !fits_in_signed_word (n
))
9378 as_bad (_("16-bit jump out of range"));
9381 md_number_to_chars (p
, n
, size
);
9384 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9385 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9388 if (i
.op
[0].imms
->X_op
== O_constant
)
9389 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9391 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9392 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9400 asection
*seg
= now_seg
;
9401 subsegT subseg
= now_subseg
;
9403 unsigned int alignment
, align_size_1
;
9404 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9405 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9406 unsigned int padding
;
9408 if (!IS_ELF
|| !x86_used_note
)
9411 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9413 /* The .note.gnu.property section layout:
9415 Field Length Contents
9418 n_descsz 4 The note descriptor size
9419 n_type 4 NT_GNU_PROPERTY_TYPE_0
9421 n_desc n_descsz The program property array
9425 /* Create the .note.gnu.property section. */
9426 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9427 bfd_set_section_flags (sec
,
9434 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9445 bfd_set_section_alignment (sec
, alignment
);
9446 elf_section_type (sec
) = SHT_NOTE
;
9448 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9450 isa_1_descsz_raw
= 4 + 4 + 4;
9451 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9452 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9454 feature_2_descsz_raw
= isa_1_descsz
;
9455 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9457 feature_2_descsz_raw
+= 4 + 4 + 4;
9458 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9459 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9462 descsz
= feature_2_descsz
;
9463 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9464 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9466 /* Write n_namsz. */
9467 md_number_to_chars (p
, (valueT
) 4, 4);
9469 /* Write n_descsz. */
9470 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9473 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9476 memcpy (p
+ 4 * 3, "GNU", 4);
9478 /* Write 4-byte type. */
9479 md_number_to_chars (p
+ 4 * 4,
9480 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9482 /* Write 4-byte data size. */
9483 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9485 /* Write 4-byte data. */
9486 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9488 /* Zero out paddings. */
9489 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9491 memset (p
+ 4 * 7, 0, padding
);
9493 /* Write 4-byte type. */
9494 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9495 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9497 /* Write 4-byte data size. */
9498 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9500 /* Write 4-byte data. */
9501 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9502 (valueT
) x86_feature_2_used
, 4);
9504 /* Zero out paddings. */
9505 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9507 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9509 /* We probably can't restore the current segment, for there likely
9512 subseg_set (seg
, subseg
);
9516 x86_support_sframe_p (void)
9518 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9519 return (x86_elf_abi
== X86_64_ABI
);
9523 x86_sframe_ra_tracking_p (void)
9525 /* In AMD64, return address is always stored on the stack at a fixed offset
9526 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9527 Do not track explicitly via an SFrame Frame Row Entry. */
9532 x86_sframe_cfa_ra_offset (void)
9534 gas_assert (x86_elf_abi
== X86_64_ABI
);
9535 return (offsetT
) -8;
9539 x86_sframe_get_abi_arch (void)
9541 unsigned char sframe_abi_arch
= 0;
9543 if (x86_support_sframe_p ())
9545 gas_assert (!target_big_endian
);
9546 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9549 return sframe_abi_arch
;
9555 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9556 const char *frag_now_ptr
)
9558 unsigned int len
= 0;
9560 if (start_frag
!= frag_now
)
9562 const fragS
*fr
= start_frag
;
9567 } while (fr
&& fr
!= frag_now
);
9570 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9573 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9574 be macro-fused with conditional jumps.
9575 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9576 or is one of the following format:
9589 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9591 /* No RIP address. */
9592 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9595 /* No opcodes outside of base encoding space. */
9596 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9599 /* add, sub without add/sub m, imm. */
9600 if (i
.tm
.base_opcode
<= 5
9601 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9602 || ((i
.tm
.base_opcode
| 3) == 0x83
9603 && (i
.tm
.extension_opcode
== 0x5
9604 || i
.tm
.extension_opcode
== 0x0)))
9606 *mf_cmp_p
= mf_cmp_alu_cmp
;
9607 return !(i
.mem_operands
&& i
.imm_operands
);
9610 /* and without and m, imm. */
9611 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9612 || ((i
.tm
.base_opcode
| 3) == 0x83
9613 && i
.tm
.extension_opcode
== 0x4))
9615 *mf_cmp_p
= mf_cmp_test_and
;
9616 return !(i
.mem_operands
&& i
.imm_operands
);
9619 /* test without test m imm. */
9620 if ((i
.tm
.base_opcode
| 1) == 0x85
9621 || (i
.tm
.base_opcode
| 1) == 0xa9
9622 || ((i
.tm
.base_opcode
| 1) == 0xf7
9623 && i
.tm
.extension_opcode
== 0))
9625 *mf_cmp_p
= mf_cmp_test_and
;
9626 return !(i
.mem_operands
&& i
.imm_operands
);
9629 /* cmp without cmp m, imm. */
9630 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9631 || ((i
.tm
.base_opcode
| 3) == 0x83
9632 && (i
.tm
.extension_opcode
== 0x7)))
9634 *mf_cmp_p
= mf_cmp_alu_cmp
;
9635 return !(i
.mem_operands
&& i
.imm_operands
);
9638 /* inc, dec without inc/dec m. */
9639 if ((is_cpu (&i
.tm
, CpuNo64
)
9640 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9641 || ((i
.tm
.base_opcode
| 1) == 0xff
9642 && i
.tm
.extension_opcode
<= 0x1))
9644 *mf_cmp_p
= mf_cmp_incdec
;
9645 return !i
.mem_operands
;
9651 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9654 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9656 /* NB: Don't work with COND_JUMP86 without i386. */
9657 if (!align_branch_power
9658 || now_seg
== absolute_section
9659 || !cpu_arch_flags
.bitfield
.cpui386
9660 || !(align_branch
& align_branch_fused_bit
))
9663 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9665 if (last_insn
.kind
== last_insn_other
9666 || last_insn
.seg
!= now_seg
)
9669 as_warn_where (last_insn
.file
, last_insn
.line
,
9670 _("`%s` skips -malign-branch-boundary on `%s`"),
9671 last_insn
.name
, insn_name (&i
.tm
));
9677 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9680 add_branch_prefix_frag_p (void)
9682 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9683 to PadLock instructions since they include prefixes in opcode. */
9684 if (!align_branch_power
9685 || !align_branch_prefix_size
9686 || now_seg
== absolute_section
9687 || is_cpu (&i
.tm
, CpuPadLock
)
9688 || !cpu_arch_flags
.bitfield
.cpui386
)
9691 /* Don't add prefix if it is a prefix or there is no operand in case
9692 that segment prefix is special. */
9693 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9696 if (last_insn
.kind
== last_insn_other
9697 || last_insn
.seg
!= now_seg
)
9701 as_warn_where (last_insn
.file
, last_insn
.line
,
9702 _("`%s` skips -malign-branch-boundary on `%s`"),
9703 last_insn
.name
, insn_name (&i
.tm
));
9708 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9711 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9712 enum mf_jcc_kind
*mf_jcc_p
)
9716 /* NB: Don't work with COND_JUMP86 without i386. */
9717 if (!align_branch_power
9718 || now_seg
== absolute_section
9719 || !cpu_arch_flags
.bitfield
.cpui386
9720 || i
.tm
.opcode_space
!= SPACE_BASE
)
9725 /* Check for jcc and direct jmp. */
9726 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9728 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9730 *branch_p
= align_branch_jmp
;
9731 add_padding
= align_branch
& align_branch_jmp_bit
;
9735 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9736 igore the lowest bit. */
9737 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9738 *branch_p
= align_branch_jcc
;
9739 if ((align_branch
& align_branch_jcc_bit
))
9743 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9746 *branch_p
= align_branch_ret
;
9747 if ((align_branch
& align_branch_ret_bit
))
9752 /* Check for indirect jmp, direct and indirect calls. */
9753 if (i
.tm
.base_opcode
== 0xe8)
9756 *branch_p
= align_branch_call
;
9757 if ((align_branch
& align_branch_call_bit
))
9760 else if (i
.tm
.base_opcode
== 0xff
9761 && (i
.tm
.extension_opcode
== 2
9762 || i
.tm
.extension_opcode
== 4))
9764 /* Indirect call and jmp. */
9765 *branch_p
= align_branch_indirect
;
9766 if ((align_branch
& align_branch_indirect_bit
))
9773 && (i
.op
[0].disps
->X_op
== O_symbol
9774 || (i
.op
[0].disps
->X_op
== O_subtract
9775 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9777 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9778 /* No padding to call to global or undefined tls_get_addr. */
9779 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9780 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9786 && last_insn
.kind
!= last_insn_other
9787 && last_insn
.seg
== now_seg
)
9790 as_warn_where (last_insn
.file
, last_insn
.line
,
9791 _("`%s` skips -malign-branch-boundary on `%s`"),
9792 last_insn
.name
, insn_name (&i
.tm
));
9802 fragS
*insn_start_frag
;
9803 offsetT insn_start_off
;
9804 fragS
*fragP
= NULL
;
9805 enum align_branch_kind branch
= align_branch_none
;
9806 /* The initializer is arbitrary just to avoid uninitialized error.
9807 it's actually either assigned in add_branch_padding_frag_p
9808 or never be used. */
9809 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9811 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9812 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9814 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9815 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9816 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9818 if (is_cpu (&i
.tm
, Cpu8087
)
9819 || is_cpu (&i
.tm
, Cpu287
)
9820 || is_cpu (&i
.tm
, Cpu387
)
9821 || is_cpu (&i
.tm
, Cpu687
)
9822 || is_cpu (&i
.tm
, CpuFISTTP
))
9823 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9825 if ((i
.xstate
& xstate_mmx
)
9826 || i
.tm
.mnem_off
== MN_emms
9827 || i
.tm
.mnem_off
== MN_femms
)
9828 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9832 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9833 i
.xstate
|= xstate_zmm
;
9834 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9835 i
.xstate
|= xstate_ymm
;
9836 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9837 i
.xstate
|= xstate_xmm
;
9840 /* vzeroall / vzeroupper */
9841 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9842 i
.xstate
|= xstate_ymm
;
9844 if ((i
.xstate
& xstate_xmm
)
9845 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9846 || (i
.tm
.base_opcode
== 0xae
9847 && (is_cpu (&i
.tm
, CpuSSE
)
9848 || is_cpu (&i
.tm
, CpuAVX
)))
9849 || is_cpu (&i
.tm
, CpuWideKL
)
9850 || is_cpu (&i
.tm
, CpuKL
))
9851 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9853 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9854 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9855 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9856 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9857 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9858 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9859 if (is_cpu (&i
.tm
, CpuFXSR
))
9860 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9861 if (is_cpu (&i
.tm
, CpuXsave
))
9862 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9863 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9864 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9865 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9866 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9868 if (x86_feature_2_used
9869 || is_cpu (&i
.tm
, CpuCMOV
)
9870 || is_cpu (&i
.tm
, CpuSYSCALL
)
9871 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9872 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9873 if (is_cpu (&i
.tm
, CpuSSE3
)
9874 || is_cpu (&i
.tm
, CpuSSSE3
)
9875 || is_cpu (&i
.tm
, CpuSSE4_1
)
9876 || is_cpu (&i
.tm
, CpuSSE4_2
)
9877 || is_cpu (&i
.tm
, CpuCX16
)
9878 || is_cpu (&i
.tm
, CpuPOPCNT
)
9879 /* LAHF-SAHF insns in 64-bit mode. */
9880 || (flag_code
== CODE_64BIT
9881 && (i
.tm
.base_opcode
| 1) == 0x9f
9882 && i
.tm
.opcode_space
== SPACE_BASE
))
9883 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9884 if (is_cpu (&i
.tm
, CpuAVX
)
9885 || is_cpu (&i
.tm
, CpuAVX2
)
9886 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9887 XOP, FMA4, LPW, TBM, and AMX. */
9888 || (i
.tm
.opcode_modifier
.vex
9889 && !is_cpu (&i
.tm
, CpuAVX512F
)
9890 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9891 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9892 && !is_cpu (&i
.tm
, CpuXOP
)
9893 && !is_cpu (&i
.tm
, CpuFMA4
)
9894 && !is_cpu (&i
.tm
, CpuLWP
)
9895 && !is_cpu (&i
.tm
, CpuTBM
)
9896 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9897 || is_cpu (&i
.tm
, CpuF16C
)
9898 || is_cpu (&i
.tm
, CpuFMA
)
9899 || is_cpu (&i
.tm
, CpuLZCNT
)
9900 || is_cpu (&i
.tm
, CpuMovbe
)
9901 || is_cpu (&i
.tm
, CpuXSAVES
)
9902 || (x86_feature_2_used
9903 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9904 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9905 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9906 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9907 if (is_cpu (&i
.tm
, CpuAVX512F
)
9908 || is_cpu (&i
.tm
, CpuAVX512BW
)
9909 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9910 || is_cpu (&i
.tm
, CpuAVX512VL
)
9911 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9912 AVX512-4FMAPS, and AVX512-4VNNIW. */
9913 || (i
.tm
.opcode_modifier
.evex
9914 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9915 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9916 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9917 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9918 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9922 /* Tie dwarf2 debug info to the address at the start of the insn.
9923 We can't do this after the insn has been output as the current
9924 frag may have been closed off. eg. by frag_var. */
9925 dwarf2_emit_insn (0);
9927 insn_start_frag
= frag_now
;
9928 insn_start_off
= frag_now_fix ();
9930 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9933 /* Branch can be 8 bytes. Leave some room for prefixes. */
9934 unsigned int max_branch_padding_size
= 14;
9936 /* Align section to boundary. */
9937 record_alignment (now_seg
, align_branch_power
);
9939 /* Make room for padding. */
9940 frag_grow (max_branch_padding_size
);
9942 /* Start of the padding. */
9947 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9948 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9951 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9952 fragP
->tc_frag_data
.branch_type
= branch
;
9953 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9956 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9957 && !pre_386_16bit_warned
)
9959 as_warn (_("use .code16 to ensure correct addressing mode"));
9960 pre_386_16bit_warned
= true;
9964 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9966 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9967 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9969 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9970 output_interseg_jump ();
9973 /* Output normal instructions here. */
9977 enum mf_cmp_kind mf_cmp
;
9980 && (i
.tm
.base_opcode
== 0xaee8
9981 || i
.tm
.base_opcode
== 0xaef0
9982 || i
.tm
.base_opcode
== 0xaef8))
9984 /* Encode lfence, mfence, and sfence as
9985 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9986 if (flag_code
== CODE_16BIT
)
9987 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9988 else if (omit_lock_prefix
)
9989 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9991 else if (now_seg
!= absolute_section
)
9993 offsetT val
= 0x240483f0ULL
;
9996 md_number_to_chars (p
, val
, 5);
9999 abs_section_offset
+= 5;
10003 /* Some processors fail on LOCK prefix. This options makes
10004 assembler ignore LOCK prefix and serves as a workaround. */
10005 if (omit_lock_prefix
)
10007 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
10008 && i
.tm
.opcode_modifier
.isprefix
)
10010 i
.prefix
[LOCK_PREFIX
] = 0;
10014 /* Skip if this is a branch. */
10016 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10018 /* Make room for padding. */
10019 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10024 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10025 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10028 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10029 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10030 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10032 else if (add_branch_prefix_frag_p ())
10034 unsigned int max_prefix_size
= align_branch_prefix_size
;
10036 /* Make room for padding. */
10037 frag_grow (max_prefix_size
);
10042 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10043 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10046 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10049 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10050 don't need the explicit prefix. */
10051 if (!is_any_vex_encoding (&i
.tm
))
10053 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10062 if (!is_cpu (&i
.tm
, CpuPadLock
)
10063 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10067 switch (i
.opcode_length
)
10072 /* Check for pseudo prefixes. */
10073 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10075 as_bad_where (insn_start_frag
->fr_file
,
10076 insn_start_frag
->fr_line
,
10077 _("pseudo prefix without instruction"));
10087 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10088 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10089 R_X86_64_GOTTPOFF relocation so that linker can safely
10090 perform IE->LE optimization. A dummy REX_OPCODE prefix
10091 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10092 relocation for GDesc -> IE/LE optimization. */
10093 if (x86_elf_abi
== X86_64_X32_ABI
10095 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10096 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10097 && i
.prefix
[REX_PREFIX
] == 0)
10098 add_prefix (REX_OPCODE
);
10101 /* The prefix bytes. */
10102 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10104 frag_opcode_byte (*q
);
10108 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10114 frag_opcode_byte (*q
);
10117 /* There should be no other prefixes for instructions
10118 with VEX prefix. */
10122 /* For EVEX instructions i.vrex should become 0 after
10123 build_evex_prefix. For VEX instructions upper 16 registers
10124 aren't available, so VREX should be 0. */
10127 /* Now the VEX prefix. */
10128 if (now_seg
!= absolute_section
)
10130 p
= frag_more (i
.vex
.length
);
10131 for (j
= 0; j
< i
.vex
.length
; j
++)
10132 p
[j
] = i
.vex
.bytes
[j
];
10135 abs_section_offset
+= i
.vex
.length
;
10138 /* Now the opcode; be careful about word order here! */
10139 j
= i
.opcode_length
;
10141 switch (i
.tm
.opcode_space
)
10156 if (now_seg
== absolute_section
)
10157 abs_section_offset
+= j
;
10160 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10166 && i
.tm
.opcode_space
!= SPACE_BASE
)
10169 if (i
.tm
.opcode_space
!= SPACE_0F
)
10170 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10174 switch (i
.opcode_length
)
10177 /* Put out high byte first: can't use md_number_to_chars! */
10178 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10179 /* Fall through. */
10181 *p
= i
.tm
.base_opcode
& 0xff;
10190 /* Now the modrm byte and sib byte (if present). */
10191 if (i
.tm
.opcode_modifier
.modrm
)
10193 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10195 | (i
.rm
.mode
<< 6));
10196 /* If i.rm.regmem == ESP (4)
10197 && i.rm.mode != (Register mode)
10199 ==> need second modrm byte. */
10200 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10202 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10203 frag_opcode_byte ((i
.sib
.base
<< 0)
10204 | (i
.sib
.index
<< 3)
10205 | (i
.sib
.scale
<< 6));
10208 if (i
.disp_operands
)
10209 output_disp (insn_start_frag
, insn_start_off
);
10211 if (i
.imm_operands
)
10212 output_imm (insn_start_frag
, insn_start_off
);
10215 * frag_now_fix () returning plain abs_section_offset when we're in the
10216 * absolute section, and abs_section_offset not getting updated as data
10217 * gets added to the frag breaks the logic below.
10219 if (now_seg
!= absolute_section
)
10221 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10223 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10227 /* NB: Don't add prefix with GOTPC relocation since
10228 output_disp() above depends on the fixed encoding
10229 length. Can't add prefix with TLS relocation since
10230 it breaks TLS linker optimization. */
10231 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10232 /* Prefix count on the current instruction. */
10233 unsigned int count
= i
.vex
.length
;
10235 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10236 /* REX byte is encoded in VEX/EVEX prefix. */
10237 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10240 /* Count prefixes for extended opcode maps. */
10242 switch (i
.tm
.opcode_space
)
10257 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10260 /* Set the maximum prefix size in BRANCH_PREFIX
10262 if (fragP
->tc_frag_data
.max_bytes
> max
)
10263 fragP
->tc_frag_data
.max_bytes
= max
;
10264 if (fragP
->tc_frag_data
.max_bytes
> count
)
10265 fragP
->tc_frag_data
.max_bytes
-= count
;
10267 fragP
->tc_frag_data
.max_bytes
= 0;
10271 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10273 unsigned int max_prefix_size
;
10274 if (align_branch_prefix_size
> max
)
10275 max_prefix_size
= max
;
10277 max_prefix_size
= align_branch_prefix_size
;
10278 if (max_prefix_size
> count
)
10279 fragP
->tc_frag_data
.max_prefix_length
10280 = max_prefix_size
- count
;
10283 /* Use existing segment prefix if possible. Use CS
10284 segment prefix in 64-bit mode. In 32-bit mode, use SS
10285 segment prefix with ESP/EBP base register and use DS
10286 segment prefix without ESP/EBP base register. */
10287 if (i
.prefix
[SEG_PREFIX
])
10288 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10289 else if (flag_code
== CODE_64BIT
)
10290 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10291 else if (i
.base_reg
10292 && (i
.base_reg
->reg_num
== 4
10293 || i
.base_reg
->reg_num
== 5))
10294 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10296 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10301 /* NB: Don't work with COND_JUMP86 without i386. */
10302 if (align_branch_power
10303 && now_seg
!= absolute_section
10304 && cpu_arch_flags
.bitfield
.cpui386
)
10306 /* Terminate each frag so that we can add prefix and check for
10308 frag_wane (frag_now
);
10315 pi ("" /*line*/, &i
);
10317 #endif /* DEBUG386 */
10320 /* Return the size of the displacement operand N. */
10323 disp_size (unsigned int n
)
10327 if (i
.types
[n
].bitfield
.disp64
)
10329 else if (i
.types
[n
].bitfield
.disp8
)
10331 else if (i
.types
[n
].bitfield
.disp16
)
10336 /* Return the size of the immediate operand N. */
10339 imm_size (unsigned int n
)
10342 if (i
.types
[n
].bitfield
.imm64
)
10344 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10346 else if (i
.types
[n
].bitfield
.imm16
)
10352 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10357 for (n
= 0; n
< i
.operands
; n
++)
10359 if (operand_type_check (i
.types
[n
], disp
))
10361 int size
= disp_size (n
);
10363 if (now_seg
== absolute_section
)
10364 abs_section_offset
+= size
;
10365 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10367 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10369 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10371 p
= frag_more (size
);
10372 md_number_to_chars (p
, val
, size
);
10376 enum bfd_reloc_code_real reloc_type
;
10377 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10378 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10379 && (!want_disp32 (&i
.tm
)
10380 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10381 && !i
.types
[n
].bitfield
.baseindex
)))
10385 /* We can't have 8 bit displacement here. */
10386 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10388 /* The PC relative address is computed relative
10389 to the instruction boundary, so in case immediate
10390 fields follows, we need to adjust the value. */
10391 if (pcrel
&& i
.imm_operands
)
10396 for (n1
= 0; n1
< i
.operands
; n1
++)
10397 if (operand_type_check (i
.types
[n1
], imm
))
10399 /* Only one immediate is allowed for PC
10400 relative address, except with .insn. */
10401 gas_assert (sz
== 0 || dot_insn ());
10402 sz
+= imm_size (n1
);
10404 /* We should find at least one immediate. */
10405 gas_assert (sz
!= 0);
10406 i
.op
[n
].disps
->X_add_number
-= sz
;
10409 p
= frag_more (size
);
10410 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10412 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10413 && (((reloc_type
== BFD_RELOC_32
10414 || reloc_type
== BFD_RELOC_X86_64_32S
10415 || (reloc_type
== BFD_RELOC_64
10417 && (i
.op
[n
].disps
->X_op
== O_symbol
10418 || (i
.op
[n
].disps
->X_op
== O_add
10419 && ((symbol_get_value_expression
10420 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10422 || reloc_type
== BFD_RELOC_32_PCREL
))
10426 reloc_type
= BFD_RELOC_386_GOTPC
;
10427 i
.has_gotpc_tls_reloc
= true;
10428 i
.op
[n
].disps
->X_add_number
+=
10429 encoding_length (insn_start_frag
, insn_start_off
, p
);
10431 else if (reloc_type
== BFD_RELOC_64
)
10432 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10434 /* Don't do the adjustment for x86-64, as there
10435 the pcrel addressing is relative to the _next_
10436 insn, and that is taken care of in other code. */
10437 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10439 else if (align_branch_power
)
10441 switch (reloc_type
)
10443 case BFD_RELOC_386_TLS_GD
:
10444 case BFD_RELOC_386_TLS_LDM
:
10445 case BFD_RELOC_386_TLS_IE
:
10446 case BFD_RELOC_386_TLS_IE_32
:
10447 case BFD_RELOC_386_TLS_GOTIE
:
10448 case BFD_RELOC_386_TLS_GOTDESC
:
10449 case BFD_RELOC_386_TLS_DESC_CALL
:
10450 case BFD_RELOC_X86_64_TLSGD
:
10451 case BFD_RELOC_X86_64_TLSLD
:
10452 case BFD_RELOC_X86_64_GOTTPOFF
:
10453 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10454 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10455 i
.has_gotpc_tls_reloc
= true;
10460 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10461 size
, i
.op
[n
].disps
, pcrel
,
10464 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10465 && !i
.prefix
[ADDR_PREFIX
])
10466 fixP
->fx_signed
= 1;
10468 /* Check for "call/jmp *mem", "mov mem, %reg",
10469 "test %reg, mem" and "binop mem, %reg" where binop
10470 is one of adc, add, and, cmp, or, sbb, sub, xor
10471 instructions without data prefix. Always generate
10472 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10473 if (i
.prefix
[DATA_PREFIX
] == 0
10474 && (generate_relax_relocations
10477 && i
.rm
.regmem
== 5))
10479 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10480 && i
.tm
.opcode_space
== SPACE_BASE
10481 && ((i
.operands
== 1
10482 && i
.tm
.base_opcode
== 0xff
10483 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10484 || (i
.operands
== 2
10485 && (i
.tm
.base_opcode
== 0x8b
10486 || i
.tm
.base_opcode
== 0x85
10487 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10491 fixP
->fx_tcbit
= i
.rex
!= 0;
10493 && (i
.base_reg
->reg_num
== RegIP
))
10494 fixP
->fx_tcbit2
= 1;
10497 fixP
->fx_tcbit2
= 1;
10505 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10510 for (n
= 0; n
< i
.operands
; n
++)
10512 if (operand_type_check (i
.types
[n
], imm
))
10514 int size
= imm_size (n
);
10516 if (now_seg
== absolute_section
)
10517 abs_section_offset
+= size
;
10518 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10522 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10524 p
= frag_more (size
);
10525 md_number_to_chars (p
, val
, size
);
10529 /* Not absolute_section.
10530 Need a 32-bit fixup (don't support 8bit
10531 non-absolute imms). Try to support other
10533 enum bfd_reloc_code_real reloc_type
;
10536 if (i
.types
[n
].bitfield
.imm32s
10537 && (i
.suffix
== QWORD_MNEM_SUFFIX
10538 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10539 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10545 p
= frag_more (size
);
10546 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10548 /* This is tough to explain. We end up with this one if we
10549 * have operands that look like
10550 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10551 * obtain the absolute address of the GOT, and it is strongly
10552 * preferable from a performance point of view to avoid using
10553 * a runtime relocation for this. The actual sequence of
10554 * instructions often look something like:
10559 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10561 * The call and pop essentially return the absolute address
10562 * of the label .L66 and store it in %ebx. The linker itself
10563 * will ultimately change the first operand of the addl so
10564 * that %ebx points to the GOT, but to keep things simple, the
10565 * .o file must have this operand set so that it generates not
10566 * the absolute address of .L66, but the absolute address of
10567 * itself. This allows the linker itself simply treat a GOTPC
10568 * relocation as asking for a pcrel offset to the GOT to be
10569 * added in, and the addend of the relocation is stored in the
10570 * operand field for the instruction itself.
10572 * Our job here is to fix the operand so that it would add
10573 * the correct offset so that %ebx would point to itself. The
10574 * thing that is tricky is that .-.L66 will point to the
10575 * beginning of the instruction, so we need to further modify
10576 * the operand so that it will point to itself. There are
10577 * other cases where you have something like:
10579 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10581 * and here no correction would be required. Internally in
10582 * the assembler we treat operands of this form as not being
10583 * pcrel since the '.' is explicitly mentioned, and I wonder
10584 * whether it would simplify matters to do it this way. Who
10585 * knows. In earlier versions of the PIC patches, the
10586 * pcrel_adjust field was used to store the correction, but
10587 * since the expression is not pcrel, I felt it would be
10588 * confusing to do it this way. */
10590 if ((reloc_type
== BFD_RELOC_32
10591 || reloc_type
== BFD_RELOC_X86_64_32S
10592 || reloc_type
== BFD_RELOC_64
)
10594 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10595 && (i
.op
[n
].imms
->X_op
== O_symbol
10596 || (i
.op
[n
].imms
->X_op
== O_add
10597 && ((symbol_get_value_expression
10598 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10602 reloc_type
= BFD_RELOC_386_GOTPC
;
10603 else if (size
== 4)
10604 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10605 else if (size
== 8)
10606 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10607 i
.has_gotpc_tls_reloc
= true;
10608 i
.op
[n
].imms
->X_add_number
+=
10609 encoding_length (insn_start_frag
, insn_start_off
, p
);
10611 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10612 i
.op
[n
].imms
, 0, reloc_type
);
10618 /* x86_cons_fix_new is called via the expression parsing code when a
10619 reloc is needed. We use this hook to get the correct .got reloc. */
10620 static int cons_sign
= -1;
10623 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10624 expressionS
*exp
, bfd_reloc_code_real_type r
)
10626 r
= reloc (len
, 0, cons_sign
, r
);
10629 if (exp
->X_op
== O_secrel
)
10631 exp
->X_op
= O_symbol
;
10632 r
= BFD_RELOC_32_SECREL
;
10634 else if (exp
->X_op
== O_secidx
)
10635 r
= BFD_RELOC_16_SECIDX
;
10638 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10641 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10642 purpose of the `.dc.a' internal pseudo-op. */
10645 x86_address_bytes (void)
10647 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10649 return stdoutput
->arch_info
->bits_per_address
/ 8;
10652 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10653 || defined (LEX_AT)) && !defined (TE_PE)
10654 # define lex_got(reloc, adjust, types) NULL
10656 /* Parse operands of the form
10657 <symbol>@GOTOFF+<nnn>
10658 and similar .plt or .got references.
10660 If we find one, set up the correct relocation in RELOC and copy the
10661 input string, minus the `@GOTOFF' into a malloc'd buffer for
10662 parsing by the calling routine. Return this buffer, and if ADJUST
10663 is non-null set it to the length of the string we removed from the
10664 input line. Otherwise return NULL. */
10666 lex_got (enum bfd_reloc_code_real
*rel
,
10668 i386_operand_type
*types
)
10670 /* Some of the relocations depend on the size of what field is to
10671 be relocated. But in our callers i386_immediate and i386_displacement
10672 we don't yet know the operand size (this will be set by insn
10673 matching). Hence we record the word32 relocation here,
10674 and adjust the reloc according to the real size in reloc(). */
10675 static const struct
10679 const enum bfd_reloc_code_real rel
[2];
10680 const i386_operand_type types64
;
10681 bool need_GOT_symbol
;
10686 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10687 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10688 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10689 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10690 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10691 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10692 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10693 { .imm64 = 1, .disp64 = 1 } }
10696 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10697 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10698 BFD_RELOC_SIZE32
},
10699 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10701 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10702 BFD_RELOC_X86_64_PLTOFF64
},
10703 { .bitfield
= { .imm64
= 1 } }, true },
10704 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10705 BFD_RELOC_X86_64_PLT32
},
10706 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10707 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10708 BFD_RELOC_X86_64_GOTPLT64
},
10709 OPERAND_TYPE_IMM64_DISP64
, true },
10710 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10711 BFD_RELOC_X86_64_GOTOFF64
},
10712 OPERAND_TYPE_IMM64_DISP64
, true },
10713 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10714 BFD_RELOC_X86_64_GOTPCREL
},
10715 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10716 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10717 BFD_RELOC_X86_64_TLSGD
},
10718 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10719 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10720 _dummy_first_bfd_reloc_code_real
},
10721 OPERAND_TYPE_NONE
, true },
10722 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10723 BFD_RELOC_X86_64_TLSLD
},
10724 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10725 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10726 BFD_RELOC_X86_64_GOTTPOFF
},
10727 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10728 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10729 BFD_RELOC_X86_64_TPOFF32
},
10730 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10731 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10732 _dummy_first_bfd_reloc_code_real
},
10733 OPERAND_TYPE_NONE
, true },
10734 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10735 BFD_RELOC_X86_64_DTPOFF32
},
10736 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10737 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10738 _dummy_first_bfd_reloc_code_real
},
10739 OPERAND_TYPE_NONE
, true },
10740 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10741 _dummy_first_bfd_reloc_code_real
},
10742 OPERAND_TYPE_NONE
, true },
10743 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10744 BFD_RELOC_X86_64_GOT32
},
10745 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10746 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10747 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10748 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10749 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10750 BFD_RELOC_X86_64_TLSDESC_CALL
},
10751 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10753 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10754 BFD_RELOC_32_SECREL
},
10755 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10758 #undef OPERAND_TYPE_IMM32_32S_DISP32
10759 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10760 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10761 #undef OPERAND_TYPE_IMM64_DISP64
10767 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10772 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10773 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10776 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10778 int len
= gotrel
[j
].len
;
10779 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10781 if (gotrel
[j
].rel
[object_64bit
] != 0)
10784 char *tmpbuf
, *past_reloc
;
10786 *rel
= gotrel
[j
].rel
[object_64bit
];
10790 if (flag_code
!= CODE_64BIT
)
10792 types
->bitfield
.imm32
= 1;
10793 types
->bitfield
.disp32
= 1;
10796 *types
= gotrel
[j
].types64
;
10799 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10800 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10802 /* The length of the first part of our input line. */
10803 first
= cp
- input_line_pointer
;
10805 /* The second part goes from after the reloc token until
10806 (and including) an end_of_line char or comma. */
10807 past_reloc
= cp
+ 1 + len
;
10809 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10811 second
= cp
+ 1 - past_reloc
;
10813 /* Allocate and copy string. The trailing NUL shouldn't
10814 be necessary, but be safe. */
10815 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10816 memcpy (tmpbuf
, input_line_pointer
, first
);
10817 if (second
!= 0 && *past_reloc
!= ' ')
10818 /* Replace the relocation token with ' ', so that
10819 errors like foo@GOTOFF1 will be detected. */
10820 tmpbuf
[first
++] = ' ';
10822 /* Increment length by 1 if the relocation token is
10827 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10828 tmpbuf
[first
+ second
] = '\0';
10832 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10833 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10838 /* Might be a symbol version string. Don't as_bad here. */
10843 bfd_reloc_code_real_type
10844 x86_cons (expressionS
*exp
, int size
)
10846 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10848 intel_syntax
= -intel_syntax
;
10850 expr_mode
= expr_operator_none
;
10852 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10853 && !defined (LEX_AT)) \
10855 if (size
== 4 || (object_64bit
&& size
== 8))
10857 /* Handle @GOTOFF and the like in an expression. */
10859 char *gotfree_input_line
;
10862 save
= input_line_pointer
;
10863 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10864 if (gotfree_input_line
)
10865 input_line_pointer
= gotfree_input_line
;
10869 if (gotfree_input_line
)
10871 /* expression () has merrily parsed up to the end of line,
10872 or a comma - in the wrong buffer. Transfer how far
10873 input_line_pointer has moved to the right buffer. */
10874 input_line_pointer
= (save
10875 + (input_line_pointer
- gotfree_input_line
)
10877 free (gotfree_input_line
);
10878 if (exp
->X_op
== O_constant
10879 || exp
->X_op
== O_absent
10880 || exp
->X_op
== O_illegal
10881 || exp
->X_op
== O_register
10882 || exp
->X_op
== O_big
)
10884 char c
= *input_line_pointer
;
10885 *input_line_pointer
= 0;
10886 as_bad (_("missing or invalid expression `%s'"), save
);
10887 *input_line_pointer
= c
;
10889 else if ((got_reloc
== BFD_RELOC_386_PLT32
10890 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10891 && exp
->X_op
!= O_symbol
)
10893 char c
= *input_line_pointer
;
10894 *input_line_pointer
= 0;
10895 as_bad (_("invalid PLT expression `%s'"), save
);
10896 *input_line_pointer
= c
;
10904 intel_syntax
= -intel_syntax
;
10907 i386_intel_simplify (exp
);
10909 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10910 if (size
<= 4 && expr_mode
== expr_operator_present
10911 && exp
->X_op
== O_constant
&& !object_64bit
)
10912 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10918 signed_cons (int size
)
10927 s_insn (int dummy ATTRIBUTE_UNUSED
)
10929 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10930 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10934 bool vex
= false, xop
= false, evex
= false;
10935 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10939 saved_char
= *saved_ilp
;
10942 end
= parse_insn (line
, mnemonic
, true);
10946 *saved_ilp
= saved_char
;
10947 ignore_rest_of_line ();
10951 line
+= end
- line
;
10953 current_templates
= &tt
;
10954 i
.tm
.mnem_off
= MN__insn
;
10955 i
.tm
.extension_opcode
= None
;
10957 if (startswith (line
, "VEX")
10958 && (line
[3] == '.' || is_space_char (line
[3])))
10963 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10966 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10968 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10969 && (*e
== '.' || is_space_char (*e
)))
10972 /* Arrange for build_vex_prefix() to emit 0x8f. */
10973 i
.tm
.opcode_space
= SPACE_XOP08
;
10974 i
.insn_opcode_space
= n
;
10978 else if (startswith (line
, "EVEX")
10979 && (line
[4] == '.' || is_space_char (line
[4])))
10986 ? i
.vec_encoding
== vex_encoding_evex
10988 ? i
.vec_encoding
== vex_encoding_vex
10989 || i
.vec_encoding
== vex_encoding_vex3
10990 : i
.vec_encoding
!= vex_encoding_default
)
10992 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10996 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10997 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10999 if (i
.vec_encoding
!= vex_encoding_default
)
11001 /* Only address size and segment override prefixes are permitted with
11002 VEX/XOP/EVEX encodings. */
11003 const unsigned char *p
= i
.prefix
;
11005 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11016 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11022 if (line
> end
&& *line
== '.')
11024 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11032 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11034 i
.tm
.opcode_modifier
.vex
= VEX128
;
11039 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11041 i
.tm
.opcode_modifier
.vex
= VEX256
;
11046 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11051 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11055 if (line
[3] == 'G')
11058 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11060 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11066 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11071 if (line
[2] == '2' && line
[3] == '8')
11074 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11076 i
.tm
.opcode_modifier
.vex
= VEX128
;
11082 if (line
[2] == '5' && line
[3] == '6')
11085 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11087 i
.tm
.opcode_modifier
.vex
= VEX256
;
11093 if (evex
&& line
[2] == '1' && line
[3] == '2')
11095 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11102 if (line
> end
&& *line
== '.')
11104 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11108 if (line
[2] == 'P')
11113 if (line
[2] == '6')
11115 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11120 case 'F': case 'f':
11121 if (line
[2] == '3')
11123 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11126 else if (line
[2] == '2')
11128 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11135 if (line
> end
&& !xop
&& *line
== '.')
11137 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11141 if (TOUPPER (line
[2]) != 'F')
11143 if (line
[3] == '.' || is_space_char (line
[3]))
11145 i
.insn_opcode_space
= SPACE_0F
;
11148 else if (line
[3] == '3'
11149 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11150 && (line
[5] == '.' || is_space_char (line
[5])))
11152 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11158 if (ISDIGIT (line
[2]) && line
[2] != '0')
11161 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11163 if (n
<= (evex
? 15 : 31)
11164 && (*e
== '.' || is_space_char (*e
)))
11166 i
.insn_opcode_space
= n
;
11174 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11176 /* VEX.W, XOP.W, EVEX.W */
11180 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11184 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11188 if (line
[3] == 'G')
11190 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11196 if (i
.tm
.opcode_modifier
.vexw
)
11200 if (line
> end
&& *line
&& !is_space_char (*line
))
11202 /* Improve diagnostic a little. */
11203 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11208 /* Before processing the opcode expression, find trailing "+r" or
11209 "/<digit>" specifiers. */
11210 for (ptr
= line
; ; ++ptr
)
11215 ptr
= strpbrk (ptr
, "+/,");
11216 if (ptr
== NULL
|| *ptr
== ',')
11219 if (*ptr
== '+' && ptr
[1] == 'r'
11220 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11224 i
.short_form
= true;
11228 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11229 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11231 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11235 i
.tm
.extension_opcode
= n
;
11236 i
.tm
.opcode_modifier
.modrm
= 1;
11241 input_line_pointer
= line
;
11242 val
= get_absolute_expression ();
11243 line
= input_line_pointer
;
11245 if (i
.short_form
&& (val
& 7))
11246 as_warn ("`+r' assumes low three opcode bits to be clear");
11248 for (j
= 1; j
< sizeof(val
); ++j
)
11249 if (!(val
>> (j
* 8)))
11252 /* Trim off a prefix if present. */
11253 if (j
> 1 && !vex
&& !xop
&& !evex
)
11255 uint8_t byte
= val
>> ((j
- 1) * 8);
11259 case DATA_PREFIX_OPCODE
:
11260 case REPE_PREFIX_OPCODE
:
11261 case REPNE_PREFIX_OPCODE
:
11262 if (!add_prefix (byte
))
11264 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11269 /* Trim off encoding space. */
11270 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11272 uint8_t byte
= val
>> ((--j
- 1) * 8);
11274 i
.insn_opcode_space
= SPACE_0F
;
11275 switch (byte
& -(j
> 1))
11278 i
.insn_opcode_space
= SPACE_0F38
;
11282 i
.insn_opcode_space
= SPACE_0F3A
;
11286 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11287 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11289 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11290 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11291 Also avoid hitting abort() there or in build_evex_prefix(). */
11292 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11297 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11300 i
.opcode_length
= j
;
11302 /* Handle operands, if any. */
11305 i386_operand_type combined
;
11306 expressionS
*disp_exp
= NULL
;
11311 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11319 as_bad (_("expecting operand after ','; got nothing"));
11323 if (i
.mem_operands
> 1)
11325 as_bad (_("too many memory references for `%s'"),
11326 &i386_mnemonics
[MN__insn
]);
11330 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11331 if (i
.vec_encoding
== vex_encoding_evex512
)
11332 i
.vec_encoding
= vex_encoding_evex
;
11334 /* Are we to emit ModR/M encoding? */
11337 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11338 || i
.tm
.extension_opcode
!= None
))
11339 i
.tm
.opcode_modifier
.modrm
= 1;
11341 if (!i
.tm
.opcode_modifier
.modrm
11343 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11344 || i
.mem_operands
))
11346 as_bad (_("too many register/memory operands"));
11350 /* Enforce certain constraints on operands. */
11351 switch (i
.reg_operands
+ i
.mem_operands
11352 + (i
.tm
.extension_opcode
!= None
))
11357 as_bad (_("too few register/memory operands"));
11360 /* Fall through. */
11362 if (i
.tm
.opcode_modifier
.modrm
)
11364 as_bad (_("too few register/memory operands"));
11374 && (i
.op
[0].imms
->X_op
!= O_constant
11375 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11377 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11380 /* Fall through. */
11382 if (i
.vec_encoding
!= vex_encoding_default
)
11384 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11387 /* Fall through. */
11389 as_bad (_("too many register/memory operands"));
11393 /* Bring operands into canonical order (imm, mem, reg). */
11398 for (j
= 1; j
< i
.operands
; ++j
)
11400 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11401 && operand_type_check (i
.types
[j
], imm
))
11402 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11403 && i
.types
[j
].bitfield
.class == ClassNone
))
11405 swap_2_operands (j
- 1, j
);
11412 /* For Intel syntax swap the order of register operands. */
11414 switch (i
.reg_operands
)
11421 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11422 /* Fall through. */
11425 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11432 /* Enforce constraints when using VSIB. */
11434 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11435 || i
.index_reg
->reg_type
.bitfield
.ymmword
11436 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11438 if (i
.vec_encoding
== vex_encoding_default
)
11440 as_bad (_("VSIB unavailable with legacy encoding"));
11444 if (i
.vec_encoding
== vex_encoding_evex
11445 && i
.reg_operands
> 1)
11447 /* We could allow two register operands, encoding the 2nd one in
11448 an 8-bit immediate like for 4-register-operand insns, but that
11449 would require ugly fiddling with process_operands() and/or
11450 build_modrm_byte(). */
11451 as_bad (_("too many register operands with VSIB"));
11455 i
.tm
.opcode_modifier
.sib
= 1;
11458 /* Establish operand size encoding. */
11459 operand_type_set (&combined
, 0);
11461 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11463 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11465 if (operand_type_check (i
.types
[j
], disp
))
11467 i
.types
[j
].bitfield
.baseindex
= 1;
11468 disp_exp
= i
.op
[j
].disps
;
11471 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11473 unsigned int n
= i
.memshift
;
11475 if (i
.types
[j
].bitfield
.byte
)
11477 else if (i
.types
[j
].bitfield
.word
)
11479 else if (i
.types
[j
].bitfield
.dword
)
11481 else if (i
.types
[j
].bitfield
.qword
)
11483 else if (i
.types
[j
].bitfield
.xmmword
)
11485 else if (i
.types
[j
].bitfield
.ymmword
)
11487 else if (i
.types
[j
].bitfield
.zmmword
)
11490 if (i
.memshift
< 32 && n
!= i
.memshift
)
11491 as_warn ("conflicting memory operand size specifiers");
11495 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11496 && j
== i
.broadcast
.operand
)
11499 combined
= operand_type_or (combined
, i
.types
[j
]);
11500 combined
.bitfield
.class = ClassNone
;
11503 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11504 << (i
.memshift
< 32 ? i
.memshift
: 0))
11506 case 64: combined
.bitfield
.zmmword
= 1; break;
11507 case 32: combined
.bitfield
.ymmword
= 1; break;
11508 case 16: combined
.bitfield
.xmmword
= 1; break;
11509 case 8: combined
.bitfield
.qword
= 1; break;
11510 case 4: combined
.bitfield
.dword
= 1; break;
11513 if (i
.vec_encoding
== vex_encoding_default
)
11515 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11517 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11518 : combined
.bitfield
.word
)
11519 && !add_prefix (DATA_PREFIX_OPCODE
))
11522 else if (!i
.tm
.opcode_modifier
.vexw
)
11524 if (flag_code
== CODE_64BIT
)
11526 if (combined
.bitfield
.qword
)
11527 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11528 else if (combined
.bitfield
.dword
)
11529 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11532 if (!i
.tm
.opcode_modifier
.vexw
)
11533 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11538 if (!i
.tm
.opcode_modifier
.vex
)
11540 if (combined
.bitfield
.ymmword
)
11541 i
.tm
.opcode_modifier
.vex
= VEX256
;
11542 else if (combined
.bitfield
.xmmword
)
11543 i
.tm
.opcode_modifier
.vex
= VEX128
;
11548 if (!i
.tm
.opcode_modifier
.evex
)
11550 /* Do _not_ consider AVX512VL here. */
11551 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11552 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11553 else if (combined
.bitfield
.ymmword
)
11554 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11555 else if (combined
.bitfield
.xmmword
)
11556 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11559 if (i
.memshift
>= 32)
11561 unsigned int n
= 0;
11563 switch (i
.tm
.opcode_modifier
.evex
)
11565 case EVEX512
: n
= 64; break;
11566 case EVEX256
: n
= 32; break;
11567 case EVEX128
: n
= 16; break;
11570 if (i
.broadcast
.type
)
11571 n
/= i
.broadcast
.type
;
11574 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11576 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11577 && disp_exp
->X_add_number
!= 0
11578 && i
.disp_encoding
!= disp_encoding_32bit
)
11580 if (!quiet_warnings
)
11581 as_warn ("cannot determine memory operand size");
11582 i
.disp_encoding
= disp_encoding_32bit
;
11587 if (i
.memshift
>= 32)
11590 i
.vec_encoding
= vex_encoding_error
;
11592 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11595 /* Establish size for immediate operands. */
11596 for (j
= 0; j
< i
.imm_operands
; ++j
)
11598 expressionS
*expP
= i
.op
[j
].imms
;
11600 gas_assert (operand_type_check (i
.types
[j
], imm
));
11601 operand_type_set (&i
.types
[j
], 0);
11603 if (i
.imm_bits
[j
] > 32)
11604 i
.types
[j
].bitfield
.imm64
= 1;
11605 else if (i
.imm_bits
[j
] > 16)
11607 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11608 i
.types
[j
].bitfield
.imm32s
= 1;
11610 i
.types
[j
].bitfield
.imm32
= 1;
11612 else if (i
.imm_bits
[j
] > 8)
11613 i
.types
[j
].bitfield
.imm16
= 1;
11614 else if (i
.imm_bits
[j
] > 0)
11616 if (i
.flags
[j
] & Operand_Signed
)
11617 i
.types
[j
].bitfield
.imm8s
= 1;
11619 i
.types
[j
].bitfield
.imm8
= 1;
11621 else if (expP
->X_op
== O_constant
)
11623 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11624 i
.types
[j
].bitfield
.imm1
= 0;
11625 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11626 zapping since smallest_imm_type() sets it unconditionally. */
11627 if (flag_code
!= CODE_64BIT
)
11629 i
.types
[j
].bitfield
.imm64
= 0;
11630 i
.types
[j
].bitfield
.imm32s
= 0;
11631 i
.types
[j
].bitfield
.imm32
= 1;
11633 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11634 i
.types
[j
].bitfield
.imm64
= 0;
11637 /* Non-constant expressions are sized heuristically. */
11640 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11641 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11642 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11646 for (j
= 0; j
< i
.operands
; ++j
)
11647 i
.tm
.operand_types
[j
] = i
.types
[j
];
11649 process_operands ();
11652 /* Don't set opcode until after processing operands, to avoid any
11653 potential special casing there. */
11654 i
.tm
.base_opcode
|= val
;
11656 if (i
.vec_encoding
== vex_encoding_error
11657 || (i
.vec_encoding
!= vex_encoding_evex
11658 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11659 || i
.rounding
.type
!= rc_none
11661 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11662 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11663 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11665 as_bad (_("conflicting .insn operands"));
11671 if (!i
.tm
.opcode_modifier
.vex
)
11672 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11674 build_vex_prefix (NULL
);
11675 i
.rex
&= REX_OPCODE
;
11679 if (!i
.tm
.opcode_modifier
.evex
)
11680 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11682 build_evex_prefix ();
11683 i
.rex
&= REX_OPCODE
;
11685 else if (i
.rex
!= 0)
11686 add_prefix (REX_OPCODE
| i
.rex
);
11691 *saved_ilp
= saved_char
;
11692 input_line_pointer
= line
;
11694 demand_empty_rest_of_line ();
11696 /* Make sure dot_insn() won't yield "true" anymore. */
11702 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11709 if (exp
.X_op
== O_symbol
)
11710 exp
.X_op
= O_secrel
;
11712 emit_expr (&exp
, 4);
11714 while (*input_line_pointer
++ == ',');
11716 input_line_pointer
--;
11717 demand_empty_rest_of_line ();
11721 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11728 if (exp
.X_op
== O_symbol
)
11729 exp
.X_op
= O_secidx
;
11731 emit_expr (&exp
, 2);
11733 while (*input_line_pointer
++ == ',');
11735 input_line_pointer
--;
11736 demand_empty_rest_of_line ();
11740 /* Handle Rounding Control / SAE specifiers. */
11743 RC_SAE_specifier (const char *pstr
)
11747 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11749 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11751 if (i
.rounding
.type
!= rc_none
)
11753 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11757 if (i
.vec_encoding
== vex_encoding_default
)
11758 i
.vec_encoding
= vex_encoding_evex512
;
11759 else if (i
.vec_encoding
!= vex_encoding_evex
11760 && i
.vec_encoding
!= vex_encoding_evex512
)
11763 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11765 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11772 /* Handle Vector operations. */
11775 check_VecOperations (char *op_string
)
11777 const reg_entry
*mask
;
11784 if (*op_string
== '{')
11788 /* Check broadcasts. */
11789 if (startswith (op_string
, "1to"))
11791 unsigned int bcst_type
;
11793 if (i
.broadcast
.type
)
11794 goto duplicated_vec_op
;
11797 if (*op_string
== '8')
11799 else if (*op_string
== '4')
11801 else if (*op_string
== '2')
11803 else if (*op_string
== '1'
11804 && *(op_string
+1) == '6')
11809 else if (*op_string
== '3'
11810 && *(op_string
+1) == '2')
11817 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11822 if (i
.vec_encoding
== vex_encoding_default
)
11823 i
.vec_encoding
= vex_encoding_evex
;
11824 else if (i
.vec_encoding
!= vex_encoding_evex
11825 && i
.vec_encoding
!= vex_encoding_evex512
)
11826 goto unknown_vec_op
;
11828 i
.broadcast
.type
= bcst_type
;
11829 i
.broadcast
.operand
= this_operand
;
11831 /* For .insn a data size specifier may be appended. */
11832 if (dot_insn () && *op_string
== ':')
11833 goto dot_insn_modifier
;
11835 /* Check .insn special cases. */
11836 else if (dot_insn () && *op_string
== ':')
11839 switch (op_string
[1])
11844 if (i
.memshift
< 32)
11845 goto duplicated_vec_op
;
11847 n
= strtoul (op_string
+ 2, &end_op
, 0);
11849 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11851 if (i
.memshift
< 32 && n
== 1)
11852 op_string
= end_op
;
11855 case 's': case 'u':
11856 /* This isn't really a "vector" operation, but a sign/size
11857 specifier for immediate operands of .insn. Note that AT&T
11858 syntax handles the same in i386_immediate(). */
11862 if (i
.imm_bits
[this_operand
])
11863 goto duplicated_vec_op
;
11865 n
= strtoul (op_string
+ 2, &end_op
, 0);
11866 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11868 i
.imm_bits
[this_operand
] = n
;
11869 if (op_string
[1] == 's')
11870 i
.flags
[this_operand
] |= Operand_Signed
;
11871 op_string
= end_op
;
11876 /* Check masking operation. */
11877 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11879 if (mask
== &bad_reg
)
11882 /* k0 can't be used for write mask. */
11883 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11885 as_bad (_("`%s%s' can't be used for write mask"),
11886 register_prefix
, mask
->reg_name
);
11893 i
.mask
.operand
= this_operand
;
11895 else if (i
.mask
.reg
->reg_num
)
11896 goto duplicated_vec_op
;
11901 /* Only "{z}" is allowed here. No need to check
11902 zeroing mask explicitly. */
11903 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11905 as_bad (_("invalid write mask `%s'"), saved
);
11910 op_string
= end_op
;
11912 /* Check zeroing-flag for masking operation. */
11913 else if (*op_string
== 'z')
11917 i
.mask
.reg
= reg_k0
;
11918 i
.mask
.zeroing
= 1;
11919 i
.mask
.operand
= this_operand
;
11923 if (i
.mask
.zeroing
)
11926 as_bad (_("duplicated `%s'"), saved
);
11930 i
.mask
.zeroing
= 1;
11932 /* Only "{%k}" is allowed here. No need to check mask
11933 register explicitly. */
11934 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11936 as_bad (_("invalid zeroing-masking `%s'"),
11944 else if (intel_syntax
11945 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11946 i
.rounding
.modifier
= true;
11948 goto unknown_vec_op
;
11950 if (*op_string
!= '}')
11952 as_bad (_("missing `}' in `%s'"), saved
);
11957 /* Strip whitespace since the addition of pseudo prefixes
11958 changed how the scrubber treats '{'. */
11959 if (is_space_char (*op_string
))
11965 /* We don't know this one. */
11966 as_bad (_("unknown vector operation: `%s'"), saved
);
11970 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11972 as_bad (_("zeroing-masking only allowed with write mask"));
11980 i386_immediate (char *imm_start
)
11982 char *save_input_line_pointer
;
11983 char *gotfree_input_line
;
11986 i386_operand_type types
;
11988 operand_type_set (&types
, ~0);
11990 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11992 as_bad (_("at most %d immediate operands are allowed"),
11993 MAX_IMMEDIATE_OPERANDS
);
11997 exp
= &im_expressions
[i
.imm_operands
++];
11998 i
.op
[this_operand
].imms
= exp
;
12000 if (is_space_char (*imm_start
))
12003 save_input_line_pointer
= input_line_pointer
;
12004 input_line_pointer
= imm_start
;
12006 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12007 if (gotfree_input_line
)
12008 input_line_pointer
= gotfree_input_line
;
12010 expr_mode
= expr_operator_none
;
12011 exp_seg
= expression (exp
);
12013 /* For .insn immediates there may be a size specifier. */
12014 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12015 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12018 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12020 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12022 i
.imm_bits
[this_operand
] = n
;
12023 if (input_line_pointer
[2] == 's')
12024 i
.flags
[this_operand
] |= Operand_Signed
;
12025 input_line_pointer
= e
+ 1;
12029 SKIP_WHITESPACE ();
12030 if (*input_line_pointer
)
12031 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12033 input_line_pointer
= save_input_line_pointer
;
12034 if (gotfree_input_line
)
12036 free (gotfree_input_line
);
12038 if (exp
->X_op
== O_constant
)
12039 exp
->X_op
= O_illegal
;
12042 if (exp_seg
== reg_section
)
12044 as_bad (_("illegal immediate register operand %s"), imm_start
);
12048 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12052 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12053 i386_operand_type types
, const char *imm_start
)
12055 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12058 as_bad (_("missing or invalid immediate expression `%s'"),
12062 else if (exp
->X_op
== O_constant
)
12064 /* Size it properly later. */
12065 i
.types
[this_operand
].bitfield
.imm64
= 1;
12067 /* If not 64bit, sign/zero extend val, to account for wraparound
12069 if (expr_mode
== expr_operator_present
12070 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12071 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12073 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12074 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12075 && exp_seg
!= absolute_section
12076 && exp_seg
!= text_section
12077 && exp_seg
!= data_section
12078 && exp_seg
!= bss_section
12079 && exp_seg
!= undefined_section
12080 && !bfd_is_com_section (exp_seg
))
12082 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12088 /* This is an address. The size of the address will be
12089 determined later, depending on destination register,
12090 suffix, or the default for the section. */
12091 i
.types
[this_operand
].bitfield
.imm8
= 1;
12092 i
.types
[this_operand
].bitfield
.imm16
= 1;
12093 i
.types
[this_operand
].bitfield
.imm32
= 1;
12094 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12095 i
.types
[this_operand
].bitfield
.imm64
= 1;
12096 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12104 i386_scale (char *scale
)
12107 char *save
= input_line_pointer
;
12109 input_line_pointer
= scale
;
12110 val
= get_absolute_expression ();
12115 i
.log2_scale_factor
= 0;
12118 i
.log2_scale_factor
= 1;
12121 i
.log2_scale_factor
= 2;
12124 i
.log2_scale_factor
= 3;
12128 char sep
= *input_line_pointer
;
12130 *input_line_pointer
= '\0';
12131 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12133 *input_line_pointer
= sep
;
12134 input_line_pointer
= save
;
12138 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12140 as_warn (_("scale factor of %d without an index register"),
12141 1 << i
.log2_scale_factor
);
12142 i
.log2_scale_factor
= 0;
12144 scale
= input_line_pointer
;
12145 input_line_pointer
= save
;
12150 i386_displacement (char *disp_start
, char *disp_end
)
12154 char *save_input_line_pointer
;
12155 char *gotfree_input_line
;
12157 i386_operand_type bigdisp
, types
= anydisp
;
12160 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12162 as_bad (_("at most %d displacement operands are allowed"),
12163 MAX_MEMORY_OPERANDS
);
12167 operand_type_set (&bigdisp
, 0);
12169 || i
.types
[this_operand
].bitfield
.baseindex
12170 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12171 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12173 i386_addressing_mode ();
12174 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12175 if (flag_code
== CODE_64BIT
)
12177 bigdisp
.bitfield
.disp32
= 1;
12179 bigdisp
.bitfield
.disp64
= 1;
12181 else if ((flag_code
== CODE_16BIT
) ^ override
)
12182 bigdisp
.bitfield
.disp16
= 1;
12184 bigdisp
.bitfield
.disp32
= 1;
12188 /* For PC-relative branches, the width of the displacement may be
12189 dependent upon data size, but is never dependent upon address size.
12190 Also make sure to not unintentionally match against a non-PC-relative
12191 branch template. */
12192 static templates aux_templates
;
12193 const insn_template
*t
= current_templates
->start
;
12194 bool has_intel64
= false;
12196 aux_templates
.start
= t
;
12197 while (++t
< current_templates
->end
)
12199 if (t
->opcode_modifier
.jump
12200 != current_templates
->start
->opcode_modifier
.jump
)
12202 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12203 has_intel64
= true;
12205 if (t
< current_templates
->end
)
12207 aux_templates
.end
= t
;
12208 current_templates
= &aux_templates
;
12211 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12212 if (flag_code
== CODE_64BIT
)
12214 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12215 && (!intel64
|| !has_intel64
))
12216 bigdisp
.bitfield
.disp16
= 1;
12218 bigdisp
.bitfield
.disp32
= 1;
12223 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12225 : LONG_MNEM_SUFFIX
));
12226 bigdisp
.bitfield
.disp32
= 1;
12227 if ((flag_code
== CODE_16BIT
) ^ override
)
12229 bigdisp
.bitfield
.disp32
= 0;
12230 bigdisp
.bitfield
.disp16
= 1;
12234 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12237 exp
= &disp_expressions
[i
.disp_operands
];
12238 i
.op
[this_operand
].disps
= exp
;
12240 save_input_line_pointer
= input_line_pointer
;
12241 input_line_pointer
= disp_start
;
12242 END_STRING_AND_SAVE (disp_end
);
12244 #ifndef GCC_ASM_O_HACK
12245 #define GCC_ASM_O_HACK 0
12248 END_STRING_AND_SAVE (disp_end
+ 1);
12249 if (i
.types
[this_operand
].bitfield
.baseIndex
12250 && displacement_string_end
[-1] == '+')
12252 /* This hack is to avoid a warning when using the "o"
12253 constraint within gcc asm statements.
12256 #define _set_tssldt_desc(n,addr,limit,type) \
12257 __asm__ __volatile__ ( \
12258 "movw %w2,%0\n\t" \
12259 "movw %w1,2+%0\n\t" \
12260 "rorl $16,%1\n\t" \
12261 "movb %b1,4+%0\n\t" \
12262 "movb %4,5+%0\n\t" \
12263 "movb $0,6+%0\n\t" \
12264 "movb %h1,7+%0\n\t" \
12266 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12268 This works great except that the output assembler ends
12269 up looking a bit weird if it turns out that there is
12270 no offset. You end up producing code that looks like:
12283 So here we provide the missing zero. */
12285 *displacement_string_end
= '0';
12288 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12289 if (gotfree_input_line
)
12290 input_line_pointer
= gotfree_input_line
;
12292 expr_mode
= expr_operator_none
;
12293 exp_seg
= expression (exp
);
12295 SKIP_WHITESPACE ();
12296 if (*input_line_pointer
)
12297 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12299 RESTORE_END_STRING (disp_end
+ 1);
12301 input_line_pointer
= save_input_line_pointer
;
12302 if (gotfree_input_line
)
12304 free (gotfree_input_line
);
12306 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12307 exp
->X_op
= O_illegal
;
12310 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12312 RESTORE_END_STRING (disp_end
);
12318 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12319 i386_operand_type types
, const char *disp_start
)
12323 /* We do this to make sure that the section symbol is in
12324 the symbol table. We will ultimately change the relocation
12325 to be relative to the beginning of the section. */
12326 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12327 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12328 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12330 if (exp
->X_op
!= O_symbol
)
12333 if (S_IS_LOCAL (exp
->X_add_symbol
)
12334 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12335 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12336 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12337 exp
->X_op
= O_subtract
;
12338 exp
->X_op_symbol
= GOT_symbol
;
12339 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12340 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12341 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12342 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12344 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12347 else if (exp
->X_op
== O_absent
12348 || exp
->X_op
== O_illegal
12349 || exp
->X_op
== O_big
)
12352 as_bad (_("missing or invalid displacement expression `%s'"),
12357 else if (exp
->X_op
== O_constant
)
12359 /* Sizing gets taken care of by optimize_disp().
12361 If not 64bit, sign/zero extend val, to account for wraparound
12363 if (expr_mode
== expr_operator_present
12364 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12365 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12368 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12369 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12370 && exp_seg
!= absolute_section
12371 && exp_seg
!= text_section
12372 && exp_seg
!= data_section
12373 && exp_seg
!= bss_section
12374 && exp_seg
!= undefined_section
12375 && !bfd_is_com_section (exp_seg
))
12377 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12382 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12383 i
.types
[this_operand
].bitfield
.disp8
= 1;
12385 /* Check if this is a displacement only operand. */
12386 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12387 i
.types
[this_operand
] =
12388 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12389 operand_type_and (i
.types
[this_operand
], types
));
12394 /* Return the active addressing mode, taking address override and
12395 registers forming the address into consideration. Update the
12396 address override prefix if necessary. */
12398 static enum flag_code
12399 i386_addressing_mode (void)
12401 enum flag_code addr_mode
;
12403 if (i
.prefix
[ADDR_PREFIX
])
12404 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12405 else if (flag_code
== CODE_16BIT
12406 && is_cpu (current_templates
->start
, CpuMPX
)
12407 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12408 from md_assemble() by "is not a valid base/index expression"
12409 when there is a base and/or index. */
12410 && !i
.types
[this_operand
].bitfield
.baseindex
)
12412 /* MPX insn memory operands with neither base nor index must be forced
12413 to use 32-bit addressing in 16-bit mode. */
12414 addr_mode
= CODE_32BIT
;
12415 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12417 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12418 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12422 addr_mode
= flag_code
;
12424 #if INFER_ADDR_PREFIX
12425 if (i
.mem_operands
== 0)
12427 /* Infer address prefix from the first memory operand. */
12428 const reg_entry
*addr_reg
= i
.base_reg
;
12430 if (addr_reg
== NULL
)
12431 addr_reg
= i
.index_reg
;
12435 if (addr_reg
->reg_type
.bitfield
.dword
)
12436 addr_mode
= CODE_32BIT
;
12437 else if (flag_code
!= CODE_64BIT
12438 && addr_reg
->reg_type
.bitfield
.word
)
12439 addr_mode
= CODE_16BIT
;
12441 if (addr_mode
!= flag_code
)
12443 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12445 /* Change the size of any displacement too. At most one
12446 of Disp16 or Disp32 is set.
12447 FIXME. There doesn't seem to be any real need for
12448 separate Disp16 and Disp32 flags. The same goes for
12449 Imm16 and Imm32. Removing them would probably clean
12450 up the code quite a lot. */
12451 if (flag_code
!= CODE_64BIT
12452 && (i
.types
[this_operand
].bitfield
.disp16
12453 || i
.types
[this_operand
].bitfield
.disp32
))
12455 static const i386_operand_type disp16_32
= {
12456 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12459 i
.types
[this_operand
]
12460 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12471 /* Make sure the memory operand we've been dealt is valid.
12472 Return 1 on success, 0 on a failure. */
12475 i386_index_check (const char *operand_string
)
12477 const char *kind
= "base/index";
12478 enum flag_code addr_mode
= i386_addressing_mode ();
12479 const insn_template
*t
= current_templates
->end
- 1;
12481 if (t
->opcode_modifier
.isstring
)
12483 /* Memory operands of string insns are special in that they only allow
12484 a single register (rDI, rSI, or rBX) as their memory address. */
12485 const reg_entry
*expected_reg
;
12486 static const char di_si
[][2][4] =
12492 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12494 kind
= "string address";
12496 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12498 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12501 if (!t
->operand_types
[0].bitfield
.baseindex
12502 || ((!i
.mem_operands
!= !intel_syntax
)
12503 && t
->operand_types
[1].bitfield
.baseindex
))
12506 = (const reg_entry
*) str_hash_find (reg_hash
,
12507 di_si
[addr_mode
][op
== es_op
]);
12511 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12513 if (i
.base_reg
!= expected_reg
12515 || operand_type_check (i
.types
[this_operand
], disp
))
12517 /* The second memory operand must have the same size as
12521 && !((addr_mode
== CODE_64BIT
12522 && i
.base_reg
->reg_type
.bitfield
.qword
)
12523 || (addr_mode
== CODE_32BIT
12524 ? i
.base_reg
->reg_type
.bitfield
.dword
12525 : i
.base_reg
->reg_type
.bitfield
.word
)))
12528 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12530 intel_syntax
? '[' : '(',
12532 expected_reg
->reg_name
,
12533 intel_syntax
? ']' : ')');
12540 as_bad (_("`%s' is not a valid %s expression"),
12541 operand_string
, kind
);
12546 t
= current_templates
->start
;
12548 if (addr_mode
!= CODE_16BIT
)
12550 /* 32-bit/64-bit checks. */
12551 if (i
.disp_encoding
== disp_encoding_16bit
)
12554 as_bad (_("invalid `%s' prefix"),
12555 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12560 && ((addr_mode
== CODE_64BIT
12561 ? !i
.base_reg
->reg_type
.bitfield
.qword
12562 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12563 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12564 || i
.base_reg
->reg_num
== RegIZ
))
12566 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12567 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12568 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12569 && ((addr_mode
== CODE_64BIT
12570 ? !i
.index_reg
->reg_type
.bitfield
.qword
12571 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12572 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12575 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12576 if (t
->mnem_off
== MN_bndmk
12577 || t
->mnem_off
== MN_bndldx
12578 || t
->mnem_off
== MN_bndstx
12579 || t
->opcode_modifier
.sib
== SIBMEM
)
12581 /* They cannot use RIP-relative addressing. */
12582 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12584 as_bad (_("`%s' cannot be used here"), operand_string
);
12588 /* bndldx and bndstx ignore their scale factor. */
12589 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12590 && i
.log2_scale_factor
)
12591 as_warn (_("register scaling is being ignored here"));
12596 /* 16-bit checks. */
12597 if (i
.disp_encoding
== disp_encoding_32bit
)
12601 && (!i
.base_reg
->reg_type
.bitfield
.word
12602 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12604 && (!i
.index_reg
->reg_type
.bitfield
.word
12605 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12607 && i
.base_reg
->reg_num
< 6
12608 && i
.index_reg
->reg_num
>= 6
12609 && i
.log2_scale_factor
== 0))))
12616 /* Handle vector immediates. */
12619 RC_SAE_immediate (const char *imm_start
)
12621 const char *pstr
= imm_start
;
12626 pstr
= RC_SAE_specifier (pstr
+ 1);
12630 if (*pstr
++ != '}')
12632 as_bad (_("Missing '}': '%s'"), imm_start
);
12635 /* RC/SAE immediate string should contain nothing more. */;
12638 as_bad (_("Junk after '}': '%s'"), imm_start
);
12642 /* Internally this doesn't count as an operand. */
12648 static INLINE
bool starts_memory_operand (char c
)
12651 || is_name_beginner (c
)
12652 || strchr ("([\"+-!~", c
);
12655 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12659 i386_att_operand (char *operand_string
)
12661 const reg_entry
*r
;
12663 char *op_string
= operand_string
;
12665 if (is_space_char (*op_string
))
12668 /* We check for an absolute prefix (differentiating,
12669 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12670 if (*op_string
== ABSOLUTE_PREFIX
12671 && current_templates
->start
->opcode_modifier
.jump
)
12674 if (is_space_char (*op_string
))
12676 i
.jumpabsolute
= true;
12679 /* Check if operand is a register. */
12680 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12682 i386_operand_type temp
;
12687 /* Check for a segment override by searching for ':' after a
12688 segment register. */
12689 op_string
= end_op
;
12690 if (is_space_char (*op_string
))
12692 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12694 i
.seg
[i
.mem_operands
] = r
;
12696 /* Skip the ':' and whitespace. */
12698 if (is_space_char (*op_string
))
12701 /* Handle case of %es:*foo. */
12702 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12703 && current_templates
->start
->opcode_modifier
.jump
)
12706 if (is_space_char (*op_string
))
12708 i
.jumpabsolute
= true;
12711 if (!starts_memory_operand (*op_string
))
12713 as_bad (_("bad memory operand `%s'"), op_string
);
12716 goto do_memory_reference
;
12719 /* Handle vector operations. */
12720 if (*op_string
== '{')
12722 op_string
= check_VecOperations (op_string
);
12723 if (op_string
== NULL
)
12729 as_bad (_("junk `%s' after register"), op_string
);
12733 /* Reject pseudo registers for .insn. */
12734 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12736 as_bad (_("`%s%s' cannot be used here"),
12737 register_prefix
, r
->reg_name
);
12741 temp
= r
->reg_type
;
12742 temp
.bitfield
.baseindex
= 0;
12743 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12745 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12746 i
.op
[this_operand
].regs
= r
;
12749 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12750 operand was also present earlier on. */
12751 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12752 && i
.reg_operands
== 1)
12756 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12757 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12759 as_bad (_("`%s': misplaced `{%s}'"),
12760 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12764 else if (*op_string
== REGISTER_PREFIX
)
12766 as_bad (_("bad register name `%s'"), op_string
);
12769 else if (*op_string
== IMMEDIATE_PREFIX
)
12772 if (i
.jumpabsolute
)
12774 as_bad (_("immediate operand illegal with absolute jump"));
12777 if (!i386_immediate (op_string
))
12779 if (i
.rounding
.type
!= rc_none
)
12781 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12782 insn_name (current_templates
->start
));
12786 else if (RC_SAE_immediate (operand_string
))
12788 /* If it is a RC or SAE immediate, do the necessary placement check:
12789 Only another immediate or a GPR may precede it. */
12790 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12791 || (i
.reg_operands
== 1
12792 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12794 as_bad (_("`%s': misplaced `%s'"),
12795 insn_name (current_templates
->start
), operand_string
);
12799 else if (starts_memory_operand (*op_string
))
12801 /* This is a memory reference of some sort. */
12804 /* Start and end of displacement string expression (if found). */
12805 char *displacement_string_start
;
12806 char *displacement_string_end
;
12808 do_memory_reference
:
12809 /* Check for base index form. We detect the base index form by
12810 looking for an ')' at the end of the operand, searching
12811 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12813 base_string
= op_string
+ strlen (op_string
);
12815 /* Handle vector operations. */
12817 if (is_space_char (*base_string
))
12820 if (*base_string
== '}')
12822 char *vop_start
= NULL
;
12824 while (base_string
-- > op_string
)
12826 if (*base_string
== '"')
12828 if (*base_string
!= '{')
12831 vop_start
= base_string
;
12834 if (is_space_char (*base_string
))
12837 if (*base_string
!= '}')
12845 as_bad (_("unbalanced figure braces"));
12849 if (check_VecOperations (vop_start
) == NULL
)
12853 /* If we only have a displacement, set-up for it to be parsed later. */
12854 displacement_string_start
= op_string
;
12855 displacement_string_end
= base_string
+ 1;
12857 if (*base_string
== ')')
12860 unsigned int parens_not_balanced
= 0;
12861 bool in_quotes
= false;
12863 /* We've already checked that the number of left & right ()'s are
12864 equal, and that there's a matching set of double quotes. */
12865 end_op
= base_string
;
12866 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12868 if (*temp_string
== '\\' && temp_string
[1] == '"')
12870 else if (*temp_string
== '"')
12871 in_quotes
= !in_quotes
;
12872 else if (!in_quotes
)
12874 if (*temp_string
== '(' && !parens_not_balanced
++)
12875 base_string
= temp_string
;
12876 if (*temp_string
== ')')
12877 --parens_not_balanced
;
12881 temp_string
= base_string
;
12883 /* Skip past '(' and whitespace. */
12884 gas_assert (*base_string
== '(');
12886 if (is_space_char (*base_string
))
12889 if (*base_string
== ','
12890 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12893 displacement_string_end
= temp_string
;
12895 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12899 if (i
.base_reg
== &bad_reg
)
12901 base_string
= end_op
;
12902 if (is_space_char (*base_string
))
12906 /* There may be an index reg or scale factor here. */
12907 if (*base_string
== ',')
12910 if (is_space_char (*base_string
))
12913 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12916 if (i
.index_reg
== &bad_reg
)
12918 base_string
= end_op
;
12919 if (is_space_char (*base_string
))
12921 if (*base_string
== ',')
12924 if (is_space_char (*base_string
))
12927 else if (*base_string
!= ')')
12929 as_bad (_("expecting `,' or `)' "
12930 "after index register in `%s'"),
12935 else if (*base_string
== REGISTER_PREFIX
)
12937 end_op
= strchr (base_string
, ',');
12940 as_bad (_("bad register name `%s'"), base_string
);
12944 /* Check for scale factor. */
12945 if (*base_string
!= ')')
12947 char *end_scale
= i386_scale (base_string
);
12952 base_string
= end_scale
;
12953 if (is_space_char (*base_string
))
12955 if (*base_string
!= ')')
12957 as_bad (_("expecting `)' "
12958 "after scale factor in `%s'"),
12963 else if (!i
.index_reg
)
12965 as_bad (_("expecting index register or scale factor "
12966 "after `,'; got '%c'"),
12971 else if (*base_string
!= ')')
12973 as_bad (_("expecting `,' or `)' "
12974 "after base register in `%s'"),
12979 else if (*base_string
== REGISTER_PREFIX
)
12981 end_op
= strchr (base_string
, ',');
12984 as_bad (_("bad register name `%s'"), base_string
);
12989 /* If there's an expression beginning the operand, parse it,
12990 assuming displacement_string_start and
12991 displacement_string_end are meaningful. */
12992 if (displacement_string_start
!= displacement_string_end
)
12994 if (!i386_displacement (displacement_string_start
,
12995 displacement_string_end
))
12999 /* Special case for (%dx) while doing input/output op. */
13001 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
13002 && i
.base_reg
->reg_type
.bitfield
.word
13003 && i
.index_reg
== 0
13004 && i
.log2_scale_factor
== 0
13005 && i
.seg
[i
.mem_operands
] == 0
13006 && !operand_type_check (i
.types
[this_operand
], disp
))
13008 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
13009 i
.input_output_operand
= true;
13013 if (i386_index_check (operand_string
) == 0)
13015 i
.flags
[this_operand
] |= Operand_Mem
;
13020 /* It's not a memory operand; argh! */
13021 as_bad (_("invalid char %s beginning operand %d `%s'"),
13022 output_invalid (*op_string
),
13027 return 1; /* Normal return. */
13030 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13031 that an rs_machine_dependent frag may reach. */
13034 i386_frag_max_var (fragS
*frag
)
13036 /* The only relaxable frags are for jumps.
13037 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13038 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13039 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13042 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13044 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13046 /* STT_GNU_IFUNC symbol must go through PLT. */
13047 if ((symbol_get_bfdsym (fr_symbol
)->flags
13048 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13051 if (!S_IS_EXTERNAL (fr_symbol
))
13052 /* Symbol may be weak or local. */
13053 return !S_IS_WEAK (fr_symbol
);
13055 /* Global symbols with non-default visibility can't be preempted. */
13056 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13059 if (fr_var
!= NO_RELOC
)
13060 switch ((enum bfd_reloc_code_real
) fr_var
)
13062 case BFD_RELOC_386_PLT32
:
13063 case BFD_RELOC_X86_64_PLT32
:
13064 /* Symbol with PLT relocation may be preempted. */
13070 /* Global symbols with default visibility in a shared library may be
13071 preempted by another definition. */
13076 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13077 Note also work for Skylake and Cascadelake.
13078 ---------------------------------------------------------------------
13079 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13080 | ------ | ----------- | ------- | -------- |
13082 | Jno | N | N | Y |
13083 | Jc/Jb | Y | N | Y |
13084 | Jae/Jnb | Y | N | Y |
13085 | Je/Jz | Y | Y | Y |
13086 | Jne/Jnz | Y | Y | Y |
13087 | Jna/Jbe | Y | N | Y |
13088 | Ja/Jnbe | Y | N | Y |
13090 | Jns | N | N | Y |
13091 | Jp/Jpe | N | N | Y |
13092 | Jnp/Jpo | N | N | Y |
13093 | Jl/Jnge | Y | Y | Y |
13094 | Jge/Jnl | Y | Y | Y |
13095 | Jle/Jng | Y | Y | Y |
13096 | Jg/Jnle | Y | Y | Y |
13097 --------------------------------------------------------------------- */
13099 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13101 if (mf_cmp
== mf_cmp_alu_cmp
)
13102 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13103 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13104 if (mf_cmp
== mf_cmp_incdec
)
13105 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13106 || mf_jcc
== mf_jcc_jle
);
13107 if (mf_cmp
== mf_cmp_test_and
)
13112 /* Return the next non-empty frag. */
13115 i386_next_non_empty_frag (fragS
*fragP
)
13117 /* There may be a frag with a ".fill 0" when there is no room in
13118 the current frag for frag_grow in output_insn. */
13119 for (fragP
= fragP
->fr_next
;
13121 && fragP
->fr_type
== rs_fill
13122 && fragP
->fr_fix
== 0);
13123 fragP
= fragP
->fr_next
)
13128 /* Return the next jcc frag after BRANCH_PADDING. */
13131 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13133 fragS
*branch_fragP
;
13137 if (pad_fragP
->fr_type
== rs_machine_dependent
13138 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13139 == BRANCH_PADDING
))
13141 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13142 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13144 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13145 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13146 pad_fragP
->tc_frag_data
.mf_type
))
13147 return branch_fragP
;
13153 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13156 i386_classify_machine_dependent_frag (fragS
*fragP
)
13160 fragS
*branch_fragP
;
13162 unsigned int max_prefix_length
;
13164 if (fragP
->tc_frag_data
.classified
)
13167 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13168 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13169 for (next_fragP
= fragP
;
13170 next_fragP
!= NULL
;
13171 next_fragP
= next_fragP
->fr_next
)
13173 next_fragP
->tc_frag_data
.classified
= 1;
13174 if (next_fragP
->fr_type
== rs_machine_dependent
)
13175 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13177 case BRANCH_PADDING
:
13178 /* The BRANCH_PADDING frag must be followed by a branch
13180 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13181 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13183 case FUSED_JCC_PADDING
:
13184 /* Check if this is a fused jcc:
13186 CMP like instruction
13190 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13191 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13192 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13195 /* The BRANCH_PADDING frag is merged with the
13196 FUSED_JCC_PADDING frag. */
13197 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13198 /* CMP like instruction size. */
13199 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13200 frag_wane (pad_fragP
);
13201 /* Skip to branch_fragP. */
13202 next_fragP
= branch_fragP
;
13204 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13206 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13208 next_fragP
->fr_subtype
13209 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13210 next_fragP
->tc_frag_data
.max_bytes
13211 = next_fragP
->tc_frag_data
.max_prefix_length
;
13212 /* This will be updated in the BRANCH_PREFIX scan. */
13213 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13216 frag_wane (next_fragP
);
13221 /* Stop if there is no BRANCH_PREFIX. */
13222 if (!align_branch_prefix_size
)
13225 /* Scan for BRANCH_PREFIX. */
13226 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13228 if (fragP
->fr_type
!= rs_machine_dependent
13229 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13233 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13234 COND_JUMP_PREFIX. */
13235 max_prefix_length
= 0;
13236 for (next_fragP
= fragP
;
13237 next_fragP
!= NULL
;
13238 next_fragP
= next_fragP
->fr_next
)
13240 if (next_fragP
->fr_type
== rs_fill
)
13241 /* Skip rs_fill frags. */
13243 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13244 /* Stop for all other frags. */
13247 /* rs_machine_dependent frags. */
13248 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13251 /* Count BRANCH_PREFIX frags. */
13252 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13254 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13255 frag_wane (next_fragP
);
13259 += next_fragP
->tc_frag_data
.max_bytes
;
13261 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13263 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13264 == FUSED_JCC_PADDING
))
13266 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13267 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13271 /* Stop for other rs_machine_dependent frags. */
13275 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13277 /* Skip to the next frag. */
13278 fragP
= next_fragP
;
13282 /* Compute padding size for
13285 CMP like instruction
13287 COND_JUMP/UNCOND_JUMP
13292 COND_JUMP/UNCOND_JUMP
13296 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13298 unsigned int offset
, size
, padding_size
;
13299 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13301 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13303 address
= fragP
->fr_address
;
13304 address
+= fragP
->fr_fix
;
13306 /* CMP like instrunction size. */
13307 size
= fragP
->tc_frag_data
.cmp_size
;
13309 /* The base size of the branch frag. */
13310 size
+= branch_fragP
->fr_fix
;
13312 /* Add opcode and displacement bytes for the rs_machine_dependent
13314 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13315 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13317 /* Check if branch is within boundary and doesn't end at the last
13319 offset
= address
& ((1U << align_branch_power
) - 1);
13320 if ((offset
+ size
) >= (1U << align_branch_power
))
13321 /* Padding needed to avoid crossing boundary. */
13322 padding_size
= (1U << align_branch_power
) - offset
;
13324 /* No padding needed. */
13327 /* The return value may be saved in tc_frag_data.length which is
13329 if (!fits_in_unsigned_byte (padding_size
))
13332 return padding_size
;
13335 /* i386_generic_table_relax_frag()
13337 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13338 grow/shrink padding to align branch frags. Hand others to
13342 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13344 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13345 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13347 long padding_size
= i386_branch_padding_size (fragP
, 0);
13348 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13350 /* When the BRANCH_PREFIX frag is used, the computed address
13351 must match the actual address and there should be no padding. */
13352 if (fragP
->tc_frag_data
.padding_address
13353 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13357 /* Update the padding size. */
13359 fragP
->tc_frag_data
.length
= padding_size
;
13363 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13365 fragS
*padding_fragP
, *next_fragP
;
13366 long padding_size
, left_size
, last_size
;
13368 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13369 if (!padding_fragP
)
13370 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13371 return (fragP
->tc_frag_data
.length
13372 - fragP
->tc_frag_data
.last_length
);
13374 /* Compute the relative address of the padding frag in the very
13375 first time where the BRANCH_PREFIX frag sizes are zero. */
13376 if (!fragP
->tc_frag_data
.padding_address
)
13377 fragP
->tc_frag_data
.padding_address
13378 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13380 /* First update the last length from the previous interation. */
13381 left_size
= fragP
->tc_frag_data
.prefix_length
;
13382 for (next_fragP
= fragP
;
13383 next_fragP
!= padding_fragP
;
13384 next_fragP
= next_fragP
->fr_next
)
13385 if (next_fragP
->fr_type
== rs_machine_dependent
13386 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13391 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13395 if (max
> left_size
)
13400 next_fragP
->tc_frag_data
.last_length
= size
;
13404 next_fragP
->tc_frag_data
.last_length
= 0;
13407 /* Check the padding size for the padding frag. */
13408 padding_size
= i386_branch_padding_size
13409 (padding_fragP
, (fragP
->fr_address
13410 + fragP
->tc_frag_data
.padding_address
));
13412 last_size
= fragP
->tc_frag_data
.prefix_length
;
13413 /* Check if there is change from the last interation. */
13414 if (padding_size
== last_size
)
13416 /* Update the expected address of the padding frag. */
13417 padding_fragP
->tc_frag_data
.padding_address
13418 = (fragP
->fr_address
+ padding_size
13419 + fragP
->tc_frag_data
.padding_address
);
13423 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13425 /* No padding if there is no sufficient room. Clear the
13426 expected address of the padding frag. */
13427 padding_fragP
->tc_frag_data
.padding_address
= 0;
13431 /* Store the expected address of the padding frag. */
13432 padding_fragP
->tc_frag_data
.padding_address
13433 = (fragP
->fr_address
+ padding_size
13434 + fragP
->tc_frag_data
.padding_address
);
13436 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13438 /* Update the length for the current interation. */
13439 left_size
= padding_size
;
13440 for (next_fragP
= fragP
;
13441 next_fragP
!= padding_fragP
;
13442 next_fragP
= next_fragP
->fr_next
)
13443 if (next_fragP
->fr_type
== rs_machine_dependent
13444 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13449 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13453 if (max
> left_size
)
13458 next_fragP
->tc_frag_data
.length
= size
;
13462 next_fragP
->tc_frag_data
.length
= 0;
13465 return (fragP
->tc_frag_data
.length
13466 - fragP
->tc_frag_data
.last_length
);
13468 return relax_frag (segment
, fragP
, stretch
);
13471 /* md_estimate_size_before_relax()
13473 Called just before relax() for rs_machine_dependent frags. The x86
13474 assembler uses these frags to handle variable size jump
13477 Any symbol that is now undefined will not become defined.
13478 Return the correct fr_subtype in the frag.
13479 Return the initial "guess for variable size of frag" to caller.
13480 The guess is actually the growth beyond the fixed part. Whatever
13481 we do to grow the fixed or variable part contributes to our
13485 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13487 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13488 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13489 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13491 i386_classify_machine_dependent_frag (fragP
);
13492 return fragP
->tc_frag_data
.length
;
13495 /* We've already got fragP->fr_subtype right; all we have to do is
13496 check for un-relaxable symbols. On an ELF system, we can't relax
13497 an externally visible symbol, because it may be overridden by a
13499 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13502 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13505 #if defined (OBJ_COFF) && defined (TE_PE)
13506 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13507 && S_IS_WEAK (fragP
->fr_symbol
))
13511 /* Symbol is undefined in this segment, or we need to keep a
13512 reloc so that weak symbols can be overridden. */
13513 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13514 enum bfd_reloc_code_real reloc_type
;
13515 unsigned char *opcode
;
13519 if (fragP
->fr_var
!= NO_RELOC
)
13520 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13521 else if (size
== 2)
13522 reloc_type
= BFD_RELOC_16_PCREL
;
13523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13524 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13525 && fragP
->fr_offset
== 0
13526 && need_plt32_p (fragP
->fr_symbol
))
13527 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13530 reloc_type
= BFD_RELOC_32_PCREL
;
13532 old_fr_fix
= fragP
->fr_fix
;
13533 opcode
= (unsigned char *) fragP
->fr_opcode
;
13535 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13538 /* Make jmp (0xeb) a (d)word displacement jump. */
13540 fragP
->fr_fix
+= size
;
13541 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13543 fragP
->fr_offset
, 1,
13549 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13551 /* Negate the condition, and branch past an
13552 unconditional jump. */
13555 /* Insert an unconditional jump. */
13557 /* We added two extra opcode bytes, and have a two byte
13559 fragP
->fr_fix
+= 2 + 2;
13560 fix_new (fragP
, old_fr_fix
+ 2, 2,
13562 fragP
->fr_offset
, 1,
13566 /* Fall through. */
13569 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13571 fragP
->fr_fix
+= 1;
13572 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13574 fragP
->fr_offset
, 1,
13575 BFD_RELOC_8_PCREL
);
13576 fixP
->fx_signed
= 1;
13580 /* This changes the byte-displacement jump 0x7N
13581 to the (d)word-displacement jump 0x0f,0x8N. */
13582 opcode
[1] = opcode
[0] + 0x10;
13583 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13584 /* We've added an opcode byte. */
13585 fragP
->fr_fix
+= 1 + size
;
13586 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13588 fragP
->fr_offset
, 1,
13593 BAD_CASE (fragP
->fr_subtype
);
13597 /* All jumps handled here are signed, but don't unconditionally use a
13598 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13599 around at 4G (outside of 64-bit mode) and 64k. */
13600 if (size
== 4 && flag_code
== CODE_64BIT
)
13601 fixP
->fx_signed
= 1;
13604 return fragP
->fr_fix
- old_fr_fix
;
13607 /* Guess size depending on current relax state. Initially the relax
13608 state will correspond to a short jump and we return 1, because
13609 the variable part of the frag (the branch offset) is one byte
13610 long. However, we can relax a section more than once and in that
13611 case we must either set fr_subtype back to the unrelaxed state,
13612 or return the value for the appropriate branch. */
13613 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13616 /* Called after relax() is finished.
13618 In: Address of frag.
13619 fr_type == rs_machine_dependent.
13620 fr_subtype is what the address relaxed to.
13622 Out: Any fixSs and constants are set up.
13623 Caller will turn frag into a ".space 0". */
13626 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13629 unsigned char *opcode
;
13630 unsigned char *where_to_put_displacement
= NULL
;
13631 offsetT target_address
;
13632 offsetT opcode_address
;
13633 unsigned int extension
= 0;
13634 offsetT displacement_from_opcode_start
;
13636 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13637 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13638 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13640 /* Generate nop padding. */
13641 unsigned int size
= fragP
->tc_frag_data
.length
;
13644 if (size
> fragP
->tc_frag_data
.max_bytes
)
13650 const char *branch
= "branch";
13651 const char *prefix
= "";
13652 fragS
*padding_fragP
;
13653 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13656 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13657 switch (fragP
->tc_frag_data
.default_prefix
)
13662 case CS_PREFIX_OPCODE
:
13665 case DS_PREFIX_OPCODE
:
13668 case ES_PREFIX_OPCODE
:
13671 case FS_PREFIX_OPCODE
:
13674 case GS_PREFIX_OPCODE
:
13677 case SS_PREFIX_OPCODE
:
13682 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13683 "%s within %d-byte boundary\n");
13685 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13686 "align %s within %d-byte boundary\n");
13690 padding_fragP
= fragP
;
13691 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13692 "%s within %d-byte boundary\n");
13696 switch (padding_fragP
->tc_frag_data
.branch_type
)
13698 case align_branch_jcc
:
13701 case align_branch_fused
:
13702 branch
= "fused jcc";
13704 case align_branch_jmp
:
13707 case align_branch_call
:
13710 case align_branch_indirect
:
13711 branch
= "indiret branch";
13713 case align_branch_ret
:
13720 fprintf (stdout
, msg
,
13721 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13722 (long long) fragP
->fr_address
, branch
,
13723 1 << align_branch_power
);
13725 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13726 memset (fragP
->fr_opcode
,
13727 fragP
->tc_frag_data
.default_prefix
, size
);
13729 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13731 fragP
->fr_fix
+= size
;
13736 opcode
= (unsigned char *) fragP
->fr_opcode
;
13738 /* Address we want to reach in file space. */
13739 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13741 /* Address opcode resides at in file space. */
13742 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13744 /* Displacement from opcode start to fill into instruction. */
13745 displacement_from_opcode_start
= target_address
- opcode_address
;
13747 if ((fragP
->fr_subtype
& BIG
) == 0)
13749 /* Don't have to change opcode. */
13750 extension
= 1; /* 1 opcode + 1 displacement */
13751 where_to_put_displacement
= &opcode
[1];
13755 if (no_cond_jump_promotion
13756 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13757 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13758 _("long jump required"));
13760 switch (fragP
->fr_subtype
)
13762 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13763 extension
= 4; /* 1 opcode + 4 displacement */
13765 where_to_put_displacement
= &opcode
[1];
13768 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13769 extension
= 2; /* 1 opcode + 2 displacement */
13771 where_to_put_displacement
= &opcode
[1];
13774 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13775 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13776 extension
= 5; /* 2 opcode + 4 displacement */
13777 opcode
[1] = opcode
[0] + 0x10;
13778 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13779 where_to_put_displacement
= &opcode
[2];
13782 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13783 extension
= 3; /* 2 opcode + 2 displacement */
13784 opcode
[1] = opcode
[0] + 0x10;
13785 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13786 where_to_put_displacement
= &opcode
[2];
13789 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13794 where_to_put_displacement
= &opcode
[3];
13798 BAD_CASE (fragP
->fr_subtype
);
13803 /* If size if less then four we are sure that the operand fits,
13804 but if it's 4, then it could be that the displacement is larger
13806 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13808 && ((addressT
) (displacement_from_opcode_start
- extension
13809 + ((addressT
) 1 << 31))
13810 > (((addressT
) 2 << 31) - 1)))
13812 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13813 _("jump target out of range"));
13814 /* Make us emit 0. */
13815 displacement_from_opcode_start
= extension
;
13817 /* Now put displacement after opcode. */
13818 md_number_to_chars ((char *) where_to_put_displacement
,
13819 (valueT
) (displacement_from_opcode_start
- extension
),
13820 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13821 fragP
->fr_fix
+= extension
;
13824 /* Apply a fixup (fixP) to segment data, once it has been determined
13825 by our caller that we have all the info we need to fix it up.
13827 Parameter valP is the pointer to the value of the bits.
13829 On the 386, immediates, displacements, and data pointers are all in
13830 the same (little-endian) format, so we don't need to care about which
13831 we are handling. */
13834 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13836 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13837 valueT value
= *valP
;
13839 #if !defined (TE_Mach)
13840 if (fixP
->fx_pcrel
)
13842 switch (fixP
->fx_r_type
)
13848 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13851 case BFD_RELOC_X86_64_32S
:
13852 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13855 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13858 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13863 if (fixP
->fx_addsy
!= NULL
13864 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13865 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13866 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13867 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13868 && !use_rela_relocations
)
13870 /* This is a hack. There should be a better way to handle this.
13871 This covers for the fact that bfd_install_relocation will
13872 subtract the current location (for partial_inplace, PC relative
13873 relocations); see more below. */
13877 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13880 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13885 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13887 if ((sym_seg
== seg
13888 || (symbol_section_p (fixP
->fx_addsy
)
13889 && sym_seg
!= absolute_section
))
13890 && !generic_force_reloc (fixP
))
13892 /* Yes, we add the values in twice. This is because
13893 bfd_install_relocation subtracts them out again. I think
13894 bfd_install_relocation is broken, but I don't dare change
13896 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13900 #if defined (OBJ_COFF) && defined (TE_PE)
13901 /* For some reason, the PE format does not store a
13902 section address offset for a PC relative symbol. */
13903 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13904 || S_IS_WEAK (fixP
->fx_addsy
))
13905 value
+= md_pcrel_from (fixP
);
13908 #if defined (OBJ_COFF) && defined (TE_PE)
13909 if (fixP
->fx_addsy
!= NULL
13910 && S_IS_WEAK (fixP
->fx_addsy
)
13911 /* PR 16858: Do not modify weak function references. */
13912 && ! fixP
->fx_pcrel
)
13914 #if !defined (TE_PEP)
13915 /* For x86 PE weak function symbols are neither PC-relative
13916 nor do they set S_IS_FUNCTION. So the only reliable way
13917 to detect them is to check the flags of their containing
13919 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13920 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13924 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13928 /* Fix a few things - the dynamic linker expects certain values here,
13929 and we must not disappoint it. */
13930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13931 if (IS_ELF
&& fixP
->fx_addsy
)
13932 switch (fixP
->fx_r_type
)
13934 case BFD_RELOC_386_PLT32
:
13935 case BFD_RELOC_X86_64_PLT32
:
13936 /* Make the jump instruction point to the address of the operand.
13937 At runtime we merely add the offset to the actual PLT entry.
13938 NB: Subtract the offset size only for jump instructions. */
13939 if (fixP
->fx_pcrel
)
13943 case BFD_RELOC_386_TLS_GD
:
13944 case BFD_RELOC_386_TLS_LDM
:
13945 case BFD_RELOC_386_TLS_IE_32
:
13946 case BFD_RELOC_386_TLS_IE
:
13947 case BFD_RELOC_386_TLS_GOTIE
:
13948 case BFD_RELOC_386_TLS_GOTDESC
:
13949 case BFD_RELOC_X86_64_TLSGD
:
13950 case BFD_RELOC_X86_64_TLSLD
:
13951 case BFD_RELOC_X86_64_GOTTPOFF
:
13952 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13953 value
= 0; /* Fully resolved at runtime. No addend. */
13955 case BFD_RELOC_386_TLS_LE
:
13956 case BFD_RELOC_386_TLS_LDO_32
:
13957 case BFD_RELOC_386_TLS_LE_32
:
13958 case BFD_RELOC_X86_64_DTPOFF32
:
13959 case BFD_RELOC_X86_64_DTPOFF64
:
13960 case BFD_RELOC_X86_64_TPOFF32
:
13961 case BFD_RELOC_X86_64_TPOFF64
:
13962 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13965 case BFD_RELOC_386_TLS_DESC_CALL
:
13966 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13967 value
= 0; /* Fully resolved at runtime. No addend. */
13968 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13972 case BFD_RELOC_VTABLE_INHERIT
:
13973 case BFD_RELOC_VTABLE_ENTRY
:
13980 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13982 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13984 value
= extend_to_32bit_address (value
);
13987 #endif /* !defined (TE_Mach) */
13989 /* Are we finished with this relocation now? */
13990 if (fixP
->fx_addsy
== NULL
)
13993 switch (fixP
->fx_r_type
)
13995 case BFD_RELOC_X86_64_32S
:
13996 fixP
->fx_signed
= 1;
14003 #if defined (OBJ_COFF) && defined (TE_PE)
14004 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
14007 /* Remember value for tc_gen_reloc. */
14008 fixP
->fx_addnumber
= value
;
14009 /* Clear out the frag for now. */
14013 else if (use_rela_relocations
)
14015 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14016 fixP
->fx_no_overflow
= 1;
14017 /* Remember value for tc_gen_reloc. */
14018 fixP
->fx_addnumber
= value
;
14022 md_number_to_chars (p
, value
, fixP
->fx_size
);
14026 md_atof (int type
, char *litP
, int *sizeP
)
14028 /* This outputs the LITTLENUMs in REVERSE order;
14029 in accord with the bigendian 386. */
14030 return ieee_md_atof (type
, litP
, sizeP
, false);
14033 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14036 output_invalid (int c
)
14039 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14042 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14043 "(0x%x)", (unsigned char) c
);
14044 return output_invalid_buf
;
14047 /* Verify that @r can be used in the current context. */
14049 static bool check_register (const reg_entry
*r
)
14051 if (allow_pseudo_reg
)
14054 if (operand_type_all_zero (&r
->reg_type
))
14057 if ((r
->reg_type
.bitfield
.dword
14058 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14059 || r
->reg_type
.bitfield
.class == RegCR
14060 || r
->reg_type
.bitfield
.class == RegDR
)
14061 && !cpu_arch_flags
.bitfield
.cpui386
)
14064 if (r
->reg_type
.bitfield
.class == RegTR
14065 && (flag_code
== CODE_64BIT
14066 || !cpu_arch_flags
.bitfield
.cpui386
14067 || cpu_arch_isa_flags
.bitfield
.cpui586
14068 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14071 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14074 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14076 if (r
->reg_type
.bitfield
.zmmword
14077 || r
->reg_type
.bitfield
.class == RegMask
)
14080 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14082 if (r
->reg_type
.bitfield
.ymmword
)
14085 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14090 if (r
->reg_type
.bitfield
.zmmword
)
14092 if (vector_size
< VSZ512
)
14095 if (i
.vec_encoding
== vex_encoding_default
)
14096 i
.vec_encoding
= vex_encoding_evex512
;
14097 else if (i
.vec_encoding
!= vex_encoding_evex
14098 && i
.vec_encoding
!= vex_encoding_evex512
)
14099 i
.vec_encoding
= vex_encoding_error
;
14102 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14105 if (r
->reg_type
.bitfield
.tmmword
14106 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14107 || flag_code
!= CODE_64BIT
))
14110 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14113 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14114 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14117 /* Upper 16 vector registers are only available with VREX in 64bit
14118 mode, and require EVEX encoding. */
14119 if (r
->reg_flags
& RegVRex
)
14121 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14122 || flag_code
!= CODE_64BIT
)
14125 if (i
.vec_encoding
== vex_encoding_default
14126 || i
.vec_encoding
== vex_encoding_evex512
)
14127 i
.vec_encoding
= vex_encoding_evex
;
14128 else if (i
.vec_encoding
!= vex_encoding_evex
)
14129 i
.vec_encoding
= vex_encoding_error
;
14132 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14133 && (!cpu_arch_flags
.bitfield
.cpu64
14134 || r
->reg_type
.bitfield
.class != RegCR
14136 && flag_code
!= CODE_64BIT
)
14139 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14146 /* REG_STRING starts *before* REGISTER_PREFIX. */
14148 static const reg_entry
*
14149 parse_real_register (const char *reg_string
, char **end_op
)
14151 const char *s
= reg_string
;
14153 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14154 const reg_entry
*r
;
14156 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14157 if (*s
== REGISTER_PREFIX
)
14160 if (is_space_char (*s
))
14163 p
= reg_name_given
;
14164 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14166 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14167 return (const reg_entry
*) NULL
;
14171 if (is_part_of_name (*s
))
14172 return (const reg_entry
*) NULL
;
14174 *end_op
= (char *) s
;
14176 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14178 /* Handle floating point regs, allowing spaces in the (i) part. */
14181 if (!cpu_arch_flags
.bitfield
.cpu8087
14182 && !cpu_arch_flags
.bitfield
.cpu287
14183 && !cpu_arch_flags
.bitfield
.cpu387
14184 && !allow_pseudo_reg
)
14185 return (const reg_entry
*) NULL
;
14187 if (is_space_char (*s
))
14192 if (is_space_char (*s
))
14194 if (*s
>= '0' && *s
<= '7')
14196 int fpr
= *s
- '0';
14198 if (is_space_char (*s
))
14202 *end_op
= (char *) s
+ 1;
14203 know (r
[fpr
].reg_num
== fpr
);
14207 /* We have "%st(" then garbage. */
14208 return (const reg_entry
*) NULL
;
14212 return r
&& check_register (r
) ? r
: NULL
;
14215 /* REG_STRING starts *before* REGISTER_PREFIX. */
14217 static const reg_entry
*
14218 parse_register (const char *reg_string
, char **end_op
)
14220 const reg_entry
*r
;
14222 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14223 r
= parse_real_register (reg_string
, end_op
);
14228 char *save
= input_line_pointer
;
14229 char *buf
= xstrdup (reg_string
), *name
;
14232 input_line_pointer
= buf
;
14233 get_symbol_name (&name
);
14234 symbolP
= symbol_find (name
);
14235 while (symbolP
&& symbol_equated_p (symbolP
))
14237 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14239 if (e
->X_add_number
)
14241 symbolP
= e
->X_add_symbol
;
14243 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14245 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14247 if (e
->X_op
== O_register
)
14249 know (e
->X_add_number
>= 0
14250 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14251 r
= i386_regtab
+ e
->X_add_number
;
14252 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14254 if (r
&& !check_register (r
))
14256 as_bad (_("register '%s%s' cannot be used here"),
14257 register_prefix
, r
->reg_name
);
14261 input_line_pointer
= save
;
14268 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14270 const reg_entry
*r
= NULL
;
14271 char *end
= input_line_pointer
;
14273 /* We only know the terminating character here. It being double quote could
14274 be the closing one of a quoted symbol name, or an opening one from a
14275 following string (or another quoted symbol name). Since the latter can't
14276 be valid syntax for anything, bailing in either case is good enough. */
14277 if (*nextcharP
== '"')
14281 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14282 r
= parse_real_register (name
, &input_line_pointer
);
14283 if (r
&& end
<= input_line_pointer
)
14285 *nextcharP
= *input_line_pointer
;
14286 *input_line_pointer
= 0;
14287 e
->X_op
= O_register
;
14288 e
->X_add_number
= r
- i386_regtab
;
14291 input_line_pointer
= end
;
14293 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14297 md_operand (expressionS
*e
)
14300 const reg_entry
*r
;
14302 switch (*input_line_pointer
)
14304 case REGISTER_PREFIX
:
14305 r
= parse_real_register (input_line_pointer
, &end
);
14308 e
->X_op
= O_register
;
14309 e
->X_add_number
= r
- i386_regtab
;
14310 input_line_pointer
= end
;
14315 gas_assert (intel_syntax
);
14316 end
= input_line_pointer
++;
14318 if (*input_line_pointer
== ']')
14320 ++input_line_pointer
;
14321 e
->X_op_symbol
= make_expr_symbol (e
);
14322 e
->X_add_symbol
= NULL
;
14323 e
->X_add_number
= 0;
14328 e
->X_op
= O_absent
;
14329 input_line_pointer
= end
;
14336 /* To maintain consistency with !BFD64 builds of gas record, whether any
14337 (binary) operator was involved in an expression. As expressions are
14338 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14339 truncate results. */
14340 bool i386_record_operator (operatorT op
,
14341 const expressionS
*left
,
14342 const expressionS
*right
)
14344 if (op
== O_absent
)
14349 /* Since the expression parser applies unary operators fine to bignum
14350 operands, we don't need to be concerned of respective operands not
14351 fitting in 32 bits. */
14352 if (right
->X_op
== O_constant
&& right
->X_unsigned
14353 && !fits_in_unsigned_long (right
->X_add_number
))
14356 /* This isn't entirely right: The pattern can also result when constant
14357 expressions are folded (e.g. 0xffffffff + 1). */
14358 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14359 && !fits_in_unsigned_long (left
->X_add_number
))
14360 || (right
->X_op
== O_constant
&& right
->X_unsigned
14361 && !fits_in_unsigned_long (right
->X_add_number
)))
14362 expr_mode
= expr_large_value
;
14364 if (expr_mode
!= expr_large_value
)
14365 expr_mode
= expr_operator_present
;
14371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14372 const char *md_shortopts
= "kVQ:sqnO::";
14374 const char *md_shortopts
= "qnO::";
14377 #define OPTION_32 (OPTION_MD_BASE + 0)
14378 #define OPTION_64 (OPTION_MD_BASE + 1)
14379 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14380 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14381 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14382 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14383 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14384 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14385 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14386 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14387 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14388 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14389 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14390 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14391 #define OPTION_X32 (OPTION_MD_BASE + 14)
14392 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14393 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14394 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14395 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14396 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14397 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14398 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14399 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14400 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14401 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14402 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14403 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14404 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14405 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14406 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14407 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14408 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14409 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14410 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14411 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14413 struct option md_longopts
[] =
14415 {"32", no_argument
, NULL
, OPTION_32
},
14416 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14417 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14418 {"64", no_argument
, NULL
, OPTION_64
},
14420 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14421 {"x32", no_argument
, NULL
, OPTION_X32
},
14422 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14423 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14425 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14426 {"march", required_argument
, NULL
, OPTION_MARCH
},
14427 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14428 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14429 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14430 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14431 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14432 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14433 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14434 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14435 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14436 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14437 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14438 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14439 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14440 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14441 # if defined (TE_PE) || defined (TE_PEP)
14442 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14444 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14445 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14446 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14447 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14448 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14449 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14450 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14451 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14452 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14453 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14454 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14455 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14456 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14457 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14458 {NULL
, no_argument
, NULL
, 0}
14460 size_t md_longopts_size
= sizeof (md_longopts
);
14463 md_parse_option (int c
, const char *arg
)
14466 char *arch
, *next
, *saved
, *type
;
14471 optimize_align_code
= 0;
14475 quiet_warnings
= 1;
14478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14479 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14480 should be emitted or not. FIXME: Not implemented. */
14482 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14486 /* -V: SVR4 argument to print version ID. */
14488 print_version_id ();
14491 /* -k: Ignore for FreeBSD compatibility. */
14496 /* -s: On i386 Solaris, this tells the native assembler to use
14497 .stab instead of .stab.excl. We always use .stab anyhow. */
14500 case OPTION_MSHARED
:
14504 case OPTION_X86_USED_NOTE
:
14505 if (strcasecmp (arg
, "yes") == 0)
14507 else if (strcasecmp (arg
, "no") == 0)
14510 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14515 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14516 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14519 const char **list
, **l
;
14521 list
= bfd_target_list ();
14522 for (l
= list
; *l
!= NULL
; l
++)
14523 if (startswith (*l
, "elf64-x86-64")
14524 || strcmp (*l
, "coff-x86-64") == 0
14525 || strcmp (*l
, "pe-x86-64") == 0
14526 || strcmp (*l
, "pei-x86-64") == 0
14527 || strcmp (*l
, "mach-o-x86-64") == 0)
14529 default_arch
= "x86_64";
14533 as_fatal (_("no compiled in support for x86_64"));
14539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14543 const char **list
, **l
;
14545 list
= bfd_target_list ();
14546 for (l
= list
; *l
!= NULL
; l
++)
14547 if (startswith (*l
, "elf32-x86-64"))
14549 default_arch
= "x86_64:32";
14553 as_fatal (_("no compiled in support for 32bit x86_64"));
14557 as_fatal (_("32bit x86_64 is only supported for ELF"));
14563 const char **list
, **l
;
14565 list
= bfd_target_list ();
14566 for (l
= list
; *l
!= NULL
; l
++)
14567 if (strstr (*l
, "-i386")
14568 || strstr (*l
, "-go32"))
14570 default_arch
= "i386";
14574 as_fatal (_("no compiled in support for ix86"));
14579 case OPTION_DIVIDE
:
14580 #ifdef SVR4_COMMENT_CHARS
14585 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14587 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14591 i386_comment_chars
= n
;
14597 saved
= xstrdup (arg
);
14599 /* Allow -march=+nosse. */
14607 as_fatal (_("invalid -march= option: `%s'"), arg
);
14608 next
= strchr (arch
, '+');
14611 vsz
= strchr (arch
, '/');
14614 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14616 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14619 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14620 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14623 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14626 cpu_arch_name
= cpu_arch
[j
].name
;
14627 free (cpu_sub_arch_name
);
14628 cpu_sub_arch_name
= NULL
;
14629 cpu_arch_flags
= cpu_arch
[j
].enable
;
14630 cpu_arch_isa
= cpu_arch
[j
].type
;
14631 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14632 if (!cpu_arch_tune_set
)
14633 cpu_arch_tune
= cpu_arch_isa
;
14634 vector_size
= VSZ_DEFAULT
;
14637 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14638 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14639 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14641 /* ISA extension. */
14644 switch (cpu_arch
[j
].vsz
)
14653 unsigned long val
= strtoul (vsz
, &end
, 0);
14659 case 512: vector_size
= VSZ512
; break;
14660 case 256: vector_size
= VSZ256
; break;
14661 case 128: vector_size
= VSZ128
; break;
14663 as_warn (_("Unrecognized vector size specifier ignored"));
14668 /* Fall through. */
14670 vector_size
= VSZ_DEFAULT
;
14678 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14680 /* Disable an ISA extension. */
14681 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14682 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14683 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14686 if (cpu_arch
[j
].vsz
== vsz_set
)
14687 vector_size
= VSZ_DEFAULT
;
14692 if (j
>= ARRAY_SIZE (cpu_arch
))
14693 as_fatal (_("invalid -march= option: `%s'"), arg
);
14697 while (next
!= NULL
);
14703 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14704 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14706 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14707 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14709 cpu_arch_tune_set
= 1;
14710 cpu_arch_tune
= cpu_arch
[j
].type
;
14714 if (j
>= ARRAY_SIZE (cpu_arch
))
14715 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14718 case OPTION_MMNEMONIC
:
14719 if (strcasecmp (arg
, "att") == 0)
14720 intel_mnemonic
= 0;
14721 else if (strcasecmp (arg
, "intel") == 0)
14722 intel_mnemonic
= 1;
14724 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14727 case OPTION_MSYNTAX
:
14728 if (strcasecmp (arg
, "att") == 0)
14730 else if (strcasecmp (arg
, "intel") == 0)
14733 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14736 case OPTION_MINDEX_REG
:
14737 allow_index_reg
= 1;
14740 case OPTION_MNAKED_REG
:
14741 allow_naked_reg
= 1;
14744 case OPTION_MSSE2AVX
:
14748 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14749 use_unaligned_vector_move
= 1;
14752 case OPTION_MSSE_CHECK
:
14753 if (strcasecmp (arg
, "error") == 0)
14754 sse_check
= check_error
;
14755 else if (strcasecmp (arg
, "warning") == 0)
14756 sse_check
= check_warning
;
14757 else if (strcasecmp (arg
, "none") == 0)
14758 sse_check
= check_none
;
14760 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14763 case OPTION_MOPERAND_CHECK
:
14764 if (strcasecmp (arg
, "error") == 0)
14765 operand_check
= check_error
;
14766 else if (strcasecmp (arg
, "warning") == 0)
14767 operand_check
= check_warning
;
14768 else if (strcasecmp (arg
, "none") == 0)
14769 operand_check
= check_none
;
14771 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14774 case OPTION_MAVXSCALAR
:
14775 if (strcasecmp (arg
, "128") == 0)
14776 avxscalar
= vex128
;
14777 else if (strcasecmp (arg
, "256") == 0)
14778 avxscalar
= vex256
;
14780 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14783 case OPTION_MVEXWIG
:
14784 if (strcmp (arg
, "0") == 0)
14786 else if (strcmp (arg
, "1") == 0)
14789 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14792 case OPTION_MADD_BND_PREFIX
:
14793 add_bnd_prefix
= 1;
14796 case OPTION_MEVEXLIG
:
14797 if (strcmp (arg
, "128") == 0)
14798 evexlig
= evexl128
;
14799 else if (strcmp (arg
, "256") == 0)
14800 evexlig
= evexl256
;
14801 else if (strcmp (arg
, "512") == 0)
14802 evexlig
= evexl512
;
14804 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14807 case OPTION_MEVEXRCIG
:
14808 if (strcmp (arg
, "rne") == 0)
14810 else if (strcmp (arg
, "rd") == 0)
14812 else if (strcmp (arg
, "ru") == 0)
14814 else if (strcmp (arg
, "rz") == 0)
14817 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14820 case OPTION_MEVEXWIG
:
14821 if (strcmp (arg
, "0") == 0)
14823 else if (strcmp (arg
, "1") == 0)
14826 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14829 # if defined (TE_PE) || defined (TE_PEP)
14830 case OPTION_MBIG_OBJ
:
14835 case OPTION_MOMIT_LOCK_PREFIX
:
14836 if (strcasecmp (arg
, "yes") == 0)
14837 omit_lock_prefix
= 1;
14838 else if (strcasecmp (arg
, "no") == 0)
14839 omit_lock_prefix
= 0;
14841 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14844 case OPTION_MFENCE_AS_LOCK_ADD
:
14845 if (strcasecmp (arg
, "yes") == 0)
14847 else if (strcasecmp (arg
, "no") == 0)
14850 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14853 case OPTION_MLFENCE_AFTER_LOAD
:
14854 if (strcasecmp (arg
, "yes") == 0)
14855 lfence_after_load
= 1;
14856 else if (strcasecmp (arg
, "no") == 0)
14857 lfence_after_load
= 0;
14859 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14862 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14863 if (strcasecmp (arg
, "all") == 0)
14865 lfence_before_indirect_branch
= lfence_branch_all
;
14866 if (lfence_before_ret
== lfence_before_ret_none
)
14867 lfence_before_ret
= lfence_before_ret_shl
;
14869 else if (strcasecmp (arg
, "memory") == 0)
14870 lfence_before_indirect_branch
= lfence_branch_memory
;
14871 else if (strcasecmp (arg
, "register") == 0)
14872 lfence_before_indirect_branch
= lfence_branch_register
;
14873 else if (strcasecmp (arg
, "none") == 0)
14874 lfence_before_indirect_branch
= lfence_branch_none
;
14876 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14880 case OPTION_MLFENCE_BEFORE_RET
:
14881 if (strcasecmp (arg
, "or") == 0)
14882 lfence_before_ret
= lfence_before_ret_or
;
14883 else if (strcasecmp (arg
, "not") == 0)
14884 lfence_before_ret
= lfence_before_ret_not
;
14885 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14886 lfence_before_ret
= lfence_before_ret_shl
;
14887 else if (strcasecmp (arg
, "none") == 0)
14888 lfence_before_ret
= lfence_before_ret_none
;
14890 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14894 case OPTION_MRELAX_RELOCATIONS
:
14895 if (strcasecmp (arg
, "yes") == 0)
14896 generate_relax_relocations
= 1;
14897 else if (strcasecmp (arg
, "no") == 0)
14898 generate_relax_relocations
= 0;
14900 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14903 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14906 long int align
= strtoul (arg
, &end
, 0);
14911 align_branch_power
= 0;
14914 else if (align
>= 16)
14917 for (align_power
= 0;
14919 align
>>= 1, align_power
++)
14921 /* Limit alignment power to 31. */
14922 if (align
== 1 && align_power
< 32)
14924 align_branch_power
= align_power
;
14929 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14933 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14936 int align
= strtoul (arg
, &end
, 0);
14937 /* Some processors only support 5 prefixes. */
14938 if (*end
== '\0' && align
>= 0 && align
< 6)
14940 align_branch_prefix_size
= align
;
14943 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14948 case OPTION_MALIGN_BRANCH
:
14950 saved
= xstrdup (arg
);
14954 next
= strchr (type
, '+');
14957 if (strcasecmp (type
, "jcc") == 0)
14958 align_branch
|= align_branch_jcc_bit
;
14959 else if (strcasecmp (type
, "fused") == 0)
14960 align_branch
|= align_branch_fused_bit
;
14961 else if (strcasecmp (type
, "jmp") == 0)
14962 align_branch
|= align_branch_jmp_bit
;
14963 else if (strcasecmp (type
, "call") == 0)
14964 align_branch
|= align_branch_call_bit
;
14965 else if (strcasecmp (type
, "ret") == 0)
14966 align_branch
|= align_branch_ret_bit
;
14967 else if (strcasecmp (type
, "indirect") == 0)
14968 align_branch
|= align_branch_indirect_bit
;
14970 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14973 while (next
!= NULL
);
14977 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14978 align_branch_power
= 5;
14979 align_branch_prefix_size
= 5;
14980 align_branch
= (align_branch_jcc_bit
14981 | align_branch_fused_bit
14982 | align_branch_jmp_bit
);
14985 case OPTION_MAMD64
:
14989 case OPTION_MINTEL64
:
14997 /* Turn off -Os. */
14998 optimize_for_space
= 0;
15000 else if (*arg
== 's')
15002 optimize_for_space
= 1;
15003 /* Turn on all encoding optimizations. */
15004 optimize
= INT_MAX
;
15008 optimize
= atoi (arg
);
15009 /* Turn off -Os. */
15010 optimize_for_space
= 0;
15020 #define MESSAGE_TEMPLATE \
15024 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15025 int *left_p
, const char *name
, int len
)
15027 int size
= sizeof (MESSAGE_TEMPLATE
);
15028 int left
= *left_p
;
15030 /* Reserve 2 spaces for ", " or ",\0" */
15033 /* Check if there is any room. */
15041 p
= mempcpy (p
, name
, len
);
15045 /* Output the current message now and start a new one. */
15048 fprintf (stream
, "%s\n", message
);
15050 left
= size
- (start
- message
) - len
- 2;
15052 gas_assert (left
>= 0);
15054 p
= mempcpy (p
, name
, len
);
15062 show_arch (FILE *stream
, int ext
, int check
)
15064 static char message
[] = MESSAGE_TEMPLATE
;
15065 char *start
= message
+ 27;
15067 int size
= sizeof (MESSAGE_TEMPLATE
);
15074 left
= size
- (start
- message
);
15078 p
= output_message (stream
, p
, message
, start
, &left
,
15079 STRING_COMMA_LEN ("default"));
15080 p
= output_message (stream
, p
, message
, start
, &left
,
15081 STRING_COMMA_LEN ("push"));
15082 p
= output_message (stream
, p
, message
, start
, &left
,
15083 STRING_COMMA_LEN ("pop"));
15086 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15088 /* Should it be skipped? */
15089 if (cpu_arch
[j
].skip
)
15092 name
= cpu_arch
[j
].name
;
15093 len
= cpu_arch
[j
].len
;
15094 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15096 /* It is an extension. Skip if we aren't asked to show it. */
15097 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15102 /* It is an processor. Skip if we show only extension. */
15105 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15107 /* It is an impossible processor - skip. */
15111 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15114 /* Display disabled extensions. */
15116 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15120 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15121 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15123 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15124 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15130 fprintf (stream
, "%s\n", message
);
15134 md_show_usage (FILE *stream
)
15136 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15137 fprintf (stream
, _("\
15138 -Qy, -Qn ignored\n\
15139 -V print assembler version number\n\
15142 fprintf (stream
, _("\
15143 -n do not optimize code alignment\n\
15144 -O{012s} attempt some code optimizations\n\
15145 -q quieten some warnings\n"));
15146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15147 fprintf (stream
, _("\
15151 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15152 fprintf (stream
, _("\
15153 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15154 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15155 fprintf (stream
, _("\
15156 --32/--64 generate 32bit/64bit object\n"));
15159 #ifdef SVR4_COMMENT_CHARS
15160 fprintf (stream
, _("\
15161 --divide do not treat `/' as a comment character\n"));
15163 fprintf (stream
, _("\
15164 --divide ignored\n"));
15166 fprintf (stream
, _("\
15167 -march=CPU[,+EXTENSION...]\n\
15168 generate code for CPU and EXTENSION, CPU is one of:\n"));
15169 show_arch (stream
, 0, 1);
15170 fprintf (stream
, _("\
15171 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15172 show_arch (stream
, 1, 0);
15173 fprintf (stream
, _("\
15174 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15175 show_arch (stream
, 0, 0);
15176 fprintf (stream
, _("\
15177 -msse2avx encode SSE instructions with VEX prefix\n"));
15178 fprintf (stream
, _("\
15179 -muse-unaligned-vector-move\n\
15180 encode aligned vector move as unaligned vector move\n"));
15181 fprintf (stream
, _("\
15182 -msse-check=[none|error|warning] (default: warning)\n\
15183 check SSE instructions\n"));
15184 fprintf (stream
, _("\
15185 -moperand-check=[none|error|warning] (default: warning)\n\
15186 check operand combinations for validity\n"));
15187 fprintf (stream
, _("\
15188 -mavxscalar=[128|256] (default: 128)\n\
15189 encode scalar AVX instructions with specific vector\n\
15191 fprintf (stream
, _("\
15192 -mvexwig=[0|1] (default: 0)\n\
15193 encode VEX instructions with specific VEX.W value\n\
15194 for VEX.W bit ignored instructions\n"));
15195 fprintf (stream
, _("\
15196 -mevexlig=[128|256|512] (default: 128)\n\
15197 encode scalar EVEX instructions with specific vector\n\
15199 fprintf (stream
, _("\
15200 -mevexwig=[0|1] (default: 0)\n\
15201 encode EVEX instructions with specific EVEX.W value\n\
15202 for EVEX.W bit ignored instructions\n"));
15203 fprintf (stream
, _("\
15204 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15205 encode EVEX instructions with specific EVEX.RC value\n\
15206 for SAE-only ignored instructions\n"));
15207 fprintf (stream
, _("\
15208 -mmnemonic=[att|intel] "));
15209 if (SYSV386_COMPAT
)
15210 fprintf (stream
, _("(default: att)\n"));
15212 fprintf (stream
, _("(default: intel)\n"));
15213 fprintf (stream
, _("\
15214 use AT&T/Intel mnemonic\n"));
15215 fprintf (stream
, _("\
15216 -msyntax=[att|intel] (default: att)\n\
15217 use AT&T/Intel syntax\n"));
15218 fprintf (stream
, _("\
15219 -mindex-reg support pseudo index registers\n"));
15220 fprintf (stream
, _("\
15221 -mnaked-reg don't require `%%' prefix for registers\n"));
15222 fprintf (stream
, _("\
15223 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15224 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15225 fprintf (stream
, _("\
15226 -mshared disable branch optimization for shared code\n"));
15227 fprintf (stream
, _("\
15228 -mx86-used-note=[no|yes] "));
15229 if (DEFAULT_X86_USED_NOTE
)
15230 fprintf (stream
, _("(default: yes)\n"));
15232 fprintf (stream
, _("(default: no)\n"));
15233 fprintf (stream
, _("\
15234 generate x86 used ISA and feature properties\n"));
15236 #if defined (TE_PE) || defined (TE_PEP)
15237 fprintf (stream
, _("\
15238 -mbig-obj generate big object files\n"));
15240 fprintf (stream
, _("\
15241 -momit-lock-prefix=[no|yes] (default: no)\n\
15242 strip all lock prefixes\n"));
15243 fprintf (stream
, _("\
15244 -mfence-as-lock-add=[no|yes] (default: no)\n\
15245 encode lfence, mfence and sfence as\n\
15246 lock addl $0x0, (%%{re}sp)\n"));
15247 fprintf (stream
, _("\
15248 -mrelax-relocations=[no|yes] "));
15249 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15250 fprintf (stream
, _("(default: yes)\n"));
15252 fprintf (stream
, _("(default: no)\n"));
15253 fprintf (stream
, _("\
15254 generate relax relocations\n"));
15255 fprintf (stream
, _("\
15256 -malign-branch-boundary=NUM (default: 0)\n\
15257 align branches within NUM byte boundary\n"));
15258 fprintf (stream
, _("\
15259 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15260 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15262 specify types of branches to align\n"));
15263 fprintf (stream
, _("\
15264 -malign-branch-prefix-size=NUM (default: 5)\n\
15265 align branches with NUM prefixes per instruction\n"));
15266 fprintf (stream
, _("\
15267 -mbranches-within-32B-boundaries\n\
15268 align branches within 32 byte boundary\n"));
15269 fprintf (stream
, _("\
15270 -mlfence-after-load=[no|yes] (default: no)\n\
15271 generate lfence after load\n"));
15272 fprintf (stream
, _("\
15273 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15274 generate lfence before indirect near branch\n"));
15275 fprintf (stream
, _("\
15276 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15277 generate lfence before ret\n"));
15278 fprintf (stream
, _("\
15279 -mamd64 accept only AMD64 ISA [default]\n"));
15280 fprintf (stream
, _("\
15281 -mintel64 accept only Intel64 ISA\n"));
15284 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15285 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15286 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15288 /* Pick the target format to use. */
15291 i386_target_format (void)
15293 if (startswith (default_arch
, "x86_64"))
15295 update_code_flag (CODE_64BIT
, 1);
15296 if (default_arch
[6] == '\0')
15297 x86_elf_abi
= X86_64_ABI
;
15299 x86_elf_abi
= X86_64_X32_ABI
;
15301 else if (!strcmp (default_arch
, "i386"))
15302 update_code_flag (CODE_32BIT
, 1);
15303 else if (!strcmp (default_arch
, "iamcu"))
15305 update_code_flag (CODE_32BIT
, 1);
15306 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15308 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15309 cpu_arch_name
= "iamcu";
15310 free (cpu_sub_arch_name
);
15311 cpu_sub_arch_name
= NULL
;
15312 cpu_arch_flags
= iamcu_flags
;
15313 cpu_arch_isa
= PROCESSOR_IAMCU
;
15314 cpu_arch_isa_flags
= iamcu_flags
;
15315 if (!cpu_arch_tune_set
)
15316 cpu_arch_tune
= PROCESSOR_IAMCU
;
15318 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15319 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15323 as_fatal (_("unknown architecture"));
15325 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15326 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15328 switch (OUTPUT_FLAVOR
)
15330 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15331 case bfd_target_aout_flavour
:
15332 return AOUT_TARGET_FORMAT
;
15334 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15335 # if defined (TE_PE) || defined (TE_PEP)
15336 case bfd_target_coff_flavour
:
15337 if (flag_code
== CODE_64BIT
)
15340 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15342 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15343 # elif defined (TE_GO32)
15344 case bfd_target_coff_flavour
:
15345 return "coff-go32";
15347 case bfd_target_coff_flavour
:
15348 return "coff-i386";
15351 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15352 case bfd_target_elf_flavour
:
15354 const char *format
;
15356 switch (x86_elf_abi
)
15359 format
= ELF_TARGET_FORMAT
;
15361 tls_get_addr
= "___tls_get_addr";
15365 use_rela_relocations
= 1;
15368 tls_get_addr
= "__tls_get_addr";
15370 format
= ELF_TARGET_FORMAT64
;
15372 case X86_64_X32_ABI
:
15373 use_rela_relocations
= 1;
15376 tls_get_addr
= "__tls_get_addr";
15378 disallow_64bit_reloc
= 1;
15379 format
= ELF_TARGET_FORMAT32
;
15382 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15384 if (x86_elf_abi
!= I386_ABI
)
15385 as_fatal (_("Intel MCU is 32bit only"));
15386 return ELF_TARGET_IAMCU_FORMAT
;
15392 #if defined (OBJ_MACH_O)
15393 case bfd_target_mach_o_flavour
:
15394 if (flag_code
== CODE_64BIT
)
15396 use_rela_relocations
= 1;
15398 return "mach-o-x86-64";
15401 return "mach-o-i386";
15409 #endif /* OBJ_MAYBE_ more than one */
15412 md_undefined_symbol (char *name
)
15414 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15415 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15416 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15417 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15421 if (symbol_find (name
))
15422 as_bad (_("GOT already in symbol table"));
15423 GOT_symbol
= symbol_new (name
, undefined_section
,
15424 &zero_address_frag
, 0);
15431 /* Round up a section size to the appropriate boundary. */
15434 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15436 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15437 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15439 /* For a.out, force the section size to be aligned. If we don't do
15440 this, BFD will align it for us, but it will not write out the
15441 final bytes of the section. This may be a bug in BFD, but it is
15442 easier to fix it here since that is how the other a.out targets
15446 align
= bfd_section_alignment (segment
);
15447 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15454 /* On the i386, PC-relative offsets are relative to the start of the
15455 next instruction. That is, the address of the offset, plus its
15456 size, since the offset is always the last part of the insn. */
15459 md_pcrel_from (fixS
*fixP
)
15461 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15467 s_bss (int ignore ATTRIBUTE_UNUSED
)
15471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15473 obj_elf_section_change_hook ();
15475 temp
= get_absolute_expression ();
15476 subseg_set (bss_section
, (subsegT
) temp
);
15477 demand_empty_rest_of_line ();
15482 /* Remember constant directive. */
15485 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15487 if (last_insn
.kind
!= last_insn_directive
15488 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15490 last_insn
.seg
= now_seg
;
15491 last_insn
.kind
= last_insn_directive
;
15492 last_insn
.name
= "constant directive";
15493 last_insn
.file
= as_where (&last_insn
.line
);
15494 if (lfence_before_ret
!= lfence_before_ret_none
)
15496 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15497 as_warn (_("constant directive skips -mlfence-before-ret "
15498 "and -mlfence-before-indirect-branch"));
15500 as_warn (_("constant directive skips -mlfence-before-ret"));
15502 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15503 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15508 i386_validate_fix (fixS
*fixp
)
15510 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15512 reloc_howto_type
*howto
;
15514 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15515 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15516 _("invalid %s relocation against register"),
15517 howto
? howto
->name
: "<unknown>");
15521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15522 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15523 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15524 return IS_ELF
&& fixp
->fx_addsy
15525 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15526 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15529 if (fixp
->fx_subsy
)
15531 if (fixp
->fx_subsy
== GOT_symbol
)
15533 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15538 if (fixp
->fx_tcbit2
)
15539 fixp
->fx_r_type
= (fixp
->fx_tcbit
15540 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15541 : BFD_RELOC_X86_64_GOTPCRELX
);
15544 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15549 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15551 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15553 fixp
->fx_subsy
= 0;
15556 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15559 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15560 to section. Since PLT32 relocation must be against symbols,
15561 turn such PLT32 relocation into PC32 relocation. */
15563 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15564 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15565 && symbol_section_p (fixp
->fx_addsy
))
15566 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15569 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15570 && fixp
->fx_tcbit2
)
15571 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15580 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15583 bfd_reloc_code_real_type code
;
15585 switch (fixp
->fx_r_type
)
15587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15590 case BFD_RELOC_SIZE32
:
15591 case BFD_RELOC_SIZE64
:
15593 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15594 && (!fixp
->fx_subsy
15595 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15596 sym
= fixp
->fx_addsy
;
15597 else if (fixp
->fx_subsy
15598 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15599 && (!fixp
->fx_addsy
15600 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15601 sym
= fixp
->fx_subsy
;
15604 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15606 /* Resolve size relocation against local symbol to size of
15607 the symbol plus addend. */
15608 valueT value
= S_GET_SIZE (sym
);
15610 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15611 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15612 if (sym
== fixp
->fx_subsy
)
15615 if (fixp
->fx_addsy
)
15616 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15618 else if (fixp
->fx_subsy
)
15619 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15620 value
+= fixp
->fx_offset
;
15621 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15623 && !fits_in_unsigned_long (value
))
15624 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15625 _("symbol size computation overflow"));
15626 fixp
->fx_addsy
= NULL
;
15627 fixp
->fx_subsy
= NULL
;
15628 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15631 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15633 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15634 "unsupported expression involving @size");
15638 /* Fall through. */
15640 case BFD_RELOC_X86_64_PLT32
:
15641 case BFD_RELOC_X86_64_GOT32
:
15642 case BFD_RELOC_X86_64_GOTPCREL
:
15643 case BFD_RELOC_X86_64_GOTPCRELX
:
15644 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15645 case BFD_RELOC_386_PLT32
:
15646 case BFD_RELOC_386_GOT32
:
15647 case BFD_RELOC_386_GOT32X
:
15648 case BFD_RELOC_386_GOTOFF
:
15649 case BFD_RELOC_386_GOTPC
:
15650 case BFD_RELOC_386_TLS_GD
:
15651 case BFD_RELOC_386_TLS_LDM
:
15652 case BFD_RELOC_386_TLS_LDO_32
:
15653 case BFD_RELOC_386_TLS_IE_32
:
15654 case BFD_RELOC_386_TLS_IE
:
15655 case BFD_RELOC_386_TLS_GOTIE
:
15656 case BFD_RELOC_386_TLS_LE_32
:
15657 case BFD_RELOC_386_TLS_LE
:
15658 case BFD_RELOC_386_TLS_GOTDESC
:
15659 case BFD_RELOC_386_TLS_DESC_CALL
:
15660 case BFD_RELOC_X86_64_TLSGD
:
15661 case BFD_RELOC_X86_64_TLSLD
:
15662 case BFD_RELOC_X86_64_DTPOFF32
:
15663 case BFD_RELOC_X86_64_DTPOFF64
:
15664 case BFD_RELOC_X86_64_GOTTPOFF
:
15665 case BFD_RELOC_X86_64_TPOFF32
:
15666 case BFD_RELOC_X86_64_TPOFF64
:
15667 case BFD_RELOC_X86_64_GOTOFF64
:
15668 case BFD_RELOC_X86_64_GOTPC32
:
15669 case BFD_RELOC_X86_64_GOT64
:
15670 case BFD_RELOC_X86_64_GOTPCREL64
:
15671 case BFD_RELOC_X86_64_GOTPC64
:
15672 case BFD_RELOC_X86_64_GOTPLT64
:
15673 case BFD_RELOC_X86_64_PLTOFF64
:
15674 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15675 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15676 case BFD_RELOC_RVA
:
15677 case BFD_RELOC_VTABLE_ENTRY
:
15678 case BFD_RELOC_VTABLE_INHERIT
:
15680 case BFD_RELOC_32_SECREL
:
15681 case BFD_RELOC_16_SECIDX
:
15683 code
= fixp
->fx_r_type
;
15685 case BFD_RELOC_X86_64_32S
:
15686 if (!fixp
->fx_pcrel
)
15688 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15689 code
= fixp
->fx_r_type
;
15692 /* Fall through. */
15694 if (fixp
->fx_pcrel
)
15696 switch (fixp
->fx_size
)
15699 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15700 _("can not do %d byte pc-relative relocation"),
15702 code
= BFD_RELOC_32_PCREL
;
15704 case 1: code
= BFD_RELOC_8_PCREL
; break;
15705 case 2: code
= BFD_RELOC_16_PCREL
; break;
15706 case 4: code
= BFD_RELOC_32_PCREL
; break;
15708 case 8: code
= BFD_RELOC_64_PCREL
; break;
15714 switch (fixp
->fx_size
)
15717 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15718 _("can not do %d byte relocation"),
15720 code
= BFD_RELOC_32
;
15722 case 1: code
= BFD_RELOC_8
; break;
15723 case 2: code
= BFD_RELOC_16
; break;
15724 case 4: code
= BFD_RELOC_32
; break;
15726 case 8: code
= BFD_RELOC_64
; break;
15733 if ((code
== BFD_RELOC_32
15734 || code
== BFD_RELOC_32_PCREL
15735 || code
== BFD_RELOC_X86_64_32S
)
15737 && fixp
->fx_addsy
== GOT_symbol
)
15740 code
= BFD_RELOC_386_GOTPC
;
15742 code
= BFD_RELOC_X86_64_GOTPC32
;
15744 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15746 && fixp
->fx_addsy
== GOT_symbol
)
15748 code
= BFD_RELOC_X86_64_GOTPC64
;
15751 rel
= XNEW (arelent
);
15752 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15753 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15755 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15757 if (!use_rela_relocations
)
15759 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15760 vtable entry to be used in the relocation's section offset. */
15761 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15762 rel
->address
= fixp
->fx_offset
;
15763 #if defined (OBJ_COFF) && defined (TE_PE)
15764 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15765 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15770 /* Use the rela in 64bit mode. */
15773 if (disallow_64bit_reloc
)
15776 case BFD_RELOC_X86_64_DTPOFF64
:
15777 case BFD_RELOC_X86_64_TPOFF64
:
15778 case BFD_RELOC_64_PCREL
:
15779 case BFD_RELOC_X86_64_GOTOFF64
:
15780 case BFD_RELOC_X86_64_GOT64
:
15781 case BFD_RELOC_X86_64_GOTPCREL64
:
15782 case BFD_RELOC_X86_64_GOTPC64
:
15783 case BFD_RELOC_X86_64_GOTPLT64
:
15784 case BFD_RELOC_X86_64_PLTOFF64
:
15785 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15786 _("cannot represent relocation type %s in x32 mode"),
15787 bfd_get_reloc_code_name (code
));
15793 if (!fixp
->fx_pcrel
)
15794 rel
->addend
= fixp
->fx_offset
;
15798 case BFD_RELOC_X86_64_PLT32
:
15799 case BFD_RELOC_X86_64_GOT32
:
15800 case BFD_RELOC_X86_64_GOTPCREL
:
15801 case BFD_RELOC_X86_64_GOTPCRELX
:
15802 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15803 case BFD_RELOC_X86_64_TLSGD
:
15804 case BFD_RELOC_X86_64_TLSLD
:
15805 case BFD_RELOC_X86_64_GOTTPOFF
:
15806 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15807 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15808 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15811 rel
->addend
= (section
->vma
15813 + fixp
->fx_addnumber
15814 + md_pcrel_from (fixp
));
15819 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15820 if (rel
->howto
== NULL
)
15822 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15823 _("cannot represent relocation type %s"),
15824 bfd_get_reloc_code_name (code
));
15825 /* Set howto to a garbage value so that we can keep going. */
15826 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15827 gas_assert (rel
->howto
!= NULL
);
15833 #include "tc-i386-intel.c"
15836 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15838 int saved_naked_reg
;
15839 char saved_register_dot
;
15841 saved_naked_reg
= allow_naked_reg
;
15842 allow_naked_reg
= 1;
15843 saved_register_dot
= register_chars
['.'];
15844 register_chars
['.'] = '.';
15845 allow_pseudo_reg
= 1;
15846 expression_and_evaluate (exp
);
15847 allow_pseudo_reg
= 0;
15848 register_chars
['.'] = saved_register_dot
;
15849 allow_naked_reg
= saved_naked_reg
;
15851 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15853 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15855 exp
->X_op
= O_constant
;
15856 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15857 .dw2_regnum
[flag_code
>> 1];
15860 exp
->X_op
= O_illegal
;
15865 tc_x86_frame_initial_instructions (void)
15867 static unsigned int sp_regno
[2];
15869 if (!sp_regno
[flag_code
>> 1])
15871 char *saved_input
= input_line_pointer
;
15872 char sp
[][4] = {"esp", "rsp"};
15875 input_line_pointer
= sp
[flag_code
>> 1];
15876 tc_x86_parse_to_dw2regnum (&exp
);
15877 gas_assert (exp
.X_op
== O_constant
);
15878 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15879 input_line_pointer
= saved_input
;
15882 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15883 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15887 x86_dwarf2_addr_size (void)
15889 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15890 if (x86_elf_abi
== X86_64_X32_ABI
)
15893 return bfd_arch_bits_per_address (stdoutput
) / 8;
15897 i386_elf_section_type (const char *str
, size_t len
)
15899 if (flag_code
== CODE_64BIT
15900 && len
== sizeof ("unwind") - 1
15901 && startswith (str
, "unwind"))
15902 return SHT_X86_64_UNWIND
;
15909 i386_solaris_fix_up_eh_frame (segT sec
)
15911 if (flag_code
== CODE_64BIT
)
15912 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15918 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15922 exp
.X_op
= O_secrel
;
15923 exp
.X_add_symbol
= symbol
;
15924 exp
.X_add_number
= 0;
15925 emit_expr (&exp
, size
);
15929 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15930 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15933 x86_64_section_letter (int letter
, const char **ptr_msg
)
15935 if (flag_code
== CODE_64BIT
)
15938 return SHF_X86_64_LARGE
;
15940 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15943 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15948 handle_large_common (int small ATTRIBUTE_UNUSED
)
15950 if (flag_code
!= CODE_64BIT
)
15952 s_comm_internal (0, elf_common_parse
);
15953 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15957 static segT lbss_section
;
15958 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15959 asection
*saved_bss_section
= bss_section
;
15961 if (lbss_section
== NULL
)
15963 flagword applicable
;
15964 segT seg
= now_seg
;
15965 subsegT subseg
= now_subseg
;
15967 /* The .lbss section is for local .largecomm symbols. */
15968 lbss_section
= subseg_new (".lbss", 0);
15969 applicable
= bfd_applicable_section_flags (stdoutput
);
15970 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15971 seg_info (lbss_section
)->bss
= 1;
15973 subseg_set (seg
, subseg
);
15976 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15977 bss_section
= lbss_section
;
15979 s_comm_internal (0, elf_common_parse
);
15981 elf_com_section_ptr
= saved_com_section_ptr
;
15982 bss_section
= saved_bss_section
;
15985 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */