1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* ISA extensions available in 64-bit mode only. */
808 static const i386_cpu_flags cpu_64_flags
= CPU_ANY_64_FLAGS
;
810 /* If we have selected a cpu we are generating instructions for. */
811 static int cpu_arch_tune_set
= 0;
813 /* Cpu we are generating instructions for. */
814 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
816 /* CPU instruction set architecture used. */
817 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of instruction set architecture used. */
820 i386_cpu_flags cpu_arch_isa_flags
;
822 /* If set, conditional jumps are not automatically promoted to handle
823 larger than a byte offset. */
824 static bool no_cond_jump_promotion
= false;
826 /* This will be set from an expression parser hook if there's any
827 applicable operator involved in an expression. */
830 expr_operator_present
,
834 /* Encode SSE instructions with VEX prefix. */
835 static unsigned int sse2avx
;
837 /* Encode aligned vector move as unaligned vector move. */
838 static unsigned int use_unaligned_vector_move
;
840 /* Maximum permitted vector size. */
841 #define VSZ_DEFAULT VSZ512
842 static unsigned int vector_size
= VSZ_DEFAULT
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
977 #define VECARCH(n, e, d, v) \
978 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
979 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
981 static const arch_entry cpu_arch
[] =
983 /* Do not replace the first two entries - i386_target_format() and
984 set_cpu_arch() rely on them being there in this order. */
985 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
986 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
987 ARCH (i8086
, UNKNOWN
, NONE
, false),
988 ARCH (i186
, UNKNOWN
, 186, false),
989 ARCH (i286
, UNKNOWN
, 286, false),
990 ARCH (i386
, I386
, 386, false),
991 ARCH (i486
, I486
, 486, false),
992 ARCH (i586
, PENTIUM
, 586, false),
993 ARCH (pentium
, PENTIUM
, 586, false),
994 ARCH (i686
, I686
, 686, false),
995 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
996 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
997 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
998 ARCH (pentium4
, PENTIUM4
, P4
, false),
999 ARCH (prescott
, NOCONA
, CORE
, false),
1000 ARCH (nocona
, NOCONA
, NOCONA
, false),
1001 ARCH (yonah
, CORE
, CORE
, true),
1002 ARCH (core
, CORE
, CORE
, false),
1003 ARCH (merom
, CORE2
, CORE2
, true),
1004 ARCH (core2
, CORE2
, CORE2
, false),
1005 ARCH (corei7
, COREI7
, COREI7
, false),
1006 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1007 ARCH (k6
, K6
, K6
, false),
1008 ARCH (k6_2
, K6
, K6_2
, false),
1009 ARCH (athlon
, ATHLON
, ATHLON
, false),
1010 ARCH (sledgehammer
, K8
, K8
, true),
1011 ARCH (opteron
, K8
, K8
, false),
1012 ARCH (k8
, K8
, K8
, false),
1013 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1014 ARCH (bdver1
, BD
, BDVER1
, false),
1015 ARCH (bdver2
, BD
, BDVER2
, false),
1016 ARCH (bdver3
, BD
, BDVER3
, false),
1017 ARCH (bdver4
, BD
, BDVER4
, false),
1018 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1019 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1020 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1021 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1022 ARCH (btver1
, BT
, BTVER1
, false),
1023 ARCH (btver2
, BT
, BTVER2
, false),
1025 SUBARCH (8087, 8087, ANY_8087
, false),
1026 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1027 SUBARCH (287, 287, ANY_287
, false),
1028 SUBARCH (387, 387, ANY_387
, false),
1029 SUBARCH (687, 687, ANY_687
, false),
1030 SUBARCH (cmov
, CMOV
, CMOV
, false),
1031 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1032 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1033 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1034 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1035 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1036 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1037 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1038 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1039 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1040 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1041 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1042 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1043 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1044 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1045 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1046 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1047 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1048 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1049 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1050 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1051 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1052 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1053 SUBARCH (smx
, SMX
, SMX
, false),
1054 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1055 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1056 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1057 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1058 SUBARCH (aes
, AES
, ANY_AES
, false),
1059 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1060 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1061 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1062 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1063 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1064 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1065 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1066 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1067 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1068 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1069 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1070 SUBARCH (cx16
, CX16
, CX16
, false),
1071 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1072 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1073 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1074 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1075 SUBARCH (hle
, HLE
, HLE
, false),
1076 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1077 SUBARCH (tsx
, TSX
, TSX
, false),
1078 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1079 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1080 SUBARCH (nop
, NOP
, NOP
, false),
1081 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1082 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1083 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1084 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1085 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1086 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1087 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1088 SUBARCH (abm
, ABM
, ABM
, false),
1089 SUBARCH (bmi
, BMI
, BMI
, false),
1090 SUBARCH (tbm
, TBM
, TBM
, false),
1091 SUBARCH (adx
, ADX
, ADX
, false),
1092 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1093 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1094 SUBARCH (smap
, SMAP
, SMAP
, false),
1095 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1096 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1097 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1098 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1099 SUBARCH (se1
, SE1
, SE1
, false),
1100 SUBARCH (clwb
, CLWB
, CLWB
, false),
1101 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1102 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1103 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1104 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1105 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1106 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1107 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1108 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1109 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1110 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1111 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1112 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1113 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1114 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1115 SUBARCH (ibt
, IBT
, IBT
, false),
1116 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1117 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1118 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1119 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1120 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1121 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1122 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1123 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1124 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1125 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1126 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1127 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1128 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1129 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1130 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1131 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1132 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1133 ANY_AVX512_VP2INTERSECT
, reset
),
1134 SUBARCH (tdx
, TDX
, TDX
, false),
1135 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1136 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1137 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1138 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1139 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1140 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1141 SUBARCH (kl
, KL
, ANY_KL
, false),
1142 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1143 SUBARCH (uintr
, UINTR
, UINTR
, false),
1144 SUBARCH (hreset
, HRESET
, HRESET
, false),
1145 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1146 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1147 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1148 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1149 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1150 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1151 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1152 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1153 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1154 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1155 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1156 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1157 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1158 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1159 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1160 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1161 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1162 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1163 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1170 /* Like s_lcomm_internal in gas/read.c but the alignment string
1171 is allowed to be optional. */
1174 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1181 && *input_line_pointer
== ',')
1183 align
= parse_align (needs_align
- 1);
1185 if (align
== (addressT
) -1)
1200 bss_alloc (symbolP
, size
, align
);
1205 pe_lcomm (int needs_align
)
1207 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1211 const pseudo_typeS md_pseudo_table
[] =
1213 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1214 {"align", s_align_bytes
, 0},
1216 {"align", s_align_ptwo
, 0},
1218 {"arch", set_cpu_arch
, 0},
1222 {"lcomm", pe_lcomm
, 1},
1224 {"ffloat", float_cons
, 'f'},
1225 {"dfloat", float_cons
, 'd'},
1226 {"tfloat", float_cons
, 'x'},
1227 {"hfloat", float_cons
, 'h'},
1228 {"bfloat16", float_cons
, 'b'},
1230 {"slong", signed_cons
, 4},
1231 {"insn", s_insn
, 0},
1232 {"noopt", s_ignore
, 0},
1233 {"optim", s_ignore
, 0},
1234 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1235 {"code16", set_code_flag
, CODE_16BIT
},
1236 {"code32", set_code_flag
, CODE_32BIT
},
1238 {"code64", set_code_flag
, CODE_64BIT
},
1240 {"intel_syntax", set_intel_syntax
, 1},
1241 {"att_syntax", set_intel_syntax
, 0},
1242 {"intel_mnemonic", set_intel_mnemonic
, 1},
1243 {"att_mnemonic", set_intel_mnemonic
, 0},
1244 {"allow_index_reg", set_allow_index_reg
, 1},
1245 {"disallow_index_reg", set_allow_index_reg
, 0},
1246 {"sse_check", set_check
, 0},
1247 {"operand_check", set_check
, 1},
1248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1249 {"largecomm", handle_large_common
, 0},
1251 {"file", dwarf2_directive_file
, 0},
1252 {"loc", dwarf2_directive_loc
, 0},
1253 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1256 {"secrel32", pe_directive_secrel
, 0},
1257 {"secidx", pe_directive_secidx
, 0},
1262 /* For interface with expression (). */
1263 extern char *input_line_pointer
;
1265 /* Hash table for instruction mnemonic lookup. */
1266 static htab_t op_hash
;
1268 /* Hash table for register lookup. */
1269 static htab_t reg_hash
;
1271 /* Various efficient no-op patterns for aligning code labels.
1272 Note: Don't try to assemble the instructions in the comments.
1273 0L and 0w are not legal. */
1274 static const unsigned char f32_1
[] =
1276 static const unsigned char f32_2
[] =
1277 {0x66,0x90}; /* xchg %ax,%ax */
1278 static const unsigned char f32_3
[] =
1279 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1280 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1281 static const unsigned char f32_5
[] =
1282 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1283 static const unsigned char f32_6
[] =
1284 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1285 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1286 static const unsigned char f32_8
[] =
1287 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1288 static const unsigned char f64_3
[] =
1289 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1290 static const unsigned char f64_4
[] =
1291 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1292 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1293 static const unsigned char f64_6
[] =
1294 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1295 static const unsigned char f64_7
[] =
1296 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1297 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1298 static const unsigned char f64_9
[] =
1299 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1300 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1301 static const unsigned char f16_3
[] =
1302 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1303 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1304 static const unsigned char f16_5
[] =
1305 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1306 static const unsigned char jump_disp8
[] =
1307 {0xeb}; /* jmp disp8 */
1308 static const unsigned char jump32_disp32
[] =
1309 {0xe9}; /* jmp disp32 */
1310 static const unsigned char jump16_disp32
[] =
1311 {0x66,0xe9}; /* jmp disp32 */
1312 /* 32-bit NOPs patterns. */
1313 static const unsigned char *const f32_patt
[] = {
1314 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1316 /* 64-bit NOPs patterns. */
1317 static const unsigned char *const f64_patt
[] = {
1318 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1320 /* 16-bit NOPs patterns. */
1321 static const unsigned char *const f16_patt
[] = {
1322 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1324 /* nopl (%[re]ax) */
1325 static const unsigned char alt_3
[] =
1327 /* nopl 0(%[re]ax) */
1328 static const unsigned char alt_4
[] =
1329 {0x0f,0x1f,0x40,0x00};
1330 /* nopl 0(%[re]ax,%[re]ax,1) */
1331 #define alt_5 (alt_6 + 1)
1332 /* nopw 0(%[re]ax,%[re]ax,1) */
1333 static const unsigned char alt_6
[] =
1334 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1335 /* nopl 0L(%[re]ax) */
1336 static const unsigned char alt_7
[] =
1337 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1338 /* nopl 0L(%[re]ax,%[re]ax,1) */
1339 #define alt_8 (alt_9 + 1)
1340 /* nopw 0L(%[re]ax,%[re]ax,1) */
1341 static const unsigned char alt_9
[] =
1342 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1343 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1344 #define alt_10 (alt_11 + 1)
1345 /* data16 nopw %cs:0L(%eax,%eax,1) */
1346 static const unsigned char alt_11
[] =
1347 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1348 /* 32-bit and 64-bit NOPs patterns. */
1349 static const unsigned char *const alt_patt
[] = {
1350 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1351 alt_9
, alt_10
, alt_11
1354 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1355 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1358 i386_output_nops (char *where
, const unsigned char *const *patt
,
1359 int count
, int max_single_nop_size
)
1362 /* Place the longer NOP first. */
1365 const unsigned char *nops
;
1367 if (max_single_nop_size
< 1)
1369 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1370 max_single_nop_size
);
1374 nops
= patt
[max_single_nop_size
- 1];
1375 last
= count
% max_single_nop_size
;
1378 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1379 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1383 nops
= patt
[last
- 1];
1384 memcpy (where
+ offset
, nops
, last
);
1389 fits_in_imm7 (offsetT num
)
1391 return (num
& 0x7f) == num
;
1395 fits_in_imm31 (offsetT num
)
1397 return (num
& 0x7fffffff) == num
;
1400 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1401 single NOP instruction LIMIT. */
1404 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1406 const unsigned char *const *patt
= NULL
;
1407 int max_single_nop_size
;
1408 /* Maximum number of NOPs before switching to jump over NOPs. */
1409 int max_number_of_nops
;
1411 switch (fragP
->fr_type
)
1416 case rs_machine_dependent
:
1417 /* Allow NOP padding for jumps and calls. */
1418 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1419 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1426 /* We need to decide which NOP sequence to use for 32bit and
1427 64bit. When -mtune= is used:
1429 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1430 PROCESSOR_GENERIC32, f32_patt will be used.
1431 2. For the rest, alt_patt will be used.
1433 When -mtune= isn't used, alt_patt will be used if
1434 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1437 When -march= or .arch is used, we can't use anything beyond
1438 cpu_arch_isa_flags. */
1440 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1443 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1444 /* Limit number of NOPs to 2 in 16-bit mode. */
1445 max_number_of_nops
= 2;
1449 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1450 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1452 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1453 explicitly disabled. */
1454 switch (fragP
->tc_frag_data
.tune
)
1456 case PROCESSOR_UNKNOWN
:
1457 /* We use cpu_arch_isa_flags to check if we SHOULD
1458 optimize with nops. */
1459 if (fragP
->tc_frag_data
.isanop
)
1463 case PROCESSOR_PENTIUMPRO
:
1464 case PROCESSOR_PENTIUM4
:
1465 case PROCESSOR_NOCONA
:
1466 case PROCESSOR_CORE
:
1467 case PROCESSOR_CORE2
:
1468 case PROCESSOR_COREI7
:
1469 case PROCESSOR_GENERIC64
:
1471 case PROCESSOR_ATHLON
:
1473 case PROCESSOR_AMDFAM10
:
1475 case PROCESSOR_ZNVER
:
1477 if (fragP
->tc_frag_data
.cpunop
)
1481 case PROCESSOR_I386
:
1482 case PROCESSOR_I486
:
1483 case PROCESSOR_PENTIUM
:
1484 case PROCESSOR_I686
:
1485 case PROCESSOR_IAMCU
:
1486 case PROCESSOR_GENERIC32
:
1488 case PROCESSOR_NONE
:
1494 switch (fragP
->tc_frag_data
.tune
)
1496 case PROCESSOR_UNKNOWN
:
1497 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1498 PROCESSOR_UNKNOWN. */
1503 /* We use cpu_arch_isa_flags to check if we CAN optimize
1505 if (fragP
->tc_frag_data
.isanop
)
1509 case PROCESSOR_NONE
:
1514 if (patt
!= alt_patt
)
1516 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1517 : ARRAY_SIZE (f64_patt
);
1518 /* Limit number of NOPs to 2 for older processors. */
1519 max_number_of_nops
= 2;
1523 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1524 /* Limit number of NOPs to 7 for newer processors. */
1525 max_number_of_nops
= 7;
1530 limit
= max_single_nop_size
;
1532 if (fragP
->fr_type
== rs_fill_nop
)
1534 /* Output NOPs for .nop directive. */
1535 if (limit
> max_single_nop_size
)
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("invalid single nop size: %d "
1539 "(expect within [0, %d])"),
1540 limit
, max_single_nop_size
);
1544 else if (fragP
->fr_type
!= rs_machine_dependent
)
1545 fragP
->fr_var
= count
;
1547 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1549 /* Generate jump over NOPs. */
1550 offsetT disp
= count
- 2;
1551 if (fits_in_imm7 (disp
))
1553 /* Use "jmp disp8" if possible. */
1555 where
[0] = jump_disp8
[0];
1561 unsigned int size_of_jump
;
1563 if (flag_code
== CODE_16BIT
)
1565 where
[0] = jump16_disp32
[0];
1566 where
[1] = jump16_disp32
[1];
1571 where
[0] = jump32_disp32
[0];
1575 count
-= size_of_jump
+ 4;
1576 if (!fits_in_imm31 (count
))
1578 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1579 _("jump over nop padding out of range"));
1583 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1584 where
+= size_of_jump
+ 4;
1588 /* Generate multiple NOPs. */
1589 i386_output_nops (where
, patt
, count
, limit
);
1593 operand_type_all_zero (const union i386_operand_type
*x
)
1595 switch (ARRAY_SIZE(x
->array
))
1606 return !x
->array
[0];
1613 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1615 switch (ARRAY_SIZE(x
->array
))
1631 x
->bitfield
.class = ClassNone
;
1632 x
->bitfield
.instance
= InstanceNone
;
1636 operand_type_equal (const union i386_operand_type
*x
,
1637 const union i386_operand_type
*y
)
1639 switch (ARRAY_SIZE(x
->array
))
1642 if (x
->array
[2] != y
->array
[2])
1646 if (x
->array
[1] != y
->array
[1])
1650 return x
->array
[0] == y
->array
[0];
1658 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1662 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1663 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1664 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1665 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1666 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1667 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1668 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1669 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1670 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1671 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1673 gas_assert (cpu
< CpuAttrEnums
);
1675 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1678 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1680 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1681 i386_cpu_flags f
= { .array
[0] = 0 };
1683 switch (ARRAY_SIZE(a
.array
))
1686 f
.array
[CpuAttrEnums
/ bps
]
1687 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1688 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1689 f
.array
[CpuAttrEnums
/ bps
+ 1]
1690 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1697 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1703 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1705 switch (ARRAY_SIZE(x
->array
))
1724 return !x
->array
[0];
1731 cpu_flags_equal (const union i386_cpu_flags
*x
,
1732 const union i386_cpu_flags
*y
)
1734 switch (ARRAY_SIZE(x
->array
))
1737 if (x
->array
[4] != y
->array
[4])
1741 if (x
->array
[3] != y
->array
[3])
1745 if (x
->array
[2] != y
->array
[2])
1749 if (x
->array
[1] != y
->array
[1])
1753 return x
->array
[0] == y
->array
[0];
1761 cpu_flags_check_cpu64 (const insn_template
*t
)
1763 return flag_code
== CODE_64BIT
1764 ? !t
->cpu
.bitfield
.cpuno64
1765 : !t
->cpu
.bitfield
.cpu64
;
1768 static INLINE i386_cpu_flags
1769 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1771 switch (ARRAY_SIZE (x
.array
))
1774 x
.array
[4] &= y
.array
[4];
1777 x
.array
[3] &= y
.array
[3];
1780 x
.array
[2] &= y
.array
[2];
1783 x
.array
[1] &= y
.array
[1];
1786 x
.array
[0] &= y
.array
[0];
1794 static INLINE i386_cpu_flags
1795 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1797 switch (ARRAY_SIZE (x
.array
))
1800 x
.array
[4] |= y
.array
[4];
1803 x
.array
[3] |= y
.array
[3];
1806 x
.array
[2] |= y
.array
[2];
1809 x
.array
[1] |= y
.array
[1];
1812 x
.array
[0] |= y
.array
[0];
1820 static INLINE i386_cpu_flags
1821 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[4] &= ~y
.array
[4];
1829 x
.array
[3] &= ~y
.array
[3];
1832 x
.array
[2] &= ~y
.array
[2];
1835 x
.array
[1] &= ~y
.array
[1];
1838 x
.array
[0] &= ~y
.array
[0];
1846 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1848 static INLINE
bool need_evex_encoding (void)
1850 return i
.vec_encoding
== vex_encoding_evex
1851 || i
.vec_encoding
== vex_encoding_evex512
1855 #define CPU_FLAGS_ARCH_MATCH 0x1
1856 #define CPU_FLAGS_64BIT_MATCH 0x2
1858 #define CPU_FLAGS_PERFECT_MATCH \
1859 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1861 /* Return CPU flags match bits. */
1864 cpu_flags_match (const insn_template
*t
)
1866 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1867 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1869 x
.bitfield
.cpu64
= 0;
1870 x
.bitfield
.cpuno64
= 0;
1872 if (cpu_flags_all_zero (&x
))
1874 /* This instruction is available on all archs. */
1875 match
|= CPU_FLAGS_ARCH_MATCH
;
1879 /* This instruction is available only on some archs. */
1880 i386_cpu_flags active
, cpu
;
1882 if (flag_code
!= CODE_64BIT
)
1883 active
= cpu_flags_and_not (cpu_arch_flags
, cpu_64_flags
);
1885 active
= cpu_arch_flags
;
1887 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1888 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1890 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1891 know that EVEX encoding will be needed. */
1892 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1893 && x
.bitfield
.cpuavx512f
)
1895 if (need_evex_encoding ())
1897 x
.bitfield
.cpuavx
= 0;
1898 x
.bitfield
.cpuavx2
= 0;
1900 /* need_evex_encoding() isn't reliable before operands were
1902 else if (i
.operands
)
1904 x
.bitfield
.cpuavx512f
= 0;
1905 x
.bitfield
.cpuavx512vl
= 0;
1906 if (x
.bitfield
.cpufma
&& !active
.bitfield
.cpufma
)
1907 x
.bitfield
.cpuavx
= 0;
1912 /* AVX512VL is no standalone feature - match it and then strip it. */
1913 if (x
.bitfield
.cpuavx512vl
&& !active
.bitfield
.cpuavx512vl
)
1915 x
.bitfield
.cpuavx512vl
= 0;
1917 /* AVX and AVX2 present at the same time express an operand size
1918 dependency - strip AVX2 for the purposes here. The operand size
1919 dependent check occurs in check_vecOperands(). */
1920 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1921 x
.bitfield
.cpuavx2
= 0;
1923 cpu
= cpu_flags_and (x
, active
);
1924 if (!cpu_flags_all_zero (&cpu
))
1926 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1928 if ((need_evex_encoding ()
1929 ? cpu
.bitfield
.cpuavx512f
1930 : cpu
.bitfield
.cpuavx
)
1931 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1932 || active
.bitfield
.cpuavx512f
)
1933 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1934 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1935 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1936 match
|= CPU_FLAGS_ARCH_MATCH
;
1938 else if (x
.bitfield
.cpuavx
)
1940 /* We need to check a few extra flags with AVX. */
1941 if (cpu
.bitfield
.cpuavx
1942 && (!t
->opcode_modifier
.sse2avx
1943 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1944 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1945 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1946 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1947 match
|= CPU_FLAGS_ARCH_MATCH
;
1949 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1950 match
|= CPU_FLAGS_ARCH_MATCH
;
1951 else if (x
.bitfield
.cpuavx512f
)
1953 /* We need to check a few extra flags with AVX512F. */
1954 if (cpu
.bitfield
.cpuavx512f
1955 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1956 match
|= CPU_FLAGS_ARCH_MATCH
;
1959 match
|= CPU_FLAGS_ARCH_MATCH
;
1965 static INLINE i386_operand_type
1966 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1968 if (x
.bitfield
.class != y
.bitfield
.class)
1969 x
.bitfield
.class = ClassNone
;
1970 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1971 x
.bitfield
.instance
= InstanceNone
;
1973 switch (ARRAY_SIZE (x
.array
))
1976 x
.array
[2] &= y
.array
[2];
1979 x
.array
[1] &= y
.array
[1];
1982 x
.array
[0] &= y
.array
[0];
1990 static INLINE i386_operand_type
1991 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1993 gas_assert (y
.bitfield
.class == ClassNone
);
1994 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1996 switch (ARRAY_SIZE (x
.array
))
1999 x
.array
[2] &= ~y
.array
[2];
2002 x
.array
[1] &= ~y
.array
[1];
2005 x
.array
[0] &= ~y
.array
[0];
2013 static INLINE i386_operand_type
2014 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2016 gas_assert (x
.bitfield
.class == ClassNone
||
2017 y
.bitfield
.class == ClassNone
||
2018 x
.bitfield
.class == y
.bitfield
.class);
2019 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2020 y
.bitfield
.instance
== InstanceNone
||
2021 x
.bitfield
.instance
== y
.bitfield
.instance
);
2023 switch (ARRAY_SIZE (x
.array
))
2026 x
.array
[2] |= y
.array
[2];
2029 x
.array
[1] |= y
.array
[1];
2032 x
.array
[0] |= y
.array
[0];
2040 static INLINE i386_operand_type
2041 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2043 gas_assert (y
.bitfield
.class == ClassNone
);
2044 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2046 switch (ARRAY_SIZE (x
.array
))
2049 x
.array
[2] ^= y
.array
[2];
2052 x
.array
[1] ^= y
.array
[1];
2055 x
.array
[0] ^= y
.array
[0];
2063 static const i386_operand_type anydisp
= {
2064 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2076 operand_type_check (i386_operand_type t
, enum operand_type c
)
2081 return t
.bitfield
.class == Reg
;
2084 return (t
.bitfield
.imm8
2088 || t
.bitfield
.imm32s
2089 || t
.bitfield
.imm64
);
2092 return (t
.bitfield
.disp8
2093 || t
.bitfield
.disp16
2094 || t
.bitfield
.disp32
2095 || t
.bitfield
.disp64
);
2098 return (t
.bitfield
.disp8
2099 || t
.bitfield
.disp16
2100 || t
.bitfield
.disp32
2101 || t
.bitfield
.disp64
2102 || t
.bitfield
.baseindex
);
2111 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2112 between operand GIVEN and opeand WANTED for instruction template T. */
2115 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2118 return !((i
.types
[given
].bitfield
.byte
2119 && !t
->operand_types
[wanted
].bitfield
.byte
)
2120 || (i
.types
[given
].bitfield
.word
2121 && !t
->operand_types
[wanted
].bitfield
.word
)
2122 || (i
.types
[given
].bitfield
.dword
2123 && !t
->operand_types
[wanted
].bitfield
.dword
)
2124 || (i
.types
[given
].bitfield
.qword
2125 && (!t
->operand_types
[wanted
].bitfield
.qword
2126 /* Don't allow 64-bit (memory) operands outside of 64-bit
2127 mode, when they're used where a 64-bit GPR could also
2128 be used. Checking is needed for Intel Syntax only. */
2130 && flag_code
!= CODE_64BIT
2131 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2132 || t
->operand_types
[wanted
].bitfield
.class == Accum
2133 || t
->opcode_modifier
.isstring
))))
2134 || (i
.types
[given
].bitfield
.tbyte
2135 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2138 /* Return 1 if there is no conflict in SIMD register between operand
2139 GIVEN and opeand WANTED for instruction template T. */
2142 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2145 return !((i
.types
[given
].bitfield
.xmmword
2146 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2147 || (i
.types
[given
].bitfield
.ymmword
2148 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2149 || (i
.types
[given
].bitfield
.zmmword
2150 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2151 || (i
.types
[given
].bitfield
.tmmword
2152 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2155 /* Return 1 if there is no conflict in any size between operand GIVEN
2156 and opeand WANTED for instruction template T. */
2159 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2162 return (match_operand_size (t
, wanted
, given
)
2163 && !((i
.types
[given
].bitfield
.unspecified
2164 && !i
.broadcast
.type
2165 && !i
.broadcast
.bytes
2166 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2167 || (i
.types
[given
].bitfield
.fword
2168 && !t
->operand_types
[wanted
].bitfield
.fword
)
2169 /* For scalar opcode templates to allow register and memory
2170 operands at the same time, some special casing is needed
2171 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2172 down-conversion vpmov*. */
2173 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2174 && t
->operand_types
[wanted
].bitfield
.byte
2175 + t
->operand_types
[wanted
].bitfield
.word
2176 + t
->operand_types
[wanted
].bitfield
.dword
2177 + t
->operand_types
[wanted
].bitfield
.qword
2178 > !!t
->opcode_modifier
.broadcast
)
2179 ? (i
.types
[given
].bitfield
.xmmword
2180 || i
.types
[given
].bitfield
.ymmword
2181 || i
.types
[given
].bitfield
.zmmword
)
2182 : !match_simd_size(t
, wanted
, given
))));
2185 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2186 operands for instruction template T, and it has MATCH_REVERSE set if there
2187 is no size conflict on any operands for the template with operands reversed
2188 (and the template allows for reversing in the first place). */
2190 #define MATCH_STRAIGHT 1
2191 #define MATCH_REVERSE 2
2193 static INLINE
unsigned int
2194 operand_size_match (const insn_template
*t
)
2196 unsigned int j
, match
= MATCH_STRAIGHT
;
2198 /* Don't check non-absolute jump instructions. */
2199 if (t
->opcode_modifier
.jump
2200 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2203 /* Check memory and accumulator operand size. */
2204 for (j
= 0; j
< i
.operands
; j
++)
2206 if (i
.types
[j
].bitfield
.class != Reg
2207 && i
.types
[j
].bitfield
.class != RegSIMD
2208 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2211 if (t
->operand_types
[j
].bitfield
.class == Reg
2212 && !match_operand_size (t
, j
, j
))
2218 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2219 && !match_simd_size (t
, j
, j
))
2225 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2226 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2232 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2239 if (!t
->opcode_modifier
.d
)
2242 /* Check reverse. */
2243 gas_assert (i
.operands
>= 2);
2245 for (j
= 0; j
< i
.operands
; j
++)
2247 unsigned int given
= i
.operands
- j
- 1;
2249 /* For FMA4 and XOP insns VEX.W controls just the first two
2250 register operands. */
2251 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2252 given
= j
< 2 ? 1 - j
: j
;
2254 if (t
->operand_types
[j
].bitfield
.class == Reg
2255 && !match_operand_size (t
, j
, given
))
2258 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2259 && !match_simd_size (t
, j
, given
))
2262 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2263 && (!match_operand_size (t
, j
, given
)
2264 || !match_simd_size (t
, j
, given
)))
2267 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2271 return match
| MATCH_REVERSE
;
2275 operand_type_match (i386_operand_type overlap
,
2276 i386_operand_type given
)
2278 i386_operand_type temp
= overlap
;
2280 temp
.bitfield
.unspecified
= 0;
2281 temp
.bitfield
.byte
= 0;
2282 temp
.bitfield
.word
= 0;
2283 temp
.bitfield
.dword
= 0;
2284 temp
.bitfield
.fword
= 0;
2285 temp
.bitfield
.qword
= 0;
2286 temp
.bitfield
.tbyte
= 0;
2287 temp
.bitfield
.xmmword
= 0;
2288 temp
.bitfield
.ymmword
= 0;
2289 temp
.bitfield
.zmmword
= 0;
2290 temp
.bitfield
.tmmword
= 0;
2291 if (operand_type_all_zero (&temp
))
2294 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2298 i
.error
= operand_type_mismatch
;
2302 /* If given types g0 and g1 are registers they must be of the same type
2303 unless the expected operand type register overlap is null.
2304 Intel syntax sized memory operands are also checked here. */
2307 operand_type_register_match (i386_operand_type g0
,
2308 i386_operand_type t0
,
2309 i386_operand_type g1
,
2310 i386_operand_type t1
)
2312 if (g0
.bitfield
.class != Reg
2313 && g0
.bitfield
.class != RegSIMD
2314 && (g0
.bitfield
.unspecified
2315 || !operand_type_check (g0
, anymem
)))
2318 if (g1
.bitfield
.class != Reg
2319 && g1
.bitfield
.class != RegSIMD
2320 && (g1
.bitfield
.unspecified
2321 || !operand_type_check (g1
, anymem
)))
2324 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2325 && g0
.bitfield
.word
== g1
.bitfield
.word
2326 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2327 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2328 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2329 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2330 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2333 /* If expectations overlap in no more than a single size, all is fine. */
2334 g0
= operand_type_and (t0
, t1
);
2335 if (g0
.bitfield
.byte
2339 + g0
.bitfield
.xmmword
2340 + g0
.bitfield
.ymmword
2341 + g0
.bitfield
.zmmword
<= 1)
2344 i
.error
= register_type_mismatch
;
2349 static INLINE
unsigned int
2350 register_number (const reg_entry
*r
)
2352 unsigned int nr
= r
->reg_num
;
2354 if (r
->reg_flags
& RegRex
)
2357 if (r
->reg_flags
& RegVRex
)
2363 static INLINE
unsigned int
2364 mode_from_disp_size (i386_operand_type t
)
2366 if (t
.bitfield
.disp8
)
2368 else if (t
.bitfield
.disp16
2369 || t
.bitfield
.disp32
)
2376 fits_in_signed_byte (addressT num
)
2378 return num
+ 0x80 <= 0xff;
2382 fits_in_unsigned_byte (addressT num
)
2388 fits_in_unsigned_word (addressT num
)
2390 return num
<= 0xffff;
2394 fits_in_signed_word (addressT num
)
2396 return num
+ 0x8000 <= 0xffff;
2400 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2405 return num
+ 0x80000000 <= 0xffffffff;
2407 } /* fits_in_signed_long() */
2410 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2415 return num
<= 0xffffffff;
2417 } /* fits_in_unsigned_long() */
2419 static INLINE valueT
extend_to_32bit_address (addressT num
)
2422 if (fits_in_unsigned_long(num
))
2423 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2425 if (!fits_in_signed_long (num
))
2426 return num
& 0xffffffff;
2433 fits_in_disp8 (offsetT num
)
2435 int shift
= i
.memshift
;
2441 mask
= (1 << shift
) - 1;
2443 /* Return 0 if NUM isn't properly aligned. */
2447 /* Check if NUM will fit in 8bit after shift. */
2448 return fits_in_signed_byte (num
>> shift
);
2452 fits_in_imm4 (offsetT num
)
2454 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2455 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2458 static i386_operand_type
2459 smallest_imm_type (offsetT num
)
2461 i386_operand_type t
;
2463 operand_type_set (&t
, 0);
2464 t
.bitfield
.imm64
= 1;
2466 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2468 /* This code is disabled on the 486 because all the Imm1 forms
2469 in the opcode table are slower on the i486. They're the
2470 versions with the implicitly specified single-position
2471 displacement, which has another syntax if you really want to
2473 t
.bitfield
.imm1
= 1;
2474 t
.bitfield
.imm8
= 1;
2475 t
.bitfield
.imm8s
= 1;
2476 t
.bitfield
.imm16
= 1;
2477 t
.bitfield
.imm32
= 1;
2478 t
.bitfield
.imm32s
= 1;
2480 else if (fits_in_signed_byte (num
))
2482 if (fits_in_unsigned_byte (num
))
2483 t
.bitfield
.imm8
= 1;
2484 t
.bitfield
.imm8s
= 1;
2485 t
.bitfield
.imm16
= 1;
2486 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2487 t
.bitfield
.imm32
= 1;
2488 t
.bitfield
.imm32s
= 1;
2490 else if (fits_in_unsigned_byte (num
))
2492 t
.bitfield
.imm8
= 1;
2493 t
.bitfield
.imm16
= 1;
2494 t
.bitfield
.imm32
= 1;
2495 t
.bitfield
.imm32s
= 1;
2497 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2499 t
.bitfield
.imm16
= 1;
2500 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2501 t
.bitfield
.imm32
= 1;
2502 t
.bitfield
.imm32s
= 1;
2504 else if (fits_in_signed_long (num
))
2506 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2507 t
.bitfield
.imm32
= 1;
2508 t
.bitfield
.imm32s
= 1;
2510 else if (fits_in_unsigned_long (num
))
2511 t
.bitfield
.imm32
= 1;
2517 offset_in_range (offsetT val
, int size
)
2523 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2524 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2526 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2528 case sizeof (val
): return val
;
2532 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2533 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2534 (uint64_t) val
, (uint64_t) (val
& mask
));
2539 static INLINE
const char *insn_name (const insn_template
*t
)
2541 return &i386_mnemonics
[t
->mnem_off
];
2554 a. PREFIX_EXIST if attempting to add a prefix where one from the
2555 same class already exists.
2556 b. PREFIX_LOCK if lock prefix is added.
2557 c. PREFIX_REP if rep/repne prefix is added.
2558 d. PREFIX_DS if ds prefix is added.
2559 e. PREFIX_OTHER if other prefix is added.
2562 static enum PREFIX_GROUP
2563 add_prefix (unsigned int prefix
)
2565 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2568 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2569 && flag_code
== CODE_64BIT
)
2571 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2572 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2585 case DS_PREFIX_OPCODE
:
2588 case CS_PREFIX_OPCODE
:
2589 case ES_PREFIX_OPCODE
:
2590 case FS_PREFIX_OPCODE
:
2591 case GS_PREFIX_OPCODE
:
2592 case SS_PREFIX_OPCODE
:
2596 case REPNE_PREFIX_OPCODE
:
2597 case REPE_PREFIX_OPCODE
:
2602 case LOCK_PREFIX_OPCODE
:
2611 case ADDR_PREFIX_OPCODE
:
2615 case DATA_PREFIX_OPCODE
:
2619 if (i
.prefix
[q
] != 0)
2627 i
.prefix
[q
] |= prefix
;
2630 as_bad (_("same type of prefix used twice"));
2636 update_code_flag (int value
, int check
)
2638 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2640 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2642 as_error (_("64bit mode not supported on `%s'."),
2643 cpu_arch_name
? cpu_arch_name
: default_arch
);
2647 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2649 as_error (_("32bit mode not supported on `%s'."),
2650 cpu_arch_name
? cpu_arch_name
: default_arch
);
2654 flag_code
= (enum flag_code
) value
;
2656 stackop_size
= '\0';
2660 set_code_flag (int value
)
2662 update_code_flag (value
, 0);
2666 set_16bit_gcc_code_flag (int new_code_flag
)
2668 flag_code
= (enum flag_code
) new_code_flag
;
2669 if (flag_code
!= CODE_16BIT
)
2671 stackop_size
= LONG_MNEM_SUFFIX
;
2675 set_intel_syntax (int syntax_flag
)
2677 /* Find out if register prefixing is specified. */
2678 int ask_naked_reg
= 0;
2681 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2684 int e
= get_symbol_name (&string
);
2686 if (strcmp (string
, "prefix") == 0)
2688 else if (strcmp (string
, "noprefix") == 0)
2691 as_bad (_("bad argument to syntax directive."));
2692 (void) restore_line_pointer (e
);
2694 demand_empty_rest_of_line ();
2696 intel_syntax
= syntax_flag
;
2698 if (ask_naked_reg
== 0)
2699 allow_naked_reg
= (intel_syntax
2700 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2702 allow_naked_reg
= (ask_naked_reg
< 0);
2704 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2706 register_prefix
= allow_naked_reg
? "" : "%";
2710 set_intel_mnemonic (int mnemonic_flag
)
2712 intel_mnemonic
= mnemonic_flag
;
2716 set_allow_index_reg (int flag
)
2718 allow_index_reg
= flag
;
2722 set_check (int what
)
2724 enum check_kind
*kind
;
2729 kind
= &operand_check
;
2740 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2743 int e
= get_symbol_name (&string
);
2745 if (strcmp (string
, "none") == 0)
2747 else if (strcmp (string
, "warning") == 0)
2748 *kind
= check_warning
;
2749 else if (strcmp (string
, "error") == 0)
2750 *kind
= check_error
;
2752 as_bad (_("bad argument to %s_check directive."), str
);
2753 (void) restore_line_pointer (e
);
2756 as_bad (_("missing argument for %s_check directive"), str
);
2758 demand_empty_rest_of_line ();
2762 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2763 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2766 static const char *arch
;
2768 /* Intel MCU is only supported on ELF. */
2774 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2775 use default_arch. */
2776 arch
= cpu_arch_name
;
2778 arch
= default_arch
;
2781 /* If we are targeting Intel MCU, we must enable it. */
2782 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2783 == new_flag
.bitfield
.cpuiamcu
)
2786 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2791 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2793 if (cpu_sub_arch_name
)
2794 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2795 pfx
, name
, (const char *) NULL
);
2797 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2800 static void isa_enable (unsigned int idx
)
2802 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2804 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2806 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2807 cpu_arch_flags
= flags
;
2810 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2813 static void isa_disable (unsigned int idx
)
2815 i386_cpu_flags flags
2816 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2818 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2820 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2821 cpu_arch_flags
= flags
;
2825 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2829 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2831 typedef struct arch_stack_entry
2833 const struct arch_stack_entry
*prev
;
2836 i386_cpu_flags flags
;
2837 i386_cpu_flags isa_flags
;
2838 enum processor_type isa
;
2839 enum flag_code flag_code
;
2840 unsigned int vector_size
;
2842 bool no_cond_jump_promotion
;
2844 static const arch_stack_entry
*arch_stack_top
;
2852 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2854 as_bad (_("missing cpu architecture"));
2855 input_line_pointer
++;
2859 e
= get_symbol_name (&s
);
2862 if (strcmp (string
, "push") == 0)
2864 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2866 top
->name
= cpu_arch_name
;
2867 if (cpu_sub_arch_name
)
2868 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2870 top
->sub_name
= NULL
;
2871 top
->flags
= cpu_arch_flags
;
2872 top
->isa
= cpu_arch_isa
;
2873 top
->isa_flags
= cpu_arch_isa_flags
;
2874 top
->flag_code
= flag_code
;
2875 top
->vector_size
= vector_size
;
2876 top
->stackop_size
= stackop_size
;
2877 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2879 top
->prev
= arch_stack_top
;
2880 arch_stack_top
= top
;
2882 (void) restore_line_pointer (e
);
2883 demand_empty_rest_of_line ();
2887 if (strcmp (string
, "pop") == 0)
2889 const arch_stack_entry
*top
= arch_stack_top
;
2892 as_bad (_(".arch stack is empty"));
2893 else if (top
->flag_code
!= flag_code
2894 || top
->stackop_size
!= stackop_size
)
2896 static const unsigned int bits
[] = {
2902 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2903 bits
[top
->flag_code
],
2904 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2908 arch_stack_top
= top
->prev
;
2910 cpu_arch_name
= top
->name
;
2911 free (cpu_sub_arch_name
);
2912 cpu_sub_arch_name
= top
->sub_name
;
2913 cpu_arch_flags
= top
->flags
;
2914 cpu_arch_isa
= top
->isa
;
2915 cpu_arch_isa_flags
= top
->isa_flags
;
2916 vector_size
= top
->vector_size
;
2917 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2922 (void) restore_line_pointer (e
);
2923 demand_empty_rest_of_line ();
2927 if (strcmp (string
, "default") == 0)
2929 if (strcmp (default_arch
, "iamcu") == 0)
2930 string
= default_arch
;
2933 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2935 cpu_arch_name
= NULL
;
2936 free (cpu_sub_arch_name
);
2937 cpu_sub_arch_name
= NULL
;
2938 cpu_arch_flags
= cpu_unknown_flags
;
2939 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2940 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2941 if (!cpu_arch_tune_set
)
2942 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2944 vector_size
= VSZ_DEFAULT
;
2946 j
= ARRAY_SIZE (cpu_arch
) + 1;
2950 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2952 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2953 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2957 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2959 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2961 as_bad (_("64bit mode not supported on `%s'."),
2963 (void) restore_line_pointer (e
);
2964 ignore_rest_of_line ();
2968 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2970 as_bad (_("32bit mode not supported on `%s'."),
2972 (void) restore_line_pointer (e
);
2973 ignore_rest_of_line ();
2977 cpu_arch_name
= cpu_arch
[j
].name
;
2978 free (cpu_sub_arch_name
);
2979 cpu_sub_arch_name
= NULL
;
2980 cpu_arch_flags
= cpu_arch
[j
].enable
;
2981 cpu_arch_isa
= cpu_arch
[j
].type
;
2982 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2983 if (!cpu_arch_tune_set
)
2984 cpu_arch_tune
= cpu_arch_isa
;
2986 vector_size
= VSZ_DEFAULT
;
2988 pre_386_16bit_warned
= false;
2992 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2997 (void) restore_line_pointer (e
);
2999 switch (cpu_arch
[j
].vsz
)
3005 #ifdef SVR4_COMMENT_CHARS
3006 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3008 if (*input_line_pointer
== '/')
3011 ++input_line_pointer
;
3012 switch (get_absolute_expression ())
3014 case 512: vector_size
= VSZ512
; break;
3015 case 256: vector_size
= VSZ256
; break;
3016 case 128: vector_size
= VSZ128
; break;
3018 as_bad (_("Unrecognized vector size specifier"));
3019 ignore_rest_of_line ();
3026 vector_size
= VSZ_DEFAULT
;
3030 demand_empty_rest_of_line ();
3035 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3037 /* Disable an ISA extension. */
3038 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3039 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3040 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3044 if (cpu_arch
[j
].vsz
== vsz_set
)
3045 vector_size
= VSZ_DEFAULT
;
3047 (void) restore_line_pointer (e
);
3048 demand_empty_rest_of_line ();
3053 if (j
== ARRAY_SIZE (cpu_arch
))
3054 as_bad (_("no such architecture: `%s'"), string
);
3056 *input_line_pointer
= e
;
3058 no_cond_jump_promotion
= 0;
3059 if (*input_line_pointer
== ','
3060 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3062 ++input_line_pointer
;
3063 e
= get_symbol_name (&s
);
3066 if (strcmp (string
, "nojumps") == 0)
3067 no_cond_jump_promotion
= 1;
3068 else if (strcmp (string
, "jumps") == 0)
3071 as_bad (_("no such architecture modifier: `%s'"), string
);
3073 (void) restore_line_pointer (e
);
3076 demand_empty_rest_of_line ();
3079 enum bfd_architecture
3082 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3084 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3085 || flag_code
== CODE_64BIT
)
3086 as_fatal (_("Intel MCU is 32bit ELF only"));
3087 return bfd_arch_iamcu
;
3090 return bfd_arch_i386
;
3096 if (startswith (default_arch
, "x86_64"))
3098 if (default_arch
[6] == '\0')
3099 return bfd_mach_x86_64
;
3101 return bfd_mach_x64_32
;
3103 else if (!strcmp (default_arch
, "i386")
3104 || !strcmp (default_arch
, "iamcu"))
3106 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3108 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3109 as_fatal (_("Intel MCU is 32bit ELF only"));
3110 return bfd_mach_i386_iamcu
;
3113 return bfd_mach_i386_i386
;
3116 as_fatal (_("unknown architecture"));
3119 #include "opcodes/i386-tbl.h"
3124 /* Support pseudo prefixes like {disp32}. */
3125 lex_type
['{'] = LEX_BEGIN_NAME
;
3127 /* Initialize op_hash hash table. */
3128 op_hash
= str_htab_create ();
3131 const insn_template
*const *sets
= i386_op_sets
;
3132 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3134 /* Type checks to compensate for the conversion through void * which
3135 occurs during hash table insertion / lookup. */
3136 (void) sizeof (sets
== ¤t_templates
->start
);
3137 (void) sizeof (end
== ¤t_templates
->end
);
3138 for (; sets
< end
; ++sets
)
3139 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3140 as_fatal (_("duplicate %s"), insn_name (*sets
));
3143 /* Initialize reg_hash hash table. */
3144 reg_hash
= str_htab_create ();
3146 const reg_entry
*regtab
;
3147 unsigned int regtab_size
= i386_regtab_size
;
3149 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3151 switch (regtab
->reg_type
.bitfield
.class)
3154 if (regtab
->reg_type
.bitfield
.dword
)
3156 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3159 else if (regtab
->reg_type
.bitfield
.tbyte
)
3161 /* There's no point inserting st(<N>) in the hash table, as
3162 parentheses aren't included in register_chars[] anyway. */
3163 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3170 switch (regtab
->reg_num
)
3172 case 0: reg_es
= regtab
; break;
3173 case 2: reg_ss
= regtab
; break;
3174 case 3: reg_ds
= regtab
; break;
3179 if (!regtab
->reg_num
)
3184 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3185 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3189 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3194 for (c
= 0; c
< 256; c
++)
3196 if (ISDIGIT (c
) || ISLOWER (c
))
3198 mnemonic_chars
[c
] = c
;
3199 register_chars
[c
] = c
;
3200 operand_chars
[c
] = c
;
3202 else if (ISUPPER (c
))
3204 mnemonic_chars
[c
] = TOLOWER (c
);
3205 register_chars
[c
] = mnemonic_chars
[c
];
3206 operand_chars
[c
] = c
;
3208 #ifdef SVR4_COMMENT_CHARS
3209 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3210 operand_chars
[c
] = c
;
3214 operand_chars
[c
] = c
;
3217 mnemonic_chars
['_'] = '_';
3218 mnemonic_chars
['-'] = '-';
3219 mnemonic_chars
['.'] = '.';
3221 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3222 operand_chars
[(unsigned char) *p
] = *p
;
3223 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3224 operand_chars
[(unsigned char) *p
] = *p
;
3227 if (flag_code
== CODE_64BIT
)
3229 #if defined (OBJ_COFF) && defined (TE_PE)
3230 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3233 x86_dwarf2_return_column
= 16;
3235 x86_cie_data_alignment
= -8;
3236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3237 x86_sframe_cfa_sp_reg
= 7;
3238 x86_sframe_cfa_fp_reg
= 6;
3243 x86_dwarf2_return_column
= 8;
3244 x86_cie_data_alignment
= -4;
3247 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3248 can be turned into BRANCH_PREFIX frag. */
3249 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3254 i386_print_statistics (FILE *file
)
3256 htab_print_statistics (file
, "i386 opcode", op_hash
);
3257 htab_print_statistics (file
, "i386 register", reg_hash
);
3263 htab_delete (op_hash
);
3264 htab_delete (reg_hash
);
3269 /* Debugging routines for md_assemble. */
3270 static void pte (insn_template
*);
3271 static void pt (i386_operand_type
);
3272 static void pe (expressionS
*);
3273 static void ps (symbolS
*);
3276 pi (const char *line
, i386_insn
*x
)
3280 fprintf (stdout
, "%s: template ", line
);
3282 fprintf (stdout
, " address: base %s index %s scale %x\n",
3283 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3284 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3285 x
->log2_scale_factor
);
3286 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3287 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3288 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3289 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3290 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3291 (x
->rex
& REX_W
) != 0,
3292 (x
->rex
& REX_R
) != 0,
3293 (x
->rex
& REX_X
) != 0,
3294 (x
->rex
& REX_B
) != 0);
3295 for (j
= 0; j
< x
->operands
; j
++)
3297 fprintf (stdout
, " #%d: ", j
+ 1);
3299 fprintf (stdout
, "\n");
3300 if (x
->types
[j
].bitfield
.class == Reg
3301 || x
->types
[j
].bitfield
.class == RegMMX
3302 || x
->types
[j
].bitfield
.class == RegSIMD
3303 || x
->types
[j
].bitfield
.class == RegMask
3304 || x
->types
[j
].bitfield
.class == SReg
3305 || x
->types
[j
].bitfield
.class == RegCR
3306 || x
->types
[j
].bitfield
.class == RegDR
3307 || x
->types
[j
].bitfield
.class == RegTR
3308 || x
->types
[j
].bitfield
.class == RegBND
)
3309 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3310 if (operand_type_check (x
->types
[j
], imm
))
3312 if (operand_type_check (x
->types
[j
], disp
))
3313 pe (x
->op
[j
].disps
);
3318 pte (insn_template
*t
)
3320 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3321 static const char *const opc_spc
[] = {
3322 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3323 "XOP08", "XOP09", "XOP0A",
3327 fprintf (stdout
, " %d operands ", t
->operands
);
3328 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3329 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3330 if (opc_spc
[t
->opcode_space
])
3331 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3332 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3333 if (t
->extension_opcode
!= None
)
3334 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3335 if (t
->opcode_modifier
.d
)
3336 fprintf (stdout
, "D");
3337 if (t
->opcode_modifier
.w
)
3338 fprintf (stdout
, "W");
3339 fprintf (stdout
, "\n");
3340 for (j
= 0; j
< t
->operands
; j
++)
3342 fprintf (stdout
, " #%d type ", j
+ 1);
3343 pt (t
->operand_types
[j
]);
3344 fprintf (stdout
, "\n");
3351 fprintf (stdout
, " operation %d\n", e
->X_op
);
3352 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3353 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3354 if (e
->X_add_symbol
)
3356 fprintf (stdout
, " add_symbol ");
3357 ps (e
->X_add_symbol
);
3358 fprintf (stdout
, "\n");
3362 fprintf (stdout
, " op_symbol ");
3363 ps (e
->X_op_symbol
);
3364 fprintf (stdout
, "\n");
3371 fprintf (stdout
, "%s type %s%s",
3373 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3374 segment_name (S_GET_SEGMENT (s
)));
3377 static struct type_name
3379 i386_operand_type mask
;
3382 const type_names
[] =
3384 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3385 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3386 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3387 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3388 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3389 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3390 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3391 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3392 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3393 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3394 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3395 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3396 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3397 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3398 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3399 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3400 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3401 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3402 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3403 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3404 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3405 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3406 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3407 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3408 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3409 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3410 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3411 { { .bitfield
= { .class = SReg
} }, "SReg" },
3412 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3413 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3414 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3415 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3416 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3417 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3421 pt (i386_operand_type t
)
3424 i386_operand_type a
;
3426 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3428 a
= operand_type_and (t
, type_names
[j
].mask
);
3429 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3430 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3435 #endif /* DEBUG386 */
3437 static bfd_reloc_code_real_type
3438 reloc (unsigned int size
,
3441 bfd_reloc_code_real_type other
)
3443 if (other
!= NO_RELOC
)
3445 reloc_howto_type
*rel
;
3450 case BFD_RELOC_X86_64_GOT32
:
3451 return BFD_RELOC_X86_64_GOT64
;
3453 case BFD_RELOC_X86_64_GOTPLT64
:
3454 return BFD_RELOC_X86_64_GOTPLT64
;
3456 case BFD_RELOC_X86_64_PLTOFF64
:
3457 return BFD_RELOC_X86_64_PLTOFF64
;
3459 case BFD_RELOC_X86_64_GOTPC32
:
3460 other
= BFD_RELOC_X86_64_GOTPC64
;
3462 case BFD_RELOC_X86_64_GOTPCREL
:
3463 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3465 case BFD_RELOC_X86_64_TPOFF32
:
3466 other
= BFD_RELOC_X86_64_TPOFF64
;
3468 case BFD_RELOC_X86_64_DTPOFF32
:
3469 other
= BFD_RELOC_X86_64_DTPOFF64
;
3475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3476 if (other
== BFD_RELOC_SIZE32
)
3479 other
= BFD_RELOC_SIZE64
;
3482 as_bad (_("there are no pc-relative size relocations"));
3488 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3489 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3492 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3494 as_bad (_("unknown relocation (%u)"), other
);
3495 else if (size
!= bfd_get_reloc_size (rel
))
3496 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3497 bfd_get_reloc_size (rel
),
3499 else if (pcrel
&& !rel
->pc_relative
)
3500 as_bad (_("non-pc-relative relocation for pc-relative field"));
3501 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3503 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3505 as_bad (_("relocated field and relocation type differ in signedness"));
3514 as_bad (_("there are no unsigned pc-relative relocations"));
3517 case 1: return BFD_RELOC_8_PCREL
;
3518 case 2: return BFD_RELOC_16_PCREL
;
3519 case 4: return BFD_RELOC_32_PCREL
;
3520 case 8: return BFD_RELOC_64_PCREL
;
3522 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3529 case 4: return BFD_RELOC_X86_64_32S
;
3534 case 1: return BFD_RELOC_8
;
3535 case 2: return BFD_RELOC_16
;
3536 case 4: return BFD_RELOC_32
;
3537 case 8: return BFD_RELOC_64
;
3539 as_bad (_("cannot do %s %u byte relocation"),
3540 sign
> 0 ? "signed" : "unsigned", size
);
3546 /* Here we decide which fixups can be adjusted to make them relative to
3547 the beginning of the section instead of the symbol. Basically we need
3548 to make sure that the dynamic relocations are done correctly, so in
3549 some cases we force the original symbol to be used. */
3552 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3558 /* Don't adjust pc-relative references to merge sections in 64-bit
3560 if (use_rela_relocations
3561 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3565 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3566 and changed later by validate_fix. */
3567 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3568 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3571 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3572 for size relocations. */
3573 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3574 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3575 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3576 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3577 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3580 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3581 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3582 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3583 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3584 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3585 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3586 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3587 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3594 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3595 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3596 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3597 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3598 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3599 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3600 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3601 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3602 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3603 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3610 want_disp32 (const insn_template
*t
)
3612 return flag_code
!= CODE_64BIT
3613 || i
.prefix
[ADDR_PREFIX
]
3614 || (t
->mnem_off
== MN_lea
3615 && (!i
.types
[1].bitfield
.qword
3616 || t
->opcode_modifier
.size
== SIZE32
));
3620 intel_float_operand (const char *mnemonic
)
3622 /* Note that the value returned is meaningful only for opcodes with (memory)
3623 operands, hence the code here is free to improperly handle opcodes that
3624 have no operands (for better performance and smaller code). */
3626 if (mnemonic
[0] != 'f')
3627 return 0; /* non-math */
3629 switch (mnemonic
[1])
3631 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3632 the fs segment override prefix not currently handled because no
3633 call path can make opcodes without operands get here */
3635 return 2 /* integer op */;
3637 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3638 return 3; /* fldcw/fldenv */
3641 if (mnemonic
[2] != 'o' /* fnop */)
3642 return 3; /* non-waiting control op */
3645 if (mnemonic
[2] == 's')
3646 return 3; /* frstor/frstpm */
3649 if (mnemonic
[2] == 'a')
3650 return 3; /* fsave */
3651 if (mnemonic
[2] == 't')
3653 switch (mnemonic
[3])
3655 case 'c': /* fstcw */
3656 case 'd': /* fstdw */
3657 case 'e': /* fstenv */
3658 case 's': /* fsts[gw] */
3664 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3665 return 0; /* fxsave/fxrstor are not really math ops */
3673 install_template (const insn_template
*t
)
3679 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3680 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3682 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3683 && is_cpu (t
, CpuAVX512F
))
3685 if (need_evex_encoding ())
3687 i
.tm
.opcode_modifier
.vex
= 0;
3688 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3689 if (is_cpu (&i
.tm
, CpuAVX2
))
3690 i
.tm
.cpu
.bitfield
.isa
= 0;
3694 i
.tm
.opcode_modifier
.evex
= 0;
3695 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3700 /* Note that for pseudo prefixes this produces a length of 1. But for them
3701 the length isn't interesting at all. */
3702 for (l
= 1; l
< 4; ++l
)
3703 if (!(t
->base_opcode
>> (8 * l
)))
3706 i
.opcode_length
= l
;
3709 /* Build the VEX prefix. */
3712 build_vex_prefix (const insn_template
*t
)
3714 unsigned int register_specifier
;
3715 unsigned int vector_length
;
3718 /* Check register specifier. */
3719 if (i
.vex
.register_specifier
)
3721 register_specifier
=
3722 ~register_number (i
.vex
.register_specifier
) & 0xf;
3723 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3726 register_specifier
= 0xf;
3728 /* Use 2-byte VEX prefix by swapping destination and source operand
3729 if there are more than 1 register operand. */
3730 if (i
.reg_operands
> 1
3731 && i
.vec_encoding
!= vex_encoding_vex3
3732 && i
.dir_encoding
== dir_encoding_default
3733 && i
.operands
== i
.reg_operands
3734 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3735 && i
.tm
.opcode_space
== SPACE_0F
3736 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3741 swap_2_operands (0, i
.operands
- 1);
3743 gas_assert (i
.rm
.mode
== 3);
3747 i
.rm
.regmem
= i
.rm
.reg
;
3750 if (i
.tm
.opcode_modifier
.d
)
3751 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3752 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3753 else /* Use the next insn. */
3754 install_template (&t
[1]);
3757 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3758 are no memory operands and at least 3 register ones. */
3759 if (i
.reg_operands
>= 3
3760 && i
.vec_encoding
!= vex_encoding_vex3
3761 && i
.reg_operands
== i
.operands
- i
.imm_operands
3762 && i
.tm
.opcode_modifier
.vex
3763 && i
.tm
.opcode_modifier
.commutative
3764 && (i
.tm
.opcode_modifier
.sse2avx
3765 || (optimize
> 1 && !i
.no_optimize
))
3767 && i
.vex
.register_specifier
3768 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3770 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3772 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3773 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3774 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3775 &i
.types
[i
.operands
- 3]));
3776 gas_assert (i
.rm
.mode
== 3);
3778 swap_2_operands (xchg
, xchg
+ 1);
3781 xchg
= i
.rm
.regmem
| 8;
3782 i
.rm
.regmem
= ~register_specifier
& 0xf;
3783 gas_assert (!(i
.rm
.regmem
& 8));
3784 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3785 register_specifier
= ~xchg
& 0xf;
3788 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3789 vector_length
= avxscalar
;
3790 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3792 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3798 /* Determine vector length from the last multi-length vector
3801 for (op
= t
->operands
; op
--;)
3802 if (t
->operand_types
[op
].bitfield
.xmmword
3803 && t
->operand_types
[op
].bitfield
.ymmword
3804 && i
.types
[op
].bitfield
.ymmword
)
3811 /* Check the REX.W bit and VEXW. */
3812 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3813 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3814 else if (i
.tm
.opcode_modifier
.vexw
)
3815 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3817 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3819 /* Use 2-byte VEX prefix if possible. */
3821 && i
.vec_encoding
!= vex_encoding_vex3
3822 && i
.tm
.opcode_space
== SPACE_0F
3823 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3825 /* 2-byte VEX prefix. */
3829 i
.vex
.bytes
[0] = 0xc5;
3831 /* Check the REX.R bit. */
3832 r
= (i
.rex
& REX_R
) ? 0 : 1;
3833 i
.vex
.bytes
[1] = (r
<< 7
3834 | register_specifier
<< 3
3835 | vector_length
<< 2
3836 | i
.tm
.opcode_modifier
.opcodeprefix
);
3840 /* 3-byte VEX prefix. */
3843 switch (i
.tm
.opcode_space
)
3849 i
.vex
.bytes
[0] = 0xc4;
3854 i
.vex
.bytes
[0] = 0x8f;
3860 /* The high 3 bits of the second VEX byte are 1's compliment
3861 of RXB bits from REX. */
3862 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3863 | (!dot_insn () ? i
.tm
.opcode_space
3864 : i
.insn_opcode_space
);
3866 i
.vex
.bytes
[2] = (w
<< 7
3867 | register_specifier
<< 3
3868 | vector_length
<< 2
3869 | i
.tm
.opcode_modifier
.opcodeprefix
);
3874 is_evex_encoding (const insn_template
*t
)
3876 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3877 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3878 || t
->opcode_modifier
.sae
;
3882 is_any_vex_encoding (const insn_template
*t
)
3884 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3888 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3890 unsigned int op
, bytes
;
3891 const i386_operand_type
*types
;
3893 if (i
.broadcast
.type
)
3894 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3896 gas_assert (intel_syntax
);
3898 for (op
= 0; op
< t
->operands
; ++op
)
3899 if (t
->operand_types
[op
].bitfield
.baseindex
)
3902 gas_assert (op
< t
->operands
);
3904 if (t
->opcode_modifier
.evex
3905 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3906 switch (i
.broadcast
.bytes
)
3909 if (t
->operand_types
[op
].bitfield
.word
)
3913 if (t
->operand_types
[op
].bitfield
.dword
)
3917 if (t
->operand_types
[op
].bitfield
.qword
)
3921 if (t
->operand_types
[op
].bitfield
.xmmword
)
3923 if (t
->operand_types
[op
].bitfield
.ymmword
)
3925 if (t
->operand_types
[op
].bitfield
.zmmword
)
3932 gas_assert (op
+ 1 < t
->operands
);
3934 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3935 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3936 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3938 types
= &i
.types
[op
+ 1];
3941 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3942 types
= &t
->operand_types
[op
];
3944 if (types
->bitfield
.zmmword
)
3946 else if (types
->bitfield
.ymmword
)
3952 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3953 insn_name (t
), bytes
* 8);
3958 /* Build the EVEX prefix. */
3961 build_evex_prefix (void)
3963 unsigned int register_specifier
, w
;
3964 rex_byte vrex_used
= 0;
3966 /* Check register specifier. */
3967 if (i
.vex
.register_specifier
)
3969 gas_assert ((i
.vrex
& REX_X
) == 0);
3971 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3972 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3973 register_specifier
+= 8;
3974 /* The upper 16 registers are encoded in the fourth byte of the
3976 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3977 i
.vex
.bytes
[3] = 0x8;
3978 register_specifier
= ~register_specifier
& 0xf;
3982 register_specifier
= 0xf;
3984 /* Encode upper 16 vector index register in the fourth byte of
3986 if (!(i
.vrex
& REX_X
))
3987 i
.vex
.bytes
[3] = 0x8;
3992 /* 4 byte EVEX prefix. */
3994 i
.vex
.bytes
[0] = 0x62;
3996 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3998 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3999 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
4000 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4001 | (!dot_insn () ? i
.tm
.opcode_space
4002 : i
.insn_opcode_space
);
4004 /* The fifth bit of the second EVEX byte is 1's compliment of the
4005 REX_R bit in VREX. */
4006 if (!(i
.vrex
& REX_R
))
4007 i
.vex
.bytes
[1] |= 0x10;
4011 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4013 /* When all operands are registers, the REX_X bit in REX is not
4014 used. We reuse it to encode the upper 16 registers, which is
4015 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4016 as 1's compliment. */
4017 if ((i
.vrex
& REX_B
))
4020 i
.vex
.bytes
[1] &= ~0x40;
4024 /* EVEX instructions shouldn't need the REX prefix. */
4025 i
.vrex
&= ~vrex_used
;
4026 gas_assert (i
.vrex
== 0);
4028 /* Check the REX.W bit and VEXW. */
4029 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4030 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4031 else if (i
.tm
.opcode_modifier
.vexw
)
4032 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4034 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4036 /* The third byte of the EVEX prefix. */
4037 i
.vex
.bytes
[2] = ((w
<< 7)
4038 | (register_specifier
<< 3)
4039 | 4 /* Encode the U bit. */
4040 | i
.tm
.opcode_modifier
.opcodeprefix
);
4042 /* The fourth byte of the EVEX prefix. */
4043 /* The zeroing-masking bit. */
4044 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4045 i
.vex
.bytes
[3] |= 0x80;
4047 /* Don't always set the broadcast bit if there is no RC. */
4048 if (i
.rounding
.type
== rc_none
)
4050 /* Encode the vector length. */
4051 unsigned int vec_length
;
4053 if (!i
.tm
.opcode_modifier
.evex
4054 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4058 /* Determine vector length from the last multi-length vector
4060 for (op
= i
.operands
; op
--;)
4061 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4062 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4063 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4065 if (i
.types
[op
].bitfield
.zmmword
)
4067 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4070 else if (i
.types
[op
].bitfield
.ymmword
)
4072 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4075 else if (i
.types
[op
].bitfield
.xmmword
)
4077 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4080 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4081 && op
== i
.broadcast
.operand
)
4083 switch (get_broadcast_bytes (&i
.tm
, true))
4086 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4089 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4092 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4101 if (op
>= MAX_OPERANDS
)
4105 switch (i
.tm
.opcode_modifier
.evex
)
4107 case EVEXLIG
: /* LL' is ignored */
4108 vec_length
= evexlig
<< 5;
4111 vec_length
= 0 << 5;
4114 vec_length
= 1 << 5;
4117 vec_length
= 2 << 5;
4122 vec_length
= 3 << 5;
4130 i
.vex
.bytes
[3] |= vec_length
;
4131 /* Encode the broadcast bit. */
4132 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4133 i
.vex
.bytes
[3] |= 0x10;
4135 else if (i
.rounding
.type
!= saeonly
)
4136 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4138 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4141 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4145 process_immext (void)
4149 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4150 which is coded in the same place as an 8-bit immediate field
4151 would be. Here we fake an 8-bit immediate operand from the
4152 opcode suffix stored in tm.extension_opcode.
4154 AVX instructions also use this encoding, for some of
4155 3 argument instructions. */
4157 gas_assert (i
.imm_operands
<= 1
4159 || (is_any_vex_encoding (&i
.tm
)
4160 && i
.operands
<= 4)));
4162 exp
= &im_expressions
[i
.imm_operands
++];
4163 i
.op
[i
.operands
].imms
= exp
;
4164 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4166 exp
->X_op
= O_constant
;
4167 exp
->X_add_number
= i
.tm
.extension_opcode
;
4168 i
.tm
.extension_opcode
= None
;
4175 switch (i
.tm
.opcode_modifier
.prefixok
)
4183 as_bad (_("invalid instruction `%s' after `%s'"),
4184 insn_name (&i
.tm
), i
.hle_prefix
);
4187 if (i
.prefix
[LOCK_PREFIX
])
4189 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4193 case PrefixHLERelease
:
4194 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4196 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4200 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4202 as_bad (_("memory destination needed for instruction `%s'"
4203 " after `xrelease'"), insn_name (&i
.tm
));
4210 /* Encode aligned vector move as unaligned vector move. */
4213 encode_with_unaligned_vector_move (void)
4215 switch (i
.tm
.base_opcode
)
4217 case 0x28: /* Load instructions. */
4218 case 0x29: /* Store instructions. */
4219 /* movaps/movapd/vmovaps/vmovapd. */
4220 if (i
.tm
.opcode_space
== SPACE_0F
4221 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4222 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4224 case 0x6f: /* Load instructions. */
4225 case 0x7f: /* Store instructions. */
4226 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4227 if (i
.tm
.opcode_space
== SPACE_0F
4228 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4229 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4236 /* Try the shortest encoding by shortening operand size. */
4239 optimize_encoding (void)
4243 if (i
.tm
.mnem_off
== MN_lea
)
4246 lea symbol, %rN -> mov $symbol, %rN
4247 lea (%rM), %rN -> mov %rM, %rN
4248 lea (,%rM,1), %rN -> mov %rM, %rN
4250 and in 32-bit mode for 16-bit addressing
4252 lea (%rM), %rN -> movzx %rM, %rN
4254 and in 64-bit mode zap 32-bit addressing in favor of using a
4255 32-bit (or less) destination.
4257 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4259 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4260 i
.tm
.opcode_modifier
.size
= SIZE32
;
4261 i
.prefix
[ADDR_PREFIX
] = 0;
4264 if (!i
.index_reg
&& !i
.base_reg
)
4267 lea symbol, %rN -> mov $symbol, %rN
4269 if (flag_code
== CODE_64BIT
)
4271 /* Don't transform a relocation to a 16-bit one. */
4273 && i
.op
[0].disps
->X_op
!= O_constant
4274 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4277 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4278 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4280 i
.tm
.base_opcode
= 0xb8;
4281 i
.tm
.opcode_modifier
.modrm
= 0;
4282 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4283 i
.types
[0].bitfield
.imm32
= 1;
4286 i
.tm
.opcode_modifier
.size
= SIZE16
;
4287 i
.types
[0].bitfield
.imm16
= 1;
4292 /* Subject to further optimization below. */
4293 i
.tm
.base_opcode
= 0xc7;
4294 i
.tm
.extension_opcode
= 0;
4295 i
.types
[0].bitfield
.imm32s
= 1;
4296 i
.types
[0].bitfield
.baseindex
= 0;
4299 /* Outside of 64-bit mode address and operand sizes have to match if
4300 a relocation is involved, as otherwise we wouldn't (currently) or
4301 even couldn't express the relocation correctly. */
4302 else if (i
.op
[0].disps
4303 && i
.op
[0].disps
->X_op
!= O_constant
4304 && ((!i
.prefix
[ADDR_PREFIX
])
4305 != (flag_code
== CODE_32BIT
4306 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4307 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4309 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4310 destination is going to grow encoding size. */
4311 else if (flag_code
== CODE_16BIT
4312 && (optimize
<= 1 || optimize_for_space
)
4313 && !i
.prefix
[ADDR_PREFIX
]
4314 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4318 i
.tm
.base_opcode
= 0xb8;
4319 i
.tm
.opcode_modifier
.modrm
= 0;
4320 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4321 i
.types
[0].bitfield
.imm32
= 1;
4323 i
.types
[0].bitfield
.imm16
= 1;
4326 && i
.op
[0].disps
->X_op
== O_constant
4327 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4328 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4330 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4331 i
.op
[0].disps
->X_add_number
&= 0xffff;
4334 i
.tm
.operand_types
[0] = i
.types
[0];
4338 i
.op
[0].imms
= &im_expressions
[0];
4339 i
.op
[0].imms
->X_op
= O_absent
;
4342 else if (i
.op
[0].disps
4343 && (i
.op
[0].disps
->X_op
!= O_constant
4344 || i
.op
[0].disps
->X_add_number
))
4349 lea (%rM), %rN -> mov %rM, %rN
4350 lea (,%rM,1), %rN -> mov %rM, %rN
4351 lea (%rM), %rN -> movzx %rM, %rN
4353 const reg_entry
*addr_reg
;
4355 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4356 addr_reg
= i
.base_reg
;
4357 else if (!i
.base_reg
4358 && i
.index_reg
->reg_num
!= RegIZ
4359 && !i
.log2_scale_factor
)
4360 addr_reg
= i
.index_reg
;
4364 if (addr_reg
->reg_type
.bitfield
.word
4365 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4367 if (flag_code
!= CODE_32BIT
)
4369 i
.tm
.opcode_space
= SPACE_0F
;
4370 i
.tm
.base_opcode
= 0xb7;
4373 i
.tm
.base_opcode
= 0x8b;
4375 if (addr_reg
->reg_type
.bitfield
.dword
4376 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4377 i
.tm
.opcode_modifier
.size
= SIZE32
;
4379 i
.op
[0].regs
= addr_reg
;
4384 i
.disp_operands
= 0;
4385 i
.prefix
[ADDR_PREFIX
] = 0;
4386 i
.prefix
[SEG_PREFIX
] = 0;
4390 if (optimize_for_space
4391 && i
.tm
.mnem_off
== MN_test
4392 && i
.reg_operands
== 1
4393 && i
.imm_operands
== 1
4394 && !i
.types
[1].bitfield
.byte
4395 && i
.op
[0].imms
->X_op
== O_constant
4396 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4399 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4401 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4402 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4404 i
.types
[1].bitfield
.byte
= 1;
4405 /* Ignore the suffix. */
4407 /* Convert to byte registers. */
4408 if (i
.types
[1].bitfield
.word
)
4410 else if (i
.types
[1].bitfield
.dword
)
4414 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4419 else if (flag_code
== CODE_64BIT
4420 && i
.tm
.opcode_space
== SPACE_BASE
4421 && ((i
.types
[1].bitfield
.qword
4422 && i
.reg_operands
== 1
4423 && i
.imm_operands
== 1
4424 && i
.op
[0].imms
->X_op
== O_constant
4425 && ((i
.tm
.base_opcode
== 0xb8
4426 && i
.tm
.extension_opcode
== None
4427 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4428 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4429 && (i
.tm
.base_opcode
== 0x24
4430 || (i
.tm
.base_opcode
== 0x80
4431 && i
.tm
.extension_opcode
== 0x4)
4432 || i
.tm
.mnem_off
== MN_test
4433 || ((i
.tm
.base_opcode
| 1) == 0xc7
4434 && i
.tm
.extension_opcode
== 0x0)))
4435 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4436 && i
.tm
.base_opcode
== 0x83
4437 && i
.tm
.extension_opcode
== 0x4)))
4438 || (i
.types
[0].bitfield
.qword
4439 && ((i
.reg_operands
== 2
4440 && i
.op
[0].regs
== i
.op
[1].regs
4441 && (i
.tm
.mnem_off
== MN_xor
4442 || i
.tm
.mnem_off
== MN_sub
))
4443 || i
.tm
.mnem_off
== MN_clr
))))
4446 andq $imm31, %r64 -> andl $imm31, %r32
4447 andq $imm7, %r64 -> andl $imm7, %r32
4448 testq $imm31, %r64 -> testl $imm31, %r32
4449 xorq %r64, %r64 -> xorl %r32, %r32
4450 subq %r64, %r64 -> subl %r32, %r32
4451 movq $imm31, %r64 -> movl $imm31, %r32
4452 movq $imm32, %r64 -> movl $imm32, %r32
4454 i
.tm
.opcode_modifier
.size
= SIZE32
;
4457 i
.types
[0].bitfield
.imm32
= 1;
4458 i
.types
[0].bitfield
.imm32s
= 0;
4459 i
.types
[0].bitfield
.imm64
= 0;
4463 i
.types
[0].bitfield
.dword
= 1;
4464 i
.types
[0].bitfield
.qword
= 0;
4466 i
.types
[1].bitfield
.dword
= 1;
4467 i
.types
[1].bitfield
.qword
= 0;
4468 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4471 movq $imm31, %r64 -> movl $imm31, %r32
4472 movq $imm32, %r64 -> movl $imm32, %r32
4474 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4475 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4476 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4477 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4480 movq $imm31, %r64 -> movl $imm31, %r32
4482 i
.tm
.base_opcode
= 0xb8;
4483 i
.tm
.extension_opcode
= None
;
4484 i
.tm
.opcode_modifier
.w
= 0;
4485 i
.tm
.opcode_modifier
.modrm
= 0;
4489 else if (optimize
> 1
4490 && !optimize_for_space
4491 && i
.reg_operands
== 2
4492 && i
.op
[0].regs
== i
.op
[1].regs
4493 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4494 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4497 andb %rN, %rN -> testb %rN, %rN
4498 andw %rN, %rN -> testw %rN, %rN
4499 andq %rN, %rN -> testq %rN, %rN
4500 orb %rN, %rN -> testb %rN, %rN
4501 orw %rN, %rN -> testw %rN, %rN
4502 orq %rN, %rN -> testq %rN, %rN
4504 and outside of 64-bit mode
4506 andl %rN, %rN -> testl %rN, %rN
4507 orl %rN, %rN -> testl %rN, %rN
4509 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4511 else if (i
.tm
.base_opcode
== 0xba
4512 && i
.tm
.opcode_space
== SPACE_0F
4513 && i
.reg_operands
== 1
4514 && i
.op
[0].imms
->X_op
== O_constant
4515 && i
.op
[0].imms
->X_add_number
>= 0)
4518 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4519 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4520 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4522 With <BT> one of bts, btr, and bts also:
4523 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4524 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4529 if (i
.tm
.extension_opcode
!= 4)
4531 if (i
.types
[1].bitfield
.qword
4532 && i
.op
[0].imms
->X_add_number
< 32
4533 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4534 i
.tm
.opcode_modifier
.size
= SIZE32
;
4537 if (i
.types
[1].bitfield
.word
4538 && i
.op
[0].imms
->X_add_number
< 16)
4539 i
.tm
.opcode_modifier
.size
= SIZE32
;
4542 if (i
.op
[0].imms
->X_add_number
< 16)
4543 i
.tm
.opcode_modifier
.size
= SIZE16
;
4547 else if (i
.reg_operands
== 3
4548 && i
.op
[0].regs
== i
.op
[1].regs
4549 && !i
.types
[2].bitfield
.xmmword
4550 && (i
.tm
.opcode_modifier
.vex
4551 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4552 && is_evex_encoding (&i
.tm
)
4553 && (i
.vec_encoding
!= vex_encoding_evex
4554 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4555 || is_cpu (&i
.tm
, CpuAVX512VL
)
4556 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4557 && i
.types
[2].bitfield
.ymmword
))))
4558 && i
.tm
.opcode_space
== SPACE_0F
4559 && ((i
.tm
.base_opcode
| 2) == 0x57
4560 || i
.tm
.base_opcode
== 0xdf
4561 || i
.tm
.base_opcode
== 0xef
4562 || (i
.tm
.base_opcode
| 3) == 0xfb
4563 || i
.tm
.base_opcode
== 0x42
4564 || i
.tm
.base_opcode
== 0x47))
4567 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4569 EVEX VOP %zmmM, %zmmM, %zmmN
4570 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4571 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4572 EVEX VOP %ymmM, %ymmM, %ymmN
4573 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4574 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4575 VEX VOP %ymmM, %ymmM, %ymmN
4576 -> VEX VOP %xmmM, %xmmM, %xmmN
4577 VOP, one of vpandn and vpxor:
4578 VEX VOP %ymmM, %ymmM, %ymmN
4579 -> VEX VOP %xmmM, %xmmM, %xmmN
4580 VOP, one of vpandnd and vpandnq:
4581 EVEX VOP %zmmM, %zmmM, %zmmN
4582 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4583 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4584 EVEX VOP %ymmM, %ymmM, %ymmN
4585 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4586 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4587 VOP, one of vpxord and vpxorq:
4588 EVEX VOP %zmmM, %zmmM, %zmmN
4589 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4590 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4591 EVEX VOP %ymmM, %ymmM, %ymmN
4592 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4593 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4594 VOP, one of kxord and kxorq:
4595 VEX VOP %kM, %kM, %kN
4596 -> VEX kxorw %kM, %kM, %kN
4597 VOP, one of kandnd and kandnq:
4598 VEX VOP %kM, %kM, %kN
4599 -> VEX kandnw %kM, %kM, %kN
4601 if (is_evex_encoding (&i
.tm
))
4603 if (i
.vec_encoding
!= vex_encoding_evex
)
4605 i
.tm
.opcode_modifier
.vex
= VEX128
;
4606 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4607 i
.tm
.opcode_modifier
.evex
= 0;
4608 i
.vec_encoding
= vex_encoding_vex
;
4611 else if (optimize
> 1)
4612 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4616 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4618 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4619 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4622 i
.tm
.opcode_modifier
.vex
= VEX128
;
4624 if (i
.tm
.opcode_modifier
.vex
)
4625 for (j
= 0; j
< 3; j
++)
4627 i
.types
[j
].bitfield
.xmmword
= 1;
4628 i
.types
[j
].bitfield
.ymmword
= 0;
4631 else if (i
.vec_encoding
!= vex_encoding_evex
4632 && !i
.types
[0].bitfield
.zmmword
4633 && !i
.types
[1].bitfield
.zmmword
4635 && !i
.broadcast
.type
4636 && !i
.broadcast
.bytes
4637 && is_evex_encoding (&i
.tm
)
4638 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4639 || (i
.tm
.base_opcode
& ~4) == 0xdb
4640 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4641 && i
.tm
.extension_opcode
== None
)
4644 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4645 vmovdqu32 and vmovdqu64:
4646 EVEX VOP %xmmM, %xmmN
4647 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4648 EVEX VOP %ymmM, %ymmN
4649 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4651 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4653 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4655 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4657 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4658 VOP, one of vpand, vpandn, vpor, vpxor:
4659 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4660 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4661 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4662 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4663 EVEX VOP{d,q} mem, %xmmM, %xmmN
4664 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4665 EVEX VOP{d,q} mem, %ymmM, %ymmN
4666 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4668 for (j
= 0; j
< i
.operands
; j
++)
4669 if (operand_type_check (i
.types
[j
], disp
)
4670 && i
.op
[j
].disps
->X_op
== O_constant
)
4672 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4673 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4674 bytes, we choose EVEX Disp8 over VEX Disp32. */
4675 int evex_disp8
, vex_disp8
;
4676 unsigned int memshift
= i
.memshift
;
4677 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4679 evex_disp8
= fits_in_disp8 (n
);
4681 vex_disp8
= fits_in_disp8 (n
);
4682 if (evex_disp8
!= vex_disp8
)
4684 i
.memshift
= memshift
;
4688 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4691 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4692 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4693 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4694 i
.tm
.opcode_modifier
.vex
4695 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4696 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4697 /* VPAND, VPOR, and VPXOR are commutative. */
4698 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4699 i
.tm
.opcode_modifier
.commutative
= 1;
4700 i
.tm
.opcode_modifier
.evex
= 0;
4701 i
.tm
.opcode_modifier
.masking
= 0;
4702 i
.tm
.opcode_modifier
.broadcast
= 0;
4703 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4706 i
.types
[j
].bitfield
.disp8
4707 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4709 else if (optimize_for_space
4710 && i
.tm
.base_opcode
== 0x29
4711 && i
.tm
.opcode_space
== SPACE_0F38
4712 && i
.operands
== i
.reg_operands
4713 && i
.op
[0].regs
== i
.op
[1].regs
4714 && (!i
.tm
.opcode_modifier
.vex
4715 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4716 && !is_evex_encoding (&i
.tm
))
4719 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4720 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4721 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4723 i
.tm
.opcode_space
= SPACE_0F
;
4724 i
.tm
.base_opcode
= 0x76;
4726 else if (((i
.tm
.base_opcode
>= 0x64
4727 && i
.tm
.base_opcode
<= 0x66
4728 && i
.tm
.opcode_space
== SPACE_0F
)
4729 || (i
.tm
.base_opcode
== 0x37
4730 && i
.tm
.opcode_space
== SPACE_0F38
))
4731 && i
.operands
== i
.reg_operands
4732 && i
.op
[0].regs
== i
.op
[1].regs
4733 && !is_evex_encoding (&i
.tm
))
4736 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4737 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4738 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4739 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4740 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4741 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4743 i
.tm
.opcode_space
= SPACE_0F
;
4744 i
.tm
.base_opcode
= 0xef;
4745 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4747 if (i
.operands
== 2)
4749 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4755 i
.op
[2].regs
= i
.op
[0].regs
;
4756 i
.types
[2] = i
.types
[0];
4757 i
.flags
[2] = i
.flags
[0];
4758 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4760 i
.tm
.opcode_modifier
.sse2avx
= 0;
4762 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4763 i
.op
[1].regs
= i
.op
[0].regs
;
4766 else if (optimize_for_space
4767 && i
.tm
.base_opcode
== 0x59
4768 && i
.tm
.opcode_space
== SPACE_0F38
4769 && i
.operands
== i
.reg_operands
4770 && i
.tm
.opcode_modifier
.vex
4771 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4772 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4773 && i
.vec_encoding
!= vex_encoding_vex3
)
4776 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4778 i
.tm
.opcode_space
= SPACE_0F
;
4779 i
.tm
.base_opcode
= 0x6c;
4780 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4786 i
.op
[2].regs
= i
.op
[0].regs
;
4787 i
.types
[2] = i
.types
[0];
4788 i
.flags
[2] = i
.flags
[0];
4789 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4791 swap_2_operands (1, 2);
4795 /* Return non-zero for load instruction. */
4801 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4802 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4806 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4807 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4808 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4812 if (i
.tm
.mnem_off
== MN_pop
)
4816 if (i
.tm
.opcode_space
== SPACE_BASE
)
4819 if (i
.tm
.base_opcode
== 0x9d
4820 || i
.tm
.base_opcode
== 0x61)
4823 /* movs, cmps, lods, scas. */
4824 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4828 if (base_opcode
== 0x6f
4829 || i
.tm
.base_opcode
== 0xd7)
4831 /* NB: For AMD-specific insns with implicit memory operands,
4832 they're intentionally not covered. */
4835 /* No memory operand. */
4836 if (!i
.mem_operands
)
4841 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4844 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4846 /* test, not, neg, mul, imul, div, idiv. */
4847 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4851 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4854 /* add, or, adc, sbb, and, sub, xor, cmp. */
4855 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4858 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4859 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4860 && i
.tm
.extension_opcode
!= 6)
4863 /* Check for x87 instructions. */
4864 if ((base_opcode
| 6) == 0xdf)
4866 /* Skip fst, fstp, fstenv, fstcw. */
4867 if (i
.tm
.base_opcode
== 0xd9
4868 && (i
.tm
.extension_opcode
== 2
4869 || i
.tm
.extension_opcode
== 3
4870 || i
.tm
.extension_opcode
== 6
4871 || i
.tm
.extension_opcode
== 7))
4874 /* Skip fisttp, fist, fistp, fstp. */
4875 if (i
.tm
.base_opcode
== 0xdb
4876 && (i
.tm
.extension_opcode
== 1
4877 || i
.tm
.extension_opcode
== 2
4878 || i
.tm
.extension_opcode
== 3
4879 || i
.tm
.extension_opcode
== 7))
4882 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4883 if (i
.tm
.base_opcode
== 0xdd
4884 && (i
.tm
.extension_opcode
== 1
4885 || i
.tm
.extension_opcode
== 2
4886 || i
.tm
.extension_opcode
== 3
4887 || i
.tm
.extension_opcode
== 6
4888 || i
.tm
.extension_opcode
== 7))
4891 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4892 if (i
.tm
.base_opcode
== 0xdf
4893 && (i
.tm
.extension_opcode
== 1
4894 || i
.tm
.extension_opcode
== 2
4895 || i
.tm
.extension_opcode
== 3
4896 || i
.tm
.extension_opcode
== 6
4897 || i
.tm
.extension_opcode
== 7))
4903 else if (i
.tm
.opcode_space
== SPACE_0F
)
4905 /* bt, bts, btr, btc. */
4906 if (i
.tm
.base_opcode
== 0xba
4907 && (i
.tm
.extension_opcode
| 3) == 7)
4910 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4911 if (i
.tm
.base_opcode
== 0xc7
4912 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4913 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4914 || i
.tm
.extension_opcode
== 6))
4917 /* fxrstor, ldmxcsr, xrstor. */
4918 if (i
.tm
.base_opcode
== 0xae
4919 && (i
.tm
.extension_opcode
== 1
4920 || i
.tm
.extension_opcode
== 2
4921 || i
.tm
.extension_opcode
== 5))
4924 /* lgdt, lidt, lmsw. */
4925 if (i
.tm
.base_opcode
== 0x01
4926 && (i
.tm
.extension_opcode
== 2
4927 || i
.tm
.extension_opcode
== 3
4928 || i
.tm
.extension_opcode
== 6))
4932 dest
= i
.operands
- 1;
4934 /* Check fake imm8 operand and 3 source operands. */
4935 if ((i
.tm
.opcode_modifier
.immext
4936 || i
.reg_operands
+ i
.mem_operands
== 4)
4937 && i
.types
[dest
].bitfield
.imm8
)
4940 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4941 if (i
.tm
.opcode_space
== SPACE_BASE
4942 && ((base_opcode
| 0x38) == 0x39
4943 || (base_opcode
| 2) == 0x87))
4946 if (i
.tm
.mnem_off
== MN_xadd
)
4949 /* Check for load instruction. */
4950 return (i
.types
[dest
].bitfield
.class != ClassNone
4951 || i
.types
[dest
].bitfield
.instance
== Accum
);
4954 /* Output lfence, 0xfaee8, after instruction. */
4957 insert_lfence_after (void)
4959 if (lfence_after_load
&& load_insn_p ())
4961 /* There are also two REP string instructions that require
4962 special treatment. Specifically, the compare string (CMPS)
4963 and scan string (SCAS) instructions set EFLAGS in a manner
4964 that depends on the data being compared/scanned. When used
4965 with a REP prefix, the number of iterations may therefore
4966 vary depending on this data. If the data is a program secret
4967 chosen by the adversary using an LVI method,
4968 then this data-dependent behavior may leak some aspect
4970 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4971 && i
.prefix
[REP_PREFIX
])
4973 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4976 char *p
= frag_more (3);
4983 /* Output lfence, 0xfaee8, before instruction. */
4986 insert_lfence_before (void)
4990 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4993 if (i
.tm
.base_opcode
== 0xff
4994 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4996 /* Insert lfence before indirect branch if needed. */
4998 if (lfence_before_indirect_branch
== lfence_branch_none
)
5001 if (i
.operands
!= 1)
5004 if (i
.reg_operands
== 1)
5006 /* Indirect branch via register. Don't insert lfence with
5007 -mlfence-after-load=yes. */
5008 if (lfence_after_load
5009 || lfence_before_indirect_branch
== lfence_branch_memory
)
5012 else if (i
.mem_operands
== 1
5013 && lfence_before_indirect_branch
!= lfence_branch_register
)
5015 as_warn (_("indirect `%s` with memory operand should be avoided"),
5022 if (last_insn
.kind
!= last_insn_other
5023 && last_insn
.seg
== now_seg
)
5025 as_warn_where (last_insn
.file
, last_insn
.line
,
5026 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5027 last_insn
.name
, insn_name (&i
.tm
));
5038 /* Output or/not/shl and lfence before near ret. */
5039 if (lfence_before_ret
!= lfence_before_ret_none
5040 && (i
.tm
.base_opcode
| 1) == 0xc3)
5042 if (last_insn
.kind
!= last_insn_other
5043 && last_insn
.seg
== now_seg
)
5045 as_warn_where (last_insn
.file
, last_insn
.line
,
5046 _("`%s` skips -mlfence-before-ret on `%s`"),
5047 last_insn
.name
, insn_name (&i
.tm
));
5051 /* Near ret ingore operand size override under CPU64. */
5052 char prefix
= flag_code
== CODE_64BIT
5054 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5056 if (lfence_before_ret
== lfence_before_ret_not
)
5058 /* not: 0xf71424, may add prefix
5059 for operand size override or 64-bit code. */
5060 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5074 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5077 if (lfence_before_ret
== lfence_before_ret_or
)
5079 /* or: 0x830c2400, may add prefix
5080 for operand size override or 64-bit code. */
5086 /* shl: 0xc1242400, may add prefix
5087 for operand size override or 64-bit code. */
5102 /* Shared helper for md_assemble() and s_insn(). */
5103 static void init_globals (void)
5107 memset (&i
, '\0', sizeof (i
));
5108 i
.rounding
.type
= rc_none
;
5109 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5110 i
.reloc
[j
] = NO_RELOC
;
5111 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5112 memset (im_expressions
, '\0', sizeof (im_expressions
));
5113 save_stack_p
= save_stack
;
5116 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5117 parsing pass. Instead of introducing a rarely use new insn attribute this
5118 utilizes a common pattern between affected templates. It is deemed
5119 acceptable that this will lead to unnecessary pass 2 preparations in a
5120 limited set of cases. */
5121 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5123 return t
->opcode_modifier
.sse2avx
5124 /* Note that all SSE2AVX templates have at least one operand. */
5125 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5126 : (t
->opcode_space
== SPACE_0F
5127 && (t
->base_opcode
| 1) == 0xbf)
5128 || (t
->opcode_space
== SPACE_BASE
5129 && t
->base_opcode
== 0x63);
5132 /* This is the guts of the machine-dependent assembler. LINE points to a
5133 machine dependent instruction. This function is supposed to emit
5134 the frags/bytes it assembles to. */
5137 md_assemble (char *line
)
5140 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5141 const char *end
, *pass1_mnem
= NULL
;
5142 enum i386_error pass1_err
= 0;
5143 const insn_template
*t
;
5145 /* Initialize globals. */
5146 current_templates
= NULL
;
5150 /* First parse an instruction mnemonic & call i386_operand for the operands.
5151 We assume that the scrubber has arranged it so that line[0] is the valid
5152 start of a (possibly prefixed) mnemonic. */
5154 end
= parse_insn (line
, mnemonic
, false);
5157 if (pass1_mnem
!= NULL
)
5159 if (i
.error
!= no_error
)
5161 gas_assert (current_templates
!= NULL
);
5162 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5164 /* No point in trying a 2nd pass - it'll only find the same suffix
5166 mnem_suffix
= i
.suffix
;
5171 t
= current_templates
->start
;
5172 if (may_need_pass2 (t
))
5174 /* Make a copy of the full line in case we need to retry. */
5175 copy
= xstrdup (line
);
5178 mnem_suffix
= i
.suffix
;
5180 line
= parse_operands (line
, mnemonic
);
5188 /* Now we've parsed the mnemonic into a set of templates, and have the
5189 operands at hand. */
5191 /* All Intel opcodes have reversed operands except for "bound", "enter",
5192 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5193 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5194 intersegment "jmp" and "call" instructions with 2 immediate operands so
5195 that the immediate segment precedes the offset consistently in Intel and
5199 && (t
->mnem_off
!= MN_bound
)
5200 && !startswith (mnemonic
, "invlpg")
5201 && !startswith (mnemonic
, "monitor")
5202 && !startswith (mnemonic
, "mwait")
5203 && (t
->mnem_off
!= MN_pvalidate
)
5204 && !startswith (mnemonic
, "rmp")
5205 && (t
->mnem_off
!= MN_tpause
)
5206 && (t
->mnem_off
!= MN_umwait
)
5207 && !(i
.operands
== 2
5208 && operand_type_check (i
.types
[0], imm
)
5209 && operand_type_check (i
.types
[1], imm
)))
5212 /* The order of the immediates should be reversed
5213 for 2 immediates extrq and insertq instructions */
5214 if (i
.imm_operands
== 2
5215 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5216 swap_2_operands (0, 1);
5220 /* For USER_MSR instructions, imm32 stands for the name of an model specific
5221 register (MSR). That's an unsigned quantity, whereas all other insns with
5222 32-bit immediate and 64-bit operand size use sign-extended
5223 immediates (imm32s). Therefore these insns are special-cased, bypassing
5224 the normal handling of immediates here. */
5225 if (is_cpu(current_templates
->start
, CpuUSER_MSR
))
5227 for (j
= 0; j
< i
.operands
; j
++)
5229 if (operand_type_check(i
.types
[j
], imm
))
5230 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
5237 if (i
.disp_operands
&& !optimize_disp (t
))
5240 /* Next, we find a template that matches the given insn,
5241 making sure the overlap of the given operands types is consistent
5242 with the template operand types. */
5244 if (!(t
= match_template (mnem_suffix
)))
5246 const char *err_msg
;
5248 if (copy
&& !mnem_suffix
)
5253 pass1_err
= i
.error
;
5254 pass1_mnem
= insn_name (current_templates
->start
);
5258 /* If a non-/only-64bit template (group) was found in pass 1, and if
5259 _some_ template (group) was found in pass 2, squash pass 1's
5261 if (pass1_err
== unsupported_64bit
)
5267 switch (pass1_mnem
? pass1_err
: i
.error
)
5271 case operand_size_mismatch
:
5272 err_msg
= _("operand size mismatch");
5274 case operand_type_mismatch
:
5275 err_msg
= _("operand type mismatch");
5277 case register_type_mismatch
:
5278 err_msg
= _("register type mismatch");
5280 case number_of_operands_mismatch
:
5281 err_msg
= _("number of operands mismatch");
5283 case invalid_instruction_suffix
:
5284 err_msg
= _("invalid instruction suffix");
5287 err_msg
= _("constant doesn't fit in 4 bits");
5289 case unsupported_with_intel_mnemonic
:
5290 err_msg
= _("unsupported with Intel mnemonic");
5292 case unsupported_syntax
:
5293 err_msg
= _("unsupported syntax");
5296 as_bad (_("unsupported instruction `%s'"),
5297 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5299 case unsupported_on_arch
:
5300 as_bad (_("`%s' is not supported on `%s%s'"),
5301 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5302 cpu_arch_name
? cpu_arch_name
: default_arch
,
5303 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5305 case unsupported_64bit
:
5306 if (ISLOWER (mnem_suffix
))
5308 if (flag_code
== CODE_64BIT
)
5309 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5310 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5313 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5314 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5319 if (flag_code
== CODE_64BIT
)
5320 as_bad (_("`%s' is not supported in 64-bit mode"),
5321 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5323 as_bad (_("`%s' is only supported in 64-bit mode"),
5324 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5327 case invalid_sib_address
:
5328 err_msg
= _("invalid SIB address");
5330 case invalid_vsib_address
:
5331 err_msg
= _("invalid VSIB address");
5333 case invalid_vector_register_set
:
5334 err_msg
= _("mask, index, and destination registers must be distinct");
5336 case invalid_tmm_register_set
:
5337 err_msg
= _("all tmm registers must be distinct");
5339 case invalid_dest_and_src_register_set
:
5340 err_msg
= _("destination and source registers must be distinct");
5342 case unsupported_vector_index_register
:
5343 err_msg
= _("unsupported vector index register");
5345 case unsupported_broadcast
:
5346 err_msg
= _("unsupported broadcast");
5348 case broadcast_needed
:
5349 err_msg
= _("broadcast is needed for operand of such type");
5351 case unsupported_masking
:
5352 err_msg
= _("unsupported masking");
5354 case mask_not_on_destination
:
5355 err_msg
= _("mask not on destination operand");
5357 case no_default_mask
:
5358 err_msg
= _("default mask isn't allowed");
5360 case unsupported_rc_sae
:
5361 err_msg
= _("unsupported static rounding/sae");
5363 case invalid_register_operand
:
5364 err_msg
= _("invalid register operand");
5366 case internal_error
:
5367 err_msg
= _("internal error");
5370 as_bad (_("%s for `%s'"), err_msg
,
5371 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5377 if (sse_check
!= check_none
5378 /* The opcode space check isn't strictly needed; it's there only to
5379 bypass the logic below when easily possible. */
5380 && t
->opcode_space
>= SPACE_0F
5381 && t
->opcode_space
<= SPACE_0F3A
5382 && !is_cpu (&i
.tm
, CpuSSE4a
)
5383 && !is_any_vex_encoding (t
))
5387 for (j
= 0; j
< t
->operands
; ++j
)
5389 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5391 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5395 if (j
>= t
->operands
&& simd
)
5396 (sse_check
== check_warning
5398 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5401 if (i
.tm
.opcode_modifier
.fwait
)
5402 if (!add_prefix (FWAIT_OPCODE
))
5405 /* Check if REP prefix is OK. */
5406 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5408 as_bad (_("invalid instruction `%s' after `%s'"),
5409 insn_name (&i
.tm
), i
.rep_prefix
);
5413 /* Check for lock without a lockable instruction. Destination operand
5414 must be memory unless it is xchg (0x86). */
5415 if (i
.prefix
[LOCK_PREFIX
])
5417 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5418 || i
.mem_operands
== 0
5419 || (i
.tm
.base_opcode
!= 0x86
5420 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5422 as_bad (_("expecting lockable instruction after `lock'"));
5426 /* Zap the redundant prefix from XCHG when optimizing. */
5427 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5428 i
.prefix
[LOCK_PREFIX
] = 0;
5431 if (is_any_vex_encoding (&i
.tm
)
5432 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5433 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5435 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5436 if (i
.prefix
[DATA_PREFIX
])
5438 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5442 /* Don't allow e.g. KMOV in TLS code sequences. */
5443 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5446 case BFD_RELOC_386_TLS_GOTIE
:
5447 case BFD_RELOC_386_TLS_LE_32
:
5448 case BFD_RELOC_X86_64_GOTTPOFF
:
5449 case BFD_RELOC_X86_64_TLSLD
:
5450 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5457 /* Check if HLE prefix is OK. */
5458 if (i
.hle_prefix
&& !check_hle ())
5461 /* Check BND prefix. */
5462 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5463 as_bad (_("expecting valid branch instruction after `bnd'"));
5465 /* Check NOTRACK prefix. */
5466 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5467 as_bad (_("expecting indirect branch instruction after `notrack'"));
5469 if (is_cpu (&i
.tm
, CpuMPX
))
5471 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5472 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5473 else if (flag_code
!= CODE_16BIT
5474 ? i
.prefix
[ADDR_PREFIX
]
5475 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5476 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5479 /* Insert BND prefix. */
5480 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5482 if (!i
.prefix
[BND_PREFIX
])
5483 add_prefix (BND_PREFIX_OPCODE
);
5484 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5486 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5487 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5491 /* Check string instruction segment overrides. */
5492 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5494 gas_assert (i
.mem_operands
);
5495 if (!check_string ())
5497 i
.disp_operands
= 0;
5500 /* The memory operand of (%dx) should be only used with input/output
5501 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5502 if (i
.input_output_operand
5503 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5504 || i
.tm
.opcode_space
!= SPACE_BASE
))
5506 as_bad (_("input/output port address isn't allowed with `%s'"),
5511 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5512 optimize_encoding ();
5514 /* Past optimization there's no need to distinguish vex_encoding_evex and
5515 vex_encoding_evex512 anymore. */
5516 if (i
.vec_encoding
== vex_encoding_evex512
)
5517 i
.vec_encoding
= vex_encoding_evex
;
5519 if (use_unaligned_vector_move
)
5520 encode_with_unaligned_vector_move ();
5522 if (!process_suffix ())
5525 /* Check if IP-relative addressing requirements can be satisfied. */
5526 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5527 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5528 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5530 /* Update operand types and check extended states. */
5531 for (j
= 0; j
< i
.operands
; j
++)
5533 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5534 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5539 i
.xstate
|= xstate_mmx
;
5542 i
.xstate
|= xstate_mask
;
5545 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5546 i
.xstate
|= xstate_tmm
;
5547 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5548 && !i
.tm
.opcode_modifier
.vex
5549 && vector_size
>= VSZ512
)
5550 i
.xstate
|= xstate_zmm
;
5551 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5552 && vector_size
>= VSZ256
)
5553 i
.xstate
|= xstate_ymm
;
5554 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5555 i
.xstate
|= xstate_xmm
;
5560 /* Make still unresolved immediate matches conform to size of immediate
5561 given in i.suffix. */
5562 if (!finalize_imm ())
5565 if (i
.types
[0].bitfield
.imm1
)
5566 i
.imm_operands
= 0; /* kludge for shift insns. */
5568 /* For insns with operands there are more diddles to do to the opcode. */
5571 if (!process_operands ())
5574 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5576 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5577 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5580 if (is_any_vex_encoding (&i
.tm
))
5582 if (!cpu_arch_flags
.bitfield
.cpui286
)
5584 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5589 /* Check for explicit REX prefix. */
5590 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5592 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5596 if (i
.tm
.opcode_modifier
.vex
)
5597 build_vex_prefix (t
);
5599 build_evex_prefix ();
5601 /* The individual REX.RXBW bits got consumed. */
5602 i
.rex
&= REX_OPCODE
;
5605 /* Handle conversion of 'int $3' --> special int3 insn. */
5606 if (i
.tm
.mnem_off
== MN_int
5607 && i
.op
[0].imms
->X_add_number
== 3)
5609 i
.tm
.base_opcode
= INT3_OPCODE
;
5613 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5614 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5615 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5616 && i
.op
[0].disps
->X_op
== O_constant
)
5618 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5619 the absolute address given by the constant. Since ix86 jumps and
5620 calls are pc relative, we need to generate a reloc. */
5621 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5622 i
.op
[0].disps
->X_op
= O_symbol
;
5625 /* For 8 bit registers we need an empty rex prefix. Also if the
5626 instruction already has a prefix, we need to convert old
5627 registers to new ones. */
5629 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5630 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5631 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5632 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5633 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5634 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5639 i
.rex
|= REX_OPCODE
;
5640 for (x
= 0; x
< 2; x
++)
5642 /* Look for 8 bit operand that uses old registers. */
5643 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5644 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5646 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5647 /* In case it is "hi" register, give up. */
5648 if (i
.op
[x
].regs
->reg_num
> 3)
5649 as_bad (_("can't encode register '%s%s' in an "
5650 "instruction requiring REX prefix."),
5651 register_prefix
, i
.op
[x
].regs
->reg_name
);
5653 /* Otherwise it is equivalent to the extended register.
5654 Since the encoding doesn't change this is merely
5655 cosmetic cleanup for debug output. */
5657 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5662 if (i
.rex
== 0 && i
.rex_encoding
)
5664 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5665 that uses legacy register. If it is "hi" register, don't add
5666 the REX_OPCODE byte. */
5668 for (x
= 0; x
< 2; x
++)
5669 if (i
.types
[x
].bitfield
.class == Reg
5670 && i
.types
[x
].bitfield
.byte
5671 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5672 && i
.op
[x
].regs
->reg_num
> 3)
5674 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5675 i
.rex_encoding
= false;
5684 add_prefix (REX_OPCODE
| i
.rex
);
5686 insert_lfence_before ();
5688 /* We are ready to output the insn. */
5691 insert_lfence_after ();
5693 last_insn
.seg
= now_seg
;
5695 if (i
.tm
.opcode_modifier
.isprefix
)
5697 last_insn
.kind
= last_insn_prefix
;
5698 last_insn
.name
= insn_name (&i
.tm
);
5699 last_insn
.file
= as_where (&last_insn
.line
);
5702 last_insn
.kind
= last_insn_other
;
5705 /* The Q suffix is generally valid only in 64-bit mode, with very few
5706 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5707 and fisttp only one of their two templates is matched below: That's
5708 sufficient since other relevant attributes are the same between both
5709 respective templates. */
5710 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5712 return flag_code
== CODE_64BIT
5713 || (t
->opcode_space
== SPACE_BASE
5714 && t
->base_opcode
== 0xdf
5715 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5716 || t
->mnem_off
== MN_cmpxchg8b
;
5720 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5722 const char *l
= line
, *token_start
= l
;
5724 bool pass1
= !current_templates
;
5726 const insn_template
*t
;
5732 /* Pseudo-prefixes start with an opening figure brace. */
5733 if ((*mnem_p
= *l
) == '{')
5738 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5743 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5746 as_bad (_("no such instruction: `%s'"), token_start
);
5751 /* Pseudo-prefixes end with a closing figure brace. */
5752 if (*mnemonic
== '{' && *l
== '}')
5755 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5759 /* Point l at the closing brace if there's no other separator. */
5760 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5761 && *l
!= PREFIX_SEPARATOR
)
5764 else if (!is_space_char (*l
)
5765 && *l
!= END_OF_INSN
5767 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5771 as_bad (_("invalid character %s in mnemonic"),
5772 output_invalid (*l
));
5775 if (token_start
== l
)
5777 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5778 as_bad (_("expecting prefix; got nothing"));
5780 as_bad (_("expecting mnemonic; got nothing"));
5784 /* Look up instruction (or prefix) via hash table. */
5785 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5787 if (*l
!= END_OF_INSN
5788 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5789 && current_templates
5790 && current_templates
->start
->opcode_modifier
.isprefix
)
5792 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5794 as_bad ((flag_code
!= CODE_64BIT
5795 ? _("`%s' is only supported in 64-bit mode")
5796 : _("`%s' is not supported in 64-bit mode")),
5797 insn_name (current_templates
->start
));
5800 /* If we are in 16-bit mode, do not allow addr16 or data16.
5801 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5802 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5803 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5804 && flag_code
!= CODE_64BIT
5805 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5806 ^ (flag_code
== CODE_16BIT
)))
5808 as_bad (_("redundant %s prefix"),
5809 insn_name (current_templates
->start
));
5813 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5815 /* Handle pseudo prefixes. */
5816 switch (current_templates
->start
->extension_opcode
)
5820 i
.disp_encoding
= disp_encoding_8bit
;
5824 i
.disp_encoding
= disp_encoding_16bit
;
5828 i
.disp_encoding
= disp_encoding_32bit
;
5832 i
.dir_encoding
= dir_encoding_load
;
5836 i
.dir_encoding
= dir_encoding_store
;
5840 i
.vec_encoding
= vex_encoding_vex
;
5844 i
.vec_encoding
= vex_encoding_vex3
;
5848 i
.vec_encoding
= vex_encoding_evex
;
5852 i
.rex_encoding
= true;
5854 case Prefix_NoOptimize
:
5856 i
.no_optimize
= true;
5864 /* Add prefix, checking for repeated prefixes. */
5865 switch (add_prefix (current_templates
->start
->base_opcode
))
5870 if (is_cpu (current_templates
->start
, CpuIBT
))
5871 i
.notrack_prefix
= insn_name (current_templates
->start
);
5874 if (is_cpu (current_templates
->start
, CpuHLE
))
5875 i
.hle_prefix
= insn_name (current_templates
->start
);
5876 else if (is_cpu (current_templates
->start
, CpuMPX
))
5877 i
.bnd_prefix
= insn_name (current_templates
->start
);
5879 i
.rep_prefix
= insn_name (current_templates
->start
);
5885 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5895 if (!current_templates
)
5897 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5898 Check if we should swap operand or force 32bit displacement in
5900 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5901 i
.dir_encoding
= dir_encoding_swap
;
5902 else if (mnem_p
- 3 == dot_p
5905 i
.disp_encoding
= disp_encoding_8bit
;
5906 else if (mnem_p
- 4 == dot_p
5910 i
.disp_encoding
= disp_encoding_32bit
;
5915 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5918 if (!current_templates
|| !pass1
)
5920 current_templates
= NULL
;
5923 if (mnem_p
> mnemonic
)
5925 /* See if we can get a match by trimming off a suffix. */
5928 case WORD_MNEM_SUFFIX
:
5929 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5930 i
.suffix
= SHORT_MNEM_SUFFIX
;
5933 case BYTE_MNEM_SUFFIX
:
5934 case QWORD_MNEM_SUFFIX
:
5935 i
.suffix
= mnem_p
[-1];
5938 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5940 case SHORT_MNEM_SUFFIX
:
5941 case LONG_MNEM_SUFFIX
:
5944 i
.suffix
= mnem_p
[-1];
5947 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5955 if (intel_float_operand (mnemonic
) == 1)
5956 i
.suffix
= SHORT_MNEM_SUFFIX
;
5958 i
.suffix
= LONG_MNEM_SUFFIX
;
5961 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5963 /* For compatibility reasons accept MOVSD and CMPSD without
5964 operands even in AT&T mode. */
5965 else if (*l
== END_OF_INSN
5966 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5970 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5971 if (current_templates
!= NULL
5973 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5974 && current_templates
->start
->opcode_space
5976 && mnem_p
[-2] == 's')
5978 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5979 mnemonic
, mnemonic
);
5980 i
.suffix
= LONG_MNEM_SUFFIX
;
5984 current_templates
= NULL
;
5992 if (!current_templates
)
5995 as_bad (_("no such instruction: `%s'"), token_start
);
6000 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
6001 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
6003 /* Check for a branch hint. We allow ",pt" and ",pn" for
6004 predict taken and predict not taken respectively.
6005 I'm not sure that branch hints actually do anything on loop
6006 and jcxz insns (JumpByte) for current Pentium4 chips. They
6007 may work in the future and it doesn't hurt to accept them
6009 if (l
[0] == ',' && l
[1] == 'p')
6013 if (!add_prefix (DS_PREFIX_OPCODE
))
6017 else if (l
[2] == 'n')
6019 if (!add_prefix (CS_PREFIX_OPCODE
))
6025 /* Any other comma loses. */
6028 as_bad (_("invalid character %s in mnemonic"),
6029 output_invalid (*l
));
6033 /* Check if instruction is supported on specified architecture. */
6035 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6037 supported
|= cpu_flags_match (t
);
6039 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6040 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6042 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6048 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6049 i
.error
= unsupported_on_arch
;
6051 i
.error
= unsupported_64bit
;
6058 parse_operands (char *l
, const char *mnemonic
)
6062 /* 1 if operand is pending after ','. */
6063 unsigned int expecting_operand
= 0;
6065 while (*l
!= END_OF_INSN
)
6067 /* Non-zero if operand parens not balanced. */
6068 unsigned int paren_not_balanced
= 0;
6069 /* True if inside double quotes. */
6070 bool in_quotes
= false;
6072 /* Skip optional white space before operand. */
6073 if (is_space_char (*l
))
6075 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6077 as_bad (_("invalid character %s before operand %d"),
6078 output_invalid (*l
),
6082 token_start
= l
; /* After white space. */
6083 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6085 if (*l
== END_OF_INSN
)
6089 as_bad (_("unbalanced double quotes in operand %d."),
6093 if (paren_not_balanced
)
6095 know (!intel_syntax
);
6096 as_bad (_("unbalanced parenthesis in operand %d."),
6101 break; /* we are done */
6103 else if (*l
== '\\' && l
[1] == '"')
6106 in_quotes
= !in_quotes
;
6107 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6109 as_bad (_("invalid character %s in operand %d"),
6110 output_invalid (*l
),
6114 if (!intel_syntax
&& !in_quotes
)
6117 ++paren_not_balanced
;
6119 --paren_not_balanced
;
6123 if (l
!= token_start
)
6124 { /* Yes, we've read in another operand. */
6125 unsigned int operand_ok
;
6126 this_operand
= i
.operands
++;
6127 if (i
.operands
> MAX_OPERANDS
)
6129 as_bad (_("spurious operands; (%d operands/instruction max)"),
6133 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6134 /* Now parse operand adding info to 'i' as we go along. */
6135 END_STRING_AND_SAVE (l
);
6137 if (i
.mem_operands
> 1)
6139 as_bad (_("too many memory references for `%s'"),
6146 i386_intel_operand (token_start
,
6147 intel_float_operand (mnemonic
));
6149 operand_ok
= i386_att_operand (token_start
);
6151 RESTORE_END_STRING (l
);
6157 if (expecting_operand
)
6159 expecting_operand_after_comma
:
6160 as_bad (_("expecting operand after ','; got nothing"));
6165 as_bad (_("expecting operand before ','; got nothing"));
6170 /* Now *l must be either ',' or END_OF_INSN. */
6173 if (*++l
== END_OF_INSN
)
6175 /* Just skip it, if it's \n complain. */
6176 goto expecting_operand_after_comma
;
6178 expecting_operand
= 1;
6185 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6187 union i386_op temp_op
;
6188 i386_operand_type temp_type
;
6189 unsigned int temp_flags
;
6190 enum bfd_reloc_code_real temp_reloc
;
6192 temp_type
= i
.types
[xchg2
];
6193 i
.types
[xchg2
] = i
.types
[xchg1
];
6194 i
.types
[xchg1
] = temp_type
;
6196 temp_flags
= i
.flags
[xchg2
];
6197 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6198 i
.flags
[xchg1
] = temp_flags
;
6200 temp_op
= i
.op
[xchg2
];
6201 i
.op
[xchg2
] = i
.op
[xchg1
];
6202 i
.op
[xchg1
] = temp_op
;
6204 temp_reloc
= i
.reloc
[xchg2
];
6205 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6206 i
.reloc
[xchg1
] = temp_reloc
;
6208 temp_flags
= i
.imm_bits
[xchg2
];
6209 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6210 i
.imm_bits
[xchg1
] = temp_flags
;
6214 if (i
.mask
.operand
== xchg1
)
6215 i
.mask
.operand
= xchg2
;
6216 else if (i
.mask
.operand
== xchg2
)
6217 i
.mask
.operand
= xchg1
;
6219 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6221 if (i
.broadcast
.operand
== xchg1
)
6222 i
.broadcast
.operand
= xchg2
;
6223 else if (i
.broadcast
.operand
== xchg2
)
6224 i
.broadcast
.operand
= xchg1
;
6229 swap_operands (void)
6235 swap_2_operands (1, i
.operands
- 2);
6239 swap_2_operands (0, i
.operands
- 1);
6245 if (i
.mem_operands
== 2)
6247 const reg_entry
*temp_seg
;
6248 temp_seg
= i
.seg
[0];
6249 i
.seg
[0] = i
.seg
[1];
6250 i
.seg
[1] = temp_seg
;
6254 /* Try to ensure constant immediates are represented in the smallest
6259 char guess_suffix
= 0;
6263 guess_suffix
= i
.suffix
;
6264 else if (i
.reg_operands
)
6266 /* Figure out a suffix from the last register operand specified.
6267 We can't do this properly yet, i.e. excluding special register
6268 instances, but the following works for instructions with
6269 immediates. In any case, we can't set i.suffix yet. */
6270 for (op
= i
.operands
; --op
>= 0;)
6271 if (i
.types
[op
].bitfield
.class != Reg
)
6273 else if (i
.types
[op
].bitfield
.byte
)
6275 guess_suffix
= BYTE_MNEM_SUFFIX
;
6278 else if (i
.types
[op
].bitfield
.word
)
6280 guess_suffix
= WORD_MNEM_SUFFIX
;
6283 else if (i
.types
[op
].bitfield
.dword
)
6285 guess_suffix
= LONG_MNEM_SUFFIX
;
6288 else if (i
.types
[op
].bitfield
.qword
)
6290 guess_suffix
= QWORD_MNEM_SUFFIX
;
6294 else if ((flag_code
== CODE_16BIT
)
6295 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6296 guess_suffix
= WORD_MNEM_SUFFIX
;
6297 else if (flag_code
!= CODE_64BIT
6298 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6299 /* A more generic (but also more involved) way of dealing
6300 with the special case(s) would be to go look for
6301 DefaultSize attributes on any of the templates. */
6302 && current_templates
->start
->mnem_off
!= MN_push
))
6303 guess_suffix
= LONG_MNEM_SUFFIX
;
6305 for (op
= i
.operands
; --op
>= 0;)
6306 if (operand_type_check (i
.types
[op
], imm
))
6308 switch (i
.op
[op
].imms
->X_op
)
6311 /* If a suffix is given, this operand may be shortened. */
6312 switch (guess_suffix
)
6314 case LONG_MNEM_SUFFIX
:
6315 i
.types
[op
].bitfield
.imm32
= 1;
6316 i
.types
[op
].bitfield
.imm64
= 1;
6318 case WORD_MNEM_SUFFIX
:
6319 i
.types
[op
].bitfield
.imm16
= 1;
6320 i
.types
[op
].bitfield
.imm32
= 1;
6321 i
.types
[op
].bitfield
.imm32s
= 1;
6322 i
.types
[op
].bitfield
.imm64
= 1;
6324 case BYTE_MNEM_SUFFIX
:
6325 i
.types
[op
].bitfield
.imm8
= 1;
6326 i
.types
[op
].bitfield
.imm8s
= 1;
6327 i
.types
[op
].bitfield
.imm16
= 1;
6328 i
.types
[op
].bitfield
.imm32
= 1;
6329 i
.types
[op
].bitfield
.imm32s
= 1;
6330 i
.types
[op
].bitfield
.imm64
= 1;
6334 /* If this operand is at most 16 bits, convert it
6335 to a signed 16 bit number before trying to see
6336 whether it will fit in an even smaller size.
6337 This allows a 16-bit operand such as $0xffe0 to
6338 be recognised as within Imm8S range. */
6339 if ((i
.types
[op
].bitfield
.imm16
)
6340 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6342 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6343 ^ 0x8000) - 0x8000);
6346 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6347 if ((i
.types
[op
].bitfield
.imm32
)
6348 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6350 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6351 ^ ((offsetT
) 1 << 31))
6352 - ((offsetT
) 1 << 31));
6356 = operand_type_or (i
.types
[op
],
6357 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6359 /* We must avoid matching of Imm32 templates when 64bit
6360 only immediate is available. */
6361 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6362 i
.types
[op
].bitfield
.imm32
= 0;
6369 /* Symbols and expressions. */
6371 /* Convert symbolic operand to proper sizes for matching, but don't
6372 prevent matching a set of insns that only supports sizes other
6373 than those matching the insn suffix. */
6375 i386_operand_type mask
, allowed
;
6376 const insn_template
*t
= current_templates
->start
;
6378 operand_type_set (&mask
, 0);
6379 switch (guess_suffix
)
6381 case QWORD_MNEM_SUFFIX
:
6382 mask
.bitfield
.imm64
= 1;
6383 mask
.bitfield
.imm32s
= 1;
6385 case LONG_MNEM_SUFFIX
:
6386 mask
.bitfield
.imm32
= 1;
6388 case WORD_MNEM_SUFFIX
:
6389 mask
.bitfield
.imm16
= 1;
6391 case BYTE_MNEM_SUFFIX
:
6392 mask
.bitfield
.imm8
= 1;
6398 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6399 while (++t
< current_templates
->end
)
6401 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6402 allowed
= operand_type_and (allowed
, mask
);
6405 if (!operand_type_all_zero (&allowed
))
6406 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6413 /* Try to use the smallest displacement type too. */
6415 optimize_disp (const insn_template
*t
)
6419 if (!want_disp32 (t
)
6420 && (!t
->opcode_modifier
.jump
6421 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6423 for (op
= 0; op
< i
.operands
; ++op
)
6425 const expressionS
*exp
= i
.op
[op
].disps
;
6427 if (!operand_type_check (i
.types
[op
], disp
))
6430 if (exp
->X_op
!= O_constant
)
6433 /* Since displacement is signed extended to 64bit, don't allow
6434 disp32 if it is out of range. */
6435 if (fits_in_signed_long (exp
->X_add_number
))
6438 i
.types
[op
].bitfield
.disp32
= 0;
6439 if (i
.types
[op
].bitfield
.baseindex
)
6441 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6442 (uint64_t) exp
->X_add_number
);
6448 /* Don't optimize displacement for movabs since it only takes 64bit
6450 if (i
.disp_encoding
> disp_encoding_8bit
6451 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6454 for (op
= i
.operands
; op
-- > 0;)
6455 if (operand_type_check (i
.types
[op
], disp
))
6457 if (i
.op
[op
].disps
->X_op
== O_constant
)
6459 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6461 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6463 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6464 i
.op
[op
].disps
= NULL
;
6469 if (i
.types
[op
].bitfield
.disp16
6470 && fits_in_unsigned_word (op_disp
))
6472 /* If this operand is at most 16 bits, convert
6473 to a signed 16 bit number and don't use 64bit
6475 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6476 i
.types
[op
].bitfield
.disp64
= 0;
6480 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6481 if ((flag_code
!= CODE_64BIT
6482 ? i
.types
[op
].bitfield
.disp32
6484 && (!t
->opcode_modifier
.jump
6485 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6486 && fits_in_unsigned_long (op_disp
))
6488 /* If this operand is at most 32 bits, convert
6489 to a signed 32 bit number and don't use 64bit
6491 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6492 i
.types
[op
].bitfield
.disp64
= 0;
6493 i
.types
[op
].bitfield
.disp32
= 1;
6496 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6498 i
.types
[op
].bitfield
.disp64
= 0;
6499 i
.types
[op
].bitfield
.disp32
= 1;
6502 if ((i
.types
[op
].bitfield
.disp32
6503 || i
.types
[op
].bitfield
.disp16
)
6504 && fits_in_disp8 (op_disp
))
6505 i
.types
[op
].bitfield
.disp8
= 1;
6507 i
.op
[op
].disps
->X_add_number
= op_disp
;
6509 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6510 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6512 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6513 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6514 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6517 /* We only support 64bit displacement on constants. */
6518 i
.types
[op
].bitfield
.disp64
= 0;
6524 /* Return 1 if there is a match in broadcast bytes between operand
6525 GIVEN and instruction template T. */
6528 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6530 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6531 && i
.types
[given
].bitfield
.byte
)
6532 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6533 && i
.types
[given
].bitfield
.word
)
6534 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6535 && i
.types
[given
].bitfield
.dword
)
6536 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6537 && i
.types
[given
].bitfield
.qword
));
6540 /* Check if operands are valid for the instruction. */
6543 check_VecOperands (const insn_template
*t
)
6548 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6549 any one operand are implicity requiring AVX512VL support if the actual
6550 operand size is YMMword or XMMword. Since this function runs after
6551 template matching, there's no need to check for YMMword/XMMword in
6553 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6554 if (!cpu_flags_all_zero (&cpu
)
6555 && !is_cpu (t
, CpuAVX512VL
)
6556 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6557 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6559 for (op
= 0; op
< t
->operands
; ++op
)
6561 if (t
->operand_types
[op
].bitfield
.zmmword
6562 && (i
.types
[op
].bitfield
.ymmword
6563 || i
.types
[op
].bitfield
.xmmword
))
6565 i
.error
= unsupported
;
6571 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6572 requiring AVX2 support if the actual operand size is YMMword. */
6573 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6574 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6576 for (op
= 0; op
< t
->operands
; ++op
)
6578 if (t
->operand_types
[op
].bitfield
.xmmword
6579 && i
.types
[op
].bitfield
.ymmword
)
6581 i
.error
= unsupported
;
6587 /* Without VSIB byte, we can't have a vector register for index. */
6588 if (!t
->opcode_modifier
.sib
6590 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6591 || i
.index_reg
->reg_type
.bitfield
.ymmword
6592 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6594 i
.error
= unsupported_vector_index_register
;
6598 /* Check if default mask is allowed. */
6599 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6600 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6602 i
.error
= no_default_mask
;
6606 /* For VSIB byte, we need a vector register for index, and all vector
6607 registers must be distinct. */
6608 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6611 || !((t
->opcode_modifier
.sib
== VECSIB128
6612 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6613 || (t
->opcode_modifier
.sib
== VECSIB256
6614 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6615 || (t
->opcode_modifier
.sib
== VECSIB512
6616 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6618 i
.error
= invalid_vsib_address
;
6622 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6623 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6625 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6626 gas_assert (i
.types
[0].bitfield
.xmmword
6627 || i
.types
[0].bitfield
.ymmword
);
6628 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6629 gas_assert (i
.types
[2].bitfield
.xmmword
6630 || i
.types
[2].bitfield
.ymmword
);
6631 if (operand_check
== check_none
)
6633 if (register_number (i
.op
[0].regs
)
6634 != register_number (i
.index_reg
)
6635 && register_number (i
.op
[2].regs
)
6636 != register_number (i
.index_reg
)
6637 && register_number (i
.op
[0].regs
)
6638 != register_number (i
.op
[2].regs
))
6640 if (operand_check
== check_error
)
6642 i
.error
= invalid_vector_register_set
;
6645 as_warn (_("mask, index, and destination registers should be distinct"));
6647 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6649 if (i
.types
[1].bitfield
.class == RegSIMD
6650 && (i
.types
[1].bitfield
.xmmword
6651 || i
.types
[1].bitfield
.ymmword
6652 || i
.types
[1].bitfield
.zmmword
)
6653 && (register_number (i
.op
[1].regs
)
6654 == register_number (i
.index_reg
)))
6656 if (operand_check
== check_error
)
6658 i
.error
= invalid_vector_register_set
;
6661 if (operand_check
!= check_none
)
6662 as_warn (_("index and destination registers should be distinct"));
6667 /* For AMX instructions with 3 TMM register operands, all operands
6668 must be distinct. */
6669 if (i
.reg_operands
== 3
6670 && t
->operand_types
[0].bitfield
.tmmword
6671 && (i
.op
[0].regs
== i
.op
[1].regs
6672 || i
.op
[0].regs
== i
.op
[2].regs
6673 || i
.op
[1].regs
== i
.op
[2].regs
))
6675 i
.error
= invalid_tmm_register_set
;
6679 /* For some special instructions require that destination must be distinct
6680 from source registers. */
6681 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6683 unsigned int dest_reg
= i
.operands
- 1;
6685 know (i
.operands
>= 3);
6687 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6688 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6689 || (i
.reg_operands
> 2
6690 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6692 i
.error
= invalid_dest_and_src_register_set
;
6697 /* Check if broadcast is supported by the instruction and is applied
6698 to the memory operand. */
6699 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6701 i386_operand_type type
, overlap
;
6703 /* Check if specified broadcast is supported in this instruction,
6704 and its broadcast bytes match the memory operand. */
6705 op
= i
.broadcast
.operand
;
6706 if (!t
->opcode_modifier
.broadcast
6707 || !(i
.flags
[op
] & Operand_Mem
)
6708 || (!i
.types
[op
].bitfield
.unspecified
6709 && !match_broadcast_size (t
, op
)))
6712 i
.error
= unsupported_broadcast
;
6716 operand_type_set (&type
, 0);
6717 switch (get_broadcast_bytes (t
, false))
6720 type
.bitfield
.word
= 1;
6723 type
.bitfield
.dword
= 1;
6726 type
.bitfield
.qword
= 1;
6729 type
.bitfield
.xmmword
= 1;
6732 if (vector_size
< VSZ256
)
6734 type
.bitfield
.ymmword
= 1;
6737 if (vector_size
< VSZ512
)
6739 type
.bitfield
.zmmword
= 1;
6745 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6746 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6747 && t
->operand_types
[op
].bitfield
.byte
6748 + t
->operand_types
[op
].bitfield
.word
6749 + t
->operand_types
[op
].bitfield
.dword
6750 + t
->operand_types
[op
].bitfield
.qword
> 1)
6752 overlap
.bitfield
.xmmword
= 0;
6753 overlap
.bitfield
.ymmword
= 0;
6754 overlap
.bitfield
.zmmword
= 0;
6756 if (operand_type_all_zero (&overlap
))
6759 if (t
->opcode_modifier
.checkoperandsize
)
6763 type
.bitfield
.baseindex
= 1;
6764 for (j
= 0; j
< i
.operands
; ++j
)
6767 && !operand_type_register_match(i
.types
[j
],
6768 t
->operand_types
[j
],
6770 t
->operand_types
[op
]))
6775 /* If broadcast is supported in this instruction, we need to check if
6776 operand of one-element size isn't specified without broadcast. */
6777 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6779 /* Find memory operand. */
6780 for (op
= 0; op
< i
.operands
; op
++)
6781 if (i
.flags
[op
] & Operand_Mem
)
6783 gas_assert (op
< i
.operands
);
6784 /* Check size of the memory operand. */
6785 if (match_broadcast_size (t
, op
))
6787 i
.error
= broadcast_needed
;
6792 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6794 /* Check if requested masking is supported. */
6797 if (!t
->opcode_modifier
.masking
)
6799 i
.error
= unsupported_masking
;
6803 /* Common rules for masking:
6804 - mask register destinations permit only zeroing-masking, without
6805 that actually being expressed by a {z} operand suffix or EVEX.z,
6806 - memory destinations allow only merging-masking,
6807 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6810 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6811 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6812 || t
->opcode_modifier
.sib
))
6814 i
.error
= unsupported_masking
;
6819 /* Check if masking is applied to dest operand. */
6820 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6822 i
.error
= mask_not_on_destination
;
6827 if (i
.rounding
.type
!= rc_none
)
6829 if (!t
->opcode_modifier
.sae
6830 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6833 i
.error
= unsupported_rc_sae
;
6837 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6839 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6841 for (op
= 0; op
< t
->operands
; ++op
)
6842 if (i
.types
[op
].bitfield
.zmmword
)
6844 if (op
>= t
->operands
)
6846 i
.error
= operand_size_mismatch
;
6852 /* Check the special Imm4 cases; must be the first operand. */
6853 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6855 if (i
.op
[0].imms
->X_op
!= O_constant
6856 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6862 /* Turn off Imm<N> so that update_imm won't complain. */
6863 operand_type_set (&i
.types
[0], 0);
6866 /* Check vector Disp8 operand. */
6867 if (t
->opcode_modifier
.disp8memshift
6868 && (!t
->opcode_modifier
.vex
6869 || need_evex_encoding ())
6870 && i
.disp_encoding
<= disp_encoding_8bit
)
6872 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6873 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6874 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6875 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6878 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6881 for (op
= 0; op
< i
.operands
; op
++)
6882 if (i
.flags
[op
] & Operand_Mem
)
6884 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6885 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6886 else if (t
->operand_types
[op
].bitfield
.xmmword
6887 + t
->operand_types
[op
].bitfield
.ymmword
6888 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6889 type
= &t
->operand_types
[op
];
6890 else if (!i
.types
[op
].bitfield
.unspecified
)
6891 type
= &i
.types
[op
];
6892 else /* Ambiguities get resolved elsewhere. */
6893 fallback
= &t
->operand_types
[op
];
6895 else if (i
.types
[op
].bitfield
.class == RegSIMD
6896 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6898 if (i
.types
[op
].bitfield
.zmmword
)
6900 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6902 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6906 if (!type
&& !i
.memshift
)
6910 if (type
->bitfield
.zmmword
)
6912 else if (type
->bitfield
.ymmword
)
6914 else if (type
->bitfield
.xmmword
)
6918 /* For the check in fits_in_disp8(). */
6919 if (i
.memshift
== 0)
6923 for (op
= 0; op
< i
.operands
; op
++)
6924 if (operand_type_check (i
.types
[op
], disp
)
6925 && i
.op
[op
].disps
->X_op
== O_constant
)
6927 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6929 i
.types
[op
].bitfield
.disp8
= 1;
6932 i
.types
[op
].bitfield
.disp8
= 0;
6941 /* Check if encoding requirements are met by the instruction. */
6944 VEX_check_encoding (const insn_template
*t
)
6946 if (i
.vec_encoding
== vex_encoding_error
)
6948 i
.error
= unsupported
;
6952 /* Vector size restrictions. */
6953 if ((vector_size
< VSZ512
6954 && (t
->opcode_modifier
.evex
== EVEX512
6955 || t
->opcode_modifier
.vsz
>= VSZ512
))
6956 || (vector_size
< VSZ256
6957 && (t
->opcode_modifier
.evex
== EVEX256
6958 || t
->opcode_modifier
.vex
== VEX256
6959 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6961 i
.error
= unsupported
;
6965 if (i
.vec_encoding
== vex_encoding_evex
6966 || i
.vec_encoding
== vex_encoding_evex512
)
6968 /* This instruction must be encoded with EVEX prefix. */
6969 if (!is_evex_encoding (t
))
6971 i
.error
= unsupported
;
6977 if (!t
->opcode_modifier
.vex
)
6979 /* This instruction template doesn't have VEX prefix. */
6980 if (i
.vec_encoding
!= vex_encoding_default
)
6982 i
.error
= unsupported
;
6991 /* Helper function for the progress() macro in match_template(). */
6992 static INLINE
enum i386_error
progress (enum i386_error
new,
6993 enum i386_error last
,
6994 unsigned int line
, unsigned int *line_p
)
6996 if (line
<= *line_p
)
7002 static const insn_template
*
7003 match_template (char mnem_suffix
)
7005 /* Points to template once we've found it. */
7006 const insn_template
*t
;
7007 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
7008 i386_operand_type overlap4
;
7009 unsigned int found_reverse_match
;
7010 i386_operand_type operand_types
[MAX_OPERANDS
];
7011 int addr_prefix_disp
;
7012 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7013 enum i386_error specific_error
= number_of_operands_mismatch
;
7014 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7016 #if MAX_OPERANDS != 5
7017 # error "MAX_OPERANDS must be 5."
7020 found_reverse_match
= 0;
7021 addr_prefix_disp
= -1;
7023 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7025 addr_prefix_disp
= -1;
7026 found_reverse_match
= 0;
7028 /* Must have right number of operands. */
7029 if (i
.operands
!= t
->operands
)
7032 /* Check processor support. */
7033 specific_error
= progress (unsupported
);
7034 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7037 /* Check AT&T mnemonic. */
7038 specific_error
= progress (unsupported_with_intel_mnemonic
);
7039 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7042 /* Check AT&T/Intel syntax. */
7043 specific_error
= progress (unsupported_syntax
);
7044 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7045 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7048 /* Check Intel64/AMD64 ISA. */
7052 /* Default: Don't accept Intel64. */
7053 if (t
->opcode_modifier
.isa64
== INTEL64
)
7057 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7058 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7062 /* -mintel64: Don't accept AMD64. */
7063 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7068 /* Check the suffix. */
7069 specific_error
= progress (invalid_instruction_suffix
);
7070 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7071 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7072 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7073 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7074 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7077 specific_error
= progress (operand_size_mismatch
);
7078 size_match
= operand_size_match (t
);
7082 /* This is intentionally not
7084 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7086 as the case of a missing * on the operand is accepted (perhaps with
7087 a warning, issued further down). */
7088 specific_error
= progress (operand_type_mismatch
);
7089 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7092 /* In Intel syntax, normally we can check for memory operand size when
7093 there is no mnemonic suffix. But jmp and call have 2 different
7094 encodings with Dword memory operand size. Skip the "near" one
7095 (permitting a register operand) when "far" was requested. */
7097 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7098 && t
->operand_types
[0].bitfield
.class == Reg
)
7101 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7102 operand_types
[j
] = t
->operand_types
[j
];
7104 /* In general, don't allow 32-bit operands on pre-386. */
7105 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7106 : operand_size_mismatch
);
7107 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7108 if (i
.suffix
== LONG_MNEM_SUFFIX
7109 && !cpu_arch_flags
.bitfield
.cpui386
7111 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7112 && !intel_float_operand (insn_name (t
)))
7113 : intel_float_operand (insn_name (t
)) != 2)
7114 && (t
->operands
== i
.imm_operands
7115 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7116 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7117 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7118 || (operand_types
[j
].bitfield
.class != RegMMX
7119 && operand_types
[j
].bitfield
.class != RegSIMD
7120 && operand_types
[j
].bitfield
.class != RegMask
))
7121 && !t
->opcode_modifier
.sib
)
7124 /* Do not verify operands when there are none. */
7127 if (VEX_check_encoding (t
))
7129 specific_error
= progress (i
.error
);
7133 /* We've found a match; break out of loop. */
7137 if (!t
->opcode_modifier
.jump
7138 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7140 /* There should be only one Disp operand. */
7141 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7142 if (operand_type_check (operand_types
[j
], disp
))
7144 if (j
< MAX_OPERANDS
)
7146 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7148 addr_prefix_disp
= j
;
7150 /* Address size prefix will turn Disp64 operand into Disp32 and
7151 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7155 override
= !override
;
7158 if (operand_types
[j
].bitfield
.disp32
7159 && operand_types
[j
].bitfield
.disp16
)
7161 operand_types
[j
].bitfield
.disp16
= override
;
7162 operand_types
[j
].bitfield
.disp32
= !override
;
7164 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7168 if (operand_types
[j
].bitfield
.disp64
)
7170 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7171 operand_types
[j
].bitfield
.disp32
= override
;
7172 operand_types
[j
].bitfield
.disp64
= !override
;
7174 operand_types
[j
].bitfield
.disp16
= 0;
7180 /* We check register size if needed. */
7181 if (t
->opcode_modifier
.checkoperandsize
)
7183 check_register
= (1 << t
->operands
) - 1;
7184 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7185 check_register
&= ~(1 << i
.broadcast
.operand
);
7190 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7191 switch (t
->operands
)
7194 if (!operand_type_match (overlap0
, i
.types
[0]))
7197 /* Allow the ModR/M encoding to be requested by using the {load} or
7198 {store} pseudo prefix on an applicable insn. */
7199 if (!t
->opcode_modifier
.modrm
7200 && i
.reg_operands
== 1
7201 && ((i
.dir_encoding
== dir_encoding_load
7202 && t
->mnem_off
!= MN_pop
)
7203 || (i
.dir_encoding
== dir_encoding_store
7204 && t
->mnem_off
!= MN_push
))
7206 && t
->mnem_off
!= MN_bswap
)
7211 /* xchg %eax, %eax is a special case. It is an alias for nop
7212 only in 32bit mode and we can use opcode 0x90. In 64bit
7213 mode, we can't use 0x90 for xchg %eax, %eax since it should
7214 zero-extend %eax to %rax. */
7215 if (t
->base_opcode
== 0x90
7216 && t
->opcode_space
== SPACE_BASE
)
7218 if (flag_code
== CODE_64BIT
7219 && i
.types
[0].bitfield
.instance
== Accum
7220 && i
.types
[0].bitfield
.dword
7221 && i
.types
[1].bitfield
.instance
== Accum
)
7224 /* Allow the ModR/M encoding to be requested by using the
7225 {load} or {store} pseudo prefix. */
7226 if (i
.dir_encoding
== dir_encoding_load
7227 || i
.dir_encoding
== dir_encoding_store
)
7231 if (t
->base_opcode
== MOV_AX_DISP32
7232 && t
->opcode_space
== SPACE_BASE
7233 && t
->mnem_off
!= MN_movabs
)
7235 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7236 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7239 /* xrelease mov %eax, <disp> is another special case. It must not
7240 match the accumulator-only encoding of mov. */
7244 /* Allow the ModR/M encoding to be requested by using a suitable
7245 {load} or {store} pseudo prefix. */
7246 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7247 ? dir_encoding_store
7248 : dir_encoding_load
)
7249 && !i
.types
[0].bitfield
.disp64
7250 && !i
.types
[1].bitfield
.disp64
)
7254 /* Allow the ModR/M encoding to be requested by using the {load} or
7255 {store} pseudo prefix on an applicable insn. */
7256 if (!t
->opcode_modifier
.modrm
7257 && i
.reg_operands
== 1
7258 && i
.imm_operands
== 1
7259 && (i
.dir_encoding
== dir_encoding_load
7260 || i
.dir_encoding
== dir_encoding_store
)
7261 && t
->opcode_space
== SPACE_BASE
)
7263 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7264 && i
.dir_encoding
== dir_encoding_store
)
7267 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7268 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7269 || i
.dir_encoding
== dir_encoding_load
))
7272 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7273 && i
.dir_encoding
== dir_encoding_load
)
7279 if (!(size_match
& MATCH_STRAIGHT
))
7281 /* Reverse direction of operands if swapping is possible in the first
7282 place (operands need to be symmetric) and
7283 - the load form is requested, and the template is a store form,
7284 - the store form is requested, and the template is a load form,
7285 - the non-default (swapped) form is requested. */
7286 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7287 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7288 && !operand_type_all_zero (&overlap1
))
7289 switch (i
.dir_encoding
)
7291 case dir_encoding_load
:
7292 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7293 || t
->opcode_modifier
.regmem
)
7297 case dir_encoding_store
:
7298 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7299 && !t
->opcode_modifier
.regmem
)
7303 case dir_encoding_swap
:
7306 case dir_encoding_default
:
7309 /* If we want store form, we skip the current load. */
7310 if ((i
.dir_encoding
== dir_encoding_store
7311 || i
.dir_encoding
== dir_encoding_swap
)
7312 && i
.mem_operands
== 0
7313 && t
->opcode_modifier
.load
)
7318 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7319 if (!operand_type_match (overlap0
, i
.types
[0])
7320 || !operand_type_match (overlap1
, i
.types
[1])
7321 || ((check_register
& 3) == 3
7322 && !operand_type_register_match (i
.types
[0],
7327 specific_error
= progress (i
.error
);
7329 /* Check if other direction is valid ... */
7330 if (!t
->opcode_modifier
.d
)
7334 if (!(size_match
& MATCH_REVERSE
))
7336 /* Try reversing direction of operands. */
7337 j
= is_cpu (t
, CpuFMA4
)
7338 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7339 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7340 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7341 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7342 gas_assert (t
->operands
!= 3 || !check_register
);
7343 if (!operand_type_match (overlap0
, i
.types
[0])
7344 || !operand_type_match (overlap1
, i
.types
[j
])
7345 || (t
->operands
== 3
7346 && !operand_type_match (overlap2
, i
.types
[1]))
7348 && !operand_type_register_match (i
.types
[0],
7353 /* Does not match either direction. */
7354 specific_error
= progress (i
.error
);
7357 /* found_reverse_match holds which variant of D
7359 if (!t
->opcode_modifier
.d
)
7360 found_reverse_match
= 0;
7361 else if (operand_types
[0].bitfield
.tbyte
)
7363 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7364 found_reverse_match
= Opcode_FloatD
;
7366 found_reverse_match
= ~0;
7367 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7368 if ((t
->extension_opcode
& 4)
7369 && (intel_syntax
|| intel_mnemonic
))
7370 found_reverse_match
|= Opcode_FloatR
;
7372 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7374 found_reverse_match
= Opcode_VexW
;
7375 goto check_operands_345
;
7377 else if (t
->opcode_space
!= SPACE_BASE
7378 && (t
->opcode_space
!= SPACE_0F
7379 /* MOV to/from CR/DR/TR, as an exception, follow
7380 the base opcode space encoding model. */
7381 || (t
->base_opcode
| 7) != 0x27))
7382 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7383 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7384 else if (!t
->opcode_modifier
.commutative
)
7385 found_reverse_match
= Opcode_D
;
7387 found_reverse_match
= ~0;
7391 /* Found a forward 2 operand match here. */
7393 switch (t
->operands
)
7396 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7397 if (!operand_type_match (overlap4
, i
.types
[4])
7398 || !operand_type_register_match (i
.types
[3],
7403 specific_error
= progress (i
.error
);
7408 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7409 if (!operand_type_match (overlap3
, i
.types
[3])
7410 || ((check_register
& 0xa) == 0xa
7411 && !operand_type_register_match (i
.types
[1],
7415 || ((check_register
& 0xc) == 0xc
7416 && !operand_type_register_match (i
.types
[2],
7421 specific_error
= progress (i
.error
);
7426 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7427 if (!operand_type_match (overlap2
, i
.types
[2])
7428 || ((check_register
& 5) == 5
7429 && !operand_type_register_match (i
.types
[0],
7433 || ((check_register
& 6) == 6
7434 && !operand_type_register_match (i
.types
[1],
7439 specific_error
= progress (i
.error
);
7445 /* Found either forward/reverse 2, 3 or 4 operand match here:
7446 slip through to break. */
7449 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7450 if (VEX_check_encoding (t
))
7452 specific_error
= progress (i
.error
);
7456 /* Check if vector operands are valid. */
7457 if (check_VecOperands (t
))
7459 specific_error
= progress (i
.error
);
7463 /* Check whether to use the shorter VEX encoding for certain insns where
7464 the EVEX enconding comes first in the table. This requires the respective
7465 AVX-* feature to be explicitly enabled. */
7466 if (t
== current_templates
->start
7467 && t
->opcode_modifier
.disp8memshift
7468 && !t
->opcode_modifier
.vex
7469 && !need_evex_encoding ()
7470 && t
+ 1 < current_templates
->end
7471 && t
[1].opcode_modifier
.vex
)
7474 unsigned int memshift
= i
.memshift
;
7477 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7478 if (!cpu_flags_all_zero (&cpu
)
7479 && (!i
.types
[0].bitfield
.disp8
7480 || !operand_type_check (i
.types
[0], disp
)
7481 || i
.op
[0].disps
->X_op
!= O_constant
7482 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7484 specific_error
= progress (internal_error
);
7487 i
.memshift
= memshift
;
7490 /* We've found a match; break out of loop. */
7496 if (t
== current_templates
->end
)
7498 /* We found no match. */
7499 i
.error
= specific_error
;
7503 if (!quiet_warnings
)
7506 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7507 as_warn (_("indirect %s without `*'"), insn_name (t
));
7509 if (t
->opcode_modifier
.isprefix
7510 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7512 /* Warn them that a data or address size prefix doesn't
7513 affect assembly of the next line of code. */
7514 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7518 /* Copy the template we found. */
7519 install_template (t
);
7521 if (addr_prefix_disp
!= -1)
7522 i
.tm
.operand_types
[addr_prefix_disp
]
7523 = operand_types
[addr_prefix_disp
];
7525 switch (found_reverse_match
)
7531 case Opcode_FloatR
| Opcode_FloatD
:
7532 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7533 found_reverse_match
&= Opcode_FloatD
;
7537 /* If we found a reverse match we must alter the opcode direction
7538 bit and clear/flip the regmem modifier one. found_reverse_match
7539 holds bits to change (different for int & float insns). */
7541 i
.tm
.base_opcode
^= found_reverse_match
;
7543 /* Certain SIMD insns have their load forms specified in the opcode
7544 table, and hence we need to _set_ RegMem instead of clearing it.
7545 We need to avoid setting the bit though on insns like KMOVW. */
7546 i
.tm
.opcode_modifier
.regmem
7547 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7548 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7549 && !i
.tm
.opcode_modifier
.regmem
;
7553 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7554 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7558 /* Only the first two register operands need reversing, alongside
7560 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7562 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7563 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7564 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7568 /* This pattern aims to put the unusually placed imm operand to a usual
7569 place. The constraints are currently only adapted to uwrmsr, and may
7570 need further tweaking when new similar instructions become available. */
7571 if (i
.imm_operands
&& i
.imm_operands
< i
.operands
7572 && operand_type_check (operand_types
[i
.operands
- 1], imm
))
7574 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7575 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7576 swap_2_operands(0, i
.operands
- 1);
7585 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7586 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7588 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7590 as_bad (_("`%s' operand %u must use `%ses' segment"),
7592 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7597 /* There's only ever one segment override allowed per instruction.
7598 This instruction possibly has a legal segment override on the
7599 second operand, so copy the segment to where non-string
7600 instructions store it, allowing common code. */
7601 i
.seg
[op
] = i
.seg
[1];
7607 process_suffix (void)
7609 bool is_movx
= false;
7611 /* If matched instruction specifies an explicit instruction mnemonic
7613 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7614 i
.suffix
= WORD_MNEM_SUFFIX
;
7615 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7616 i
.suffix
= LONG_MNEM_SUFFIX
;
7617 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7618 i
.suffix
= QWORD_MNEM_SUFFIX
;
7619 else if (i
.reg_operands
7620 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7621 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7623 unsigned int numop
= i
.operands
;
7626 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7627 && (i
.tm
.base_opcode
| 8) == 0xbe)
7628 || (i
.tm
.opcode_space
== SPACE_BASE
7629 && i
.tm
.base_opcode
== 0x63
7630 && is_cpu (&i
.tm
, Cpu64
));
7632 /* movsx/movzx want only their source operand considered here, for the
7633 ambiguity checking below. The suffix will be replaced afterwards
7634 to represent the destination (register). */
7635 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7638 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7639 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7642 /* If there's no instruction mnemonic suffix we try to invent one
7643 based on GPR operands. */
7646 /* We take i.suffix from the last register operand specified,
7647 Destination register type is more significant than source
7648 register type. crc32 in SSE4.2 prefers source register
7650 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7653 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7654 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7656 if (i
.types
[op
].bitfield
.class != Reg
)
7658 if (i
.types
[op
].bitfield
.byte
)
7659 i
.suffix
= BYTE_MNEM_SUFFIX
;
7660 else if (i
.types
[op
].bitfield
.word
)
7661 i
.suffix
= WORD_MNEM_SUFFIX
;
7662 else if (i
.types
[op
].bitfield
.dword
)
7663 i
.suffix
= LONG_MNEM_SUFFIX
;
7664 else if (i
.types
[op
].bitfield
.qword
)
7665 i
.suffix
= QWORD_MNEM_SUFFIX
;
7671 /* As an exception, movsx/movzx silently default to a byte source
7673 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7674 i
.suffix
= BYTE_MNEM_SUFFIX
;
7676 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7678 if (!check_byte_reg ())
7681 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7683 if (!check_long_reg ())
7686 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7688 if (!check_qword_reg ())
7691 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7693 if (!check_word_reg ())
7696 else if (intel_syntax
7697 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7698 /* Do nothing if the instruction is going to ignore the prefix. */
7703 /* Undo the movsx/movzx change done above. */
7706 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7709 i
.suffix
= stackop_size
;
7710 if (stackop_size
== LONG_MNEM_SUFFIX
)
7712 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7713 .code16gcc directive to support 16-bit mode with
7714 32-bit address. For IRET without a suffix, generate
7715 16-bit IRET (opcode 0xcf) to return from an interrupt
7717 if (i
.tm
.base_opcode
== 0xcf)
7719 i
.suffix
= WORD_MNEM_SUFFIX
;
7720 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7722 /* Warn about changed behavior for segment register push/pop. */
7723 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7724 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7729 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7730 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7731 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7732 || (i
.tm
.opcode_space
== SPACE_0F
7733 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7734 && i
.tm
.extension_opcode
<= 3)))
7739 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7741 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7742 || i
.tm
.opcode_modifier
.no_lsuf
)
7743 i
.suffix
= QWORD_MNEM_SUFFIX
;
7748 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7749 i
.suffix
= LONG_MNEM_SUFFIX
;
7752 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7753 i
.suffix
= WORD_MNEM_SUFFIX
;
7759 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7760 /* Also cover lret/retf/iret in 64-bit mode. */
7761 || (flag_code
== CODE_64BIT
7762 && !i
.tm
.opcode_modifier
.no_lsuf
7763 && !i
.tm
.opcode_modifier
.no_qsuf
))
7764 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7765 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7766 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7767 /* Accept FLDENV et al without suffix. */
7768 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7770 unsigned int suffixes
, evex
= 0;
7772 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7773 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7775 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7777 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7779 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7782 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7783 also suitable for AT&T syntax mode, it was requested that this be
7784 restricted to just Intel syntax. */
7785 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7786 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7790 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7792 if (vector_size
< VSZ512
)
7794 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7795 if (vector_size
< VSZ256
)
7797 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7798 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7799 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7800 || (!i
.tm
.opcode_modifier
.evex
7801 && is_evex_encoding (&i
.tm
))))
7802 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7804 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7805 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7806 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7807 || (!i
.tm
.opcode_modifier
.evex
7808 && is_evex_encoding (&i
.tm
))))
7809 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7811 else if (is_evex_encoding (&i
.tm
)
7812 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7814 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7815 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7816 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7817 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7818 if (!i
.tm
.opcode_modifier
.evex
7819 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7820 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7823 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7824 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7825 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7828 /* Any properly sized operand disambiguates the insn. */
7829 if (i
.types
[op
].bitfield
.xmmword
7830 || i
.types
[op
].bitfield
.ymmword
7831 || i
.types
[op
].bitfield
.zmmword
)
7833 suffixes
&= ~(7 << 6);
7838 if ((i
.flags
[op
] & Operand_Mem
)
7839 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7841 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7843 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7845 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7847 if (is_evex_encoding (&i
.tm
))
7853 /* Are multiple suffixes / operand sizes allowed? */
7854 if (suffixes
& (suffixes
- 1))
7857 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7858 || operand_check
== check_error
))
7860 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7863 if (operand_check
== check_error
)
7865 as_bad (_("no instruction mnemonic suffix given and "
7866 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7869 if (operand_check
== check_warning
)
7870 as_warn (_("%s; using default for `%s'"),
7872 ? _("ambiguous operand size")
7873 : _("no instruction mnemonic suffix given and "
7874 "no register operands"),
7877 if (i
.tm
.opcode_modifier
.floatmf
)
7878 i
.suffix
= SHORT_MNEM_SUFFIX
;
7880 /* handled below */;
7882 i
.tm
.opcode_modifier
.evex
= evex
;
7883 else if (flag_code
== CODE_16BIT
)
7884 i
.suffix
= WORD_MNEM_SUFFIX
;
7885 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7886 i
.suffix
= LONG_MNEM_SUFFIX
;
7888 i
.suffix
= QWORD_MNEM_SUFFIX
;
7894 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7895 In AT&T syntax, if there is no suffix (warned about above), the default
7896 will be byte extension. */
7897 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7898 i
.tm
.base_opcode
|= 1;
7900 /* For further processing, the suffix should represent the destination
7901 (register). This is already the case when one was used with
7902 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7903 no suffix to begin with. */
7904 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7906 if (i
.types
[1].bitfield
.word
)
7907 i
.suffix
= WORD_MNEM_SUFFIX
;
7908 else if (i
.types
[1].bitfield
.qword
)
7909 i
.suffix
= QWORD_MNEM_SUFFIX
;
7911 i
.suffix
= LONG_MNEM_SUFFIX
;
7913 i
.tm
.opcode_modifier
.w
= 0;
7917 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7918 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7919 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7921 /* Change the opcode based on the operand size given by i.suffix. */
7924 /* Size floating point instruction. */
7925 case LONG_MNEM_SUFFIX
:
7926 if (i
.tm
.opcode_modifier
.floatmf
)
7928 i
.tm
.base_opcode
^= 4;
7932 case WORD_MNEM_SUFFIX
:
7933 case QWORD_MNEM_SUFFIX
:
7934 /* It's not a byte, select word/dword operation. */
7935 if (i
.tm
.opcode_modifier
.w
)
7938 i
.tm
.base_opcode
|= 8;
7940 i
.tm
.base_opcode
|= 1;
7943 case SHORT_MNEM_SUFFIX
:
7944 /* Now select between word & dword operations via the operand
7945 size prefix, except for instructions that will ignore this
7947 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7948 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7949 && !i
.tm
.opcode_modifier
.floatmf
7950 && !is_any_vex_encoding (&i
.tm
)
7951 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7952 || (flag_code
== CODE_64BIT
7953 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7955 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7957 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7958 prefix
= ADDR_PREFIX_OPCODE
;
7960 if (!add_prefix (prefix
))
7964 /* Set mode64 for an operand. */
7965 if (i
.suffix
== QWORD_MNEM_SUFFIX
7966 && flag_code
== CODE_64BIT
7967 && !i
.tm
.opcode_modifier
.norex64
7968 && !i
.tm
.opcode_modifier
.vexw
7969 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7971 && ! (i
.operands
== 2
7972 && i
.tm
.base_opcode
== 0x90
7973 && i
.tm
.opcode_space
== SPACE_BASE
7974 && i
.types
[0].bitfield
.instance
== Accum
7975 && i
.types
[0].bitfield
.qword
7976 && i
.types
[1].bitfield
.instance
== Accum
))
7982 /* Select word/dword/qword operation with explicit data sizing prefix
7983 when there are no suitable register operands. */
7984 if (i
.tm
.opcode_modifier
.w
7985 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7987 || (i
.reg_operands
== 1
7989 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7991 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7992 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7993 || i
.tm
.mnem_off
== MN_crc32
))))
7994 i
.tm
.base_opcode
|= 1;
7998 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
8000 gas_assert (!i
.suffix
);
8001 gas_assert (i
.reg_operands
);
8003 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8006 /* The address size override prefix changes the size of the
8008 if (flag_code
== CODE_64BIT
8009 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
8011 as_bad (_("16-bit addressing unavailable for `%s'"),
8016 if ((flag_code
== CODE_32BIT
8017 ? i
.op
[0].regs
->reg_type
.bitfield
.word
8018 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
8019 && !add_prefix (ADDR_PREFIX_OPCODE
))
8024 /* Check invalid register operand when the address size override
8025 prefix changes the size of register operands. */
8027 enum { need_word
, need_dword
, need_qword
} need
;
8029 /* Check the register operand for the address size prefix if
8030 the memory operand has no real registers, like symbol, DISP
8031 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8032 if (i
.mem_operands
== 1
8033 && i
.reg_operands
== 1
8035 && i
.types
[1].bitfield
.class == Reg
8036 && (flag_code
== CODE_32BIT
8037 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8038 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8039 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8040 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8041 || (x86_elf_abi
== X86_64_X32_ABI
8043 && i
.base_reg
->reg_num
== RegIP
8044 && i
.base_reg
->reg_type
.bitfield
.qword
))
8048 && !add_prefix (ADDR_PREFIX_OPCODE
))
8051 if (flag_code
== CODE_32BIT
)
8052 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8053 else if (i
.prefix
[ADDR_PREFIX
])
8056 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8058 for (op
= 0; op
< i
.operands
; op
++)
8060 if (i
.types
[op
].bitfield
.class != Reg
)
8066 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8070 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8074 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8079 as_bad (_("invalid register operand size for `%s'"),
8090 check_byte_reg (void)
8094 for (op
= i
.operands
; --op
>= 0;)
8096 /* Skip non-register operands. */
8097 if (i
.types
[op
].bitfield
.class != Reg
)
8100 /* If this is an eight bit register, it's OK. If it's the 16 or
8101 32 bit version of an eight bit register, we will just use the
8102 low portion, and that's OK too. */
8103 if (i
.types
[op
].bitfield
.byte
)
8106 /* I/O port address operands are OK too. */
8107 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8108 && i
.tm
.operand_types
[op
].bitfield
.word
)
8111 /* crc32 only wants its source operand checked here. */
8112 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8115 /* Any other register is bad. */
8116 as_bad (_("`%s%s' not allowed with `%s%c'"),
8117 register_prefix
, i
.op
[op
].regs
->reg_name
,
8118 insn_name (&i
.tm
), i
.suffix
);
8125 check_long_reg (void)
8129 for (op
= i
.operands
; --op
>= 0;)
8130 /* Skip non-register operands. */
8131 if (i
.types
[op
].bitfield
.class != Reg
)
8133 /* Reject eight bit registers, except where the template requires
8134 them. (eg. movzb) */
8135 else if (i
.types
[op
].bitfield
.byte
8136 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8137 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8138 && (i
.tm
.operand_types
[op
].bitfield
.word
8139 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8141 as_bad (_("`%s%s' not allowed with `%s%c'"),
8143 i
.op
[op
].regs
->reg_name
,
8148 /* Error if the e prefix on a general reg is missing. */
8149 else if (i
.types
[op
].bitfield
.word
8150 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8151 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8152 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8154 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8155 register_prefix
, i
.op
[op
].regs
->reg_name
,
8159 /* Warn if the r prefix on a general reg is present. */
8160 else if (i
.types
[op
].bitfield
.qword
8161 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8162 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8163 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8165 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8166 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8173 check_qword_reg (void)
8177 for (op
= i
.operands
; --op
>= 0; )
8178 /* Skip non-register operands. */
8179 if (i
.types
[op
].bitfield
.class != Reg
)
8181 /* Reject eight bit registers, except where the template requires
8182 them. (eg. movzb) */
8183 else if (i
.types
[op
].bitfield
.byte
8184 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8185 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8186 && (i
.tm
.operand_types
[op
].bitfield
.word
8187 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8189 as_bad (_("`%s%s' not allowed with `%s%c'"),
8191 i
.op
[op
].regs
->reg_name
,
8196 /* Warn if the r prefix on a general reg is missing. */
8197 else if ((i
.types
[op
].bitfield
.word
8198 || i
.types
[op
].bitfield
.dword
)
8199 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8200 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8201 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8203 /* Prohibit these changes in the 64bit mode, since the
8204 lowering is more complicated. */
8205 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8206 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8213 check_word_reg (void)
8216 for (op
= i
.operands
; --op
>= 0;)
8217 /* Skip non-register operands. */
8218 if (i
.types
[op
].bitfield
.class != Reg
)
8220 /* Reject eight bit registers, except where the template requires
8221 them. (eg. movzb) */
8222 else if (i
.types
[op
].bitfield
.byte
8223 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8224 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8225 && (i
.tm
.operand_types
[op
].bitfield
.word
8226 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8228 as_bad (_("`%s%s' not allowed with `%s%c'"),
8230 i
.op
[op
].regs
->reg_name
,
8235 /* Error if the e or r prefix on a general reg is present. */
8236 else if ((i
.types
[op
].bitfield
.dword
8237 || i
.types
[op
].bitfield
.qword
)
8238 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8239 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8240 && i
.tm
.operand_types
[op
].bitfield
.word
)
8242 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8243 register_prefix
, i
.op
[op
].regs
->reg_name
,
8251 update_imm (unsigned int j
)
8253 i386_operand_type overlap
= i
.types
[j
];
8255 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8256 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8257 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8259 /* This combination is used on 8-bit immediates where e.g. $~0 is
8260 desirable to permit. We're past operand type matching, so simply
8261 put things back in the shape they were before introducing the
8262 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8263 overlap
.bitfield
.imm8s
= 0;
8266 if (overlap
.bitfield
.imm8
8267 + overlap
.bitfield
.imm8s
8268 + overlap
.bitfield
.imm16
8269 + overlap
.bitfield
.imm32
8270 + overlap
.bitfield
.imm32s
8271 + overlap
.bitfield
.imm64
> 1)
8273 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8274 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8275 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8276 static const i386_operand_type imm16_32
= { .bitfield
=
8277 { .imm16
= 1, .imm32
= 1 }
8279 static const i386_operand_type imm16_32s
= { .bitfield
=
8280 { .imm16
= 1, .imm32s
= 1 }
8282 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8283 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8288 i386_operand_type temp
;
8290 operand_type_set (&temp
, 0);
8291 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8293 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8294 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8296 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8297 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8298 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8300 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8301 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8304 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8307 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8308 || operand_type_equal (&overlap
, &imm16_32
)
8309 || operand_type_equal (&overlap
, &imm16_32s
))
8311 if ((flag_code
== CODE_16BIT
)
8312 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8317 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8318 overlap
= operand_type_and (overlap
, imm32s
);
8319 else if (i
.prefix
[DATA_PREFIX
])
8320 overlap
= operand_type_and (overlap
,
8321 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8322 if (overlap
.bitfield
.imm8
8323 + overlap
.bitfield
.imm8s
8324 + overlap
.bitfield
.imm16
8325 + overlap
.bitfield
.imm32
8326 + overlap
.bitfield
.imm32s
8327 + overlap
.bitfield
.imm64
!= 1)
8329 as_bad (_("no instruction mnemonic suffix given; "
8330 "can't determine immediate size"));
8334 i
.types
[j
] = overlap
;
8344 /* Update the first 2 immediate operands. */
8345 n
= i
.operands
> 2 ? 2 : i
.operands
;
8348 for (j
= 0; j
< n
; j
++)
8349 if (update_imm (j
) == 0)
8352 /* The 3rd operand can't be immediate operand. */
8353 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8359 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8362 if (r
->reg_flags
& RegRex
)
8364 if (i
.rex
& rex_bit
)
8365 as_bad (_("same type of prefix used twice"));
8368 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8370 gas_assert (i
.vex
.register_specifier
== r
);
8371 i
.vex
.register_specifier
+= 8;
8374 if (r
->reg_flags
& RegVRex
)
8379 process_operands (void)
8381 /* Default segment register this instruction will use for memory
8382 accesses. 0 means unknown. This is only for optimizing out
8383 unnecessary segment overrides. */
8384 const reg_entry
*default_seg
= NULL
;
8386 /* We only need to check those implicit registers for instructions
8387 with 3 operands or less. */
8388 if (i
.operands
<= 3)
8389 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8390 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8393 if (i
.tm
.opcode_modifier
.sse2avx
)
8395 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8397 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8398 i
.prefix
[REX_PREFIX
] = 0;
8401 /* ImmExt should be processed after SSE2AVX. */
8402 else if (i
.tm
.opcode_modifier
.immext
)
8405 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8406 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8407 new destination operand here, while converting the source one to register
8409 if (i
.tm
.mnem_off
== MN_tilezero
)
8411 i
.op
[1].regs
= i
.op
[0].regs
;
8412 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8413 i
.types
[1] = i
.types
[0];
8414 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8415 i
.flags
[1] = i
.flags
[0];
8421 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8423 static const i386_operand_type regxmm
= {
8424 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8426 unsigned int dupl
= i
.operands
;
8427 unsigned int dest
= dupl
- 1;
8430 /* The destination must be an xmm register. */
8431 gas_assert (i
.reg_operands
8432 && MAX_OPERANDS
> dupl
8433 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8435 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8436 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8438 /* Keep xmm0 for instructions with VEX prefix and 3
8440 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8441 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8446 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8448 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8450 /* Add the implicit xmm0 for instructions with VEX prefix
8452 for (j
= i
.operands
; j
> 0; j
--)
8454 i
.op
[j
] = i
.op
[j
- 1];
8455 i
.types
[j
] = i
.types
[j
- 1];
8456 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8457 i
.flags
[j
] = i
.flags
[j
- 1];
8460 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8461 i
.types
[0] = regxmm
;
8462 i
.tm
.operand_types
[0] = regxmm
;
8465 i
.reg_operands
+= 2;
8470 i
.op
[dupl
] = i
.op
[dest
];
8471 i
.types
[dupl
] = i
.types
[dest
];
8472 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8473 i
.flags
[dupl
] = i
.flags
[dest
];
8482 i
.op
[dupl
] = i
.op
[dest
];
8483 i
.types
[dupl
] = i
.types
[dest
];
8484 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8485 i
.flags
[dupl
] = i
.flags
[dest
];
8488 if (i
.tm
.opcode_modifier
.immext
)
8491 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8492 && i
.tm
.opcode_modifier
.modrm
)
8496 for (j
= 1; j
< i
.operands
; j
++)
8498 i
.op
[j
- 1] = i
.op
[j
];
8499 i
.types
[j
- 1] = i
.types
[j
];
8501 /* We need to adjust fields in i.tm since they are used by
8502 build_modrm_byte. */
8503 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8505 i
.flags
[j
- 1] = i
.flags
[j
];
8508 /* No adjustment to i.reg_operands: This was already done at the top
8513 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8515 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8517 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8518 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8519 regnum
= register_number (i
.op
[1].regs
);
8520 first_reg_in_group
= regnum
& ~3;
8521 last_reg_in_group
= first_reg_in_group
+ 3;
8522 if (regnum
!= first_reg_in_group
)
8523 as_warn (_("source register `%s%s' implicitly denotes"
8524 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8525 register_prefix
, i
.op
[1].regs
->reg_name
,
8526 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8527 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8530 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8532 /* The imul $imm, %reg instruction is converted into
8533 imul $imm, %reg, %reg, and the clr %reg instruction
8534 is converted into xor %reg, %reg. */
8536 unsigned int first_reg_op
;
8538 if (operand_type_check (i
.types
[0], reg
))
8542 /* Pretend we saw the extra register operand. */
8543 gas_assert (i
.reg_operands
== 1
8544 && i
.op
[first_reg_op
+ 1].regs
== 0);
8545 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8546 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8551 if (i
.tm
.opcode_modifier
.modrm
)
8553 /* The opcode is completed (modulo i.tm.extension_opcode which
8554 must be put into the modrm byte). Now, we make the modrm and
8555 index base bytes based on all the info we've collected. */
8557 default_seg
= build_modrm_byte ();
8559 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8561 /* Warn about some common errors, but press on regardless. */
8562 if (i
.operands
== 2)
8564 /* Reversed arguments on faddp or fmulp. */
8565 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8566 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8567 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8569 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8571 /* Extraneous `l' suffix on fp insn. */
8572 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8573 register_prefix
, i
.op
[0].regs
->reg_name
);
8577 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8579 if (flag_code
!= CODE_64BIT
8580 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8581 && i
.op
[0].regs
->reg_num
== 1
8582 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8583 && i
.op
[0].regs
->reg_num
< 4)
8585 as_bad (_("you can't `%s %s%s'"),
8586 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8589 if (i
.op
[0].regs
->reg_num
> 3
8590 && i
.tm
.opcode_space
== SPACE_BASE
)
8592 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8593 i
.tm
.opcode_space
= SPACE_0F
;
8595 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8597 else if (i
.tm
.opcode_space
== SPACE_BASE
8598 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8600 default_seg
= reg_ds
;
8602 else if (i
.tm
.opcode_modifier
.isstring
)
8604 /* For the string instructions that allow a segment override
8605 on one of their operands, the default segment is ds. */
8606 default_seg
= reg_ds
;
8608 else if (i
.short_form
)
8610 /* The register operand is in the 1st or 2nd non-immediate operand. */
8611 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8614 && r
->reg_type
.bitfield
.instance
== Accum
8615 && i
.op
[i
.imm_operands
+ 1].regs
)
8616 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8617 /* Register goes in low 3 bits of opcode. */
8618 i
.tm
.base_opcode
|= r
->reg_num
;
8619 set_rex_vrex (r
, REX_B
, false);
8621 if (dot_insn () && i
.reg_operands
== 2)
8623 gas_assert (is_any_vex_encoding (&i
.tm
)
8624 || i
.vec_encoding
!= vex_encoding_default
);
8625 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8628 else if (i
.reg_operands
== 1
8629 && !i
.flags
[i
.operands
- 1]
8630 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8633 gas_assert (is_any_vex_encoding (&i
.tm
)
8634 || i
.vec_encoding
!= vex_encoding_default
);
8635 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8638 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8639 && i
.tm
.mnem_off
== MN_lea
)
8641 if (!quiet_warnings
)
8642 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8643 if (optimize
&& !i
.no_optimize
)
8646 i
.prefix
[SEG_PREFIX
] = 0;
8650 /* If a segment was explicitly specified, and the specified segment
8651 is neither the default nor the one already recorded from a prefix,
8652 use an opcode prefix to select it. If we never figured out what
8653 the default segment is, then default_seg will be zero at this
8654 point, and the specified segment prefix will always be used. */
8656 && i
.seg
[0] != default_seg
8657 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8659 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8665 static const reg_entry
*
8666 build_modrm_byte (void)
8668 const reg_entry
*default_seg
= NULL
;
8669 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8670 /* Compensate for kludge in md_assemble(). */
8671 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8672 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8673 unsigned int v
, op
, reg_slot
= ~0;
8675 /* Accumulator (in particular %st), shift count (%cl), and alike need
8676 to be skipped just like immediate operands do. */
8677 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8679 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8682 for (op
= source
; op
< i
.operands
; ++op
)
8683 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8686 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8690 /* There are 2 kinds of instructions:
8691 1. 5 operands: 4 register operands or 3 register operands
8692 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8693 VexW0 or VexW1. The destination must be either XMM, YMM or
8695 2. 4 operands: 4 register operands or 3 register operands
8696 plus 1 memory operand, with VexXDS.
8697 3. Other equivalent combinations when coming from s_insn(). */
8698 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8699 && i
.tm
.opcode_modifier
.vexw
);
8700 gas_assert (dot_insn ()
8701 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8703 /* Of the first two non-immediate operands the one with the template
8704 not allowing for a memory one is encoded in the immediate operand. */
8706 reg_slot
= source
+ 1;
8708 reg_slot
= source
++;
8712 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8713 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8716 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8718 if (i
.imm_operands
== 0)
8720 /* When there is no immediate operand, generate an 8bit
8721 immediate operand to encode the first operand. */
8722 exp
= &im_expressions
[i
.imm_operands
++];
8723 i
.op
[i
.operands
].imms
= exp
;
8724 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8727 exp
->X_op
= O_constant
;
8731 gas_assert (i
.imm_operands
== 1);
8732 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8733 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8735 /* Turn on Imm8 again so that output_imm will generate it. */
8736 i
.types
[0].bitfield
.imm8
= 1;
8740 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8741 << (3 + !(is_evex_encoding (&i
.tm
)
8742 || i
.vec_encoding
== vex_encoding_evex
));
8745 for (v
= source
+ 1; v
< dest
; ++v
)
8750 if (i
.tm
.extension_opcode
!= None
)
8756 gas_assert (source
< dest
);
8757 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8760 unsigned int tmp
= source
;
8766 if (v
< MAX_OPERANDS
)
8768 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8769 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8772 if (op
< i
.operands
)
8776 unsigned int fake_zero_displacement
= 0;
8778 gas_assert (i
.flags
[op
] & Operand_Mem
);
8780 if (i
.tm
.opcode_modifier
.sib
)
8782 /* The index register of VSIB shouldn't be RegIZ. */
8783 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8784 && i
.index_reg
->reg_num
== RegIZ
)
8787 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8790 i
.sib
.base
= NO_BASE_REGISTER
;
8791 i
.sib
.scale
= i
.log2_scale_factor
;
8792 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8793 i
.types
[op
].bitfield
.disp32
= 1;
8796 /* Since the mandatory SIB always has index register, so
8797 the code logic remains unchanged. The non-mandatory SIB
8798 without index register is allowed and will be handled
8802 if (i
.index_reg
->reg_num
== RegIZ
)
8803 i
.sib
.index
= NO_INDEX_REGISTER
;
8805 i
.sib
.index
= i
.index_reg
->reg_num
;
8806 set_rex_vrex (i
.index_reg
, REX_X
, false);
8810 default_seg
= reg_ds
;
8812 if (i
.base_reg
== 0)
8815 if (!i
.disp_operands
)
8816 fake_zero_displacement
= 1;
8817 if (i
.index_reg
== 0)
8819 /* Both check for VSIB and mandatory non-vector SIB. */
8820 gas_assert (!i
.tm
.opcode_modifier
.sib
8821 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8822 /* Operand is just <disp> */
8823 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8824 if (flag_code
== CODE_64BIT
)
8826 /* 64bit mode overwrites the 32bit absolute
8827 addressing by RIP relative addressing and
8828 absolute addressing is encoded by one of the
8829 redundant SIB forms. */
8830 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8831 i
.sib
.base
= NO_BASE_REGISTER
;
8832 i
.sib
.index
= NO_INDEX_REGISTER
;
8833 i
.types
[op
].bitfield
.disp32
= 1;
8835 else if ((flag_code
== CODE_16BIT
)
8836 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8838 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8839 i
.types
[op
].bitfield
.disp16
= 1;
8843 i
.rm
.regmem
= NO_BASE_REGISTER
;
8844 i
.types
[op
].bitfield
.disp32
= 1;
8847 else if (!i
.tm
.opcode_modifier
.sib
)
8849 /* !i.base_reg && i.index_reg */
8850 if (i
.index_reg
->reg_num
== RegIZ
)
8851 i
.sib
.index
= NO_INDEX_REGISTER
;
8853 i
.sib
.index
= i
.index_reg
->reg_num
;
8854 i
.sib
.base
= NO_BASE_REGISTER
;
8855 i
.sib
.scale
= i
.log2_scale_factor
;
8856 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8857 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8858 i
.types
[op
].bitfield
.disp32
= 1;
8859 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8863 /* RIP addressing for 64bit mode. */
8864 else if (i
.base_reg
->reg_num
== RegIP
)
8866 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8867 i
.rm
.regmem
= NO_BASE_REGISTER
;
8868 i
.types
[op
].bitfield
.disp8
= 0;
8869 i
.types
[op
].bitfield
.disp16
= 0;
8870 i
.types
[op
].bitfield
.disp32
= 1;
8871 i
.types
[op
].bitfield
.disp64
= 0;
8872 i
.flags
[op
] |= Operand_PCrel
;
8873 if (! i
.disp_operands
)
8874 fake_zero_displacement
= 1;
8876 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8878 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8879 switch (i
.base_reg
->reg_num
)
8882 if (i
.index_reg
== 0)
8884 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8885 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8888 default_seg
= reg_ss
;
8889 if (i
.index_reg
== 0)
8892 if (operand_type_check (i
.types
[op
], disp
) == 0)
8894 /* fake (%bp) into 0(%bp) */
8895 if (i
.disp_encoding
== disp_encoding_16bit
)
8896 i
.types
[op
].bitfield
.disp16
= 1;
8898 i
.types
[op
].bitfield
.disp8
= 1;
8899 fake_zero_displacement
= 1;
8902 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8903 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8905 default: /* (%si) -> 4 or (%di) -> 5 */
8906 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8908 if (!fake_zero_displacement
8912 fake_zero_displacement
= 1;
8913 if (i
.disp_encoding
== disp_encoding_8bit
)
8914 i
.types
[op
].bitfield
.disp8
= 1;
8916 i
.types
[op
].bitfield
.disp16
= 1;
8918 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8920 else /* i.base_reg and 32/64 bit mode */
8922 if (operand_type_check (i
.types
[op
], disp
))
8924 i
.types
[op
].bitfield
.disp16
= 0;
8925 i
.types
[op
].bitfield
.disp64
= 0;
8926 i
.types
[op
].bitfield
.disp32
= 1;
8929 if (!i
.tm
.opcode_modifier
.sib
)
8930 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8931 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8933 i
.sib
.base
= i
.base_reg
->reg_num
;
8934 /* x86-64 ignores REX prefix bit here to avoid decoder
8936 if (!(i
.base_reg
->reg_flags
& RegRex
)
8937 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8938 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8939 default_seg
= reg_ss
;
8940 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8942 fake_zero_displacement
= 1;
8943 if (i
.disp_encoding
== disp_encoding_32bit
)
8944 i
.types
[op
].bitfield
.disp32
= 1;
8946 i
.types
[op
].bitfield
.disp8
= 1;
8948 i
.sib
.scale
= i
.log2_scale_factor
;
8949 if (i
.index_reg
== 0)
8951 /* Only check for VSIB. */
8952 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8953 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8954 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8956 /* <disp>(%esp) becomes two byte modrm with no index
8957 register. We've already stored the code for esp
8958 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8959 Any base register besides %esp will not use the
8960 extra modrm byte. */
8961 i
.sib
.index
= NO_INDEX_REGISTER
;
8963 else if (!i
.tm
.opcode_modifier
.sib
)
8965 if (i
.index_reg
->reg_num
== RegIZ
)
8966 i
.sib
.index
= NO_INDEX_REGISTER
;
8968 i
.sib
.index
= i
.index_reg
->reg_num
;
8969 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8970 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8975 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8976 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8980 if (!fake_zero_displacement
8984 fake_zero_displacement
= 1;
8985 if (i
.disp_encoding
== disp_encoding_8bit
)
8986 i
.types
[op
].bitfield
.disp8
= 1;
8988 i
.types
[op
].bitfield
.disp32
= 1;
8990 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8994 if (fake_zero_displacement
)
8996 /* Fakes a zero displacement assuming that i.types[op]
8997 holds the correct displacement size. */
9000 gas_assert (i
.op
[op
].disps
== 0);
9001 exp
= &disp_expressions
[i
.disp_operands
++];
9002 i
.op
[op
].disps
= exp
;
9003 exp
->X_op
= O_constant
;
9004 exp
->X_add_number
= 0;
9005 exp
->X_add_symbol
= (symbolS
*) 0;
9006 exp
->X_op_symbol
= (symbolS
*) 0;
9012 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
9013 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
9024 if (!i
.tm
.opcode_modifier
.regmem
)
9026 gas_assert (source
< MAX_OPERANDS
);
9027 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9028 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9029 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9034 gas_assert (dest
< MAX_OPERANDS
);
9035 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9036 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9041 /* Fill in i.rm.reg field with extension opcode (if any) or the
9042 appropriate register. */
9043 if (i
.tm
.extension_opcode
!= None
)
9044 i
.rm
.reg
= i
.tm
.extension_opcode
;
9045 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9047 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9048 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9052 gas_assert (source
< MAX_OPERANDS
);
9053 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9054 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9057 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9059 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9061 add_prefix (LOCK_PREFIX_OPCODE
);
9068 frag_opcode_byte (unsigned char byte
)
9070 if (now_seg
!= absolute_section
)
9071 FRAG_APPEND_1_CHAR (byte
);
9073 ++abs_section_offset
;
9077 flip_code16 (unsigned int code16
)
9079 gas_assert (i
.tm
.operands
== 1);
9081 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9082 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9083 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9088 output_branch (void)
9094 relax_substateT subtype
;
9098 if (now_seg
== absolute_section
)
9100 as_bad (_("relaxable branches not supported in absolute section"));
9104 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9105 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9108 if (i
.prefix
[DATA_PREFIX
] != 0)
9112 code16
^= flip_code16(code16
);
9114 /* Pentium4 branch hints. */
9115 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9116 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9121 if (i
.prefix
[REX_PREFIX
] != 0)
9127 /* BND prefixed jump. */
9128 if (i
.prefix
[BND_PREFIX
] != 0)
9134 if (i
.prefixes
!= 0)
9135 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9137 /* It's always a symbol; End frag & setup for relax.
9138 Make sure there is enough room in this frag for the largest
9139 instruction we may generate in md_convert_frag. This is 2
9140 bytes for the opcode and room for the prefix and largest
9142 frag_grow (prefix
+ 2 + 4);
9143 /* Prefix and 1 opcode byte go in fr_fix. */
9144 p
= frag_more (prefix
+ 1);
9145 if (i
.prefix
[DATA_PREFIX
] != 0)
9146 *p
++ = DATA_PREFIX_OPCODE
;
9147 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9148 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9149 *p
++ = i
.prefix
[SEG_PREFIX
];
9150 if (i
.prefix
[BND_PREFIX
] != 0)
9151 *p
++ = BND_PREFIX_OPCODE
;
9152 if (i
.prefix
[REX_PREFIX
] != 0)
9153 *p
++ = i
.prefix
[REX_PREFIX
];
9154 *p
= i
.tm
.base_opcode
;
9156 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9157 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9158 else if (cpu_arch_flags
.bitfield
.cpui386
)
9159 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9161 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9164 sym
= i
.op
[0].disps
->X_add_symbol
;
9165 off
= i
.op
[0].disps
->X_add_number
;
9167 if (i
.op
[0].disps
->X_op
!= O_constant
9168 && i
.op
[0].disps
->X_op
!= O_symbol
)
9170 /* Handle complex expressions. */
9171 sym
= make_expr_symbol (i
.op
[0].disps
);
9175 /* 1 possible extra opcode + 4 byte displacement go in var part.
9176 Pass reloc in fr_var. */
9177 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9181 /* Return TRUE iff PLT32 relocation should be used for branching to
9185 need_plt32_p (symbolS
*s
)
9187 /* PLT32 relocation is ELF only. */
9192 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9193 krtld support it. */
9197 /* Since there is no need to prepare for PLT branch on x86-64, we
9198 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9199 be used as a marker for 32-bit PC-relative branches. */
9206 /* Weak or undefined symbol need PLT32 relocation. */
9207 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9210 /* Non-global symbol doesn't need PLT32 relocation. */
9211 if (! S_IS_EXTERNAL (s
))
9214 /* Other global symbols need PLT32 relocation. NB: Symbol with
9215 non-default visibilities are treated as normal global symbol
9216 so that PLT32 relocation can be used as a marker for 32-bit
9217 PC-relative branches. It is useful for linker relaxation. */
9228 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9230 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9232 /* This is a loop or jecxz type instruction. */
9234 if (i
.prefix
[ADDR_PREFIX
] != 0)
9236 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9239 /* Pentium4 branch hints. */
9240 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9241 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9243 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9252 if (flag_code
== CODE_16BIT
)
9255 if (i
.prefix
[DATA_PREFIX
] != 0)
9257 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9259 code16
^= flip_code16(code16
);
9267 /* BND prefixed jump. */
9268 if (i
.prefix
[BND_PREFIX
] != 0)
9270 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9274 if (i
.prefix
[REX_PREFIX
] != 0)
9276 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9280 if (i
.prefixes
!= 0)
9281 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9283 if (now_seg
== absolute_section
)
9285 abs_section_offset
+= i
.opcode_length
+ size
;
9289 p
= frag_more (i
.opcode_length
+ size
);
9290 switch (i
.opcode_length
)
9293 *p
++ = i
.tm
.base_opcode
>> 8;
9296 *p
++ = i
.tm
.base_opcode
;
9302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9303 if (flag_code
== CODE_64BIT
&& size
== 4
9304 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9305 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9306 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9309 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9311 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9312 i
.op
[0].disps
, 1, jump_reloc
);
9314 /* All jumps handled here are signed, but don't unconditionally use a
9315 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9316 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9321 fixP
->fx_signed
= 1;
9325 if (i
.tm
.mnem_off
== MN_xbegin
)
9326 fixP
->fx_signed
= 1;
9330 if (flag_code
== CODE_64BIT
)
9331 fixP
->fx_signed
= 1;
9337 output_interseg_jump (void)
9345 if (flag_code
== CODE_16BIT
)
9349 if (i
.prefix
[DATA_PREFIX
] != 0)
9356 gas_assert (!i
.prefix
[REX_PREFIX
]);
9362 if (i
.prefixes
!= 0)
9363 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9365 if (now_seg
== absolute_section
)
9367 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9371 /* 1 opcode; 2 segment; offset */
9372 p
= frag_more (prefix
+ 1 + 2 + size
);
9374 if (i
.prefix
[DATA_PREFIX
] != 0)
9375 *p
++ = DATA_PREFIX_OPCODE
;
9377 if (i
.prefix
[REX_PREFIX
] != 0)
9378 *p
++ = i
.prefix
[REX_PREFIX
];
9380 *p
++ = i
.tm
.base_opcode
;
9381 if (i
.op
[1].imms
->X_op
== O_constant
)
9383 offsetT n
= i
.op
[1].imms
->X_add_number
;
9386 && !fits_in_unsigned_word (n
)
9387 && !fits_in_signed_word (n
))
9389 as_bad (_("16-bit jump out of range"));
9392 md_number_to_chars (p
, n
, size
);
9395 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9396 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9399 if (i
.op
[0].imms
->X_op
== O_constant
)
9400 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9402 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9403 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9406 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9411 asection
*seg
= now_seg
;
9412 subsegT subseg
= now_subseg
;
9414 unsigned int alignment
, align_size_1
;
9415 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9416 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9417 unsigned int padding
;
9419 if (!IS_ELF
|| !x86_used_note
)
9422 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9424 /* The .note.gnu.property section layout:
9426 Field Length Contents
9429 n_descsz 4 The note descriptor size
9430 n_type 4 NT_GNU_PROPERTY_TYPE_0
9432 n_desc n_descsz The program property array
9436 /* Create the .note.gnu.property section. */
9437 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9438 bfd_set_section_flags (sec
,
9445 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9456 bfd_set_section_alignment (sec
, alignment
);
9457 elf_section_type (sec
) = SHT_NOTE
;
9459 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9461 isa_1_descsz_raw
= 4 + 4 + 4;
9462 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9463 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9465 feature_2_descsz_raw
= isa_1_descsz
;
9466 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9468 feature_2_descsz_raw
+= 4 + 4 + 4;
9469 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9470 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9473 descsz
= feature_2_descsz
;
9474 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9475 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9477 /* Write n_namsz. */
9478 md_number_to_chars (p
, (valueT
) 4, 4);
9480 /* Write n_descsz. */
9481 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9484 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9487 memcpy (p
+ 4 * 3, "GNU", 4);
9489 /* Write 4-byte type. */
9490 md_number_to_chars (p
+ 4 * 4,
9491 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9493 /* Write 4-byte data size. */
9494 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9496 /* Write 4-byte data. */
9497 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9499 /* Zero out paddings. */
9500 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9502 memset (p
+ 4 * 7, 0, padding
);
9504 /* Write 4-byte type. */
9505 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9506 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9508 /* Write 4-byte data size. */
9509 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9511 /* Write 4-byte data. */
9512 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9513 (valueT
) x86_feature_2_used
, 4);
9515 /* Zero out paddings. */
9516 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9518 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9520 /* We probably can't restore the current segment, for there likely
9523 subseg_set (seg
, subseg
);
9527 x86_support_sframe_p (void)
9529 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9530 return (x86_elf_abi
== X86_64_ABI
);
9534 x86_sframe_ra_tracking_p (void)
9536 /* In AMD64, return address is always stored on the stack at a fixed offset
9537 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9538 Do not track explicitly via an SFrame Frame Row Entry. */
9543 x86_sframe_cfa_ra_offset (void)
9545 gas_assert (x86_elf_abi
== X86_64_ABI
);
9546 return (offsetT
) -8;
9550 x86_sframe_get_abi_arch (void)
9552 unsigned char sframe_abi_arch
= 0;
9554 if (x86_support_sframe_p ())
9556 gas_assert (!target_big_endian
);
9557 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9560 return sframe_abi_arch
;
9566 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9567 const char *frag_now_ptr
)
9569 unsigned int len
= 0;
9571 if (start_frag
!= frag_now
)
9573 const fragS
*fr
= start_frag
;
9578 } while (fr
&& fr
!= frag_now
);
9581 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9584 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9585 be macro-fused with conditional jumps.
9586 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9587 or is one of the following format:
9600 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9602 /* No RIP address. */
9603 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9606 /* No opcodes outside of base encoding space. */
9607 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9610 /* add, sub without add/sub m, imm. */
9611 if (i
.tm
.base_opcode
<= 5
9612 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9613 || ((i
.tm
.base_opcode
| 3) == 0x83
9614 && (i
.tm
.extension_opcode
== 0x5
9615 || i
.tm
.extension_opcode
== 0x0)))
9617 *mf_cmp_p
= mf_cmp_alu_cmp
;
9618 return !(i
.mem_operands
&& i
.imm_operands
);
9621 /* and without and m, imm. */
9622 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9623 || ((i
.tm
.base_opcode
| 3) == 0x83
9624 && i
.tm
.extension_opcode
== 0x4))
9626 *mf_cmp_p
= mf_cmp_test_and
;
9627 return !(i
.mem_operands
&& i
.imm_operands
);
9630 /* test without test m imm. */
9631 if ((i
.tm
.base_opcode
| 1) == 0x85
9632 || (i
.tm
.base_opcode
| 1) == 0xa9
9633 || ((i
.tm
.base_opcode
| 1) == 0xf7
9634 && i
.tm
.extension_opcode
== 0))
9636 *mf_cmp_p
= mf_cmp_test_and
;
9637 return !(i
.mem_operands
&& i
.imm_operands
);
9640 /* cmp without cmp m, imm. */
9641 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9642 || ((i
.tm
.base_opcode
| 3) == 0x83
9643 && (i
.tm
.extension_opcode
== 0x7)))
9645 *mf_cmp_p
= mf_cmp_alu_cmp
;
9646 return !(i
.mem_operands
&& i
.imm_operands
);
9649 /* inc, dec without inc/dec m. */
9650 if ((is_cpu (&i
.tm
, CpuNo64
)
9651 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9652 || ((i
.tm
.base_opcode
| 1) == 0xff
9653 && i
.tm
.extension_opcode
<= 0x1))
9655 *mf_cmp_p
= mf_cmp_incdec
;
9656 return !i
.mem_operands
;
9662 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9665 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9667 /* NB: Don't work with COND_JUMP86 without i386. */
9668 if (!align_branch_power
9669 || now_seg
== absolute_section
9670 || !cpu_arch_flags
.bitfield
.cpui386
9671 || !(align_branch
& align_branch_fused_bit
))
9674 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9676 if (last_insn
.kind
== last_insn_other
9677 || last_insn
.seg
!= now_seg
)
9680 as_warn_where (last_insn
.file
, last_insn
.line
,
9681 _("`%s` skips -malign-branch-boundary on `%s`"),
9682 last_insn
.name
, insn_name (&i
.tm
));
9688 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9691 add_branch_prefix_frag_p (void)
9693 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9694 to PadLock instructions since they include prefixes in opcode. */
9695 if (!align_branch_power
9696 || !align_branch_prefix_size
9697 || now_seg
== absolute_section
9698 || is_cpu (&i
.tm
, CpuPadLock
)
9699 || !cpu_arch_flags
.bitfield
.cpui386
)
9702 /* Don't add prefix if it is a prefix or there is no operand in case
9703 that segment prefix is special. */
9704 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9707 if (last_insn
.kind
== last_insn_other
9708 || last_insn
.seg
!= now_seg
)
9712 as_warn_where (last_insn
.file
, last_insn
.line
,
9713 _("`%s` skips -malign-branch-boundary on `%s`"),
9714 last_insn
.name
, insn_name (&i
.tm
));
9719 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9722 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9723 enum mf_jcc_kind
*mf_jcc_p
)
9727 /* NB: Don't work with COND_JUMP86 without i386. */
9728 if (!align_branch_power
9729 || now_seg
== absolute_section
9730 || !cpu_arch_flags
.bitfield
.cpui386
9731 || i
.tm
.opcode_space
!= SPACE_BASE
)
9736 /* Check for jcc and direct jmp. */
9737 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9739 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9741 *branch_p
= align_branch_jmp
;
9742 add_padding
= align_branch
& align_branch_jmp_bit
;
9746 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9747 igore the lowest bit. */
9748 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9749 *branch_p
= align_branch_jcc
;
9750 if ((align_branch
& align_branch_jcc_bit
))
9754 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9757 *branch_p
= align_branch_ret
;
9758 if ((align_branch
& align_branch_ret_bit
))
9763 /* Check for indirect jmp, direct and indirect calls. */
9764 if (i
.tm
.base_opcode
== 0xe8)
9767 *branch_p
= align_branch_call
;
9768 if ((align_branch
& align_branch_call_bit
))
9771 else if (i
.tm
.base_opcode
== 0xff
9772 && (i
.tm
.extension_opcode
== 2
9773 || i
.tm
.extension_opcode
== 4))
9775 /* Indirect call and jmp. */
9776 *branch_p
= align_branch_indirect
;
9777 if ((align_branch
& align_branch_indirect_bit
))
9784 && (i
.op
[0].disps
->X_op
== O_symbol
9785 || (i
.op
[0].disps
->X_op
== O_subtract
9786 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9788 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9789 /* No padding to call to global or undefined tls_get_addr. */
9790 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9791 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9797 && last_insn
.kind
!= last_insn_other
9798 && last_insn
.seg
== now_seg
)
9801 as_warn_where (last_insn
.file
, last_insn
.line
,
9802 _("`%s` skips -malign-branch-boundary on `%s`"),
9803 last_insn
.name
, insn_name (&i
.tm
));
9813 fragS
*insn_start_frag
;
9814 offsetT insn_start_off
;
9815 fragS
*fragP
= NULL
;
9816 enum align_branch_kind branch
= align_branch_none
;
9817 /* The initializer is arbitrary just to avoid uninitialized error.
9818 it's actually either assigned in add_branch_padding_frag_p
9819 or never be used. */
9820 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9823 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9825 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9826 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9827 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9829 if (is_cpu (&i
.tm
, Cpu8087
)
9830 || is_cpu (&i
.tm
, Cpu287
)
9831 || is_cpu (&i
.tm
, Cpu387
)
9832 || is_cpu (&i
.tm
, Cpu687
)
9833 || is_cpu (&i
.tm
, CpuFISTTP
))
9834 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9836 if ((i
.xstate
& xstate_mmx
)
9837 || i
.tm
.mnem_off
== MN_emms
9838 || i
.tm
.mnem_off
== MN_femms
)
9839 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9843 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9844 i
.xstate
|= xstate_zmm
;
9845 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9846 i
.xstate
|= xstate_ymm
;
9847 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9848 i
.xstate
|= xstate_xmm
;
9851 /* vzeroall / vzeroupper */
9852 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9853 i
.xstate
|= xstate_ymm
;
9855 if ((i
.xstate
& xstate_xmm
)
9856 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9857 || (i
.tm
.base_opcode
== 0xae
9858 && (is_cpu (&i
.tm
, CpuSSE
)
9859 || is_cpu (&i
.tm
, CpuAVX
)))
9860 || is_cpu (&i
.tm
, CpuWideKL
)
9861 || is_cpu (&i
.tm
, CpuKL
))
9862 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9864 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9865 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9866 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9867 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9868 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9869 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9870 if (is_cpu (&i
.tm
, CpuFXSR
))
9871 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9872 if (is_cpu (&i
.tm
, CpuXsave
))
9873 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9874 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9875 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9876 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9877 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9879 if (x86_feature_2_used
9880 || is_cpu (&i
.tm
, CpuCMOV
)
9881 || is_cpu (&i
.tm
, CpuSYSCALL
)
9882 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9883 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9884 if (is_cpu (&i
.tm
, CpuSSE3
)
9885 || is_cpu (&i
.tm
, CpuSSSE3
)
9886 || is_cpu (&i
.tm
, CpuSSE4_1
)
9887 || is_cpu (&i
.tm
, CpuSSE4_2
)
9888 || is_cpu (&i
.tm
, CpuCX16
)
9889 || is_cpu (&i
.tm
, CpuPOPCNT
)
9890 /* LAHF-SAHF insns in 64-bit mode. */
9891 || (flag_code
== CODE_64BIT
9892 && (i
.tm
.base_opcode
| 1) == 0x9f
9893 && i
.tm
.opcode_space
== SPACE_BASE
))
9894 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9895 if (is_cpu (&i
.tm
, CpuAVX
)
9896 || is_cpu (&i
.tm
, CpuAVX2
)
9897 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9898 XOP, FMA4, LPW, TBM, and AMX. */
9899 || (i
.tm
.opcode_modifier
.vex
9900 && !is_cpu (&i
.tm
, CpuAVX512F
)
9901 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9902 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9903 && !is_cpu (&i
.tm
, CpuXOP
)
9904 && !is_cpu (&i
.tm
, CpuFMA4
)
9905 && !is_cpu (&i
.tm
, CpuLWP
)
9906 && !is_cpu (&i
.tm
, CpuTBM
)
9907 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9908 || is_cpu (&i
.tm
, CpuF16C
)
9909 || is_cpu (&i
.tm
, CpuFMA
)
9910 || is_cpu (&i
.tm
, CpuLZCNT
)
9911 || is_cpu (&i
.tm
, CpuMovbe
)
9912 || is_cpu (&i
.tm
, CpuXSAVES
)
9913 || (x86_feature_2_used
9914 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9915 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9916 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9917 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9918 if (is_cpu (&i
.tm
, CpuAVX512F
)
9919 || is_cpu (&i
.tm
, CpuAVX512BW
)
9920 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9921 || is_cpu (&i
.tm
, CpuAVX512VL
)
9922 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9923 AVX512-4FMAPS, and AVX512-4VNNIW. */
9924 || (i
.tm
.opcode_modifier
.evex
9925 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9926 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9927 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9928 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9929 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9933 /* Tie dwarf2 debug info to the address at the start of the insn.
9934 We can't do this after the insn has been output as the current
9935 frag may have been closed off. eg. by frag_var. */
9936 dwarf2_emit_insn (0);
9938 insn_start_frag
= frag_now
;
9939 insn_start_off
= frag_now_fix ();
9941 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9944 /* Branch can be 8 bytes. Leave some room for prefixes. */
9945 unsigned int max_branch_padding_size
= 14;
9947 /* Align section to boundary. */
9948 record_alignment (now_seg
, align_branch_power
);
9950 /* Make room for padding. */
9951 frag_grow (max_branch_padding_size
);
9953 /* Start of the padding. */
9958 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9959 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9962 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9963 fragP
->tc_frag_data
.branch_type
= branch
;
9964 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9967 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9968 && !pre_386_16bit_warned
)
9970 as_warn (_("use .code16 to ensure correct addressing mode"));
9971 pre_386_16bit_warned
= true;
9975 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9977 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9978 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9980 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9981 output_interseg_jump ();
9984 /* Output normal instructions here. */
9988 enum mf_cmp_kind mf_cmp
;
9991 && (i
.tm
.base_opcode
== 0xaee8
9992 || i
.tm
.base_opcode
== 0xaef0
9993 || i
.tm
.base_opcode
== 0xaef8))
9995 /* Encode lfence, mfence, and sfence as
9996 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9997 if (flag_code
== CODE_16BIT
)
9998 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9999 else if (omit_lock_prefix
)
10000 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
10001 insn_name (&i
.tm
));
10002 else if (now_seg
!= absolute_section
)
10004 offsetT val
= 0x240483f0ULL
;
10007 md_number_to_chars (p
, val
, 5);
10010 abs_section_offset
+= 5;
10014 /* Some processors fail on LOCK prefix. This options makes
10015 assembler ignore LOCK prefix and serves as a workaround. */
10016 if (omit_lock_prefix
)
10018 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
10019 && i
.tm
.opcode_modifier
.isprefix
)
10021 i
.prefix
[LOCK_PREFIX
] = 0;
10025 /* Skip if this is a branch. */
10027 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10029 /* Make room for padding. */
10030 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10035 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10036 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10039 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10040 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10041 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10043 else if (add_branch_prefix_frag_p ())
10045 unsigned int max_prefix_size
= align_branch_prefix_size
;
10047 /* Make room for padding. */
10048 frag_grow (max_prefix_size
);
10053 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10054 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10057 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10060 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10061 don't need the explicit prefix. */
10062 if (!is_any_vex_encoding (&i
.tm
))
10064 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10073 if (!is_cpu (&i
.tm
, CpuPadLock
)
10074 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10078 switch (i
.opcode_length
)
10083 /* Check for pseudo prefixes. */
10084 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10086 as_bad_where (insn_start_frag
->fr_file
,
10087 insn_start_frag
->fr_line
,
10088 _("pseudo prefix without instruction"));
10098 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10099 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10100 R_X86_64_GOTTPOFF relocation so that linker can safely
10101 perform IE->LE optimization. A dummy REX_OPCODE prefix
10102 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10103 relocation for GDesc -> IE/LE optimization. */
10104 if (x86_elf_abi
== X86_64_X32_ABI
10106 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10107 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10108 && i
.prefix
[REX_PREFIX
] == 0)
10109 add_prefix (REX_OPCODE
);
10112 /* The prefix bytes. */
10113 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10115 frag_opcode_byte (*q
);
10119 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10125 frag_opcode_byte (*q
);
10128 /* There should be no other prefixes for instructions
10129 with VEX prefix. */
10133 /* For EVEX instructions i.vrex should become 0 after
10134 build_evex_prefix. For VEX instructions upper 16 registers
10135 aren't available, so VREX should be 0. */
10138 /* Now the VEX prefix. */
10139 if (now_seg
!= absolute_section
)
10141 p
= frag_more (i
.vex
.length
);
10142 for (j
= 0; j
< i
.vex
.length
; j
++)
10143 p
[j
] = i
.vex
.bytes
[j
];
10146 abs_section_offset
+= i
.vex
.length
;
10149 /* Now the opcode; be careful about word order here! */
10150 j
= i
.opcode_length
;
10152 switch (i
.tm
.opcode_space
)
10167 if (now_seg
== absolute_section
)
10168 abs_section_offset
+= j
;
10171 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10177 && i
.tm
.opcode_space
!= SPACE_BASE
)
10180 if (i
.tm
.opcode_space
!= SPACE_0F
)
10181 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10185 switch (i
.opcode_length
)
10188 /* Put out high byte first: can't use md_number_to_chars! */
10189 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10190 /* Fall through. */
10192 *p
= i
.tm
.base_opcode
& 0xff;
10201 /* Now the modrm byte and sib byte (if present). */
10202 if (i
.tm
.opcode_modifier
.modrm
)
10204 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10206 | (i
.rm
.mode
<< 6));
10207 /* If i.rm.regmem == ESP (4)
10208 && i.rm.mode != (Register mode)
10210 ==> need second modrm byte. */
10211 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10213 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10214 frag_opcode_byte ((i
.sib
.base
<< 0)
10215 | (i
.sib
.index
<< 3)
10216 | (i
.sib
.scale
<< 6));
10219 if (i
.disp_operands
)
10220 output_disp (insn_start_frag
, insn_start_off
);
10222 if (i
.imm_operands
)
10223 output_imm (insn_start_frag
, insn_start_off
);
10226 * frag_now_fix () returning plain abs_section_offset when we're in the
10227 * absolute section, and abs_section_offset not getting updated as data
10228 * gets added to the frag breaks the logic below.
10230 if (now_seg
!= absolute_section
)
10232 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10234 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10238 /* NB: Don't add prefix with GOTPC relocation since
10239 output_disp() above depends on the fixed encoding
10240 length. Can't add prefix with TLS relocation since
10241 it breaks TLS linker optimization. */
10242 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10243 /* Prefix count on the current instruction. */
10244 unsigned int count
= i
.vex
.length
;
10246 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10247 /* REX byte is encoded in VEX/EVEX prefix. */
10248 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10251 /* Count prefixes for extended opcode maps. */
10253 switch (i
.tm
.opcode_space
)
10268 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10271 /* Set the maximum prefix size in BRANCH_PREFIX
10273 if (fragP
->tc_frag_data
.max_bytes
> max
)
10274 fragP
->tc_frag_data
.max_bytes
= max
;
10275 if (fragP
->tc_frag_data
.max_bytes
> count
)
10276 fragP
->tc_frag_data
.max_bytes
-= count
;
10278 fragP
->tc_frag_data
.max_bytes
= 0;
10282 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10284 unsigned int max_prefix_size
;
10285 if (align_branch_prefix_size
> max
)
10286 max_prefix_size
= max
;
10288 max_prefix_size
= align_branch_prefix_size
;
10289 if (max_prefix_size
> count
)
10290 fragP
->tc_frag_data
.max_prefix_length
10291 = max_prefix_size
- count
;
10294 /* Use existing segment prefix if possible. Use CS
10295 segment prefix in 64-bit mode. In 32-bit mode, use SS
10296 segment prefix with ESP/EBP base register and use DS
10297 segment prefix without ESP/EBP base register. */
10298 if (i
.prefix
[SEG_PREFIX
])
10299 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10300 else if (flag_code
== CODE_64BIT
)
10301 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10302 else if (i
.base_reg
10303 && (i
.base_reg
->reg_num
== 4
10304 || i
.base_reg
->reg_num
== 5))
10305 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10307 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10312 /* NB: Don't work with COND_JUMP86 without i386. */
10313 if (align_branch_power
10314 && now_seg
!= absolute_section
10315 && cpu_arch_flags
.bitfield
.cpui386
)
10317 /* Terminate each frag so that we can add prefix and check for
10319 frag_wane (frag_now
);
10326 pi ("" /*line*/, &i
);
10328 #endif /* DEBUG386 */
10331 /* Return the size of the displacement operand N. */
10334 disp_size (unsigned int n
)
10338 if (i
.types
[n
].bitfield
.disp64
)
10340 else if (i
.types
[n
].bitfield
.disp8
)
10342 else if (i
.types
[n
].bitfield
.disp16
)
10347 /* Return the size of the immediate operand N. */
10350 imm_size (unsigned int n
)
10353 if (i
.types
[n
].bitfield
.imm64
)
10355 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10357 else if (i
.types
[n
].bitfield
.imm16
)
10363 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10368 for (n
= 0; n
< i
.operands
; n
++)
10370 if (operand_type_check (i
.types
[n
], disp
))
10372 int size
= disp_size (n
);
10374 if (now_seg
== absolute_section
)
10375 abs_section_offset
+= size
;
10376 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10378 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10380 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10382 p
= frag_more (size
);
10383 md_number_to_chars (p
, val
, size
);
10387 enum bfd_reloc_code_real reloc_type
;
10388 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10389 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10390 && (!want_disp32 (&i
.tm
)
10391 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10392 && !i
.types
[n
].bitfield
.baseindex
)))
10396 /* We can't have 8 bit displacement here. */
10397 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10399 /* The PC relative address is computed relative
10400 to the instruction boundary, so in case immediate
10401 fields follows, we need to adjust the value. */
10402 if (pcrel
&& i
.imm_operands
)
10407 for (n1
= 0; n1
< i
.operands
; n1
++)
10408 if (operand_type_check (i
.types
[n1
], imm
))
10410 /* Only one immediate is allowed for PC
10411 relative address, except with .insn. */
10412 gas_assert (sz
== 0 || dot_insn ());
10413 sz
+= imm_size (n1
);
10415 /* We should find at least one immediate. */
10416 gas_assert (sz
!= 0);
10417 i
.op
[n
].disps
->X_add_number
-= sz
;
10420 p
= frag_more (size
);
10421 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10423 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10424 && (((reloc_type
== BFD_RELOC_32
10425 || reloc_type
== BFD_RELOC_X86_64_32S
10426 || (reloc_type
== BFD_RELOC_64
10428 && (i
.op
[n
].disps
->X_op
== O_symbol
10429 || (i
.op
[n
].disps
->X_op
== O_add
10430 && ((symbol_get_value_expression
10431 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10433 || reloc_type
== BFD_RELOC_32_PCREL
))
10437 reloc_type
= BFD_RELOC_386_GOTPC
;
10438 i
.has_gotpc_tls_reloc
= true;
10439 i
.op
[n
].disps
->X_add_number
+=
10440 encoding_length (insn_start_frag
, insn_start_off
, p
);
10442 else if (reloc_type
== BFD_RELOC_64
)
10443 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10445 /* Don't do the adjustment for x86-64, as there
10446 the pcrel addressing is relative to the _next_
10447 insn, and that is taken care of in other code. */
10448 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10450 else if (align_branch_power
)
10452 switch (reloc_type
)
10454 case BFD_RELOC_386_TLS_GD
:
10455 case BFD_RELOC_386_TLS_LDM
:
10456 case BFD_RELOC_386_TLS_IE
:
10457 case BFD_RELOC_386_TLS_IE_32
:
10458 case BFD_RELOC_386_TLS_GOTIE
:
10459 case BFD_RELOC_386_TLS_GOTDESC
:
10460 case BFD_RELOC_386_TLS_DESC_CALL
:
10461 case BFD_RELOC_X86_64_TLSGD
:
10462 case BFD_RELOC_X86_64_TLSLD
:
10463 case BFD_RELOC_X86_64_GOTTPOFF
:
10464 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10465 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10466 i
.has_gotpc_tls_reloc
= true;
10471 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10472 size
, i
.op
[n
].disps
, pcrel
,
10475 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10476 && !i
.prefix
[ADDR_PREFIX
])
10477 fixP
->fx_signed
= 1;
10479 /* Check for "call/jmp *mem", "mov mem, %reg",
10480 "test %reg, mem" and "binop mem, %reg" where binop
10481 is one of adc, add, and, cmp, or, sbb, sub, xor
10482 instructions without data prefix. Always generate
10483 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10484 if (i
.prefix
[DATA_PREFIX
] == 0
10485 && (generate_relax_relocations
10488 && i
.rm
.regmem
== 5))
10490 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10491 && i
.tm
.opcode_space
== SPACE_BASE
10492 && ((i
.operands
== 1
10493 && i
.tm
.base_opcode
== 0xff
10494 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10495 || (i
.operands
== 2
10496 && (i
.tm
.base_opcode
== 0x8b
10497 || i
.tm
.base_opcode
== 0x85
10498 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10502 fixP
->fx_tcbit
= i
.rex
!= 0;
10504 && (i
.base_reg
->reg_num
== RegIP
))
10505 fixP
->fx_tcbit2
= 1;
10508 fixP
->fx_tcbit2
= 1;
10516 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10521 for (n
= 0; n
< i
.operands
; n
++)
10523 if (operand_type_check (i
.types
[n
], imm
))
10525 int size
= imm_size (n
);
10527 if (now_seg
== absolute_section
)
10528 abs_section_offset
+= size
;
10529 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10533 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10535 p
= frag_more (size
);
10536 md_number_to_chars (p
, val
, size
);
10540 /* Not absolute_section.
10541 Need a 32-bit fixup (don't support 8bit
10542 non-absolute imms). Try to support other
10544 enum bfd_reloc_code_real reloc_type
;
10547 if (i
.types
[n
].bitfield
.imm32s
10548 && (i
.suffix
== QWORD_MNEM_SUFFIX
10549 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10550 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10556 p
= frag_more (size
);
10557 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10559 /* This is tough to explain. We end up with this one if we
10560 * have operands that look like
10561 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10562 * obtain the absolute address of the GOT, and it is strongly
10563 * preferable from a performance point of view to avoid using
10564 * a runtime relocation for this. The actual sequence of
10565 * instructions often look something like:
10570 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10572 * The call and pop essentially return the absolute address
10573 * of the label .L66 and store it in %ebx. The linker itself
10574 * will ultimately change the first operand of the addl so
10575 * that %ebx points to the GOT, but to keep things simple, the
10576 * .o file must have this operand set so that it generates not
10577 * the absolute address of .L66, but the absolute address of
10578 * itself. This allows the linker itself simply treat a GOTPC
10579 * relocation as asking for a pcrel offset to the GOT to be
10580 * added in, and the addend of the relocation is stored in the
10581 * operand field for the instruction itself.
10583 * Our job here is to fix the operand so that it would add
10584 * the correct offset so that %ebx would point to itself. The
10585 * thing that is tricky is that .-.L66 will point to the
10586 * beginning of the instruction, so we need to further modify
10587 * the operand so that it will point to itself. There are
10588 * other cases where you have something like:
10590 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10592 * and here no correction would be required. Internally in
10593 * the assembler we treat operands of this form as not being
10594 * pcrel since the '.' is explicitly mentioned, and I wonder
10595 * whether it would simplify matters to do it this way. Who
10596 * knows. In earlier versions of the PIC patches, the
10597 * pcrel_adjust field was used to store the correction, but
10598 * since the expression is not pcrel, I felt it would be
10599 * confusing to do it this way. */
10601 if ((reloc_type
== BFD_RELOC_32
10602 || reloc_type
== BFD_RELOC_X86_64_32S
10603 || reloc_type
== BFD_RELOC_64
)
10605 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10606 && (i
.op
[n
].imms
->X_op
== O_symbol
10607 || (i
.op
[n
].imms
->X_op
== O_add
10608 && ((symbol_get_value_expression
10609 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10613 reloc_type
= BFD_RELOC_386_GOTPC
;
10614 else if (size
== 4)
10615 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10616 else if (size
== 8)
10617 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10618 i
.has_gotpc_tls_reloc
= true;
10619 i
.op
[n
].imms
->X_add_number
+=
10620 encoding_length (insn_start_frag
, insn_start_off
, p
);
10622 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10623 i
.op
[n
].imms
, 0, reloc_type
);
10629 /* x86_cons_fix_new is called via the expression parsing code when a
10630 reloc is needed. We use this hook to get the correct .got reloc. */
10631 static int cons_sign
= -1;
10634 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10635 expressionS
*exp
, bfd_reloc_code_real_type r
)
10637 r
= reloc (len
, 0, cons_sign
, r
);
10640 if (exp
->X_op
== O_secrel
)
10642 exp
->X_op
= O_symbol
;
10643 r
= BFD_RELOC_32_SECREL
;
10645 else if (exp
->X_op
== O_secidx
)
10646 r
= BFD_RELOC_16_SECIDX
;
10649 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10652 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10653 purpose of the `.dc.a' internal pseudo-op. */
10656 x86_address_bytes (void)
10658 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10660 return stdoutput
->arch_info
->bits_per_address
/ 8;
10663 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10664 || defined (LEX_AT)) && !defined (TE_PE)
10665 # define lex_got(reloc, adjust, types) NULL
10667 /* Parse operands of the form
10668 <symbol>@GOTOFF+<nnn>
10669 and similar .plt or .got references.
10671 If we find one, set up the correct relocation in RELOC and copy the
10672 input string, minus the `@GOTOFF' into a malloc'd buffer for
10673 parsing by the calling routine. Return this buffer, and if ADJUST
10674 is non-null set it to the length of the string we removed from the
10675 input line. Otherwise return NULL. */
10677 lex_got (enum bfd_reloc_code_real
*rel
,
10679 i386_operand_type
*types
)
10681 /* Some of the relocations depend on the size of what field is to
10682 be relocated. But in our callers i386_immediate and i386_displacement
10683 we don't yet know the operand size (this will be set by insn
10684 matching). Hence we record the word32 relocation here,
10685 and adjust the reloc according to the real size in reloc(). */
10686 static const struct
10690 const enum bfd_reloc_code_real rel
[2];
10691 const i386_operand_type types64
;
10692 bool need_GOT_symbol
;
10697 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10698 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10699 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10700 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10701 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10702 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10703 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10704 { .imm64 = 1, .disp64 = 1 } }
10707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10708 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10709 BFD_RELOC_SIZE32
},
10710 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10712 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10713 BFD_RELOC_X86_64_PLTOFF64
},
10714 { .bitfield
= { .imm64
= 1 } }, true },
10715 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10716 BFD_RELOC_X86_64_PLT32
},
10717 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10718 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10719 BFD_RELOC_X86_64_GOTPLT64
},
10720 OPERAND_TYPE_IMM64_DISP64
, true },
10721 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10722 BFD_RELOC_X86_64_GOTOFF64
},
10723 OPERAND_TYPE_IMM64_DISP64
, true },
10724 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10725 BFD_RELOC_X86_64_GOTPCREL
},
10726 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10727 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10728 BFD_RELOC_X86_64_TLSGD
},
10729 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10730 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10731 _dummy_first_bfd_reloc_code_real
},
10732 OPERAND_TYPE_NONE
, true },
10733 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10734 BFD_RELOC_X86_64_TLSLD
},
10735 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10736 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10737 BFD_RELOC_X86_64_GOTTPOFF
},
10738 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10739 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10740 BFD_RELOC_X86_64_TPOFF32
},
10741 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10742 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10743 _dummy_first_bfd_reloc_code_real
},
10744 OPERAND_TYPE_NONE
, true },
10745 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10746 BFD_RELOC_X86_64_DTPOFF32
},
10747 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10748 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10749 _dummy_first_bfd_reloc_code_real
},
10750 OPERAND_TYPE_NONE
, true },
10751 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10752 _dummy_first_bfd_reloc_code_real
},
10753 OPERAND_TYPE_NONE
, true },
10754 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10755 BFD_RELOC_X86_64_GOT32
},
10756 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10757 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10758 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10759 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10760 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10761 BFD_RELOC_X86_64_TLSDESC_CALL
},
10762 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10764 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10765 BFD_RELOC_32_SECREL
},
10766 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10769 #undef OPERAND_TYPE_IMM32_32S_DISP32
10770 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10771 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10772 #undef OPERAND_TYPE_IMM64_DISP64
10778 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10783 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10784 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10787 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10789 int len
= gotrel
[j
].len
;
10790 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10792 if (gotrel
[j
].rel
[object_64bit
] != 0)
10795 char *tmpbuf
, *past_reloc
;
10797 *rel
= gotrel
[j
].rel
[object_64bit
];
10801 if (flag_code
!= CODE_64BIT
)
10803 types
->bitfield
.imm32
= 1;
10804 types
->bitfield
.disp32
= 1;
10807 *types
= gotrel
[j
].types64
;
10810 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10811 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10813 /* The length of the first part of our input line. */
10814 first
= cp
- input_line_pointer
;
10816 /* The second part goes from after the reloc token until
10817 (and including) an end_of_line char or comma. */
10818 past_reloc
= cp
+ 1 + len
;
10820 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10822 second
= cp
+ 1 - past_reloc
;
10824 /* Allocate and copy string. The trailing NUL shouldn't
10825 be necessary, but be safe. */
10826 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10827 memcpy (tmpbuf
, input_line_pointer
, first
);
10828 if (second
!= 0 && *past_reloc
!= ' ')
10829 /* Replace the relocation token with ' ', so that
10830 errors like foo@GOTOFF1 will be detected. */
10831 tmpbuf
[first
++] = ' ';
10833 /* Increment length by 1 if the relocation token is
10838 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10839 tmpbuf
[first
+ second
] = '\0';
10843 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10844 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10849 /* Might be a symbol version string. Don't as_bad here. */
10854 bfd_reloc_code_real_type
10855 x86_cons (expressionS
*exp
, int size
)
10857 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10859 intel_syntax
= -intel_syntax
;
10861 expr_mode
= expr_operator_none
;
10863 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10864 && !defined (LEX_AT)) \
10866 if (size
== 4 || (object_64bit
&& size
== 8))
10868 /* Handle @GOTOFF and the like in an expression. */
10870 char *gotfree_input_line
;
10873 save
= input_line_pointer
;
10874 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10875 if (gotfree_input_line
)
10876 input_line_pointer
= gotfree_input_line
;
10880 if (gotfree_input_line
)
10882 /* expression () has merrily parsed up to the end of line,
10883 or a comma - in the wrong buffer. Transfer how far
10884 input_line_pointer has moved to the right buffer. */
10885 input_line_pointer
= (save
10886 + (input_line_pointer
- gotfree_input_line
)
10888 free (gotfree_input_line
);
10889 if (exp
->X_op
== O_constant
10890 || exp
->X_op
== O_absent
10891 || exp
->X_op
== O_illegal
10892 || exp
->X_op
== O_register
10893 || exp
->X_op
== O_big
)
10895 char c
= *input_line_pointer
;
10896 *input_line_pointer
= 0;
10897 as_bad (_("missing or invalid expression `%s'"), save
);
10898 *input_line_pointer
= c
;
10900 else if ((got_reloc
== BFD_RELOC_386_PLT32
10901 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10902 && exp
->X_op
!= O_symbol
)
10904 char c
= *input_line_pointer
;
10905 *input_line_pointer
= 0;
10906 as_bad (_("invalid PLT expression `%s'"), save
);
10907 *input_line_pointer
= c
;
10915 intel_syntax
= -intel_syntax
;
10918 i386_intel_simplify (exp
);
10920 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10921 if (size
<= 4 && expr_mode
== expr_operator_present
10922 && exp
->X_op
== O_constant
&& !object_64bit
)
10923 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10929 signed_cons (int size
)
10938 s_insn (int dummy ATTRIBUTE_UNUSED
)
10940 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10941 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10945 bool vex
= false, xop
= false, evex
= false;
10946 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10950 saved_char
= *saved_ilp
;
10953 end
= parse_insn (line
, mnemonic
, true);
10957 *saved_ilp
= saved_char
;
10958 ignore_rest_of_line ();
10962 line
+= end
- line
;
10964 current_templates
= &tt
;
10965 i
.tm
.mnem_off
= MN__insn
;
10966 i
.tm
.extension_opcode
= None
;
10968 if (startswith (line
, "VEX")
10969 && (line
[3] == '.' || is_space_char (line
[3])))
10974 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10977 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10979 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10980 && (*e
== '.' || is_space_char (*e
)))
10983 /* Arrange for build_vex_prefix() to emit 0x8f. */
10984 i
.tm
.opcode_space
= SPACE_XOP08
;
10985 i
.insn_opcode_space
= n
;
10989 else if (startswith (line
, "EVEX")
10990 && (line
[4] == '.' || is_space_char (line
[4])))
10997 ? i
.vec_encoding
== vex_encoding_evex
10999 ? i
.vec_encoding
== vex_encoding_vex
11000 || i
.vec_encoding
== vex_encoding_vex3
11001 : i
.vec_encoding
!= vex_encoding_default
)
11003 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
11007 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
11008 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
11010 if (i
.vec_encoding
!= vex_encoding_default
)
11012 /* Only address size and segment override prefixes are permitted with
11013 VEX/XOP/EVEX encodings. */
11014 const unsigned char *p
= i
.prefix
;
11016 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11027 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11033 if (line
> end
&& *line
== '.')
11035 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11043 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11045 i
.tm
.opcode_modifier
.vex
= VEX128
;
11050 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11052 i
.tm
.opcode_modifier
.vex
= VEX256
;
11057 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11062 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11066 if (line
[3] == 'G')
11069 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11071 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11077 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11082 if (line
[2] == '2' && line
[3] == '8')
11085 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11087 i
.tm
.opcode_modifier
.vex
= VEX128
;
11093 if (line
[2] == '5' && line
[3] == '6')
11096 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11098 i
.tm
.opcode_modifier
.vex
= VEX256
;
11104 if (evex
&& line
[2] == '1' && line
[3] == '2')
11106 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11113 if (line
> end
&& *line
== '.')
11115 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11119 if (line
[2] == 'P')
11124 if (line
[2] == '6')
11126 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11131 case 'F': case 'f':
11132 if (line
[2] == '3')
11134 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11137 else if (line
[2] == '2')
11139 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11146 if (line
> end
&& !xop
&& *line
== '.')
11148 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11152 if (TOUPPER (line
[2]) != 'F')
11154 if (line
[3] == '.' || is_space_char (line
[3]))
11156 i
.insn_opcode_space
= SPACE_0F
;
11159 else if (line
[3] == '3'
11160 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11161 && (line
[5] == '.' || is_space_char (line
[5])))
11163 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11169 if (ISDIGIT (line
[2]) && line
[2] != '0')
11172 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11174 if (n
<= (evex
? 15 : 31)
11175 && (*e
== '.' || is_space_char (*e
)))
11177 i
.insn_opcode_space
= n
;
11185 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11187 /* VEX.W, XOP.W, EVEX.W */
11191 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11195 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11199 if (line
[3] == 'G')
11201 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11207 if (i
.tm
.opcode_modifier
.vexw
)
11211 if (line
> end
&& *line
&& !is_space_char (*line
))
11213 /* Improve diagnostic a little. */
11214 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11219 /* Before processing the opcode expression, find trailing "+r" or
11220 "/<digit>" specifiers. */
11221 for (ptr
= line
; ; ++ptr
)
11226 ptr
= strpbrk (ptr
, "+/,");
11227 if (ptr
== NULL
|| *ptr
== ',')
11230 if (*ptr
== '+' && ptr
[1] == 'r'
11231 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11235 i
.short_form
= true;
11239 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11240 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11242 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11246 i
.tm
.extension_opcode
= n
;
11247 i
.tm
.opcode_modifier
.modrm
= 1;
11252 input_line_pointer
= line
;
11253 val
= get_absolute_expression ();
11254 line
= input_line_pointer
;
11256 if (i
.short_form
&& (val
& 7))
11257 as_warn ("`+r' assumes low three opcode bits to be clear");
11259 for (j
= 1; j
< sizeof(val
); ++j
)
11260 if (!(val
>> (j
* 8)))
11263 /* Trim off a prefix if present. */
11264 if (j
> 1 && !vex
&& !xop
&& !evex
)
11266 uint8_t byte
= val
>> ((j
- 1) * 8);
11270 case DATA_PREFIX_OPCODE
:
11271 case REPE_PREFIX_OPCODE
:
11272 case REPNE_PREFIX_OPCODE
:
11273 if (!add_prefix (byte
))
11275 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11280 /* Trim off encoding space. */
11281 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11283 uint8_t byte
= val
>> ((--j
- 1) * 8);
11285 i
.insn_opcode_space
= SPACE_0F
;
11286 switch (byte
& -(j
> 1))
11289 i
.insn_opcode_space
= SPACE_0F38
;
11293 i
.insn_opcode_space
= SPACE_0F3A
;
11297 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11298 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11300 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11301 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11302 Also avoid hitting abort() there or in build_evex_prefix(). */
11303 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11308 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11311 i
.opcode_length
= j
;
11313 /* Handle operands, if any. */
11316 i386_operand_type combined
;
11317 expressionS
*disp_exp
= NULL
;
11322 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11330 as_bad (_("expecting operand after ','; got nothing"));
11334 if (i
.mem_operands
> 1)
11336 as_bad (_("too many memory references for `%s'"),
11337 &i386_mnemonics
[MN__insn
]);
11341 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11342 if (i
.vec_encoding
== vex_encoding_evex512
)
11343 i
.vec_encoding
= vex_encoding_evex
;
11345 /* Are we to emit ModR/M encoding? */
11348 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11349 || i
.tm
.extension_opcode
!= None
))
11350 i
.tm
.opcode_modifier
.modrm
= 1;
11352 if (!i
.tm
.opcode_modifier
.modrm
11354 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11355 || i
.mem_operands
))
11357 as_bad (_("too many register/memory operands"));
11361 /* Enforce certain constraints on operands. */
11362 switch (i
.reg_operands
+ i
.mem_operands
11363 + (i
.tm
.extension_opcode
!= None
))
11368 as_bad (_("too few register/memory operands"));
11371 /* Fall through. */
11373 if (i
.tm
.opcode_modifier
.modrm
)
11375 as_bad (_("too few register/memory operands"));
11385 && (i
.op
[0].imms
->X_op
!= O_constant
11386 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11388 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11391 /* Fall through. */
11393 if (i
.vec_encoding
!= vex_encoding_default
)
11395 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11398 /* Fall through. */
11400 as_bad (_("too many register/memory operands"));
11404 /* Bring operands into canonical order (imm, mem, reg). */
11409 for (j
= 1; j
< i
.operands
; ++j
)
11411 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11412 && operand_type_check (i
.types
[j
], imm
))
11413 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11414 && i
.types
[j
].bitfield
.class == ClassNone
))
11416 swap_2_operands (j
- 1, j
);
11423 /* For Intel syntax swap the order of register operands. */
11425 switch (i
.reg_operands
)
11432 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11433 /* Fall through. */
11436 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11443 /* Enforce constraints when using VSIB. */
11445 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11446 || i
.index_reg
->reg_type
.bitfield
.ymmword
11447 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11449 if (i
.vec_encoding
== vex_encoding_default
)
11451 as_bad (_("VSIB unavailable with legacy encoding"));
11455 if (i
.vec_encoding
== vex_encoding_evex
11456 && i
.reg_operands
> 1)
11458 /* We could allow two register operands, encoding the 2nd one in
11459 an 8-bit immediate like for 4-register-operand insns, but that
11460 would require ugly fiddling with process_operands() and/or
11461 build_modrm_byte(). */
11462 as_bad (_("too many register operands with VSIB"));
11466 i
.tm
.opcode_modifier
.sib
= 1;
11469 /* Establish operand size encoding. */
11470 operand_type_set (&combined
, 0);
11472 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11474 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11476 if (operand_type_check (i
.types
[j
], disp
))
11478 i
.types
[j
].bitfield
.baseindex
= 1;
11479 disp_exp
= i
.op
[j
].disps
;
11482 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11484 unsigned int n
= i
.memshift
;
11486 if (i
.types
[j
].bitfield
.byte
)
11488 else if (i
.types
[j
].bitfield
.word
)
11490 else if (i
.types
[j
].bitfield
.dword
)
11492 else if (i
.types
[j
].bitfield
.qword
)
11494 else if (i
.types
[j
].bitfield
.xmmword
)
11496 else if (i
.types
[j
].bitfield
.ymmword
)
11498 else if (i
.types
[j
].bitfield
.zmmword
)
11501 if (i
.memshift
< 32 && n
!= i
.memshift
)
11502 as_warn ("conflicting memory operand size specifiers");
11506 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11507 && j
== i
.broadcast
.operand
)
11510 combined
= operand_type_or (combined
, i
.types
[j
]);
11511 combined
.bitfield
.class = ClassNone
;
11514 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11515 << (i
.memshift
< 32 ? i
.memshift
: 0))
11517 case 64: combined
.bitfield
.zmmword
= 1; break;
11518 case 32: combined
.bitfield
.ymmword
= 1; break;
11519 case 16: combined
.bitfield
.xmmword
= 1; break;
11520 case 8: combined
.bitfield
.qword
= 1; break;
11521 case 4: combined
.bitfield
.dword
= 1; break;
11524 if (i
.vec_encoding
== vex_encoding_default
)
11526 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11528 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11529 : combined
.bitfield
.word
)
11530 && !add_prefix (DATA_PREFIX_OPCODE
))
11533 else if (!i
.tm
.opcode_modifier
.vexw
)
11535 if (flag_code
== CODE_64BIT
)
11537 if (combined
.bitfield
.qword
)
11538 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11539 else if (combined
.bitfield
.dword
)
11540 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11543 if (!i
.tm
.opcode_modifier
.vexw
)
11544 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11549 if (!i
.tm
.opcode_modifier
.vex
)
11551 if (combined
.bitfield
.ymmword
)
11552 i
.tm
.opcode_modifier
.vex
= VEX256
;
11553 else if (combined
.bitfield
.xmmword
)
11554 i
.tm
.opcode_modifier
.vex
= VEX128
;
11559 if (!i
.tm
.opcode_modifier
.evex
)
11561 /* Do _not_ consider AVX512VL here. */
11562 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11563 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11564 else if (combined
.bitfield
.ymmword
)
11565 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11566 else if (combined
.bitfield
.xmmword
)
11567 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11570 if (i
.memshift
>= 32)
11572 unsigned int n
= 0;
11574 switch (i
.tm
.opcode_modifier
.evex
)
11576 case EVEX512
: n
= 64; break;
11577 case EVEX256
: n
= 32; break;
11578 case EVEX128
: n
= 16; break;
11581 if (i
.broadcast
.type
)
11582 n
/= i
.broadcast
.type
;
11585 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11587 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11588 && disp_exp
->X_add_number
!= 0
11589 && i
.disp_encoding
!= disp_encoding_32bit
)
11591 if (!quiet_warnings
)
11592 as_warn ("cannot determine memory operand size");
11593 i
.disp_encoding
= disp_encoding_32bit
;
11598 if (i
.memshift
>= 32)
11601 i
.vec_encoding
= vex_encoding_error
;
11603 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11606 /* Establish size for immediate operands. */
11607 for (j
= 0; j
< i
.imm_operands
; ++j
)
11609 expressionS
*expP
= i
.op
[j
].imms
;
11611 gas_assert (operand_type_check (i
.types
[j
], imm
));
11612 operand_type_set (&i
.types
[j
], 0);
11614 if (i
.imm_bits
[j
] > 32)
11615 i
.types
[j
].bitfield
.imm64
= 1;
11616 else if (i
.imm_bits
[j
] > 16)
11618 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11619 i
.types
[j
].bitfield
.imm32s
= 1;
11621 i
.types
[j
].bitfield
.imm32
= 1;
11623 else if (i
.imm_bits
[j
] > 8)
11624 i
.types
[j
].bitfield
.imm16
= 1;
11625 else if (i
.imm_bits
[j
] > 0)
11627 if (i
.flags
[j
] & Operand_Signed
)
11628 i
.types
[j
].bitfield
.imm8s
= 1;
11630 i
.types
[j
].bitfield
.imm8
= 1;
11632 else if (expP
->X_op
== O_constant
)
11634 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11635 i
.types
[j
].bitfield
.imm1
= 0;
11636 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11637 zapping since smallest_imm_type() sets it unconditionally. */
11638 if (flag_code
!= CODE_64BIT
)
11640 i
.types
[j
].bitfield
.imm64
= 0;
11641 i
.types
[j
].bitfield
.imm32s
= 0;
11642 i
.types
[j
].bitfield
.imm32
= 1;
11644 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11645 i
.types
[j
].bitfield
.imm64
= 0;
11648 /* Non-constant expressions are sized heuristically. */
11651 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11652 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11653 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11657 for (j
= 0; j
< i
.operands
; ++j
)
11658 i
.tm
.operand_types
[j
] = i
.types
[j
];
11660 process_operands ();
11663 /* Don't set opcode until after processing operands, to avoid any
11664 potential special casing there. */
11665 i
.tm
.base_opcode
|= val
;
11667 if (i
.vec_encoding
== vex_encoding_error
11668 || (i
.vec_encoding
!= vex_encoding_evex
11669 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11670 || i
.rounding
.type
!= rc_none
11672 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11673 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11674 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11676 as_bad (_("conflicting .insn operands"));
11682 if (!i
.tm
.opcode_modifier
.vex
)
11683 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11685 build_vex_prefix (NULL
);
11686 i
.rex
&= REX_OPCODE
;
11690 if (!i
.tm
.opcode_modifier
.evex
)
11691 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11693 build_evex_prefix ();
11694 i
.rex
&= REX_OPCODE
;
11696 else if (i
.rex
!= 0)
11697 add_prefix (REX_OPCODE
| i
.rex
);
11702 *saved_ilp
= saved_char
;
11703 input_line_pointer
= line
;
11705 demand_empty_rest_of_line ();
11707 /* Make sure dot_insn() won't yield "true" anymore. */
11713 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11720 if (exp
.X_op
== O_symbol
)
11721 exp
.X_op
= O_secrel
;
11723 emit_expr (&exp
, 4);
11725 while (*input_line_pointer
++ == ',');
11727 input_line_pointer
--;
11728 demand_empty_rest_of_line ();
11732 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11739 if (exp
.X_op
== O_symbol
)
11740 exp
.X_op
= O_secidx
;
11742 emit_expr (&exp
, 2);
11744 while (*input_line_pointer
++ == ',');
11746 input_line_pointer
--;
11747 demand_empty_rest_of_line ();
11751 /* Handle Rounding Control / SAE specifiers. */
11754 RC_SAE_specifier (const char *pstr
)
11758 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11760 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11762 if (i
.rounding
.type
!= rc_none
)
11764 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11768 if (i
.vec_encoding
== vex_encoding_default
)
11769 i
.vec_encoding
= vex_encoding_evex512
;
11770 else if (i
.vec_encoding
!= vex_encoding_evex
11771 && i
.vec_encoding
!= vex_encoding_evex512
)
11774 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11776 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11783 /* Handle Vector operations. */
11786 check_VecOperations (char *op_string
)
11788 const reg_entry
*mask
;
11795 if (*op_string
== '{')
11799 /* Check broadcasts. */
11800 if (startswith (op_string
, "1to"))
11802 unsigned int bcst_type
;
11804 if (i
.broadcast
.type
)
11805 goto duplicated_vec_op
;
11808 if (*op_string
== '8')
11810 else if (*op_string
== '4')
11812 else if (*op_string
== '2')
11814 else if (*op_string
== '1'
11815 && *(op_string
+1) == '6')
11820 else if (*op_string
== '3'
11821 && *(op_string
+1) == '2')
11828 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11833 if (i
.vec_encoding
== vex_encoding_default
)
11834 i
.vec_encoding
= vex_encoding_evex
;
11835 else if (i
.vec_encoding
!= vex_encoding_evex
11836 && i
.vec_encoding
!= vex_encoding_evex512
)
11837 goto unknown_vec_op
;
11839 i
.broadcast
.type
= bcst_type
;
11840 i
.broadcast
.operand
= this_operand
;
11842 /* For .insn a data size specifier may be appended. */
11843 if (dot_insn () && *op_string
== ':')
11844 goto dot_insn_modifier
;
11846 /* Check .insn special cases. */
11847 else if (dot_insn () && *op_string
== ':')
11850 switch (op_string
[1])
11855 if (i
.memshift
< 32)
11856 goto duplicated_vec_op
;
11858 n
= strtoul (op_string
+ 2, &end_op
, 0);
11860 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11862 if (i
.memshift
< 32 && n
== 1)
11863 op_string
= end_op
;
11866 case 's': case 'u':
11867 /* This isn't really a "vector" operation, but a sign/size
11868 specifier for immediate operands of .insn. Note that AT&T
11869 syntax handles the same in i386_immediate(). */
11873 if (i
.imm_bits
[this_operand
])
11874 goto duplicated_vec_op
;
11876 n
= strtoul (op_string
+ 2, &end_op
, 0);
11877 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11879 i
.imm_bits
[this_operand
] = n
;
11880 if (op_string
[1] == 's')
11881 i
.flags
[this_operand
] |= Operand_Signed
;
11882 op_string
= end_op
;
11887 /* Check masking operation. */
11888 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11890 if (mask
== &bad_reg
)
11893 /* k0 can't be used for write mask. */
11894 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11896 as_bad (_("`%s%s' can't be used for write mask"),
11897 register_prefix
, mask
->reg_name
);
11904 i
.mask
.operand
= this_operand
;
11906 else if (i
.mask
.reg
->reg_num
)
11907 goto duplicated_vec_op
;
11912 /* Only "{z}" is allowed here. No need to check
11913 zeroing mask explicitly. */
11914 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11916 as_bad (_("invalid write mask `%s'"), saved
);
11921 op_string
= end_op
;
11923 /* Check zeroing-flag for masking operation. */
11924 else if (*op_string
== 'z')
11928 i
.mask
.reg
= reg_k0
;
11929 i
.mask
.zeroing
= 1;
11930 i
.mask
.operand
= this_operand
;
11934 if (i
.mask
.zeroing
)
11937 as_bad (_("duplicated `%s'"), saved
);
11941 i
.mask
.zeroing
= 1;
11943 /* Only "{%k}" is allowed here. No need to check mask
11944 register explicitly. */
11945 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11947 as_bad (_("invalid zeroing-masking `%s'"),
11955 else if (intel_syntax
11956 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11957 i
.rounding
.modifier
= true;
11959 goto unknown_vec_op
;
11961 if (*op_string
!= '}')
11963 as_bad (_("missing `}' in `%s'"), saved
);
11968 /* Strip whitespace since the addition of pseudo prefixes
11969 changed how the scrubber treats '{'. */
11970 if (is_space_char (*op_string
))
11976 /* We don't know this one. */
11977 as_bad (_("unknown vector operation: `%s'"), saved
);
11981 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11983 as_bad (_("zeroing-masking only allowed with write mask"));
11991 i386_immediate (char *imm_start
)
11993 char *save_input_line_pointer
;
11994 char *gotfree_input_line
;
11997 i386_operand_type types
;
11999 operand_type_set (&types
, ~0);
12001 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
12003 as_bad (_("at most %d immediate operands are allowed"),
12004 MAX_IMMEDIATE_OPERANDS
);
12008 exp
= &im_expressions
[i
.imm_operands
++];
12009 i
.op
[this_operand
].imms
= exp
;
12011 if (is_space_char (*imm_start
))
12014 save_input_line_pointer
= input_line_pointer
;
12015 input_line_pointer
= imm_start
;
12017 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12018 if (gotfree_input_line
)
12019 input_line_pointer
= gotfree_input_line
;
12021 expr_mode
= expr_operator_none
;
12022 exp_seg
= expression (exp
);
12024 /* For .insn immediates there may be a size specifier. */
12025 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12026 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12029 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12031 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12033 i
.imm_bits
[this_operand
] = n
;
12034 if (input_line_pointer
[2] == 's')
12035 i
.flags
[this_operand
] |= Operand_Signed
;
12036 input_line_pointer
= e
+ 1;
12040 SKIP_WHITESPACE ();
12041 if (*input_line_pointer
)
12042 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12044 input_line_pointer
= save_input_line_pointer
;
12045 if (gotfree_input_line
)
12047 free (gotfree_input_line
);
12049 if (exp
->X_op
== O_constant
)
12050 exp
->X_op
= O_illegal
;
12053 if (exp_seg
== reg_section
)
12055 as_bad (_("illegal immediate register operand %s"), imm_start
);
12059 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12063 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12064 i386_operand_type types
, const char *imm_start
)
12066 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12069 as_bad (_("missing or invalid immediate expression `%s'"),
12073 else if (exp
->X_op
== O_constant
)
12075 /* Size it properly later. */
12076 i
.types
[this_operand
].bitfield
.imm64
= 1;
12078 /* If not 64bit, sign/zero extend val, to account for wraparound
12080 if (expr_mode
== expr_operator_present
12081 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12082 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12084 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12085 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12086 && exp_seg
!= absolute_section
12087 && exp_seg
!= text_section
12088 && exp_seg
!= data_section
12089 && exp_seg
!= bss_section
12090 && exp_seg
!= undefined_section
12091 && !bfd_is_com_section (exp_seg
))
12093 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12099 /* This is an address. The size of the address will be
12100 determined later, depending on destination register,
12101 suffix, or the default for the section. */
12102 i
.types
[this_operand
].bitfield
.imm8
= 1;
12103 i
.types
[this_operand
].bitfield
.imm16
= 1;
12104 i
.types
[this_operand
].bitfield
.imm32
= 1;
12105 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12106 i
.types
[this_operand
].bitfield
.imm64
= 1;
12107 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12115 i386_scale (char *scale
)
12118 char *save
= input_line_pointer
;
12120 input_line_pointer
= scale
;
12121 val
= get_absolute_expression ();
12126 i
.log2_scale_factor
= 0;
12129 i
.log2_scale_factor
= 1;
12132 i
.log2_scale_factor
= 2;
12135 i
.log2_scale_factor
= 3;
12139 char sep
= *input_line_pointer
;
12141 *input_line_pointer
= '\0';
12142 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12144 *input_line_pointer
= sep
;
12145 input_line_pointer
= save
;
12149 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12151 as_warn (_("scale factor of %d without an index register"),
12152 1 << i
.log2_scale_factor
);
12153 i
.log2_scale_factor
= 0;
12155 scale
= input_line_pointer
;
12156 input_line_pointer
= save
;
12161 i386_displacement (char *disp_start
, char *disp_end
)
12165 char *save_input_line_pointer
;
12166 char *gotfree_input_line
;
12168 i386_operand_type bigdisp
, types
= anydisp
;
12171 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12173 as_bad (_("at most %d displacement operands are allowed"),
12174 MAX_MEMORY_OPERANDS
);
12178 operand_type_set (&bigdisp
, 0);
12180 || i
.types
[this_operand
].bitfield
.baseindex
12181 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12182 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12184 i386_addressing_mode ();
12185 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12186 if (flag_code
== CODE_64BIT
)
12188 bigdisp
.bitfield
.disp32
= 1;
12190 bigdisp
.bitfield
.disp64
= 1;
12192 else if ((flag_code
== CODE_16BIT
) ^ override
)
12193 bigdisp
.bitfield
.disp16
= 1;
12195 bigdisp
.bitfield
.disp32
= 1;
12199 /* For PC-relative branches, the width of the displacement may be
12200 dependent upon data size, but is never dependent upon address size.
12201 Also make sure to not unintentionally match against a non-PC-relative
12202 branch template. */
12203 static templates aux_templates
;
12204 const insn_template
*t
= current_templates
->start
;
12205 bool has_intel64
= false;
12207 aux_templates
.start
= t
;
12208 while (++t
< current_templates
->end
)
12210 if (t
->opcode_modifier
.jump
12211 != current_templates
->start
->opcode_modifier
.jump
)
12213 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12214 has_intel64
= true;
12216 if (t
< current_templates
->end
)
12218 aux_templates
.end
= t
;
12219 current_templates
= &aux_templates
;
12222 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12223 if (flag_code
== CODE_64BIT
)
12225 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12226 && (!intel64
|| !has_intel64
))
12227 bigdisp
.bitfield
.disp16
= 1;
12229 bigdisp
.bitfield
.disp32
= 1;
12234 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12236 : LONG_MNEM_SUFFIX
));
12237 bigdisp
.bitfield
.disp32
= 1;
12238 if ((flag_code
== CODE_16BIT
) ^ override
)
12240 bigdisp
.bitfield
.disp32
= 0;
12241 bigdisp
.bitfield
.disp16
= 1;
12245 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12248 exp
= &disp_expressions
[i
.disp_operands
];
12249 i
.op
[this_operand
].disps
= exp
;
12251 save_input_line_pointer
= input_line_pointer
;
12252 input_line_pointer
= disp_start
;
12253 END_STRING_AND_SAVE (disp_end
);
12255 #ifndef GCC_ASM_O_HACK
12256 #define GCC_ASM_O_HACK 0
12259 END_STRING_AND_SAVE (disp_end
+ 1);
12260 if (i
.types
[this_operand
].bitfield
.baseIndex
12261 && displacement_string_end
[-1] == '+')
12263 /* This hack is to avoid a warning when using the "o"
12264 constraint within gcc asm statements.
12267 #define _set_tssldt_desc(n,addr,limit,type) \
12268 __asm__ __volatile__ ( \
12269 "movw %w2,%0\n\t" \
12270 "movw %w1,2+%0\n\t" \
12271 "rorl $16,%1\n\t" \
12272 "movb %b1,4+%0\n\t" \
12273 "movb %4,5+%0\n\t" \
12274 "movb $0,6+%0\n\t" \
12275 "movb %h1,7+%0\n\t" \
12277 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12279 This works great except that the output assembler ends
12280 up looking a bit weird if it turns out that there is
12281 no offset. You end up producing code that looks like:
12294 So here we provide the missing zero. */
12296 *displacement_string_end
= '0';
12299 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12300 if (gotfree_input_line
)
12301 input_line_pointer
= gotfree_input_line
;
12303 expr_mode
= expr_operator_none
;
12304 exp_seg
= expression (exp
);
12306 SKIP_WHITESPACE ();
12307 if (*input_line_pointer
)
12308 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12310 RESTORE_END_STRING (disp_end
+ 1);
12312 input_line_pointer
= save_input_line_pointer
;
12313 if (gotfree_input_line
)
12315 free (gotfree_input_line
);
12317 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12318 exp
->X_op
= O_illegal
;
12321 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12323 RESTORE_END_STRING (disp_end
);
12329 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12330 i386_operand_type types
, const char *disp_start
)
12334 /* We do this to make sure that the section symbol is in
12335 the symbol table. We will ultimately change the relocation
12336 to be relative to the beginning of the section. */
12337 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12338 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12339 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12341 if (exp
->X_op
!= O_symbol
)
12344 if (S_IS_LOCAL (exp
->X_add_symbol
)
12345 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12346 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12347 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12348 exp
->X_op
= O_subtract
;
12349 exp
->X_op_symbol
= GOT_symbol
;
12350 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12351 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12352 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12353 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12355 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12358 else if (exp
->X_op
== O_absent
12359 || exp
->X_op
== O_illegal
12360 || exp
->X_op
== O_big
)
12363 as_bad (_("missing or invalid displacement expression `%s'"),
12368 else if (exp
->X_op
== O_constant
)
12370 /* Sizing gets taken care of by optimize_disp().
12372 If not 64bit, sign/zero extend val, to account for wraparound
12374 if (expr_mode
== expr_operator_present
12375 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12376 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12379 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12380 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12381 && exp_seg
!= absolute_section
12382 && exp_seg
!= text_section
12383 && exp_seg
!= data_section
12384 && exp_seg
!= bss_section
12385 && exp_seg
!= undefined_section
12386 && !bfd_is_com_section (exp_seg
))
12388 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12393 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12394 i
.types
[this_operand
].bitfield
.disp8
= 1;
12396 /* Check if this is a displacement only operand. */
12397 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12398 i
.types
[this_operand
] =
12399 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12400 operand_type_and (i
.types
[this_operand
], types
));
12405 /* Return the active addressing mode, taking address override and
12406 registers forming the address into consideration. Update the
12407 address override prefix if necessary. */
12409 static enum flag_code
12410 i386_addressing_mode (void)
12412 enum flag_code addr_mode
;
12414 if (i
.prefix
[ADDR_PREFIX
])
12415 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12416 else if (flag_code
== CODE_16BIT
12417 && is_cpu (current_templates
->start
, CpuMPX
)
12418 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12419 from md_assemble() by "is not a valid base/index expression"
12420 when there is a base and/or index. */
12421 && !i
.types
[this_operand
].bitfield
.baseindex
)
12423 /* MPX insn memory operands with neither base nor index must be forced
12424 to use 32-bit addressing in 16-bit mode. */
12425 addr_mode
= CODE_32BIT
;
12426 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12428 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12429 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12433 addr_mode
= flag_code
;
12435 #if INFER_ADDR_PREFIX
12436 if (i
.mem_operands
== 0)
12438 /* Infer address prefix from the first memory operand. */
12439 const reg_entry
*addr_reg
= i
.base_reg
;
12441 if (addr_reg
== NULL
)
12442 addr_reg
= i
.index_reg
;
12446 if (addr_reg
->reg_type
.bitfield
.dword
)
12447 addr_mode
= CODE_32BIT
;
12448 else if (flag_code
!= CODE_64BIT
12449 && addr_reg
->reg_type
.bitfield
.word
)
12450 addr_mode
= CODE_16BIT
;
12452 if (addr_mode
!= flag_code
)
12454 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12456 /* Change the size of any displacement too. At most one
12457 of Disp16 or Disp32 is set.
12458 FIXME. There doesn't seem to be any real need for
12459 separate Disp16 and Disp32 flags. The same goes for
12460 Imm16 and Imm32. Removing them would probably clean
12461 up the code quite a lot. */
12462 if (flag_code
!= CODE_64BIT
12463 && (i
.types
[this_operand
].bitfield
.disp16
12464 || i
.types
[this_operand
].bitfield
.disp32
))
12466 static const i386_operand_type disp16_32
= {
12467 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12470 i
.types
[this_operand
]
12471 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12482 /* Make sure the memory operand we've been dealt is valid.
12483 Return 1 on success, 0 on a failure. */
12486 i386_index_check (const char *operand_string
)
12488 const char *kind
= "base/index";
12489 enum flag_code addr_mode
= i386_addressing_mode ();
12490 const insn_template
*t
= current_templates
->end
- 1;
12492 if (t
->opcode_modifier
.isstring
)
12494 /* Memory operands of string insns are special in that they only allow
12495 a single register (rDI, rSI, or rBX) as their memory address. */
12496 const reg_entry
*expected_reg
;
12497 static const char di_si
[][2][4] =
12503 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12505 kind
= "string address";
12507 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12509 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12512 if (!t
->operand_types
[0].bitfield
.baseindex
12513 || ((!i
.mem_operands
!= !intel_syntax
)
12514 && t
->operand_types
[1].bitfield
.baseindex
))
12517 = (const reg_entry
*) str_hash_find (reg_hash
,
12518 di_si
[addr_mode
][op
== es_op
]);
12522 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12524 if (i
.base_reg
!= expected_reg
12526 || operand_type_check (i
.types
[this_operand
], disp
))
12528 /* The second memory operand must have the same size as
12532 && !((addr_mode
== CODE_64BIT
12533 && i
.base_reg
->reg_type
.bitfield
.qword
)
12534 || (addr_mode
== CODE_32BIT
12535 ? i
.base_reg
->reg_type
.bitfield
.dword
12536 : i
.base_reg
->reg_type
.bitfield
.word
)))
12539 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12541 intel_syntax
? '[' : '(',
12543 expected_reg
->reg_name
,
12544 intel_syntax
? ']' : ')');
12551 as_bad (_("`%s' is not a valid %s expression"),
12552 operand_string
, kind
);
12557 t
= current_templates
->start
;
12559 if (addr_mode
!= CODE_16BIT
)
12561 /* 32-bit/64-bit checks. */
12562 if (i
.disp_encoding
== disp_encoding_16bit
)
12565 as_bad (_("invalid `%s' prefix"),
12566 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12571 && ((addr_mode
== CODE_64BIT
12572 ? !i
.base_reg
->reg_type
.bitfield
.qword
12573 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12574 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12575 || i
.base_reg
->reg_num
== RegIZ
))
12577 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12578 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12579 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12580 && ((addr_mode
== CODE_64BIT
12581 ? !i
.index_reg
->reg_type
.bitfield
.qword
12582 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12583 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12586 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12587 if (t
->mnem_off
== MN_bndmk
12588 || t
->mnem_off
== MN_bndldx
12589 || t
->mnem_off
== MN_bndstx
12590 || t
->opcode_modifier
.sib
== SIBMEM
)
12592 /* They cannot use RIP-relative addressing. */
12593 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12595 as_bad (_("`%s' cannot be used here"), operand_string
);
12599 /* bndldx and bndstx ignore their scale factor. */
12600 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12601 && i
.log2_scale_factor
)
12602 as_warn (_("register scaling is being ignored here"));
12607 /* 16-bit checks. */
12608 if (i
.disp_encoding
== disp_encoding_32bit
)
12612 && (!i
.base_reg
->reg_type
.bitfield
.word
12613 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12615 && (!i
.index_reg
->reg_type
.bitfield
.word
12616 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12618 && i
.base_reg
->reg_num
< 6
12619 && i
.index_reg
->reg_num
>= 6
12620 && i
.log2_scale_factor
== 0))))
12627 /* Handle vector immediates. */
12630 RC_SAE_immediate (const char *imm_start
)
12632 const char *pstr
= imm_start
;
12637 pstr
= RC_SAE_specifier (pstr
+ 1);
12641 if (*pstr
++ != '}')
12643 as_bad (_("Missing '}': '%s'"), imm_start
);
12646 /* RC/SAE immediate string should contain nothing more. */;
12649 as_bad (_("Junk after '}': '%s'"), imm_start
);
12653 /* Internally this doesn't count as an operand. */
12659 static INLINE
bool starts_memory_operand (char c
)
12662 || is_name_beginner (c
)
12663 || strchr ("([\"+-!~", c
);
12666 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12670 i386_att_operand (char *operand_string
)
12672 const reg_entry
*r
;
12674 char *op_string
= operand_string
;
12676 if (is_space_char (*op_string
))
12679 /* We check for an absolute prefix (differentiating,
12680 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12681 if (*op_string
== ABSOLUTE_PREFIX
12682 && current_templates
->start
->opcode_modifier
.jump
)
12685 if (is_space_char (*op_string
))
12687 i
.jumpabsolute
= true;
12690 /* Check if operand is a register. */
12691 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12693 i386_operand_type temp
;
12698 /* Check for a segment override by searching for ':' after a
12699 segment register. */
12700 op_string
= end_op
;
12701 if (is_space_char (*op_string
))
12703 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12705 i
.seg
[i
.mem_operands
] = r
;
12707 /* Skip the ':' and whitespace. */
12709 if (is_space_char (*op_string
))
12712 /* Handle case of %es:*foo. */
12713 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12714 && current_templates
->start
->opcode_modifier
.jump
)
12717 if (is_space_char (*op_string
))
12719 i
.jumpabsolute
= true;
12722 if (!starts_memory_operand (*op_string
))
12724 as_bad (_("bad memory operand `%s'"), op_string
);
12727 goto do_memory_reference
;
12730 /* Handle vector operations. */
12731 if (*op_string
== '{')
12733 op_string
= check_VecOperations (op_string
);
12734 if (op_string
== NULL
)
12740 as_bad (_("junk `%s' after register"), op_string
);
12744 /* Reject pseudo registers for .insn. */
12745 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12747 as_bad (_("`%s%s' cannot be used here"),
12748 register_prefix
, r
->reg_name
);
12752 temp
= r
->reg_type
;
12753 temp
.bitfield
.baseindex
= 0;
12754 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12756 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12757 i
.op
[this_operand
].regs
= r
;
12760 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12761 operand was also present earlier on. */
12762 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12763 && i
.reg_operands
== 1)
12767 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12768 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12770 as_bad (_("`%s': misplaced `{%s}'"),
12771 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12775 else if (*op_string
== REGISTER_PREFIX
)
12777 as_bad (_("bad register name `%s'"), op_string
);
12780 else if (*op_string
== IMMEDIATE_PREFIX
)
12783 if (i
.jumpabsolute
)
12785 as_bad (_("immediate operand illegal with absolute jump"));
12788 if (!i386_immediate (op_string
))
12790 if (i
.rounding
.type
!= rc_none
)
12792 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12793 insn_name (current_templates
->start
));
12797 else if (RC_SAE_immediate (operand_string
))
12799 /* If it is a RC or SAE immediate, do the necessary placement check:
12800 Only another immediate or a GPR may precede it. */
12801 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12802 || (i
.reg_operands
== 1
12803 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12805 as_bad (_("`%s': misplaced `%s'"),
12806 insn_name (current_templates
->start
), operand_string
);
12810 else if (starts_memory_operand (*op_string
))
12812 /* This is a memory reference of some sort. */
12815 /* Start and end of displacement string expression (if found). */
12816 char *displacement_string_start
;
12817 char *displacement_string_end
;
12819 do_memory_reference
:
12820 /* Check for base index form. We detect the base index form by
12821 looking for an ')' at the end of the operand, searching
12822 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12824 base_string
= op_string
+ strlen (op_string
);
12826 /* Handle vector operations. */
12828 if (is_space_char (*base_string
))
12831 if (*base_string
== '}')
12833 char *vop_start
= NULL
;
12835 while (base_string
-- > op_string
)
12837 if (*base_string
== '"')
12839 if (*base_string
!= '{')
12842 vop_start
= base_string
;
12845 if (is_space_char (*base_string
))
12848 if (*base_string
!= '}')
12856 as_bad (_("unbalanced figure braces"));
12860 if (check_VecOperations (vop_start
) == NULL
)
12864 /* If we only have a displacement, set-up for it to be parsed later. */
12865 displacement_string_start
= op_string
;
12866 displacement_string_end
= base_string
+ 1;
12868 if (*base_string
== ')')
12871 unsigned int parens_not_balanced
= 0;
12872 bool in_quotes
= false;
12874 /* We've already checked that the number of left & right ()'s are
12875 equal, and that there's a matching set of double quotes. */
12876 end_op
= base_string
;
12877 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12879 if (*temp_string
== '\\' && temp_string
[1] == '"')
12881 else if (*temp_string
== '"')
12882 in_quotes
= !in_quotes
;
12883 else if (!in_quotes
)
12885 if (*temp_string
== '(' && !parens_not_balanced
++)
12886 base_string
= temp_string
;
12887 if (*temp_string
== ')')
12888 --parens_not_balanced
;
12892 temp_string
= base_string
;
12894 /* Skip past '(' and whitespace. */
12895 gas_assert (*base_string
== '(');
12897 if (is_space_char (*base_string
))
12900 if (*base_string
== ','
12901 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12904 displacement_string_end
= temp_string
;
12906 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12910 if (i
.base_reg
== &bad_reg
)
12912 base_string
= end_op
;
12913 if (is_space_char (*base_string
))
12917 /* There may be an index reg or scale factor here. */
12918 if (*base_string
== ',')
12921 if (is_space_char (*base_string
))
12924 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12927 if (i
.index_reg
== &bad_reg
)
12929 base_string
= end_op
;
12930 if (is_space_char (*base_string
))
12932 if (*base_string
== ',')
12935 if (is_space_char (*base_string
))
12938 else if (*base_string
!= ')')
12940 as_bad (_("expecting `,' or `)' "
12941 "after index register in `%s'"),
12946 else if (*base_string
== REGISTER_PREFIX
)
12948 end_op
= strchr (base_string
, ',');
12951 as_bad (_("bad register name `%s'"), base_string
);
12955 /* Check for scale factor. */
12956 if (*base_string
!= ')')
12958 char *end_scale
= i386_scale (base_string
);
12963 base_string
= end_scale
;
12964 if (is_space_char (*base_string
))
12966 if (*base_string
!= ')')
12968 as_bad (_("expecting `)' "
12969 "after scale factor in `%s'"),
12974 else if (!i
.index_reg
)
12976 as_bad (_("expecting index register or scale factor "
12977 "after `,'; got '%c'"),
12982 else if (*base_string
!= ')')
12984 as_bad (_("expecting `,' or `)' "
12985 "after base register in `%s'"),
12990 else if (*base_string
== REGISTER_PREFIX
)
12992 end_op
= strchr (base_string
, ',');
12995 as_bad (_("bad register name `%s'"), base_string
);
13000 /* If there's an expression beginning the operand, parse it,
13001 assuming displacement_string_start and
13002 displacement_string_end are meaningful. */
13003 if (displacement_string_start
!= displacement_string_end
)
13005 if (!i386_displacement (displacement_string_start
,
13006 displacement_string_end
))
13010 /* Special case for (%dx) while doing input/output op. */
13012 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
13013 && i
.base_reg
->reg_type
.bitfield
.word
13014 && i
.index_reg
== 0
13015 && i
.log2_scale_factor
== 0
13016 && i
.seg
[i
.mem_operands
] == 0
13017 && !operand_type_check (i
.types
[this_operand
], disp
))
13019 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
13020 i
.input_output_operand
= true;
13024 if (i386_index_check (operand_string
) == 0)
13026 i
.flags
[this_operand
] |= Operand_Mem
;
13031 /* It's not a memory operand; argh! */
13032 as_bad (_("invalid char %s beginning operand %d `%s'"),
13033 output_invalid (*op_string
),
13038 return 1; /* Normal return. */
13041 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13042 that an rs_machine_dependent frag may reach. */
13045 i386_frag_max_var (fragS
*frag
)
13047 /* The only relaxable frags are for jumps.
13048 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13049 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13050 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13055 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13057 /* STT_GNU_IFUNC symbol must go through PLT. */
13058 if ((symbol_get_bfdsym (fr_symbol
)->flags
13059 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13062 if (!S_IS_EXTERNAL (fr_symbol
))
13063 /* Symbol may be weak or local. */
13064 return !S_IS_WEAK (fr_symbol
);
13066 /* Global symbols with non-default visibility can't be preempted. */
13067 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13070 if (fr_var
!= NO_RELOC
)
13071 switch ((enum bfd_reloc_code_real
) fr_var
)
13073 case BFD_RELOC_386_PLT32
:
13074 case BFD_RELOC_X86_64_PLT32
:
13075 /* Symbol with PLT relocation may be preempted. */
13081 /* Global symbols with default visibility in a shared library may be
13082 preempted by another definition. */
13087 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13088 Note also work for Skylake and Cascadelake.
13089 ---------------------------------------------------------------------
13090 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13091 | ------ | ----------- | ------- | -------- |
13093 | Jno | N | N | Y |
13094 | Jc/Jb | Y | N | Y |
13095 | Jae/Jnb | Y | N | Y |
13096 | Je/Jz | Y | Y | Y |
13097 | Jne/Jnz | Y | Y | Y |
13098 | Jna/Jbe | Y | N | Y |
13099 | Ja/Jnbe | Y | N | Y |
13101 | Jns | N | N | Y |
13102 | Jp/Jpe | N | N | Y |
13103 | Jnp/Jpo | N | N | Y |
13104 | Jl/Jnge | Y | Y | Y |
13105 | Jge/Jnl | Y | Y | Y |
13106 | Jle/Jng | Y | Y | Y |
13107 | Jg/Jnle | Y | Y | Y |
13108 --------------------------------------------------------------------- */
13110 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13112 if (mf_cmp
== mf_cmp_alu_cmp
)
13113 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13114 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13115 if (mf_cmp
== mf_cmp_incdec
)
13116 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13117 || mf_jcc
== mf_jcc_jle
);
13118 if (mf_cmp
== mf_cmp_test_and
)
13123 /* Return the next non-empty frag. */
13126 i386_next_non_empty_frag (fragS
*fragP
)
13128 /* There may be a frag with a ".fill 0" when there is no room in
13129 the current frag for frag_grow in output_insn. */
13130 for (fragP
= fragP
->fr_next
;
13132 && fragP
->fr_type
== rs_fill
13133 && fragP
->fr_fix
== 0);
13134 fragP
= fragP
->fr_next
)
13139 /* Return the next jcc frag after BRANCH_PADDING. */
13142 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13144 fragS
*branch_fragP
;
13148 if (pad_fragP
->fr_type
== rs_machine_dependent
13149 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13150 == BRANCH_PADDING
))
13152 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13153 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13155 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13156 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13157 pad_fragP
->tc_frag_data
.mf_type
))
13158 return branch_fragP
;
13164 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13167 i386_classify_machine_dependent_frag (fragS
*fragP
)
13171 fragS
*branch_fragP
;
13173 unsigned int max_prefix_length
;
13175 if (fragP
->tc_frag_data
.classified
)
13178 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13179 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13180 for (next_fragP
= fragP
;
13181 next_fragP
!= NULL
;
13182 next_fragP
= next_fragP
->fr_next
)
13184 next_fragP
->tc_frag_data
.classified
= 1;
13185 if (next_fragP
->fr_type
== rs_machine_dependent
)
13186 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13188 case BRANCH_PADDING
:
13189 /* The BRANCH_PADDING frag must be followed by a branch
13191 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13192 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13194 case FUSED_JCC_PADDING
:
13195 /* Check if this is a fused jcc:
13197 CMP like instruction
13201 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13202 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13203 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13206 /* The BRANCH_PADDING frag is merged with the
13207 FUSED_JCC_PADDING frag. */
13208 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13209 /* CMP like instruction size. */
13210 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13211 frag_wane (pad_fragP
);
13212 /* Skip to branch_fragP. */
13213 next_fragP
= branch_fragP
;
13215 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13217 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13219 next_fragP
->fr_subtype
13220 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13221 next_fragP
->tc_frag_data
.max_bytes
13222 = next_fragP
->tc_frag_data
.max_prefix_length
;
13223 /* This will be updated in the BRANCH_PREFIX scan. */
13224 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13227 frag_wane (next_fragP
);
13232 /* Stop if there is no BRANCH_PREFIX. */
13233 if (!align_branch_prefix_size
)
13236 /* Scan for BRANCH_PREFIX. */
13237 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13239 if (fragP
->fr_type
!= rs_machine_dependent
13240 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13244 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13245 COND_JUMP_PREFIX. */
13246 max_prefix_length
= 0;
13247 for (next_fragP
= fragP
;
13248 next_fragP
!= NULL
;
13249 next_fragP
= next_fragP
->fr_next
)
13251 if (next_fragP
->fr_type
== rs_fill
)
13252 /* Skip rs_fill frags. */
13254 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13255 /* Stop for all other frags. */
13258 /* rs_machine_dependent frags. */
13259 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13262 /* Count BRANCH_PREFIX frags. */
13263 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13265 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13266 frag_wane (next_fragP
);
13270 += next_fragP
->tc_frag_data
.max_bytes
;
13272 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13274 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13275 == FUSED_JCC_PADDING
))
13277 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13278 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13282 /* Stop for other rs_machine_dependent frags. */
13286 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13288 /* Skip to the next frag. */
13289 fragP
= next_fragP
;
13293 /* Compute padding size for
13296 CMP like instruction
13298 COND_JUMP/UNCOND_JUMP
13303 COND_JUMP/UNCOND_JUMP
13307 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13309 unsigned int offset
, size
, padding_size
;
13310 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13312 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13314 address
= fragP
->fr_address
;
13315 address
+= fragP
->fr_fix
;
13317 /* CMP like instrunction size. */
13318 size
= fragP
->tc_frag_data
.cmp_size
;
13320 /* The base size of the branch frag. */
13321 size
+= branch_fragP
->fr_fix
;
13323 /* Add opcode and displacement bytes for the rs_machine_dependent
13325 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13326 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13328 /* Check if branch is within boundary and doesn't end at the last
13330 offset
= address
& ((1U << align_branch_power
) - 1);
13331 if ((offset
+ size
) >= (1U << align_branch_power
))
13332 /* Padding needed to avoid crossing boundary. */
13333 padding_size
= (1U << align_branch_power
) - offset
;
13335 /* No padding needed. */
13338 /* The return value may be saved in tc_frag_data.length which is
13340 if (!fits_in_unsigned_byte (padding_size
))
13343 return padding_size
;
13346 /* i386_generic_table_relax_frag()
13348 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13349 grow/shrink padding to align branch frags. Hand others to
13353 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13355 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13356 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13358 long padding_size
= i386_branch_padding_size (fragP
, 0);
13359 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13361 /* When the BRANCH_PREFIX frag is used, the computed address
13362 must match the actual address and there should be no padding. */
13363 if (fragP
->tc_frag_data
.padding_address
13364 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13368 /* Update the padding size. */
13370 fragP
->tc_frag_data
.length
= padding_size
;
13374 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13376 fragS
*padding_fragP
, *next_fragP
;
13377 long padding_size
, left_size
, last_size
;
13379 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13380 if (!padding_fragP
)
13381 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13382 return (fragP
->tc_frag_data
.length
13383 - fragP
->tc_frag_data
.last_length
);
13385 /* Compute the relative address of the padding frag in the very
13386 first time where the BRANCH_PREFIX frag sizes are zero. */
13387 if (!fragP
->tc_frag_data
.padding_address
)
13388 fragP
->tc_frag_data
.padding_address
13389 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13391 /* First update the last length from the previous interation. */
13392 left_size
= fragP
->tc_frag_data
.prefix_length
;
13393 for (next_fragP
= fragP
;
13394 next_fragP
!= padding_fragP
;
13395 next_fragP
= next_fragP
->fr_next
)
13396 if (next_fragP
->fr_type
== rs_machine_dependent
13397 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13402 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13406 if (max
> left_size
)
13411 next_fragP
->tc_frag_data
.last_length
= size
;
13415 next_fragP
->tc_frag_data
.last_length
= 0;
13418 /* Check the padding size for the padding frag. */
13419 padding_size
= i386_branch_padding_size
13420 (padding_fragP
, (fragP
->fr_address
13421 + fragP
->tc_frag_data
.padding_address
));
13423 last_size
= fragP
->tc_frag_data
.prefix_length
;
13424 /* Check if there is change from the last interation. */
13425 if (padding_size
== last_size
)
13427 /* Update the expected address of the padding frag. */
13428 padding_fragP
->tc_frag_data
.padding_address
13429 = (fragP
->fr_address
+ padding_size
13430 + fragP
->tc_frag_data
.padding_address
);
13434 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13436 /* No padding if there is no sufficient room. Clear the
13437 expected address of the padding frag. */
13438 padding_fragP
->tc_frag_data
.padding_address
= 0;
13442 /* Store the expected address of the padding frag. */
13443 padding_fragP
->tc_frag_data
.padding_address
13444 = (fragP
->fr_address
+ padding_size
13445 + fragP
->tc_frag_data
.padding_address
);
13447 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13449 /* Update the length for the current interation. */
13450 left_size
= padding_size
;
13451 for (next_fragP
= fragP
;
13452 next_fragP
!= padding_fragP
;
13453 next_fragP
= next_fragP
->fr_next
)
13454 if (next_fragP
->fr_type
== rs_machine_dependent
13455 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13460 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13464 if (max
> left_size
)
13469 next_fragP
->tc_frag_data
.length
= size
;
13473 next_fragP
->tc_frag_data
.length
= 0;
13476 return (fragP
->tc_frag_data
.length
13477 - fragP
->tc_frag_data
.last_length
);
13479 return relax_frag (segment
, fragP
, stretch
);
13482 /* md_estimate_size_before_relax()
13484 Called just before relax() for rs_machine_dependent frags. The x86
13485 assembler uses these frags to handle variable size jump
13488 Any symbol that is now undefined will not become defined.
13489 Return the correct fr_subtype in the frag.
13490 Return the initial "guess for variable size of frag" to caller.
13491 The guess is actually the growth beyond the fixed part. Whatever
13492 we do to grow the fixed or variable part contributes to our
13496 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13498 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13499 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13500 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13502 i386_classify_machine_dependent_frag (fragP
);
13503 return fragP
->tc_frag_data
.length
;
13506 /* We've already got fragP->fr_subtype right; all we have to do is
13507 check for un-relaxable symbols. On an ELF system, we can't relax
13508 an externally visible symbol, because it may be overridden by a
13510 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13511 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13513 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13516 #if defined (OBJ_COFF) && defined (TE_PE)
13517 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13518 && S_IS_WEAK (fragP
->fr_symbol
))
13522 /* Symbol is undefined in this segment, or we need to keep a
13523 reloc so that weak symbols can be overridden. */
13524 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13525 enum bfd_reloc_code_real reloc_type
;
13526 unsigned char *opcode
;
13530 if (fragP
->fr_var
!= NO_RELOC
)
13531 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13532 else if (size
== 2)
13533 reloc_type
= BFD_RELOC_16_PCREL
;
13534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13535 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13536 && fragP
->fr_offset
== 0
13537 && need_plt32_p (fragP
->fr_symbol
))
13538 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13541 reloc_type
= BFD_RELOC_32_PCREL
;
13543 old_fr_fix
= fragP
->fr_fix
;
13544 opcode
= (unsigned char *) fragP
->fr_opcode
;
13546 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13549 /* Make jmp (0xeb) a (d)word displacement jump. */
13551 fragP
->fr_fix
+= size
;
13552 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13554 fragP
->fr_offset
, 1,
13560 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13562 /* Negate the condition, and branch past an
13563 unconditional jump. */
13566 /* Insert an unconditional jump. */
13568 /* We added two extra opcode bytes, and have a two byte
13570 fragP
->fr_fix
+= 2 + 2;
13571 fix_new (fragP
, old_fr_fix
+ 2, 2,
13573 fragP
->fr_offset
, 1,
13577 /* Fall through. */
13580 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13582 fragP
->fr_fix
+= 1;
13583 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13585 fragP
->fr_offset
, 1,
13586 BFD_RELOC_8_PCREL
);
13587 fixP
->fx_signed
= 1;
13591 /* This changes the byte-displacement jump 0x7N
13592 to the (d)word-displacement jump 0x0f,0x8N. */
13593 opcode
[1] = opcode
[0] + 0x10;
13594 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13595 /* We've added an opcode byte. */
13596 fragP
->fr_fix
+= 1 + size
;
13597 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13599 fragP
->fr_offset
, 1,
13604 BAD_CASE (fragP
->fr_subtype
);
13608 /* All jumps handled here are signed, but don't unconditionally use a
13609 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13610 around at 4G (outside of 64-bit mode) and 64k. */
13611 if (size
== 4 && flag_code
== CODE_64BIT
)
13612 fixP
->fx_signed
= 1;
13615 return fragP
->fr_fix
- old_fr_fix
;
13618 /* Guess size depending on current relax state. Initially the relax
13619 state will correspond to a short jump and we return 1, because
13620 the variable part of the frag (the branch offset) is one byte
13621 long. However, we can relax a section more than once and in that
13622 case we must either set fr_subtype back to the unrelaxed state,
13623 or return the value for the appropriate branch. */
13624 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13627 /* Called after relax() is finished.
13629 In: Address of frag.
13630 fr_type == rs_machine_dependent.
13631 fr_subtype is what the address relaxed to.
13633 Out: Any fixSs and constants are set up.
13634 Caller will turn frag into a ".space 0". */
13637 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13640 unsigned char *opcode
;
13641 unsigned char *where_to_put_displacement
= NULL
;
13642 offsetT target_address
;
13643 offsetT opcode_address
;
13644 unsigned int extension
= 0;
13645 offsetT displacement_from_opcode_start
;
13647 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13648 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13649 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13651 /* Generate nop padding. */
13652 unsigned int size
= fragP
->tc_frag_data
.length
;
13655 if (size
> fragP
->tc_frag_data
.max_bytes
)
13661 const char *branch
= "branch";
13662 const char *prefix
= "";
13663 fragS
*padding_fragP
;
13664 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13667 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13668 switch (fragP
->tc_frag_data
.default_prefix
)
13673 case CS_PREFIX_OPCODE
:
13676 case DS_PREFIX_OPCODE
:
13679 case ES_PREFIX_OPCODE
:
13682 case FS_PREFIX_OPCODE
:
13685 case GS_PREFIX_OPCODE
:
13688 case SS_PREFIX_OPCODE
:
13693 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13694 "%s within %d-byte boundary\n");
13696 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13697 "align %s within %d-byte boundary\n");
13701 padding_fragP
= fragP
;
13702 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13703 "%s within %d-byte boundary\n");
13707 switch (padding_fragP
->tc_frag_data
.branch_type
)
13709 case align_branch_jcc
:
13712 case align_branch_fused
:
13713 branch
= "fused jcc";
13715 case align_branch_jmp
:
13718 case align_branch_call
:
13721 case align_branch_indirect
:
13722 branch
= "indiret branch";
13724 case align_branch_ret
:
13731 fprintf (stdout
, msg
,
13732 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13733 (long long) fragP
->fr_address
, branch
,
13734 1 << align_branch_power
);
13736 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13737 memset (fragP
->fr_opcode
,
13738 fragP
->tc_frag_data
.default_prefix
, size
);
13740 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13742 fragP
->fr_fix
+= size
;
13747 opcode
= (unsigned char *) fragP
->fr_opcode
;
13749 /* Address we want to reach in file space. */
13750 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13752 /* Address opcode resides at in file space. */
13753 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13755 /* Displacement from opcode start to fill into instruction. */
13756 displacement_from_opcode_start
= target_address
- opcode_address
;
13758 if ((fragP
->fr_subtype
& BIG
) == 0)
13760 /* Don't have to change opcode. */
13761 extension
= 1; /* 1 opcode + 1 displacement */
13762 where_to_put_displacement
= &opcode
[1];
13766 if (no_cond_jump_promotion
13767 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13768 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13769 _("long jump required"));
13771 switch (fragP
->fr_subtype
)
13773 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13774 extension
= 4; /* 1 opcode + 4 displacement */
13776 where_to_put_displacement
= &opcode
[1];
13779 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13780 extension
= 2; /* 1 opcode + 2 displacement */
13782 where_to_put_displacement
= &opcode
[1];
13785 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13786 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13787 extension
= 5; /* 2 opcode + 4 displacement */
13788 opcode
[1] = opcode
[0] + 0x10;
13789 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13790 where_to_put_displacement
= &opcode
[2];
13793 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13794 extension
= 3; /* 2 opcode + 2 displacement */
13795 opcode
[1] = opcode
[0] + 0x10;
13796 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13797 where_to_put_displacement
= &opcode
[2];
13800 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13805 where_to_put_displacement
= &opcode
[3];
13809 BAD_CASE (fragP
->fr_subtype
);
13814 /* If size if less then four we are sure that the operand fits,
13815 but if it's 4, then it could be that the displacement is larger
13817 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13819 && ((addressT
) (displacement_from_opcode_start
- extension
13820 + ((addressT
) 1 << 31))
13821 > (((addressT
) 2 << 31) - 1)))
13823 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13824 _("jump target out of range"));
13825 /* Make us emit 0. */
13826 displacement_from_opcode_start
= extension
;
13828 /* Now put displacement after opcode. */
13829 md_number_to_chars ((char *) where_to_put_displacement
,
13830 (valueT
) (displacement_from_opcode_start
- extension
),
13831 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13832 fragP
->fr_fix
+= extension
;
13835 /* Apply a fixup (fixP) to segment data, once it has been determined
13836 by our caller that we have all the info we need to fix it up.
13838 Parameter valP is the pointer to the value of the bits.
13840 On the 386, immediates, displacements, and data pointers are all in
13841 the same (little-endian) format, so we don't need to care about which
13842 we are handling. */
13845 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13847 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13848 valueT value
= *valP
;
13850 #if !defined (TE_Mach)
13851 if (fixP
->fx_pcrel
)
13853 switch (fixP
->fx_r_type
)
13859 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13862 case BFD_RELOC_X86_64_32S
:
13863 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13866 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13869 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13874 if (fixP
->fx_addsy
!= NULL
13875 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13876 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13877 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13878 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13879 && !use_rela_relocations
)
13881 /* This is a hack. There should be a better way to handle this.
13882 This covers for the fact that bfd_install_relocation will
13883 subtract the current location (for partial_inplace, PC relative
13884 relocations); see more below. */
13888 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13891 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13896 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13898 if ((sym_seg
== seg
13899 || (symbol_section_p (fixP
->fx_addsy
)
13900 && sym_seg
!= absolute_section
))
13901 && !generic_force_reloc (fixP
))
13903 /* Yes, we add the values in twice. This is because
13904 bfd_install_relocation subtracts them out again. I think
13905 bfd_install_relocation is broken, but I don't dare change
13907 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13911 #if defined (OBJ_COFF) && defined (TE_PE)
13912 /* For some reason, the PE format does not store a
13913 section address offset for a PC relative symbol. */
13914 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13915 || S_IS_WEAK (fixP
->fx_addsy
))
13916 value
+= md_pcrel_from (fixP
);
13919 #if defined (OBJ_COFF) && defined (TE_PE)
13920 if (fixP
->fx_addsy
!= NULL
13921 && S_IS_WEAK (fixP
->fx_addsy
)
13922 /* PR 16858: Do not modify weak function references. */
13923 && ! fixP
->fx_pcrel
)
13925 #if !defined (TE_PEP)
13926 /* For x86 PE weak function symbols are neither PC-relative
13927 nor do they set S_IS_FUNCTION. So the only reliable way
13928 to detect them is to check the flags of their containing
13930 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13931 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13935 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13939 /* Fix a few things - the dynamic linker expects certain values here,
13940 and we must not disappoint it. */
13941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13942 if (IS_ELF
&& fixP
->fx_addsy
)
13943 switch (fixP
->fx_r_type
)
13945 case BFD_RELOC_386_PLT32
:
13946 case BFD_RELOC_X86_64_PLT32
:
13947 /* Make the jump instruction point to the address of the operand.
13948 At runtime we merely add the offset to the actual PLT entry.
13949 NB: Subtract the offset size only for jump instructions. */
13950 if (fixP
->fx_pcrel
)
13954 case BFD_RELOC_386_TLS_GD
:
13955 case BFD_RELOC_386_TLS_LDM
:
13956 case BFD_RELOC_386_TLS_IE_32
:
13957 case BFD_RELOC_386_TLS_IE
:
13958 case BFD_RELOC_386_TLS_GOTIE
:
13959 case BFD_RELOC_386_TLS_GOTDESC
:
13960 case BFD_RELOC_X86_64_TLSGD
:
13961 case BFD_RELOC_X86_64_TLSLD
:
13962 case BFD_RELOC_X86_64_GOTTPOFF
:
13963 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13964 value
= 0; /* Fully resolved at runtime. No addend. */
13966 case BFD_RELOC_386_TLS_LE
:
13967 case BFD_RELOC_386_TLS_LDO_32
:
13968 case BFD_RELOC_386_TLS_LE_32
:
13969 case BFD_RELOC_X86_64_DTPOFF32
:
13970 case BFD_RELOC_X86_64_DTPOFF64
:
13971 case BFD_RELOC_X86_64_TPOFF32
:
13972 case BFD_RELOC_X86_64_TPOFF64
:
13973 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13976 case BFD_RELOC_386_TLS_DESC_CALL
:
13977 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13978 value
= 0; /* Fully resolved at runtime. No addend. */
13979 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13983 case BFD_RELOC_VTABLE_INHERIT
:
13984 case BFD_RELOC_VTABLE_ENTRY
:
13991 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13993 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13995 value
= extend_to_32bit_address (value
);
13998 #endif /* !defined (TE_Mach) */
14000 /* Are we finished with this relocation now? */
14001 if (fixP
->fx_addsy
== NULL
)
14004 switch (fixP
->fx_r_type
)
14006 case BFD_RELOC_X86_64_32S
:
14007 fixP
->fx_signed
= 1;
14014 #if defined (OBJ_COFF) && defined (TE_PE)
14015 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
14018 /* Remember value for tc_gen_reloc. */
14019 fixP
->fx_addnumber
= value
;
14020 /* Clear out the frag for now. */
14024 else if (use_rela_relocations
)
14026 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14027 fixP
->fx_no_overflow
= 1;
14028 /* Remember value for tc_gen_reloc. */
14029 fixP
->fx_addnumber
= value
;
14033 md_number_to_chars (p
, value
, fixP
->fx_size
);
14037 md_atof (int type
, char *litP
, int *sizeP
)
14039 /* This outputs the LITTLENUMs in REVERSE order;
14040 in accord with the bigendian 386. */
14041 return ieee_md_atof (type
, litP
, sizeP
, false);
14044 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14047 output_invalid (int c
)
14050 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14053 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14054 "(0x%x)", (unsigned char) c
);
14055 return output_invalid_buf
;
14058 /* Verify that @r can be used in the current context. */
14060 static bool check_register (const reg_entry
*r
)
14062 if (allow_pseudo_reg
)
14065 if (operand_type_all_zero (&r
->reg_type
))
14068 if ((r
->reg_type
.bitfield
.dword
14069 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14070 || r
->reg_type
.bitfield
.class == RegCR
14071 || r
->reg_type
.bitfield
.class == RegDR
)
14072 && !cpu_arch_flags
.bitfield
.cpui386
)
14075 if (r
->reg_type
.bitfield
.class == RegTR
14076 && (flag_code
== CODE_64BIT
14077 || !cpu_arch_flags
.bitfield
.cpui386
14078 || cpu_arch_isa_flags
.bitfield
.cpui586
14079 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14082 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14085 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14087 if (r
->reg_type
.bitfield
.zmmword
14088 || r
->reg_type
.bitfield
.class == RegMask
)
14091 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14093 if (r
->reg_type
.bitfield
.ymmword
)
14096 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14101 if (r
->reg_type
.bitfield
.zmmword
)
14103 if (vector_size
< VSZ512
)
14106 if (i
.vec_encoding
== vex_encoding_default
)
14107 i
.vec_encoding
= vex_encoding_evex512
;
14108 else if (i
.vec_encoding
!= vex_encoding_evex
14109 && i
.vec_encoding
!= vex_encoding_evex512
)
14110 i
.vec_encoding
= vex_encoding_error
;
14113 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14116 if (r
->reg_type
.bitfield
.tmmword
14117 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14118 || flag_code
!= CODE_64BIT
))
14121 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14124 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14125 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14128 /* Upper 16 vector registers are only available with VREX in 64bit
14129 mode, and require EVEX encoding. */
14130 if (r
->reg_flags
& RegVRex
)
14132 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14133 || flag_code
!= CODE_64BIT
)
14136 if (i
.vec_encoding
== vex_encoding_default
14137 || i
.vec_encoding
== vex_encoding_evex512
)
14138 i
.vec_encoding
= vex_encoding_evex
;
14139 else if (i
.vec_encoding
!= vex_encoding_evex
)
14140 i
.vec_encoding
= vex_encoding_error
;
14143 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14144 && (!cpu_arch_flags
.bitfield
.cpu64
14145 || r
->reg_type
.bitfield
.class != RegCR
14147 && flag_code
!= CODE_64BIT
)
14150 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14157 /* REG_STRING starts *before* REGISTER_PREFIX. */
14159 static const reg_entry
*
14160 parse_real_register (const char *reg_string
, char **end_op
)
14162 const char *s
= reg_string
;
14164 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14165 const reg_entry
*r
;
14167 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14168 if (*s
== REGISTER_PREFIX
)
14171 if (is_space_char (*s
))
14174 p
= reg_name_given
;
14175 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14177 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14178 return (const reg_entry
*) NULL
;
14182 if (is_part_of_name (*s
))
14183 return (const reg_entry
*) NULL
;
14185 *end_op
= (char *) s
;
14187 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14189 /* Handle floating point regs, allowing spaces in the (i) part. */
14192 if (!cpu_arch_flags
.bitfield
.cpu8087
14193 && !cpu_arch_flags
.bitfield
.cpu287
14194 && !cpu_arch_flags
.bitfield
.cpu387
14195 && !allow_pseudo_reg
)
14196 return (const reg_entry
*) NULL
;
14198 if (is_space_char (*s
))
14203 if (is_space_char (*s
))
14205 if (*s
>= '0' && *s
<= '7')
14207 int fpr
= *s
- '0';
14209 if (is_space_char (*s
))
14213 *end_op
= (char *) s
+ 1;
14214 know (r
[fpr
].reg_num
== fpr
);
14218 /* We have "%st(" then garbage. */
14219 return (const reg_entry
*) NULL
;
14223 return r
&& check_register (r
) ? r
: NULL
;
14226 /* REG_STRING starts *before* REGISTER_PREFIX. */
14228 static const reg_entry
*
14229 parse_register (const char *reg_string
, char **end_op
)
14231 const reg_entry
*r
;
14233 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14234 r
= parse_real_register (reg_string
, end_op
);
14239 char *save
= input_line_pointer
;
14240 char *buf
= xstrdup (reg_string
), *name
;
14243 input_line_pointer
= buf
;
14244 get_symbol_name (&name
);
14245 symbolP
= symbol_find (name
);
14246 while (symbolP
&& symbol_equated_p (symbolP
))
14248 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14250 if (e
->X_add_number
)
14252 symbolP
= e
->X_add_symbol
;
14254 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14256 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14258 if (e
->X_op
== O_register
)
14260 know (e
->X_add_number
>= 0
14261 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14262 r
= i386_regtab
+ e
->X_add_number
;
14263 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14265 if (r
&& !check_register (r
))
14267 as_bad (_("register '%s%s' cannot be used here"),
14268 register_prefix
, r
->reg_name
);
14272 input_line_pointer
= save
;
14279 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14281 const reg_entry
*r
= NULL
;
14282 char *end
= input_line_pointer
;
14284 /* We only know the terminating character here. It being double quote could
14285 be the closing one of a quoted symbol name, or an opening one from a
14286 following string (or another quoted symbol name). Since the latter can't
14287 be valid syntax for anything, bailing in either case is good enough. */
14288 if (*nextcharP
== '"')
14292 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14293 r
= parse_real_register (name
, &input_line_pointer
);
14294 if (r
&& end
<= input_line_pointer
)
14296 *nextcharP
= *input_line_pointer
;
14297 *input_line_pointer
= 0;
14298 e
->X_op
= O_register
;
14299 e
->X_add_number
= r
- i386_regtab
;
14302 input_line_pointer
= end
;
14304 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14308 md_operand (expressionS
*e
)
14311 const reg_entry
*r
;
14313 switch (*input_line_pointer
)
14315 case REGISTER_PREFIX
:
14316 r
= parse_real_register (input_line_pointer
, &end
);
14319 e
->X_op
= O_register
;
14320 e
->X_add_number
= r
- i386_regtab
;
14321 input_line_pointer
= end
;
14326 gas_assert (intel_syntax
);
14327 end
= input_line_pointer
++;
14329 if (*input_line_pointer
== ']')
14331 ++input_line_pointer
;
14332 e
->X_op_symbol
= make_expr_symbol (e
);
14333 e
->X_add_symbol
= NULL
;
14334 e
->X_add_number
= 0;
14339 e
->X_op
= O_absent
;
14340 input_line_pointer
= end
;
14347 /* To maintain consistency with !BFD64 builds of gas record, whether any
14348 (binary) operator was involved in an expression. As expressions are
14349 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14350 truncate results. */
14351 bool i386_record_operator (operatorT op
,
14352 const expressionS
*left
,
14353 const expressionS
*right
)
14355 if (op
== O_absent
)
14360 /* Since the expression parser applies unary operators fine to bignum
14361 operands, we don't need to be concerned of respective operands not
14362 fitting in 32 bits. */
14363 if (right
->X_op
== O_constant
&& right
->X_unsigned
14364 && !fits_in_unsigned_long (right
->X_add_number
))
14367 /* This isn't entirely right: The pattern can also result when constant
14368 expressions are folded (e.g. 0xffffffff + 1). */
14369 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14370 && !fits_in_unsigned_long (left
->X_add_number
))
14371 || (right
->X_op
== O_constant
&& right
->X_unsigned
14372 && !fits_in_unsigned_long (right
->X_add_number
)))
14373 expr_mode
= expr_large_value
;
14375 if (expr_mode
!= expr_large_value
)
14376 expr_mode
= expr_operator_present
;
14382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14383 const char *md_shortopts
= "kVQ:sqnO::";
14385 const char *md_shortopts
= "qnO::";
14388 #define OPTION_32 (OPTION_MD_BASE + 0)
14389 #define OPTION_64 (OPTION_MD_BASE + 1)
14390 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14391 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14392 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14393 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14394 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14395 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14396 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14397 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14398 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14399 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14400 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14401 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14402 #define OPTION_X32 (OPTION_MD_BASE + 14)
14403 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14404 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14405 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14406 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14407 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14408 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14409 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14410 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14411 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14412 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14413 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14414 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14415 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14416 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14417 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14418 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14419 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14420 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14421 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14422 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14424 struct option md_longopts
[] =
14426 {"32", no_argument
, NULL
, OPTION_32
},
14427 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14428 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14429 {"64", no_argument
, NULL
, OPTION_64
},
14431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14432 {"x32", no_argument
, NULL
, OPTION_X32
},
14433 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14434 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14436 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14437 {"march", required_argument
, NULL
, OPTION_MARCH
},
14438 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14439 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14440 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14441 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14442 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14443 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14444 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14445 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14446 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14447 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14448 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14449 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14450 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14451 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14452 # if defined (TE_PE) || defined (TE_PEP)
14453 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14455 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14456 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14457 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14458 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14459 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14460 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14461 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14462 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14463 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14464 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14465 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14466 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14467 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14468 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14469 {NULL
, no_argument
, NULL
, 0}
14471 size_t md_longopts_size
= sizeof (md_longopts
);
14474 md_parse_option (int c
, const char *arg
)
14477 char *arch
, *next
, *saved
, *type
;
14482 optimize_align_code
= 0;
14486 quiet_warnings
= 1;
14489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14490 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14491 should be emitted or not. FIXME: Not implemented. */
14493 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14497 /* -V: SVR4 argument to print version ID. */
14499 print_version_id ();
14502 /* -k: Ignore for FreeBSD compatibility. */
14507 /* -s: On i386 Solaris, this tells the native assembler to use
14508 .stab instead of .stab.excl. We always use .stab anyhow. */
14511 case OPTION_MSHARED
:
14515 case OPTION_X86_USED_NOTE
:
14516 if (strcasecmp (arg
, "yes") == 0)
14518 else if (strcasecmp (arg
, "no") == 0)
14521 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14526 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14530 const char **list
, **l
;
14532 list
= bfd_target_list ();
14533 for (l
= list
; *l
!= NULL
; l
++)
14534 if (startswith (*l
, "elf64-x86-64")
14535 || strcmp (*l
, "coff-x86-64") == 0
14536 || strcmp (*l
, "pe-x86-64") == 0
14537 || strcmp (*l
, "pei-x86-64") == 0
14538 || strcmp (*l
, "mach-o-x86-64") == 0)
14540 default_arch
= "x86_64";
14544 as_fatal (_("no compiled in support for x86_64"));
14550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14554 const char **list
, **l
;
14556 list
= bfd_target_list ();
14557 for (l
= list
; *l
!= NULL
; l
++)
14558 if (startswith (*l
, "elf32-x86-64"))
14560 default_arch
= "x86_64:32";
14564 as_fatal (_("no compiled in support for 32bit x86_64"));
14568 as_fatal (_("32bit x86_64 is only supported for ELF"));
14574 const char **list
, **l
;
14576 list
= bfd_target_list ();
14577 for (l
= list
; *l
!= NULL
; l
++)
14578 if (strstr (*l
, "-i386")
14579 || strstr (*l
, "-go32"))
14581 default_arch
= "i386";
14585 as_fatal (_("no compiled in support for ix86"));
14590 case OPTION_DIVIDE
:
14591 #ifdef SVR4_COMMENT_CHARS
14596 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14598 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14602 i386_comment_chars
= n
;
14608 saved
= xstrdup (arg
);
14610 /* Allow -march=+nosse. */
14618 as_fatal (_("invalid -march= option: `%s'"), arg
);
14619 next
= strchr (arch
, '+');
14622 vsz
= strchr (arch
, '/');
14625 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14627 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14630 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14631 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14634 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14637 cpu_arch_name
= cpu_arch
[j
].name
;
14638 free (cpu_sub_arch_name
);
14639 cpu_sub_arch_name
= NULL
;
14640 cpu_arch_flags
= cpu_arch
[j
].enable
;
14641 cpu_arch_isa
= cpu_arch
[j
].type
;
14642 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14643 if (!cpu_arch_tune_set
)
14644 cpu_arch_tune
= cpu_arch_isa
;
14645 vector_size
= VSZ_DEFAULT
;
14648 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14649 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14650 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14652 /* ISA extension. */
14655 switch (cpu_arch
[j
].vsz
)
14664 unsigned long val
= strtoul (vsz
, &end
, 0);
14670 case 512: vector_size
= VSZ512
; break;
14671 case 256: vector_size
= VSZ256
; break;
14672 case 128: vector_size
= VSZ128
; break;
14674 as_warn (_("Unrecognized vector size specifier ignored"));
14679 /* Fall through. */
14681 vector_size
= VSZ_DEFAULT
;
14689 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14691 /* Disable an ISA extension. */
14692 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14693 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14694 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14697 if (cpu_arch
[j
].vsz
== vsz_set
)
14698 vector_size
= VSZ_DEFAULT
;
14703 if (j
>= ARRAY_SIZE (cpu_arch
))
14704 as_fatal (_("invalid -march= option: `%s'"), arg
);
14708 while (next
!= NULL
);
14714 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14715 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14717 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14718 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14720 cpu_arch_tune_set
= 1;
14721 cpu_arch_tune
= cpu_arch
[j
].type
;
14725 if (j
>= ARRAY_SIZE (cpu_arch
))
14726 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14729 case OPTION_MMNEMONIC
:
14730 if (strcasecmp (arg
, "att") == 0)
14731 intel_mnemonic
= 0;
14732 else if (strcasecmp (arg
, "intel") == 0)
14733 intel_mnemonic
= 1;
14735 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14738 case OPTION_MSYNTAX
:
14739 if (strcasecmp (arg
, "att") == 0)
14741 else if (strcasecmp (arg
, "intel") == 0)
14744 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14747 case OPTION_MINDEX_REG
:
14748 allow_index_reg
= 1;
14751 case OPTION_MNAKED_REG
:
14752 allow_naked_reg
= 1;
14755 case OPTION_MSSE2AVX
:
14759 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14760 use_unaligned_vector_move
= 1;
14763 case OPTION_MSSE_CHECK
:
14764 if (strcasecmp (arg
, "error") == 0)
14765 sse_check
= check_error
;
14766 else if (strcasecmp (arg
, "warning") == 0)
14767 sse_check
= check_warning
;
14768 else if (strcasecmp (arg
, "none") == 0)
14769 sse_check
= check_none
;
14771 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14774 case OPTION_MOPERAND_CHECK
:
14775 if (strcasecmp (arg
, "error") == 0)
14776 operand_check
= check_error
;
14777 else if (strcasecmp (arg
, "warning") == 0)
14778 operand_check
= check_warning
;
14779 else if (strcasecmp (arg
, "none") == 0)
14780 operand_check
= check_none
;
14782 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14785 case OPTION_MAVXSCALAR
:
14786 if (strcasecmp (arg
, "128") == 0)
14787 avxscalar
= vex128
;
14788 else if (strcasecmp (arg
, "256") == 0)
14789 avxscalar
= vex256
;
14791 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14794 case OPTION_MVEXWIG
:
14795 if (strcmp (arg
, "0") == 0)
14797 else if (strcmp (arg
, "1") == 0)
14800 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14803 case OPTION_MADD_BND_PREFIX
:
14804 add_bnd_prefix
= 1;
14807 case OPTION_MEVEXLIG
:
14808 if (strcmp (arg
, "128") == 0)
14809 evexlig
= evexl128
;
14810 else if (strcmp (arg
, "256") == 0)
14811 evexlig
= evexl256
;
14812 else if (strcmp (arg
, "512") == 0)
14813 evexlig
= evexl512
;
14815 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14818 case OPTION_MEVEXRCIG
:
14819 if (strcmp (arg
, "rne") == 0)
14821 else if (strcmp (arg
, "rd") == 0)
14823 else if (strcmp (arg
, "ru") == 0)
14825 else if (strcmp (arg
, "rz") == 0)
14828 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14831 case OPTION_MEVEXWIG
:
14832 if (strcmp (arg
, "0") == 0)
14834 else if (strcmp (arg
, "1") == 0)
14837 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14840 # if defined (TE_PE) || defined (TE_PEP)
14841 case OPTION_MBIG_OBJ
:
14846 case OPTION_MOMIT_LOCK_PREFIX
:
14847 if (strcasecmp (arg
, "yes") == 0)
14848 omit_lock_prefix
= 1;
14849 else if (strcasecmp (arg
, "no") == 0)
14850 omit_lock_prefix
= 0;
14852 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14855 case OPTION_MFENCE_AS_LOCK_ADD
:
14856 if (strcasecmp (arg
, "yes") == 0)
14858 else if (strcasecmp (arg
, "no") == 0)
14861 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14864 case OPTION_MLFENCE_AFTER_LOAD
:
14865 if (strcasecmp (arg
, "yes") == 0)
14866 lfence_after_load
= 1;
14867 else if (strcasecmp (arg
, "no") == 0)
14868 lfence_after_load
= 0;
14870 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14873 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14874 if (strcasecmp (arg
, "all") == 0)
14876 lfence_before_indirect_branch
= lfence_branch_all
;
14877 if (lfence_before_ret
== lfence_before_ret_none
)
14878 lfence_before_ret
= lfence_before_ret_shl
;
14880 else if (strcasecmp (arg
, "memory") == 0)
14881 lfence_before_indirect_branch
= lfence_branch_memory
;
14882 else if (strcasecmp (arg
, "register") == 0)
14883 lfence_before_indirect_branch
= lfence_branch_register
;
14884 else if (strcasecmp (arg
, "none") == 0)
14885 lfence_before_indirect_branch
= lfence_branch_none
;
14887 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14891 case OPTION_MLFENCE_BEFORE_RET
:
14892 if (strcasecmp (arg
, "or") == 0)
14893 lfence_before_ret
= lfence_before_ret_or
;
14894 else if (strcasecmp (arg
, "not") == 0)
14895 lfence_before_ret
= lfence_before_ret_not
;
14896 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14897 lfence_before_ret
= lfence_before_ret_shl
;
14898 else if (strcasecmp (arg
, "none") == 0)
14899 lfence_before_ret
= lfence_before_ret_none
;
14901 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14905 case OPTION_MRELAX_RELOCATIONS
:
14906 if (strcasecmp (arg
, "yes") == 0)
14907 generate_relax_relocations
= 1;
14908 else if (strcasecmp (arg
, "no") == 0)
14909 generate_relax_relocations
= 0;
14911 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14914 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14917 long int align
= strtoul (arg
, &end
, 0);
14922 align_branch_power
= 0;
14925 else if (align
>= 16)
14928 for (align_power
= 0;
14930 align
>>= 1, align_power
++)
14932 /* Limit alignment power to 31. */
14933 if (align
== 1 && align_power
< 32)
14935 align_branch_power
= align_power
;
14940 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14944 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14947 int align
= strtoul (arg
, &end
, 0);
14948 /* Some processors only support 5 prefixes. */
14949 if (*end
== '\0' && align
>= 0 && align
< 6)
14951 align_branch_prefix_size
= align
;
14954 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14959 case OPTION_MALIGN_BRANCH
:
14961 saved
= xstrdup (arg
);
14965 next
= strchr (type
, '+');
14968 if (strcasecmp (type
, "jcc") == 0)
14969 align_branch
|= align_branch_jcc_bit
;
14970 else if (strcasecmp (type
, "fused") == 0)
14971 align_branch
|= align_branch_fused_bit
;
14972 else if (strcasecmp (type
, "jmp") == 0)
14973 align_branch
|= align_branch_jmp_bit
;
14974 else if (strcasecmp (type
, "call") == 0)
14975 align_branch
|= align_branch_call_bit
;
14976 else if (strcasecmp (type
, "ret") == 0)
14977 align_branch
|= align_branch_ret_bit
;
14978 else if (strcasecmp (type
, "indirect") == 0)
14979 align_branch
|= align_branch_indirect_bit
;
14981 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14984 while (next
!= NULL
);
14988 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14989 align_branch_power
= 5;
14990 align_branch_prefix_size
= 5;
14991 align_branch
= (align_branch_jcc_bit
14992 | align_branch_fused_bit
14993 | align_branch_jmp_bit
);
14996 case OPTION_MAMD64
:
15000 case OPTION_MINTEL64
:
15008 /* Turn off -Os. */
15009 optimize_for_space
= 0;
15011 else if (*arg
== 's')
15013 optimize_for_space
= 1;
15014 /* Turn on all encoding optimizations. */
15015 optimize
= INT_MAX
;
15019 optimize
= atoi (arg
);
15020 /* Turn off -Os. */
15021 optimize_for_space
= 0;
15031 #define MESSAGE_TEMPLATE \
15035 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15036 int *left_p
, const char *name
, int len
)
15038 int size
= sizeof (MESSAGE_TEMPLATE
);
15039 int left
= *left_p
;
15041 /* Reserve 2 spaces for ", " or ",\0" */
15044 /* Check if there is any room. */
15052 p
= mempcpy (p
, name
, len
);
15056 /* Output the current message now and start a new one. */
15059 fprintf (stream
, "%s\n", message
);
15061 left
= size
- (start
- message
) - len
- 2;
15063 gas_assert (left
>= 0);
15065 p
= mempcpy (p
, name
, len
);
15073 show_arch (FILE *stream
, int ext
, int check
)
15075 static char message
[] = MESSAGE_TEMPLATE
;
15076 char *start
= message
+ 27;
15078 int size
= sizeof (MESSAGE_TEMPLATE
);
15085 left
= size
- (start
- message
);
15089 p
= output_message (stream
, p
, message
, start
, &left
,
15090 STRING_COMMA_LEN ("default"));
15091 p
= output_message (stream
, p
, message
, start
, &left
,
15092 STRING_COMMA_LEN ("push"));
15093 p
= output_message (stream
, p
, message
, start
, &left
,
15094 STRING_COMMA_LEN ("pop"));
15097 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15099 /* Should it be skipped? */
15100 if (cpu_arch
[j
].skip
)
15103 name
= cpu_arch
[j
].name
;
15104 len
= cpu_arch
[j
].len
;
15105 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15107 /* It is an extension. Skip if we aren't asked to show it. */
15108 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15113 /* It is an processor. Skip if we show only extension. */
15116 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15118 /* It is an impossible processor - skip. */
15122 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15125 /* Display disabled extensions. */
15127 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15131 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15132 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15134 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15135 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15141 fprintf (stream
, "%s\n", message
);
15145 md_show_usage (FILE *stream
)
15147 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15148 fprintf (stream
, _("\
15149 -Qy, -Qn ignored\n\
15150 -V print assembler version number\n\
15153 fprintf (stream
, _("\
15154 -n do not optimize code alignment\n\
15155 -O{012s} attempt some code optimizations\n\
15156 -q quieten some warnings\n"));
15157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15158 fprintf (stream
, _("\
15162 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15163 fprintf (stream
, _("\
15164 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15165 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15166 fprintf (stream
, _("\
15167 --32/--64 generate 32bit/64bit object\n"));
15170 #ifdef SVR4_COMMENT_CHARS
15171 fprintf (stream
, _("\
15172 --divide do not treat `/' as a comment character\n"));
15174 fprintf (stream
, _("\
15175 --divide ignored\n"));
15177 fprintf (stream
, _("\
15178 -march=CPU[,+EXTENSION...]\n\
15179 generate code for CPU and EXTENSION, CPU is one of:\n"));
15180 show_arch (stream
, 0, 1);
15181 fprintf (stream
, _("\
15182 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15183 show_arch (stream
, 1, 0);
15184 fprintf (stream
, _("\
15185 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15186 show_arch (stream
, 0, 0);
15187 fprintf (stream
, _("\
15188 -msse2avx encode SSE instructions with VEX prefix\n"));
15189 fprintf (stream
, _("\
15190 -muse-unaligned-vector-move\n\
15191 encode aligned vector move as unaligned vector move\n"));
15192 fprintf (stream
, _("\
15193 -msse-check=[none|error|warning] (default: warning)\n\
15194 check SSE instructions\n"));
15195 fprintf (stream
, _("\
15196 -moperand-check=[none|error|warning] (default: warning)\n\
15197 check operand combinations for validity\n"));
15198 fprintf (stream
, _("\
15199 -mavxscalar=[128|256] (default: 128)\n\
15200 encode scalar AVX instructions with specific vector\n\
15202 fprintf (stream
, _("\
15203 -mvexwig=[0|1] (default: 0)\n\
15204 encode VEX instructions with specific VEX.W value\n\
15205 for VEX.W bit ignored instructions\n"));
15206 fprintf (stream
, _("\
15207 -mevexlig=[128|256|512] (default: 128)\n\
15208 encode scalar EVEX instructions with specific vector\n\
15210 fprintf (stream
, _("\
15211 -mevexwig=[0|1] (default: 0)\n\
15212 encode EVEX instructions with specific EVEX.W value\n\
15213 for EVEX.W bit ignored instructions\n"));
15214 fprintf (stream
, _("\
15215 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15216 encode EVEX instructions with specific EVEX.RC value\n\
15217 for SAE-only ignored instructions\n"));
15218 fprintf (stream
, _("\
15219 -mmnemonic=[att|intel] "));
15220 if (SYSV386_COMPAT
)
15221 fprintf (stream
, _("(default: att)\n"));
15223 fprintf (stream
, _("(default: intel)\n"));
15224 fprintf (stream
, _("\
15225 use AT&T/Intel mnemonic\n"));
15226 fprintf (stream
, _("\
15227 -msyntax=[att|intel] (default: att)\n\
15228 use AT&T/Intel syntax\n"));
15229 fprintf (stream
, _("\
15230 -mindex-reg support pseudo index registers\n"));
15231 fprintf (stream
, _("\
15232 -mnaked-reg don't require `%%' prefix for registers\n"));
15233 fprintf (stream
, _("\
15234 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15236 fprintf (stream
, _("\
15237 -mshared disable branch optimization for shared code\n"));
15238 fprintf (stream
, _("\
15239 -mx86-used-note=[no|yes] "));
15240 if (DEFAULT_X86_USED_NOTE
)
15241 fprintf (stream
, _("(default: yes)\n"));
15243 fprintf (stream
, _("(default: no)\n"));
15244 fprintf (stream
, _("\
15245 generate x86 used ISA and feature properties\n"));
15247 #if defined (TE_PE) || defined (TE_PEP)
15248 fprintf (stream
, _("\
15249 -mbig-obj generate big object files\n"));
15251 fprintf (stream
, _("\
15252 -momit-lock-prefix=[no|yes] (default: no)\n\
15253 strip all lock prefixes\n"));
15254 fprintf (stream
, _("\
15255 -mfence-as-lock-add=[no|yes] (default: no)\n\
15256 encode lfence, mfence and sfence as\n\
15257 lock addl $0x0, (%%{re}sp)\n"));
15258 fprintf (stream
, _("\
15259 -mrelax-relocations=[no|yes] "));
15260 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15261 fprintf (stream
, _("(default: yes)\n"));
15263 fprintf (stream
, _("(default: no)\n"));
15264 fprintf (stream
, _("\
15265 generate relax relocations\n"));
15266 fprintf (stream
, _("\
15267 -malign-branch-boundary=NUM (default: 0)\n\
15268 align branches within NUM byte boundary\n"));
15269 fprintf (stream
, _("\
15270 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15271 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15273 specify types of branches to align\n"));
15274 fprintf (stream
, _("\
15275 -malign-branch-prefix-size=NUM (default: 5)\n\
15276 align branches with NUM prefixes per instruction\n"));
15277 fprintf (stream
, _("\
15278 -mbranches-within-32B-boundaries\n\
15279 align branches within 32 byte boundary\n"));
15280 fprintf (stream
, _("\
15281 -mlfence-after-load=[no|yes] (default: no)\n\
15282 generate lfence after load\n"));
15283 fprintf (stream
, _("\
15284 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15285 generate lfence before indirect near branch\n"));
15286 fprintf (stream
, _("\
15287 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15288 generate lfence before ret\n"));
15289 fprintf (stream
, _("\
15290 -mamd64 accept only AMD64 ISA [default]\n"));
15291 fprintf (stream
, _("\
15292 -mintel64 accept only Intel64 ISA\n"));
15295 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15296 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15297 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15299 /* Pick the target format to use. */
15302 i386_target_format (void)
15304 if (startswith (default_arch
, "x86_64"))
15306 update_code_flag (CODE_64BIT
, 1);
15307 if (default_arch
[6] == '\0')
15308 x86_elf_abi
= X86_64_ABI
;
15310 x86_elf_abi
= X86_64_X32_ABI
;
15312 else if (!strcmp (default_arch
, "i386"))
15313 update_code_flag (CODE_32BIT
, 1);
15314 else if (!strcmp (default_arch
, "iamcu"))
15316 update_code_flag (CODE_32BIT
, 1);
15317 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15319 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15320 cpu_arch_name
= "iamcu";
15321 free (cpu_sub_arch_name
);
15322 cpu_sub_arch_name
= NULL
;
15323 cpu_arch_flags
= iamcu_flags
;
15324 cpu_arch_isa
= PROCESSOR_IAMCU
;
15325 cpu_arch_isa_flags
= iamcu_flags
;
15326 if (!cpu_arch_tune_set
)
15327 cpu_arch_tune
= PROCESSOR_IAMCU
;
15329 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15330 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15334 as_fatal (_("unknown architecture"));
15336 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15337 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15339 switch (OUTPUT_FLAVOR
)
15341 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15342 case bfd_target_aout_flavour
:
15343 return AOUT_TARGET_FORMAT
;
15345 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15346 # if defined (TE_PE) || defined (TE_PEP)
15347 case bfd_target_coff_flavour
:
15348 if (flag_code
== CODE_64BIT
)
15351 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15353 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15354 # elif defined (TE_GO32)
15355 case bfd_target_coff_flavour
:
15356 return "coff-go32";
15358 case bfd_target_coff_flavour
:
15359 return "coff-i386";
15362 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15363 case bfd_target_elf_flavour
:
15365 const char *format
;
15367 switch (x86_elf_abi
)
15370 format
= ELF_TARGET_FORMAT
;
15372 tls_get_addr
= "___tls_get_addr";
15376 use_rela_relocations
= 1;
15379 tls_get_addr
= "__tls_get_addr";
15381 format
= ELF_TARGET_FORMAT64
;
15383 case X86_64_X32_ABI
:
15384 use_rela_relocations
= 1;
15387 tls_get_addr
= "__tls_get_addr";
15389 disallow_64bit_reloc
= 1;
15390 format
= ELF_TARGET_FORMAT32
;
15393 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15395 if (x86_elf_abi
!= I386_ABI
)
15396 as_fatal (_("Intel MCU is 32bit only"));
15397 return ELF_TARGET_IAMCU_FORMAT
;
15403 #if defined (OBJ_MACH_O)
15404 case bfd_target_mach_o_flavour
:
15405 if (flag_code
== CODE_64BIT
)
15407 use_rela_relocations
= 1;
15409 return "mach-o-x86-64";
15412 return "mach-o-i386";
15420 #endif /* OBJ_MAYBE_ more than one */
15423 md_undefined_symbol (char *name
)
15425 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15426 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15427 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15428 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15432 if (symbol_find (name
))
15433 as_bad (_("GOT already in symbol table"));
15434 GOT_symbol
= symbol_new (name
, undefined_section
,
15435 &zero_address_frag
, 0);
15442 /* Round up a section size to the appropriate boundary. */
15445 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15447 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15448 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15450 /* For a.out, force the section size to be aligned. If we don't do
15451 this, BFD will align it for us, but it will not write out the
15452 final bytes of the section. This may be a bug in BFD, but it is
15453 easier to fix it here since that is how the other a.out targets
15457 align
= bfd_section_alignment (segment
);
15458 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15465 /* On the i386, PC-relative offsets are relative to the start of the
15466 next instruction. That is, the address of the offset, plus its
15467 size, since the offset is always the last part of the insn. */
15470 md_pcrel_from (fixS
*fixP
)
15472 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15478 s_bss (int ignore ATTRIBUTE_UNUSED
)
15482 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15484 obj_elf_section_change_hook ();
15486 temp
= get_absolute_expression ();
15487 subseg_set (bss_section
, (subsegT
) temp
);
15488 demand_empty_rest_of_line ();
15493 /* Remember constant directive. */
15496 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15498 if (last_insn
.kind
!= last_insn_directive
15499 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15501 last_insn
.seg
= now_seg
;
15502 last_insn
.kind
= last_insn_directive
;
15503 last_insn
.name
= "constant directive";
15504 last_insn
.file
= as_where (&last_insn
.line
);
15505 if (lfence_before_ret
!= lfence_before_ret_none
)
15507 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15508 as_warn (_("constant directive skips -mlfence-before-ret "
15509 "and -mlfence-before-indirect-branch"));
15511 as_warn (_("constant directive skips -mlfence-before-ret"));
15513 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15514 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15519 i386_validate_fix (fixS
*fixp
)
15521 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15523 reloc_howto_type
*howto
;
15525 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15526 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15527 _("invalid %s relocation against register"),
15528 howto
? howto
->name
: "<unknown>");
15532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15533 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15534 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15535 return IS_ELF
&& fixp
->fx_addsy
15536 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15537 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15540 if (fixp
->fx_subsy
)
15542 if (fixp
->fx_subsy
== GOT_symbol
)
15544 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15549 if (fixp
->fx_tcbit2
)
15550 fixp
->fx_r_type
= (fixp
->fx_tcbit
15551 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15552 : BFD_RELOC_X86_64_GOTPCRELX
);
15555 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15560 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15562 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15564 fixp
->fx_subsy
= 0;
15567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15570 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15571 to section. Since PLT32 relocation must be against symbols,
15572 turn such PLT32 relocation into PC32 relocation. */
15574 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15575 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15576 && symbol_section_p (fixp
->fx_addsy
))
15577 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15580 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15581 && fixp
->fx_tcbit2
)
15582 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15591 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15594 bfd_reloc_code_real_type code
;
15596 switch (fixp
->fx_r_type
)
15598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15601 case BFD_RELOC_SIZE32
:
15602 case BFD_RELOC_SIZE64
:
15604 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15605 && (!fixp
->fx_subsy
15606 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15607 sym
= fixp
->fx_addsy
;
15608 else if (fixp
->fx_subsy
15609 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15610 && (!fixp
->fx_addsy
15611 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15612 sym
= fixp
->fx_subsy
;
15615 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15617 /* Resolve size relocation against local symbol to size of
15618 the symbol plus addend. */
15619 valueT value
= S_GET_SIZE (sym
);
15621 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15622 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15623 if (sym
== fixp
->fx_subsy
)
15626 if (fixp
->fx_addsy
)
15627 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15629 else if (fixp
->fx_subsy
)
15630 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15631 value
+= fixp
->fx_offset
;
15632 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15634 && !fits_in_unsigned_long (value
))
15635 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15636 _("symbol size computation overflow"));
15637 fixp
->fx_addsy
= NULL
;
15638 fixp
->fx_subsy
= NULL
;
15639 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15642 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15644 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15645 "unsupported expression involving @size");
15649 /* Fall through. */
15651 case BFD_RELOC_X86_64_PLT32
:
15652 case BFD_RELOC_X86_64_GOT32
:
15653 case BFD_RELOC_X86_64_GOTPCREL
:
15654 case BFD_RELOC_X86_64_GOTPCRELX
:
15655 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15656 case BFD_RELOC_386_PLT32
:
15657 case BFD_RELOC_386_GOT32
:
15658 case BFD_RELOC_386_GOT32X
:
15659 case BFD_RELOC_386_GOTOFF
:
15660 case BFD_RELOC_386_GOTPC
:
15661 case BFD_RELOC_386_TLS_GD
:
15662 case BFD_RELOC_386_TLS_LDM
:
15663 case BFD_RELOC_386_TLS_LDO_32
:
15664 case BFD_RELOC_386_TLS_IE_32
:
15665 case BFD_RELOC_386_TLS_IE
:
15666 case BFD_RELOC_386_TLS_GOTIE
:
15667 case BFD_RELOC_386_TLS_LE_32
:
15668 case BFD_RELOC_386_TLS_LE
:
15669 case BFD_RELOC_386_TLS_GOTDESC
:
15670 case BFD_RELOC_386_TLS_DESC_CALL
:
15671 case BFD_RELOC_X86_64_TLSGD
:
15672 case BFD_RELOC_X86_64_TLSLD
:
15673 case BFD_RELOC_X86_64_DTPOFF32
:
15674 case BFD_RELOC_X86_64_DTPOFF64
:
15675 case BFD_RELOC_X86_64_GOTTPOFF
:
15676 case BFD_RELOC_X86_64_TPOFF32
:
15677 case BFD_RELOC_X86_64_TPOFF64
:
15678 case BFD_RELOC_X86_64_GOTOFF64
:
15679 case BFD_RELOC_X86_64_GOTPC32
:
15680 case BFD_RELOC_X86_64_GOT64
:
15681 case BFD_RELOC_X86_64_GOTPCREL64
:
15682 case BFD_RELOC_X86_64_GOTPC64
:
15683 case BFD_RELOC_X86_64_GOTPLT64
:
15684 case BFD_RELOC_X86_64_PLTOFF64
:
15685 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15686 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15687 case BFD_RELOC_RVA
:
15688 case BFD_RELOC_VTABLE_ENTRY
:
15689 case BFD_RELOC_VTABLE_INHERIT
:
15691 case BFD_RELOC_32_SECREL
:
15692 case BFD_RELOC_16_SECIDX
:
15694 code
= fixp
->fx_r_type
;
15696 case BFD_RELOC_X86_64_32S
:
15697 if (!fixp
->fx_pcrel
)
15699 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15700 code
= fixp
->fx_r_type
;
15703 /* Fall through. */
15705 if (fixp
->fx_pcrel
)
15707 switch (fixp
->fx_size
)
15710 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15711 _("can not do %d byte pc-relative relocation"),
15713 code
= BFD_RELOC_32_PCREL
;
15715 case 1: code
= BFD_RELOC_8_PCREL
; break;
15716 case 2: code
= BFD_RELOC_16_PCREL
; break;
15717 case 4: code
= BFD_RELOC_32_PCREL
; break;
15719 case 8: code
= BFD_RELOC_64_PCREL
; break;
15725 switch (fixp
->fx_size
)
15728 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15729 _("can not do %d byte relocation"),
15731 code
= BFD_RELOC_32
;
15733 case 1: code
= BFD_RELOC_8
; break;
15734 case 2: code
= BFD_RELOC_16
; break;
15735 case 4: code
= BFD_RELOC_32
; break;
15737 case 8: code
= BFD_RELOC_64
; break;
15744 if ((code
== BFD_RELOC_32
15745 || code
== BFD_RELOC_32_PCREL
15746 || code
== BFD_RELOC_X86_64_32S
)
15748 && fixp
->fx_addsy
== GOT_symbol
)
15751 code
= BFD_RELOC_386_GOTPC
;
15753 code
= BFD_RELOC_X86_64_GOTPC32
;
15755 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15757 && fixp
->fx_addsy
== GOT_symbol
)
15759 code
= BFD_RELOC_X86_64_GOTPC64
;
15762 rel
= XNEW (arelent
);
15763 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15764 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15766 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15768 if (!use_rela_relocations
)
15770 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15771 vtable entry to be used in the relocation's section offset. */
15772 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15773 rel
->address
= fixp
->fx_offset
;
15774 #if defined (OBJ_COFF) && defined (TE_PE)
15775 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15776 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15781 /* Use the rela in 64bit mode. */
15784 if (disallow_64bit_reloc
)
15787 case BFD_RELOC_X86_64_DTPOFF64
:
15788 case BFD_RELOC_X86_64_TPOFF64
:
15789 case BFD_RELOC_64_PCREL
:
15790 case BFD_RELOC_X86_64_GOTOFF64
:
15791 case BFD_RELOC_X86_64_GOT64
:
15792 case BFD_RELOC_X86_64_GOTPCREL64
:
15793 case BFD_RELOC_X86_64_GOTPC64
:
15794 case BFD_RELOC_X86_64_GOTPLT64
:
15795 case BFD_RELOC_X86_64_PLTOFF64
:
15796 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15797 _("cannot represent relocation type %s in x32 mode"),
15798 bfd_get_reloc_code_name (code
));
15804 if (!fixp
->fx_pcrel
)
15805 rel
->addend
= fixp
->fx_offset
;
15809 case BFD_RELOC_X86_64_PLT32
:
15810 case BFD_RELOC_X86_64_GOT32
:
15811 case BFD_RELOC_X86_64_GOTPCREL
:
15812 case BFD_RELOC_X86_64_GOTPCRELX
:
15813 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15814 case BFD_RELOC_X86_64_TLSGD
:
15815 case BFD_RELOC_X86_64_TLSLD
:
15816 case BFD_RELOC_X86_64_GOTTPOFF
:
15817 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15818 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15819 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15822 rel
->addend
= (section
->vma
15824 + fixp
->fx_addnumber
15825 + md_pcrel_from (fixp
));
15830 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15831 if (rel
->howto
== NULL
)
15833 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15834 _("cannot represent relocation type %s"),
15835 bfd_get_reloc_code_name (code
));
15836 /* Set howto to a garbage value so that we can keep going. */
15837 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15838 gas_assert (rel
->howto
!= NULL
);
15844 #include "tc-i386-intel.c"
15847 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15849 int saved_naked_reg
;
15850 char saved_register_dot
;
15852 saved_naked_reg
= allow_naked_reg
;
15853 allow_naked_reg
= 1;
15854 saved_register_dot
= register_chars
['.'];
15855 register_chars
['.'] = '.';
15856 allow_pseudo_reg
= 1;
15857 expression_and_evaluate (exp
);
15858 allow_pseudo_reg
= 0;
15859 register_chars
['.'] = saved_register_dot
;
15860 allow_naked_reg
= saved_naked_reg
;
15862 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15864 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15866 exp
->X_op
= O_constant
;
15867 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15868 .dw2_regnum
[flag_code
>> 1];
15871 exp
->X_op
= O_illegal
;
15876 tc_x86_frame_initial_instructions (void)
15878 static unsigned int sp_regno
[2];
15880 if (!sp_regno
[flag_code
>> 1])
15882 char *saved_input
= input_line_pointer
;
15883 char sp
[][4] = {"esp", "rsp"};
15886 input_line_pointer
= sp
[flag_code
>> 1];
15887 tc_x86_parse_to_dw2regnum (&exp
);
15888 gas_assert (exp
.X_op
== O_constant
);
15889 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15890 input_line_pointer
= saved_input
;
15893 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15894 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15898 x86_dwarf2_addr_size (void)
15900 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15901 if (x86_elf_abi
== X86_64_X32_ABI
)
15904 return bfd_arch_bits_per_address (stdoutput
) / 8;
15908 i386_elf_section_type (const char *str
, size_t len
)
15910 if (flag_code
== CODE_64BIT
15911 && len
== sizeof ("unwind") - 1
15912 && startswith (str
, "unwind"))
15913 return SHT_X86_64_UNWIND
;
15920 i386_solaris_fix_up_eh_frame (segT sec
)
15922 if (flag_code
== CODE_64BIT
)
15923 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15929 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15933 exp
.X_op
= O_secrel
;
15934 exp
.X_add_symbol
= symbol
;
15935 exp
.X_add_number
= 0;
15936 emit_expr (&exp
, size
);
15940 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15941 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15944 x86_64_section_letter (int letter
, const char **ptr_msg
)
15946 if (flag_code
== CODE_64BIT
)
15949 return SHF_X86_64_LARGE
;
15951 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15954 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15959 handle_large_common (int small ATTRIBUTE_UNUSED
)
15961 if (flag_code
!= CODE_64BIT
)
15963 s_comm_internal (0, elf_common_parse
);
15964 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15968 static segT lbss_section
;
15969 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15970 asection
*saved_bss_section
= bss_section
;
15972 if (lbss_section
== NULL
)
15974 flagword applicable
;
15975 segT seg
= now_seg
;
15976 subsegT subseg
= now_subseg
;
15978 /* The .lbss section is for local .largecomm symbols. */
15979 lbss_section
= subseg_new (".lbss", 0);
15980 applicable
= bfd_applicable_section_flags (stdoutput
);
15981 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15982 seg_info (lbss_section
)->bss
= 1;
15984 subseg_set (seg
, subseg
);
15987 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15988 bss_section
= lbss_section
;
15990 s_comm_internal (0, elf_common_parse
);
15992 elf_com_section_ptr
= saved_com_section_ptr
;
15993 bss_section
= saved_bss_section
;
15996 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */