1 /* Verify that overloaded built-ins for vec_insert() with int
2 inputs produce the right codegen. Power8 variant. */
4 /* { dg-do compile } */
5 /* { dg-require-effective-target powerpc_p8vector_ok } */
6 /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
11 testbi_var(unsigned int x
, vector
bool int v
, signed int i
)
13 return vec_insert(x
, v
, i
);
16 testsi_var(signed int x
, vector
signed int v
, signed int i
)
18 return vec_insert(x
, v
, i
);
21 testui1_var(signed int x
, vector
unsigned int v
, signed int i
)
23 return vec_insert(x
, v
, i
);
26 testui2_var(unsigned int x
, vector
unsigned int v
, signed int i
)
28 return vec_insert(x
, v
, i
);
31 testbi_cst(unsigned int x
, vector
bool int v
)
33 return vec_insert(x
, v
, 12);
36 testsi_cst(signed int x
, vector
signed int v
)
38 return vec_insert(x
, v
, 12);
41 testui1_cst(signed int x
, vector
unsigned int v
)
43 return vec_insert(x
, v
, 12);
46 testui2_cst(unsigned int x
, vector
unsigned int v
)
48 return vec_insert(x
, v
, 12);
51 /* Each test has lvx (8). cst tests have additional lvewx. (4) */
52 /* var tests have no stwx and stvx. cst tests have stw (4).*/
53 /* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 } } */
54 /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target le } } } */
55 /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target be } } } */
57 /* { dg-final { scan-assembler-times {\mlvewx\M} 4 } } */
58 /* { dg-final { scan-assembler-times {\mvperm\M} 12 } } */