1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2023 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 frame_info_ptr
, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (_("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
440 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
442 else if (ELF_ST_IS_MIPS16 (st_other
))
444 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
445 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
446 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
450 /* Return one iff MSYM refers to standard ISA code. */
453 msymbol_is_mips (struct minimal_symbol
*msym
)
455 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
456 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
459 /* Return one iff MSYM refers to MIPS16 code. */
462 msymbol_is_mips16 (struct minimal_symbol
*msym
)
464 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
467 /* Return one iff MSYM refers to microMIPS code. */
470 msymbol_is_micromips (struct minimal_symbol
*msym
)
472 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
475 /* Set the ISA bit in the main symbol too, complementing the corresponding
476 minimal symbol setting and reflecting the run-time value of the symbol.
477 The need for comes from the ISA bit having been cleared as code in
478 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
479 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
480 of symbols referring to compressed code different in GDB to the values
481 used by actual code. That in turn makes them evaluate incorrectly in
482 expressions, producing results different to what the same expressions
483 yield when compiled into the program being debugged. */
486 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
488 if (sym
->aclass () == LOC_BLOCK
)
490 /* We are in symbol reading so it is OK to cast away constness. */
491 struct block
*block
= (struct block
*) sym
->value_block ();
492 CORE_ADDR compact_block_start
;
493 struct bound_minimal_symbol msym
;
495 compact_block_start
= block
->start () | 1;
496 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
497 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
499 block
->set_start (compact_block_start
);
504 /* XFER a value from the big/little/left end of the register.
505 Depending on the size of the value it might occupy the entire
506 register or just part of it. Make an allowance for this, aligning
507 things accordingly. */
510 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
511 int reg_num
, int length
,
512 enum bfd_endian endian
, gdb_byte
*in
,
513 const gdb_byte
*out
, int buf_offset
)
517 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
518 /* Need to transfer the left or right part of the register, based on
519 the targets byte order. */
523 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
525 case BFD_ENDIAN_LITTLE
:
528 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
532 internal_error (_("bad switch"));
535 gdb_printf (gdb_stderr
,
536 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
537 reg_num
, reg_offset
, buf_offset
, length
);
538 if (mips_debug
&& out
!= NULL
)
541 gdb_printf (gdb_stdlog
, "out ");
542 for (i
= 0; i
< length
; i
++)
543 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
546 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
548 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
549 if (mips_debug
&& in
!= NULL
)
552 gdb_printf (gdb_stdlog
, "in ");
553 for (i
= 0; i
< length
; i
++)
554 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
557 gdb_printf (gdb_stdlog
, "\n");
560 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
561 compatiblity mode. A return value of 1 means that we have
562 physical 64-bit registers, but should treat them as 32-bit registers. */
565 mips2_fp_compat (frame_info_ptr frame
)
567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
568 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
570 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
574 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
575 in all the places we deal with FP registers. PR gdb/413. */
576 /* Otherwise check the FR bit in the status register - it controls
577 the FP compatiblity mode. If it is clear we are in compatibility
579 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
586 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
588 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
590 /* The list of available "set mips " and "show mips " commands. */
592 static struct cmd_list_element
*setmipscmdlist
= NULL
;
593 static struct cmd_list_element
*showmipscmdlist
= NULL
;
595 /* Integer registers 0 thru 31 are handled explicitly by
596 mips_register_name(). Processor specific registers 32 and above
597 are listed in the following tables. */
600 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
604 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
613 /* Names of tx39 registers. */
615 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
616 "sr", "lo", "hi", "bad", "cause", "pc",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
619 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
622 "", "", "", "", "", "", "", "",
623 "", "", "config", "cache", "debug", "depc", "epc",
626 /* Names of registers with Linux kernels. */
627 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
628 "sr", "lo", "hi", "bad", "cause", "pc",
629 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
630 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
631 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
632 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
637 /* Return the name of the register corresponding to REGNO. */
639 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
641 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
642 /* GPR names for all ABIs other than n32/n64. */
643 static const char *mips_gpr_names
[] = {
644 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
645 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
646 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
647 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
650 /* GPR names for n32 and n64 ABIs. */
651 static const char *mips_n32_n64_gpr_names
[] = {
652 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
653 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
654 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
655 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
658 enum mips_abi abi
= mips_abi (gdbarch
);
660 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
661 but then don't make the raw register names visible. This (upper)
662 range of user visible register numbers are the pseudo-registers.
664 This approach was adopted accommodate the following scenario:
665 It is possible to debug a 64-bit device using a 32-bit
666 programming model. In such instances, the raw registers are
667 configured to be 64-bits wide, while the pseudo registers are
668 configured to be 32-bits wide. The registers that the user
669 sees - the pseudo registers - match the users expectations
670 given the programming model being used. */
671 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
672 if (regno
< gdbarch_num_regs (gdbarch
))
675 /* The MIPS integer registers are always mapped from 0 to 31. The
676 names of the registers (which reflects the conventions regarding
677 register use) vary depending on the ABI. */
678 if (0 <= rawnum
&& rawnum
< 32)
680 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
681 return mips_n32_n64_gpr_names
[rawnum
];
683 return mips_gpr_names
[rawnum
];
685 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
686 return tdesc_register_name (gdbarch
, rawnum
);
687 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
689 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
690 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
691 return tdep
->mips_processor_reg_names
[rawnum
- 32];
695 internal_error (_("mips_register_name: bad register number %d"), rawnum
);
698 /* Return the groups that a MIPS register can be categorised into. */
701 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
702 const struct reggroup
*reggroup
)
707 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
708 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
709 if (reggroup
== all_reggroup
)
711 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
712 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
713 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
714 (gdbarch), as not all architectures are multi-arch. */
715 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
716 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (_("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (_("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (_("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& type
->length () == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && type
->length () < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (frame_info_ptr frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= type
->length ();
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (_("mips_register_to_value: unrecognized case"));
986 mips_value_to_register (frame_info_ptr frame
, int regnum
,
987 struct type
*type
, const gdb_byte
*from
)
989 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
991 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
993 put_frame_register (frame
, regnum
+ 0, from
+ 4);
994 put_frame_register (frame
, regnum
+ 1, from
+ 0);
996 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
999 size_t len
= type
->length ();
1001 /* Sign extend values, irrespective of type, that are stored to
1002 a 64-bit general purpose register. (32-bit unsigned values
1003 are stored as signed quantities within a 64-bit register.
1004 When performing an operation, in compiled code, that combines
1005 a 32-bit unsigned value with a signed 64-bit value, a type
1006 conversion is first performed that zeroes out the high 32 bits.) */
1007 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1010 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1012 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1013 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1014 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1018 if (from
[len
-1] & 0x80)
1019 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1021 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1022 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1023 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1028 internal_error (_("mips_value_to_register: unrecognized case"));
1032 /* Return the GDB type object for the "standard" data type of data in
1035 static struct type
*
1036 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1038 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1039 if (mips_float_register_p (gdbarch
, regnum
))
1041 /* The floating-point registers raw, or cooked, always match
1042 mips_isa_regsize(), and also map 1:1, byte for byte. */
1043 if (mips_isa_regsize (gdbarch
) == 4)
1044 return builtin_type (gdbarch
)->builtin_float
;
1046 return builtin_type (gdbarch
)->builtin_double
;
1048 else if (regnum
< gdbarch_num_regs (gdbarch
))
1050 /* The raw or ISA registers. These are all sized according to
1052 if (mips_isa_regsize (gdbarch
) == 4)
1053 return builtin_type (gdbarch
)->builtin_int32
;
1055 return builtin_type (gdbarch
)->builtin_int64
;
1059 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1060 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1062 /* The cooked or ABI registers. These are sized according to
1063 the ABI (with a few complications). */
1064 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1065 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1066 return builtin_type (gdbarch
)->builtin_int32
;
1067 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1068 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1069 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1070 /* The pseudo/cooked view of the embedded registers is always
1071 32-bit. The raw view is handled below. */
1072 return builtin_type (gdbarch
)->builtin_int32
;
1073 else if (tdep
->mips64_transfers_32bit_regs_p
)
1074 /* The target, while possibly using a 64-bit register buffer,
1075 is only transfering 32-bits of each integer register.
1076 Reflect this in the cooked/pseudo (ABI) register value. */
1077 return builtin_type (gdbarch
)->builtin_int32
;
1078 else if (mips_abi_regsize (gdbarch
) == 4)
1079 /* The ABI is restricted to 32-bit registers (the ISA could be
1081 return builtin_type (gdbarch
)->builtin_int32
;
1084 return builtin_type (gdbarch
)->builtin_int64
;
1088 /* Return the GDB type for the pseudo register REGNUM, which is the
1089 ABI-level view. This function is only called if there is a target
1090 description which includes registers, so we know precisely the
1091 types of hardware registers. */
1093 static struct type
*
1094 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1096 const int num_regs
= gdbarch_num_regs (gdbarch
);
1097 int rawnum
= regnum
% num_regs
;
1098 struct type
*rawtype
;
1100 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1102 /* Absent registers are still absent. */
1103 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1104 if (rawtype
->length () == 0)
1107 /* Present the floating point registers however the hardware did;
1108 do not try to convert between FPU layouts. */
1109 if (mips_float_register_p (gdbarch
, rawnum
))
1112 /* Floating-point control registers are always 32-bit even though for
1113 backwards compatibility reasons 64-bit targets will transfer them
1114 as 64-bit quantities even if using XML descriptions. */
1115 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1116 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1117 return builtin_type (gdbarch
)->builtin_int32
;
1119 /* Use pointer types for registers if we can. For n32 we can not,
1120 since we do not have a 64-bit pointer type. */
1121 if (mips_abi_regsize (gdbarch
)
1122 == builtin_type (gdbarch
)->builtin_data_ptr
->length())
1124 if (rawnum
== MIPS_SP_REGNUM
1125 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1126 return builtin_type (gdbarch
)->builtin_data_ptr
;
1127 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1128 return builtin_type (gdbarch
)->builtin_func_ptr
;
1131 if (mips_abi_regsize (gdbarch
) == 4 && rawtype
->length () == 8
1132 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1133 || rawnum
== mips_regnum (gdbarch
)->lo
1134 || rawnum
== mips_regnum (gdbarch
)->hi
1135 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1136 || rawnum
== mips_regnum (gdbarch
)->cause
1137 || rawnum
== mips_regnum (gdbarch
)->pc
1138 || (mips_regnum (gdbarch
)->dspacc
!= -1
1139 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1140 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1141 return builtin_type (gdbarch
)->builtin_int32
;
1143 /* The pseudo/cooked view of embedded registers is always
1144 32-bit, even if the target transfers 64-bit values for them.
1145 New targets relying on XML descriptions should only transfer
1146 the necessary 32 bits, but older versions of GDB expected 64,
1147 so allow the target to provide 64 bits without interfering
1148 with the displayed type. */
1149 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1150 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1151 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1152 return builtin_type (gdbarch
)->builtin_int32
;
1154 /* For all other registers, pass through the hardware type. */
1158 /* Should the upper word of 64-bit addresses be zeroed? */
1159 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1162 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1164 switch (mask_address_var
)
1166 case AUTO_BOOLEAN_TRUE
:
1168 case AUTO_BOOLEAN_FALSE
:
1171 case AUTO_BOOLEAN_AUTO
:
1172 return tdep
->default_mask_address_p
;
1174 internal_error (_("mips_mask_address_p: bad switch"));
1180 show_mask_address (struct ui_file
*file
, int from_tty
,
1181 struct cmd_list_element
*c
, const char *value
)
1183 const char *additional_text
= "";
1184 if (mask_address_var
== AUTO_BOOLEAN_AUTO
)
1186 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
1188 additional_text
= _(" (current architecture is not MIPS)");
1191 mips_gdbarch_tdep
*tdep
1192 = gdbarch_tdep
<mips_gdbarch_tdep
> (current_inferior ()->arch ());
1194 if (mips_mask_address_p (tdep
))
1195 additional_text
= _(" (currently \"on\")");
1197 additional_text
= _(" (currently \"off\")");
1201 gdb_printf (file
, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
1202 value
, additional_text
);
1205 /* Tell if the program counter value in MEMADDR is in a standard ISA
1209 mips_pc_is_mips (CORE_ADDR memaddr
)
1211 struct bound_minimal_symbol sym
;
1213 /* Flags indicating that this is a MIPS16 or microMIPS function is
1214 stored by elfread.c in the high bit of the info field. Use this
1215 to decide if the function is standard MIPS. Otherwise if bit 0
1216 of the address is clear, then this is a standard MIPS function. */
1217 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1219 return msymbol_is_mips (sym
.minsym
);
1221 return is_mips_addr (memaddr
);
1224 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1227 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1229 struct bound_minimal_symbol sym
;
1231 /* A flag indicating that this is a MIPS16 function is stored by
1232 elfread.c in the high bit of the info field. Use this to decide
1233 if the function is MIPS16. Otherwise if bit 0 of the address is
1234 set, then ELF file flags will tell if this is a MIPS16 function. */
1235 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1237 return msymbol_is_mips16 (sym
.minsym
);
1239 return is_mips16_addr (gdbarch
, memaddr
);
1242 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1245 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1247 struct bound_minimal_symbol sym
;
1249 /* A flag indicating that this is a microMIPS function is stored by
1250 elfread.c in the high bit of the info field. Use this to decide
1251 if the function is microMIPS. Otherwise if bit 0 of the address
1252 is set, then ELF file flags will tell if this is a microMIPS
1254 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1256 return msymbol_is_micromips (sym
.minsym
);
1258 return is_micromips_addr (gdbarch
, memaddr
);
1261 /* Tell the ISA type of the function the program counter value in MEMADDR
1264 static enum mips_isa
1265 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1267 struct bound_minimal_symbol sym
;
1269 /* A flag indicating that this is a MIPS16 or a microMIPS function
1270 is stored by elfread.c in the high bit of the info field. Use
1271 this to decide if the function is MIPS16 or microMIPS or normal
1272 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1273 flags will tell if this is a MIPS16 or a microMIPS function. */
1274 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1277 if (msymbol_is_micromips (sym
.minsym
))
1278 return ISA_MICROMIPS
;
1279 else if (msymbol_is_mips16 (sym
.minsym
))
1286 if (is_mips_addr (memaddr
))
1288 else if (is_micromips_addr (gdbarch
, memaddr
))
1289 return ISA_MICROMIPS
;
1295 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1296 The need for comes from the ISA bit having been cleared, making
1297 addresses in FDE, range records, etc. referring to compressed code
1298 different to those in line information, the symbol table and finally
1299 the PC register. That in turn confuses many operations. */
1302 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1304 pc
= unmake_compact_addr (pc
);
1305 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1308 /* Recalculate the line record requested so that the resulting PC has
1309 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1310 this adjustment comes from some records associated with compressed
1311 code having the ISA bit cleared, most notably at function prologue
1312 ends. The ISA bit is in this context retrieved from the minimal
1313 symbol covering the address requested, which in turn has been
1314 constructed from the binary's symbol table rather than DWARF-2
1315 information. The correct setting of the ISA bit is required for
1316 breakpoint addresses to correctly match against the stop PC.
1318 As line entries can specify relative address adjustments we need to
1319 keep track of the absolute value of the last line address recorded
1320 in line information, so that we can calculate the actual address to
1321 apply the ISA bit adjustment to. We use PC for this tracking and
1322 keep the original address there.
1324 As such relative address adjustments can be odd within compressed
1325 code we need to keep track of the last line address with the ISA
1326 bit adjustment applied too, as the original address may or may not
1327 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1328 the adjusted address there.
1330 For relative address adjustments we then use these variables to
1331 calculate the address intended by line information, which will be
1332 PC-relative, and return an updated adjustment carrying ISA bit
1333 information, which will be ADJ_PC-relative. For absolute address
1334 adjustments we just return the same address that we store in ADJ_PC
1337 As the first line entry can be relative to an implied address value
1338 of 0 we need to have the initial address set up that we store in PC
1339 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1340 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1343 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1345 static CORE_ADDR adj_pc
;
1346 static CORE_ADDR pc
;
1349 pc
= rel
? pc
+ addr
: addr
;
1350 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1351 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1356 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1358 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1359 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1360 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1361 static const char mips_str_call_stub
[] = "__call_stub_";
1362 static const char mips_str_fn_stub
[] = "__fn_stub_";
1364 /* This is used as a PIC thunk prefix. */
1366 static const char mips_str_pic
[] = ".pic.";
1368 /* Return non-zero if the PC is inside a call thunk (aka stub or
1369 trampoline) that should be treated as a temporary frame. */
1372 mips_in_frame_stub (CORE_ADDR pc
)
1374 CORE_ADDR start_addr
;
1377 /* Find the starting address of the function containing the PC. */
1378 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1381 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1382 if (startswith (name
, mips_str_mips16_call_stub
))
1384 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1385 if (startswith (name
, mips_str_call_stub
))
1387 /* If the PC is in __fn_stub_*, this is a call stub. */
1388 if (startswith (name
, mips_str_fn_stub
))
1391 return 0; /* Not a stub. */
1394 /* MIPS believes that the PC has a sign extended value. Perhaps the
1395 all registers should be sign extended for simplicity? */
1398 mips_read_pc (readable_regcache
*regcache
)
1400 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1403 regcache
->cooked_read (regnum
, &pc
);
1408 mips_unwind_pc (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1412 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1413 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1414 intermediate frames. In this case we can get the caller's address
1415 from $ra, or if $ra contains an address within a thunk as well, then
1416 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1417 and thus the caller's address is in $s2. */
1418 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1420 pc
= frame_unwind_register_signed
1421 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1422 if (mips_in_frame_stub (pc
))
1423 pc
= frame_unwind_register_signed
1424 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1430 mips_unwind_sp (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1432 return frame_unwind_register_signed
1433 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1436 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1437 dummy frame. The frame ID's base needs to match the TOS value
1438 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1441 static struct frame_id
1442 mips_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
1444 return frame_id_build
1445 (get_frame_register_signed (this_frame
,
1446 gdbarch_num_regs (gdbarch
)
1448 get_frame_pc (this_frame
));
1451 /* Implement the "write_pc" gdbarch method. */
1454 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1456 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1458 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1461 /* Fetch and return instruction from the specified location. Handle
1462 MIPS16/microMIPS as appropriate. */
1465 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1466 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1468 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1469 gdb_byte buf
[MIPS_INSN32_SIZE
];
1477 instlen
= MIPS_INSN16_SIZE
;
1478 addr
= unmake_compact_addr (addr
);
1481 instlen
= MIPS_INSN32_SIZE
;
1484 internal_error (_("invalid ISA"));
1487 err
= target_read_memory (addr
, buf
, instlen
);
1493 memory_error (TARGET_XFER_E_IO
, addr
);
1496 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1499 /* These are the fields of 32 bit mips instructions. */
1500 #define mips32_op(x) (x >> 26)
1501 #define itype_op(x) (x >> 26)
1502 #define itype_rs(x) ((x >> 21) & 0x1f)
1503 #define itype_rt(x) ((x >> 16) & 0x1f)
1504 #define itype_immediate(x) (x & 0xffff)
1506 #define jtype_op(x) (x >> 26)
1507 #define jtype_target(x) (x & 0x03ffffff)
1509 #define rtype_op(x) (x >> 26)
1510 #define rtype_rs(x) ((x >> 21) & 0x1f)
1511 #define rtype_rt(x) ((x >> 16) & 0x1f)
1512 #define rtype_rd(x) ((x >> 11) & 0x1f)
1513 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1514 #define rtype_funct(x) (x & 0x3f)
1516 /* MicroMIPS instruction fields. */
1517 #define micromips_op(x) ((x) >> 10)
1519 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1520 bit and the size respectively of the field extracted. */
1521 #define b0s4_imm(x) ((x) & 0xf)
1522 #define b0s5_imm(x) ((x) & 0x1f)
1523 #define b0s5_reg(x) ((x) & 0x1f)
1524 #define b0s7_imm(x) ((x) & 0x7f)
1525 #define b0s10_imm(x) ((x) & 0x3ff)
1526 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1527 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1528 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1529 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1530 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1531 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1532 #define b6s4_op(x) (((x) >> 6) & 0xf)
1533 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1535 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1536 respectively of the field extracted. */
1537 #define b0s6_op(x) ((x) & 0x3f)
1538 #define b0s11_op(x) ((x) & 0x7ff)
1539 #define b0s12_imm(x) ((x) & 0xfff)
1540 #define b0s16_imm(x) ((x) & 0xffff)
1541 #define b0s26_imm(x) ((x) & 0x3ffffff)
1542 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1543 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1544 #define b12s4_op(x) (((x) >> 12) & 0xf)
1546 /* Return the size in bytes of the instruction INSN encoded in the ISA
1550 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1555 if ((micromips_op (insn
) & 0x4) == 0x4
1556 || (micromips_op (insn
) & 0x7) == 0x0)
1557 return 2 * MIPS_INSN16_SIZE
;
1559 return MIPS_INSN16_SIZE
;
1561 if ((insn
& 0xf800) == 0xf000)
1562 return 2 * MIPS_INSN16_SIZE
;
1564 return MIPS_INSN16_SIZE
;
1566 return MIPS_INSN32_SIZE
;
1568 internal_error (_("invalid ISA"));
1572 mips32_relative_offset (ULONGEST inst
)
1574 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1577 /* Determine the address of the next instruction executed after the INST
1578 floating condition branch instruction at PC. COUNT specifies the
1579 number of the floating condition bits tested by the branch. */
1582 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1583 ULONGEST inst
, CORE_ADDR pc
, int count
)
1585 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1586 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1587 int tf
= itype_rt (inst
) & 1;
1588 int mask
= (1 << count
) - 1;
1593 /* No way to handle; it'll most likely trap anyway. */
1596 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1597 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1599 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1600 pc
+= mips32_relative_offset (inst
);
1607 /* Return nonzero if the gdbarch is an Octeon series. */
1610 is_octeon (struct gdbarch
*gdbarch
)
1612 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1614 return (info
->mach
== bfd_mach_mips_octeon
1615 || info
->mach
== bfd_mach_mips_octeonp
1616 || info
->mach
== bfd_mach_mips_octeon2
);
1619 /* Return true if the OP represents the Octeon's BBIT instruction. */
1622 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1624 if (!is_octeon (gdbarch
))
1626 /* BBIT0 is encoded as LWC2: 110 010. */
1627 /* BBIT032 is encoded as LDC2: 110 110. */
1628 /* BBIT1 is encoded as SWC2: 111 010. */
1629 /* BBIT132 is encoded as SDC2: 111 110. */
1630 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1636 /* Determine where to set a single step breakpoint while considering
1637 branch prediction. */
1640 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1642 struct gdbarch
*gdbarch
= regcache
->arch ();
1645 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1646 op
= itype_op (inst
);
1647 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1651 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1662 goto greater_branch
;
1667 else if (op
== 17 && itype_rs (inst
) == 8)
1668 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1669 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1670 else if (op
== 17 && itype_rs (inst
) == 9
1671 && (itype_rt (inst
) & 2) == 0)
1672 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1673 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1674 else if (op
== 17 && itype_rs (inst
) == 10
1675 && (itype_rt (inst
) & 2) == 0)
1676 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1677 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1680 /* The new PC will be alternate mode. */
1684 reg
= jtype_target (inst
) << 2;
1685 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1686 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1688 else if (is_octeon_bbit_op (op
, gdbarch
))
1692 branch_if
= op
== 58 || op
== 62;
1693 bit
= itype_rt (inst
);
1695 /* Take into account the *32 instructions. */
1696 if (op
== 54 || op
== 62)
1699 if (((regcache_raw_get_signed (regcache
,
1700 itype_rs (inst
)) >> bit
) & 1)
1702 pc
+= mips32_relative_offset (inst
) + 4;
1704 pc
+= 8; /* After the delay slot. */
1708 pc
+= 4; /* Not a branch, next instruction is easy. */
1711 { /* This gets way messy. */
1713 /* Further subdivide into SPECIAL, REGIMM and other. */
1714 switch (op
& 0x07) /* Extract bits 28,27,26. */
1716 case 0: /* SPECIAL */
1717 op
= rtype_funct (inst
);
1722 /* Set PC to that address. */
1723 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1725 case 12: /* SYSCALL */
1727 mips_gdbarch_tdep
*tdep
1728 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1730 if (tdep
->syscall_next_pc
!= NULL
)
1731 pc
= tdep
->syscall_next_pc (get_current_frame ());
1740 break; /* end SPECIAL */
1741 case 1: /* REGIMM */
1743 op
= itype_rt (inst
); /* branch condition */
1748 case 16: /* BLTZAL */
1749 case 18: /* BLTZALL */
1751 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1752 pc
+= mips32_relative_offset (inst
) + 4;
1754 pc
+= 8; /* after the delay slot */
1758 case 17: /* BGEZAL */
1759 case 19: /* BGEZALL */
1760 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1761 pc
+= mips32_relative_offset (inst
) + 4;
1763 pc
+= 8; /* after the delay slot */
1765 case 0x1c: /* BPOSGE32 */
1766 case 0x1e: /* BPOSGE64 */
1768 if (itype_rs (inst
) == 0)
1770 unsigned int pos
= (op
& 2) ? 64 : 32;
1771 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1774 /* No way to handle; it'll most likely trap anyway. */
1777 if ((regcache_raw_get_unsigned (regcache
,
1778 dspctl
) & 0x7f) >= pos
)
1779 pc
+= mips32_relative_offset (inst
);
1784 /* All of the other instructions in the REGIMM category */
1789 break; /* end REGIMM */
1794 reg
= jtype_target (inst
) << 2;
1795 /* Upper four bits get never changed... */
1796 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1799 case 4: /* BEQ, BEQL */
1801 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1802 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1803 pc
+= mips32_relative_offset (inst
) + 4;
1807 case 5: /* BNE, BNEL */
1809 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1810 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1811 pc
+= mips32_relative_offset (inst
) + 4;
1815 case 6: /* BLEZ, BLEZL */
1816 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1817 pc
+= mips32_relative_offset (inst
) + 4;
1823 greater_branch
: /* BGTZ, BGTZL */
1824 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1825 pc
+= mips32_relative_offset (inst
) + 4;
1832 } /* mips32_next_pc */
1834 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1838 micromips_relative_offset7 (ULONGEST insn
)
1840 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1843 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1847 micromips_relative_offset10 (ULONGEST insn
)
1849 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1852 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1856 micromips_relative_offset16 (ULONGEST insn
)
1858 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1861 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1864 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1868 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1869 return mips_insn_size (ISA_MICROMIPS
, insn
);
1872 /* Calculate the address of the next microMIPS instruction to execute
1873 after the INSN coprocessor 1 conditional branch instruction at the
1874 address PC. COUNT denotes the number of coprocessor condition bits
1875 examined by the branch. */
1878 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1879 ULONGEST insn
, CORE_ADDR pc
, int count
)
1881 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1882 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1883 int tf
= b5s5_op (insn
>> 16) & 1;
1884 int mask
= (1 << count
) - 1;
1889 /* No way to handle; it'll most likely trap anyway. */
1892 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1893 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1895 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1896 pc
+= micromips_relative_offset16 (insn
);
1898 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1903 /* Calculate the address of the next microMIPS instruction to execute
1904 after the instruction at the address PC. */
1907 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1909 struct gdbarch
*gdbarch
= regcache
->arch ();
1912 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1913 pc
+= MIPS_INSN16_SIZE
;
1914 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1916 /* 32-bit instructions. */
1917 case 2 * MIPS_INSN16_SIZE
:
1919 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1920 pc
+= MIPS_INSN16_SIZE
;
1921 switch (micromips_op (insn
>> 16))
1923 case 0x00: /* POOL32A: bits 000000 */
1924 switch (b0s6_op (insn
))
1926 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1927 switch (b6s10_ext (insn
))
1929 case 0x3c: /* JALR: 000000 0000111100 111100 */
1930 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1931 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1932 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1933 pc
= regcache_raw_get_signed (regcache
,
1934 b0s5_reg (insn
>> 16));
1936 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1938 mips_gdbarch_tdep
*tdep
1939 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1941 if (tdep
->syscall_next_pc
!= NULL
)
1942 pc
= tdep
->syscall_next_pc (get_current_frame ());
1950 case 0x10: /* POOL32I: bits 010000 */
1951 switch (b5s5_op (insn
>> 16))
1953 case 0x00: /* BLTZ: bits 010000 00000 */
1954 case 0x01: /* BLTZAL: bits 010000 00001 */
1955 case 0x11: /* BLTZALS: bits 010000 10001 */
1956 if (regcache_raw_get_signed (regcache
,
1957 b0s5_reg (insn
>> 16)) < 0)
1958 pc
+= micromips_relative_offset16 (insn
);
1960 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1963 case 0x02: /* BGEZ: bits 010000 00010 */
1964 case 0x03: /* BGEZAL: bits 010000 00011 */
1965 case 0x13: /* BGEZALS: bits 010000 10011 */
1966 if (regcache_raw_get_signed (regcache
,
1967 b0s5_reg (insn
>> 16)) >= 0)
1968 pc
+= micromips_relative_offset16 (insn
);
1970 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1973 case 0x04: /* BLEZ: bits 010000 00100 */
1974 if (regcache_raw_get_signed (regcache
,
1975 b0s5_reg (insn
>> 16)) <= 0)
1976 pc
+= micromips_relative_offset16 (insn
);
1978 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1981 case 0x05: /* BNEZC: bits 010000 00101 */
1982 if (regcache_raw_get_signed (regcache
,
1983 b0s5_reg (insn
>> 16)) != 0)
1984 pc
+= micromips_relative_offset16 (insn
);
1987 case 0x06: /* BGTZ: bits 010000 00110 */
1988 if (regcache_raw_get_signed (regcache
,
1989 b0s5_reg (insn
>> 16)) > 0)
1990 pc
+= micromips_relative_offset16 (insn
);
1992 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1995 case 0x07: /* BEQZC: bits 010000 00111 */
1996 if (regcache_raw_get_signed (regcache
,
1997 b0s5_reg (insn
>> 16)) == 0)
1998 pc
+= micromips_relative_offset16 (insn
);
2001 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2002 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2003 if (((insn
>> 16) & 0x3) == 0x0)
2004 /* BC2F, BC2T: don't know how to handle these. */
2008 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2009 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2011 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2012 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2015 /* No way to handle; it'll most likely trap anyway. */
2018 if ((regcache_raw_get_unsigned (regcache
,
2019 dspctl
) & 0x7f) >= pos
)
2020 pc
+= micromips_relative_offset16 (insn
);
2022 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2026 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2027 /* BC1ANY2F: bits 010000 11100 xxx01 */
2028 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2029 /* BC1ANY2T: bits 010000 11101 xxx01 */
2030 if (((insn
>> 16) & 0x2) == 0x0)
2031 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2032 ((insn
>> 16) & 0x1) + 1);
2035 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2036 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2037 if (((insn
>> 16) & 0x3) == 0x1)
2038 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2043 case 0x1d: /* JALS: bits 011101 */
2044 case 0x35: /* J: bits 110101 */
2045 case 0x3d: /* JAL: bits 111101 */
2046 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2049 case 0x25: /* BEQ: bits 100101 */
2050 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2051 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2052 pc
+= micromips_relative_offset16 (insn
);
2054 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2057 case 0x2d: /* BNE: bits 101101 */
2058 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2059 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2060 pc
+= micromips_relative_offset16 (insn
);
2062 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2065 case 0x3c: /* JALX: bits 111100 */
2066 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2071 /* 16-bit instructions. */
2072 case MIPS_INSN16_SIZE
:
2073 switch (micromips_op (insn
))
2075 case 0x11: /* POOL16C: bits 010001 */
2076 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2077 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2078 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2079 else if (b5s5_op (insn
) == 0x18)
2080 /* JRADDIUSP: bits 010001 11000 */
2081 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2084 case 0x23: /* BEQZ16: bits 100011 */
2086 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2088 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2089 pc
+= micromips_relative_offset7 (insn
);
2091 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2095 case 0x2b: /* BNEZ16: bits 101011 */
2097 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2099 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2100 pc
+= micromips_relative_offset7 (insn
);
2102 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2106 case 0x33: /* B16: bits 110011 */
2107 pc
+= micromips_relative_offset10 (insn
);
2116 /* Decoding the next place to set a breakpoint is irregular for the
2117 mips 16 variant, but fortunately, there fewer instructions. We have
2118 to cope ith extensions for 16 bit instructions and a pair of actual
2119 32 bit instructions. We dont want to set a single step instruction
2120 on the extend instruction either. */
2122 /* Lots of mips16 instruction formats */
2123 /* Predicting jumps requires itype,ritype,i8type
2124 and their extensions extItype,extritype,extI8type. */
2125 enum mips16_inst_fmts
2127 itype
, /* 0 immediate 5,10 */
2128 ritype
, /* 1 5,3,8 */
2129 rrtype
, /* 2 5,3,3,5 */
2130 rritype
, /* 3 5,3,3,5 */
2131 rrrtype
, /* 4 5,3,3,3,2 */
2132 rriatype
, /* 5 5,3,3,1,4 */
2133 shifttype
, /* 6 5,3,3,3,2 */
2134 i8type
, /* 7 5,3,8 */
2135 i8movtype
, /* 8 5,3,3,5 */
2136 i8mov32rtype
, /* 9 5,3,5,3 */
2137 i64type
, /* 10 5,3,8 */
2138 ri64type
, /* 11 5,3,3,5 */
2139 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2140 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2141 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2142 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2143 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2144 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2145 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2146 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2147 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2148 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2150 /* I am heaping all the fields of the formats into one structure and
2151 then, only the fields which are involved in instruction extension. */
2155 unsigned int regx
; /* Function in i8 type. */
2160 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2161 for the bits which make up the immediate extension. */
2164 extended_offset (unsigned int extension
)
2168 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2170 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2172 value
|= extension
& 0x1f; /* Extract 4:0. */
2177 /* Only call this function if you know that this is an extendable
2178 instruction. It won't malfunction, but why make excess remote memory
2179 references? If the immediate operands get sign extended or something,
2180 do it after the extension is performed. */
2181 /* FIXME: Every one of these cases needs to worry about sign extension
2182 when the offset is to be used in relative addressing. */
2185 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2187 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2190 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2191 target_read_memory (pc
, buf
, 2);
2192 return extract_unsigned_integer (buf
, 2, byte_order
);
2196 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2197 unsigned int extension
,
2199 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2204 switch (insn_format
)
2211 value
= extended_offset ((extension
<< 16) | inst
);
2212 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2216 value
= inst
& 0x7ff;
2217 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2226 { /* A register identifier and an offset. */
2227 /* Most of the fields are the same as I type but the
2228 immediate value is of a different length. */
2232 value
= extended_offset ((extension
<< 16) | inst
);
2233 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2237 value
= inst
& 0xff; /* 8 bits */
2238 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2241 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2247 unsigned long value
;
2248 unsigned int nexthalf
;
2249 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2250 value
= value
<< 16;
2251 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2252 /* Low bit still set. */
2260 internal_error (_("bad switch"));
2262 upk
->offset
= offset
;
2268 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2269 and having a signed 16-bit OFFSET. */
2272 add_offset_16 (CORE_ADDR pc
, int offset
)
2274 return pc
+ (offset
<< 1) + 2;
2278 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2279 unsigned int extension
, unsigned int insn
)
2281 struct gdbarch
*gdbarch
= regcache
->arch ();
2282 int op
= (insn
>> 11);
2285 case 2: /* Branch */
2287 struct upk_mips16 upk
;
2288 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2289 pc
= add_offset_16 (pc
, upk
.offset
);
2292 case 3: /* JAL , JALX - Watch out, these are 32 bit
2295 struct upk_mips16 upk
;
2296 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2297 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2298 if ((insn
>> 10) & 0x01) /* Exchange mode */
2299 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2306 struct upk_mips16 upk
;
2308 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2309 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2311 pc
= add_offset_16 (pc
, upk
.offset
);
2318 struct upk_mips16 upk
;
2320 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2321 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2323 pc
= add_offset_16 (pc
, upk
.offset
);
2328 case 12: /* I8 Formats btez btnez */
2330 struct upk_mips16 upk
;
2332 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2333 /* upk.regx contains the opcode */
2334 /* Test register is 24 */
2335 reg
= regcache_raw_get_signed (regcache
, 24);
2336 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2337 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2338 pc
= add_offset_16 (pc
, upk
.offset
);
2343 case 29: /* RR Formats JR, JALR, JALR-RA */
2345 struct upk_mips16 upk
;
2346 /* upk.fmt = rrtype; */
2351 upk
.regx
= (insn
>> 8) & 0x07;
2352 upk
.regy
= (insn
>> 5) & 0x07;
2353 if ((upk
.regy
& 1) == 0)
2354 reg
= mips_reg3_to_reg
[upk
.regx
];
2356 reg
= 31; /* Function return instruction. */
2357 pc
= regcache_raw_get_signed (regcache
, reg
);
2364 /* This is an instruction extension. Fetch the real instruction
2365 (which follows the extension) and decode things based on
2369 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2370 fetch_mips_16 (gdbarch
, pc
));
2383 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2385 struct gdbarch
*gdbarch
= regcache
->arch ();
2386 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2387 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2390 /* The mips_next_pc function supports single_step when the remote
2391 target monitor or stub is not developed enough to do a single_step.
2392 It works by decoding the current instruction and predicting where a
2393 branch will go. This isn't hard because all the data is available.
2394 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2396 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2398 struct gdbarch
*gdbarch
= regcache
->arch ();
2400 if (mips_pc_is_mips16 (gdbarch
, pc
))
2401 return mips16_next_pc (regcache
, pc
);
2402 else if (mips_pc_is_micromips (gdbarch
, pc
))
2403 return micromips_next_pc (regcache
, pc
);
2405 return mips32_next_pc (regcache
, pc
);
2408 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2412 mips16_instruction_is_compact_branch (unsigned short insn
)
2414 switch (insn
& 0xf800)
2417 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2419 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2420 case 0x2800: /* BNEZ */
2421 case 0x2000: /* BEQZ */
2422 case 0x1000: /* B */
2429 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2433 micromips_instruction_is_compact_branch (unsigned short insn
)
2435 switch (micromips_op (insn
))
2437 case 0x11: /* POOL16C: bits 010001 */
2438 return (b5s5_op (insn
) == 0x18
2439 /* JRADDIUSP: bits 010001 11000 */
2440 || b5s5_op (insn
) == 0xd);
2441 /* JRC: bits 010011 01101 */
2442 case 0x10: /* POOL32I: bits 010000 */
2443 return (b5s5_op (insn
) & 0x1d) == 0x5;
2444 /* BEQZC/BNEZC: bits 010000 001x1 */
2450 struct mips_frame_cache
2453 trad_frame_saved_reg
*saved_regs
;
2456 /* Set a register's saved stack address in temp_saved_regs. If an
2457 address has already been set for this register, do nothing; this
2458 way we will only recognize the first save of a given register in a
2461 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2462 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2463 Strictly speaking, only the second range is used as it is only second
2464 range (the ABI instead of ISA registers) that comes into play when finding
2465 saved registers in a frame. */
2468 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2469 int regnum
, CORE_ADDR offset
)
2471 if (this_cache
!= NULL
2472 && this_cache
->saved_regs
[regnum
].is_realreg ()
2473 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2475 this_cache
->saved_regs
[regnum
+ 0
2476 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2477 this_cache
->saved_regs
[regnum
+ 1
2478 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2483 /* Fetch the immediate value from a MIPS16 instruction.
2484 If the previous instruction was an EXTEND, use it to extend
2485 the upper bits of the immediate value. This is a helper function
2486 for mips16_scan_prologue. */
2489 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2490 unsigned short inst
, /* current instruction */
2491 int nbits
, /* number of bits in imm field */
2492 int scale
, /* scale factor to be applied to imm */
2493 int is_signed
) /* is the imm field signed? */
2497 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2499 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2500 if (offset
& 0x8000) /* check for negative extend */
2501 offset
= 0 - (0x10000 - (offset
& 0xffff));
2502 return offset
| (inst
& 0x1f);
2506 int max_imm
= 1 << nbits
;
2507 int mask
= max_imm
- 1;
2508 int sign_bit
= max_imm
>> 1;
2510 offset
= inst
& mask
;
2511 if (is_signed
&& (offset
& sign_bit
))
2512 offset
= 0 - (max_imm
- offset
);
2513 return offset
* scale
;
2518 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2519 the associated FRAME_CACHE if not null.
2520 Return the address of the first instruction past the prologue. */
2523 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2524 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2525 frame_info_ptr this_frame
,
2526 struct mips_frame_cache
*this_cache
)
2528 int prev_non_prologue_insn
= 0;
2529 int this_non_prologue_insn
;
2530 int non_prologue_insns
= 0;
2533 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2535 long frame_offset
= 0; /* Size of stack frame. */
2536 long frame_adjust
= 0; /* Offset of FP from SP. */
2537 int frame_reg
= MIPS_SP_REGNUM
;
2538 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2539 unsigned inst
= 0; /* current instruction */
2540 unsigned entry_inst
= 0; /* the entry instruction */
2541 unsigned save_inst
= 0; /* the save instruction */
2542 int prev_delay_slot
= 0;
2546 int extend_bytes
= 0;
2547 int prev_extend_bytes
= 0;
2548 CORE_ADDR end_prologue_addr
;
2550 /* Can be called when there's no process, and hence when there's no
2552 if (this_frame
!= NULL
)
2553 sp
= get_frame_register_signed (this_frame
,
2554 gdbarch_num_regs (gdbarch
)
2559 if (limit_pc
> start_pc
+ 200)
2560 limit_pc
= start_pc
+ 200;
2563 /* Permit at most one non-prologue non-control-transfer instruction
2564 in the middle which may have been reordered by the compiler for
2566 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2568 this_non_prologue_insn
= 0;
2571 /* Save the previous instruction. If it's an EXTEND, we'll extract
2572 the immediate offset extension from it in mips16_get_imm. */
2575 /* Fetch and decode the instruction. */
2576 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2579 /* Normally we ignore extend instructions. However, if it is
2580 not followed by a valid prologue instruction, then this
2581 instruction is not part of the prologue either. We must
2582 remember in this case to adjust the end_prologue_addr back
2584 if ((inst
& 0xf800) == 0xf000) /* extend */
2586 extend_bytes
= MIPS_INSN16_SIZE
;
2590 prev_extend_bytes
= extend_bytes
;
2593 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2594 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2596 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2597 if (offset
< 0) /* Negative stack adjustment? */
2598 frame_offset
-= offset
;
2600 /* Exit loop if a positive stack adjustment is found, which
2601 usually means that the stack cleanup code in the function
2602 epilogue is reached. */
2605 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2607 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2608 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2609 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2611 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2613 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2614 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2615 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2617 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2619 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2620 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2622 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2624 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2625 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2627 else if (inst
== 0x673d) /* move $s1, $sp */
2632 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2634 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2635 frame_addr
= sp
+ offset
;
2637 frame_adjust
= offset
;
2639 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2641 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2642 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2643 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2645 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2647 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2648 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2649 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2651 else if ((inst
& 0xf81f) == 0xe809
2652 && (inst
& 0x700) != 0x700) /* entry */
2653 entry_inst
= inst
; /* Save for later processing. */
2654 else if ((inst
& 0xff80) == 0x6480) /* save */
2656 save_inst
= inst
; /* Save for later processing. */
2657 if (prev_extend_bytes
) /* extend */
2658 save_inst
|= prev_inst
<< 16;
2660 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2662 /* This instruction is part of the prologue, but we don't
2663 need to do anything special to handle it. */
2665 else if (mips16_instruction_has_delay_slot (inst
, 0))
2666 /* JAL/JALR/JALX/JR */
2668 /* The instruction in the delay slot can be a part
2669 of the prologue, so move forward once more. */
2671 if (mips16_instruction_has_delay_slot (inst
, 1))
2674 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2675 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2680 this_non_prologue_insn
= 1;
2683 non_prologue_insns
+= this_non_prologue_insn
;
2685 /* A jump or branch, or enough non-prologue insns seen? If so,
2686 then we must have reached the end of the prologue by now. */
2687 if (prev_delay_slot
|| non_prologue_insns
> 1
2688 || mips16_instruction_is_compact_branch (inst
))
2691 prev_non_prologue_insn
= this_non_prologue_insn
;
2692 prev_delay_slot
= in_delay_slot
;
2693 prev_pc
= cur_pc
- prev_extend_bytes
;
2696 /* The entry instruction is typically the first instruction in a function,
2697 and it stores registers at offsets relative to the value of the old SP
2698 (before the prologue). But the value of the sp parameter to this
2699 function is the new SP (after the prologue has been executed). So we
2700 can't calculate those offsets until we've seen the entire prologue,
2701 and can calculate what the old SP must have been. */
2702 if (entry_inst
!= 0)
2704 int areg_count
= (entry_inst
>> 8) & 7;
2705 int sreg_count
= (entry_inst
>> 6) & 3;
2707 /* The entry instruction always subtracts 32 from the SP. */
2710 /* Now we can calculate what the SP must have been at the
2711 start of the function prologue. */
2714 /* Check if a0-a3 were saved in the caller's argument save area. */
2715 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2717 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2718 offset
+= mips_abi_regsize (gdbarch
);
2721 /* Check if the ra register was pushed on the stack. */
2723 if (entry_inst
& 0x20)
2725 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2726 offset
-= mips_abi_regsize (gdbarch
);
2729 /* Check if the s0 and s1 registers were pushed on the stack. */
2730 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2732 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2733 offset
-= mips_abi_regsize (gdbarch
);
2737 /* The SAVE instruction is similar to ENTRY, except that defined by the
2738 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2739 size of the frame is specified as an immediate field of instruction
2740 and an extended variation exists which lets additional registers and
2741 frame space to be specified. The instruction always treats registers
2742 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2743 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2745 static int args_table
[16] = {
2746 0, 0, 0, 0, 1, 1, 1, 1,
2747 2, 2, 2, 0, 3, 3, 4, -1,
2749 static int astatic_table
[16] = {
2750 0, 1, 2, 3, 0, 1, 2, 3,
2751 0, 1, 2, 4, 0, 1, 0, -1,
2753 int aregs
= (save_inst
>> 16) & 0xf;
2754 int xsregs
= (save_inst
>> 24) & 0x7;
2755 int args
= args_table
[aregs
];
2756 int astatic
= astatic_table
[aregs
];
2761 warning (_("Invalid number of argument registers encoded in SAVE."));
2766 warning (_("Invalid number of static registers encoded in SAVE."));
2770 /* For standard SAVE the frame size of 0 means 128. */
2771 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2772 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2775 frame_offset
+= frame_size
;
2777 /* Now we can calculate what the SP must have been at the
2778 start of the function prologue. */
2781 /* Check if A0-A3 were saved in the caller's argument save area. */
2782 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2784 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2785 offset
+= mips_abi_regsize (gdbarch
);
2790 /* Check if the RA register was pushed on the stack. */
2791 if (save_inst
& 0x40)
2793 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2794 offset
-= mips_abi_regsize (gdbarch
);
2797 /* Check if the S8 register was pushed on the stack. */
2800 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2801 offset
-= mips_abi_regsize (gdbarch
);
2804 /* Check if S2-S7 were pushed on the stack. */
2805 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2807 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2808 offset
-= mips_abi_regsize (gdbarch
);
2811 /* Check if the S1 register was pushed on the stack. */
2812 if (save_inst
& 0x10)
2814 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2815 offset
-= mips_abi_regsize (gdbarch
);
2817 /* Check if the S0 register was pushed on the stack. */
2818 if (save_inst
& 0x20)
2820 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2821 offset
-= mips_abi_regsize (gdbarch
);
2824 /* Check if A0-A3 were pushed on the stack. */
2825 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2827 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2828 offset
-= mips_abi_regsize (gdbarch
);
2832 if (this_cache
!= NULL
)
2835 (get_frame_register_signed (this_frame
,
2836 gdbarch_num_regs (gdbarch
) + frame_reg
)
2837 + frame_offset
- frame_adjust
);
2838 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2839 be able to get rid of the assignment below, evetually. But it's
2840 still needed for now. */
2841 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2842 + mips_regnum (gdbarch
)->pc
]
2843 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2846 /* Set end_prologue_addr to the address of the instruction immediately
2847 after the last one we scanned. Unless the last one looked like a
2848 non-prologue instruction (and we looked ahead), in which case use
2849 its address instead. */
2850 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2851 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2853 return end_prologue_addr
;
2856 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2857 Procedures that use the 32-bit instruction set are handled by the
2858 mips_insn32 unwinder. */
2860 static struct mips_frame_cache
*
2861 mips_insn16_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2863 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2864 struct mips_frame_cache
*cache
;
2866 if ((*this_cache
) != NULL
)
2867 return (struct mips_frame_cache
*) (*this_cache
);
2868 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2869 (*this_cache
) = cache
;
2870 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2872 /* Analyze the function prologue. */
2874 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2875 CORE_ADDR start_addr
;
2877 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2878 if (start_addr
== 0)
2879 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2880 /* We can't analyze the prologue if we couldn't find the begining
2882 if (start_addr
== 0)
2885 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2886 (struct mips_frame_cache
*) *this_cache
);
2889 /* gdbarch_sp_regnum contains the value and not the address. */
2890 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2891 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2893 return (struct mips_frame_cache
*) (*this_cache
);
2897 mips_insn16_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2898 struct frame_id
*this_id
)
2900 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2902 /* This marks the outermost frame. */
2903 if (info
->base
== 0)
2905 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2908 static struct value
*
2909 mips_insn16_frame_prev_register (frame_info_ptr this_frame
,
2910 void **this_cache
, int regnum
)
2912 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2914 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2918 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2919 frame_info_ptr this_frame
, void **this_cache
)
2921 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2922 CORE_ADDR pc
= get_frame_pc (this_frame
);
2923 if (mips_pc_is_mips16 (gdbarch
, pc
))
2928 static const struct frame_unwind mips_insn16_frame_unwind
=
2930 "mips insn16 prologue",
2932 default_frame_unwind_stop_reason
,
2933 mips_insn16_frame_this_id
,
2934 mips_insn16_frame_prev_register
,
2936 mips_insn16_frame_sniffer
2940 mips_insn16_frame_base_address (frame_info_ptr this_frame
,
2943 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2948 static const struct frame_base mips_insn16_frame_base
=
2950 &mips_insn16_frame_unwind
,
2951 mips_insn16_frame_base_address
,
2952 mips_insn16_frame_base_address
,
2953 mips_insn16_frame_base_address
2956 static const struct frame_base
*
2957 mips_insn16_frame_base_sniffer (frame_info_ptr this_frame
)
2959 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2960 CORE_ADDR pc
= get_frame_pc (this_frame
);
2961 if (mips_pc_is_mips16 (gdbarch
, pc
))
2962 return &mips_insn16_frame_base
;
2967 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2968 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2969 interpreted directly, and then multiplied by 4. */
2972 micromips_decode_imm9 (int imm
)
2974 imm
= (imm
^ 0x100) - 0x100;
2975 if (imm
> -3 && imm
< 2)
2980 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2981 the address of the first instruction past the prologue. */
2984 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2985 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2986 frame_info_ptr this_frame
,
2987 struct mips_frame_cache
*this_cache
)
2989 CORE_ADDR end_prologue_addr
;
2990 int prev_non_prologue_insn
= 0;
2991 int frame_reg
= MIPS_SP_REGNUM
;
2992 int this_non_prologue_insn
;
2993 int non_prologue_insns
= 0;
2994 long frame_offset
= 0; /* Size of stack frame. */
2995 long frame_adjust
= 0; /* Offset of FP from SP. */
2996 int prev_delay_slot
= 0;
3000 ULONGEST insn
; /* current instruction */
3004 long v1_off
= 0; /* The assumption is LUI will replace it. */
3015 /* Can be called when there's no process, and hence when there's no
3017 if (this_frame
!= NULL
)
3018 sp
= get_frame_register_signed (this_frame
,
3019 gdbarch_num_regs (gdbarch
)
3024 if (limit_pc
> start_pc
+ 200)
3025 limit_pc
= start_pc
+ 200;
3028 /* Permit at most one non-prologue non-control-transfer instruction
3029 in the middle which may have been reordered by the compiler for
3031 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3033 this_non_prologue_insn
= 0;
3037 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3038 loc
+= MIPS_INSN16_SIZE
;
3039 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3041 /* 32-bit instructions. */
3042 case 2 * MIPS_INSN16_SIZE
:
3044 insn
|= mips_fetch_instruction (gdbarch
,
3045 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3046 loc
+= MIPS_INSN16_SIZE
;
3047 switch (micromips_op (insn
>> 16))
3049 /* Record $sp/$fp adjustment. */
3050 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3051 case 0x0: /* POOL32A: bits 000000 */
3052 case 0x16: /* POOL32S: bits 010110 */
3053 op
= b0s11_op (insn
);
3054 sreg
= b0s5_reg (insn
>> 16);
3055 treg
= b5s5_reg (insn
>> 16);
3056 dreg
= b11s5_reg (insn
);
3058 /* SUBU: bits 000000 00111010000 */
3059 /* DSUBU: bits 010110 00111010000 */
3060 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3062 /* (D)SUBU $sp, $v1 */
3064 else if (op
!= 0x150
3065 /* ADDU: bits 000000 00101010000 */
3066 /* DADDU: bits 010110 00101010000 */
3067 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3068 this_non_prologue_insn
= 1;
3071 case 0x8: /* POOL32B: bits 001000 */
3072 op
= b12s4_op (insn
);
3073 breg
= b0s5_reg (insn
>> 16);
3074 reglist
= sreg
= b5s5_reg (insn
>> 16);
3075 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3076 if ((op
== 0x9 || op
== 0xc)
3077 /* SWP: bits 001000 1001 */
3078 /* SDP: bits 001000 1100 */
3079 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3080 /* S[DW]P reg,offset($sp) */
3082 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3083 set_reg_offset (gdbarch
, this_cache
,
3085 set_reg_offset (gdbarch
, this_cache
,
3086 sreg
+ 1, sp
+ offset
+ s
);
3088 else if ((op
== 0xd || op
== 0xf)
3089 /* SWM: bits 001000 1101 */
3090 /* SDM: bits 001000 1111 */
3091 && breg
== MIPS_SP_REGNUM
3092 /* SWM reglist,offset($sp) */
3093 && ((reglist
>= 1 && reglist
<= 9)
3094 || (reglist
>= 16 && reglist
<= 25)))
3096 int sreglist
= std::min(reglist
& 0xf, 8);
3098 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3099 for (i
= 0; i
< sreglist
; i
++)
3100 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3101 if ((reglist
& 0xf) > 8)
3102 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3103 if ((reglist
& 0x10) == 0x10)
3104 set_reg_offset (gdbarch
, this_cache
,
3105 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3108 this_non_prologue_insn
= 1;
3111 /* Record $sp/$fp adjustment. */
3112 /* Discard (D)ADDIU $gp used for PIC code. */
3113 case 0xc: /* ADDIU: bits 001100 */
3114 case 0x17: /* DADDIU: bits 010111 */
3115 sreg
= b0s5_reg (insn
>> 16);
3116 dreg
= b5s5_reg (insn
>> 16);
3117 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3118 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3119 /* (D)ADDIU $sp, imm */
3121 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3122 /* (D)ADDIU $fp, $sp, imm */
3124 frame_adjust
= offset
;
3127 else if (sreg
!= 28 || dreg
!= 28)
3128 /* (D)ADDIU $gp, imm */
3129 this_non_prologue_insn
= 1;
3132 /* LUI $v1 is used for larger $sp adjustments. */
3133 /* Discard LUI $gp used for PIC code. */
3134 case 0x10: /* POOL32I: bits 010000 */
3135 if (b5s5_op (insn
>> 16) == 0xd
3136 /* LUI: bits 010000 001101 */
3137 && b0s5_reg (insn
>> 16) == 3)
3139 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3140 else if (b5s5_op (insn
>> 16) != 0xd
3141 /* LUI: bits 010000 001101 */
3142 || b0s5_reg (insn
>> 16) != 28)
3144 this_non_prologue_insn
= 1;
3147 /* ORI $v1 is used for larger $sp adjustments. */
3148 case 0x14: /* ORI: bits 010100 */
3149 sreg
= b0s5_reg (insn
>> 16);
3150 dreg
= b5s5_reg (insn
>> 16);
3151 if (sreg
== 3 && dreg
== 3)
3153 v1_off
|= b0s16_imm (insn
);
3155 this_non_prologue_insn
= 1;
3158 case 0x26: /* SWC1: bits 100110 */
3159 case 0x2e: /* SDC1: bits 101110 */
3160 breg
= b0s5_reg (insn
>> 16);
3161 if (breg
!= MIPS_SP_REGNUM
)
3162 /* S[DW]C1 reg,offset($sp) */
3163 this_non_prologue_insn
= 1;
3166 case 0x36: /* SD: bits 110110 */
3167 case 0x3e: /* SW: bits 111110 */
3168 breg
= b0s5_reg (insn
>> 16);
3169 sreg
= b5s5_reg (insn
>> 16);
3170 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3171 if (breg
== MIPS_SP_REGNUM
)
3172 /* S[DW] reg,offset($sp) */
3173 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3175 this_non_prologue_insn
= 1;
3179 /* The instruction in the delay slot can be a part
3180 of the prologue, so move forward once more. */
3181 if (micromips_instruction_has_delay_slot (insn
, 0))
3184 this_non_prologue_insn
= 1;
3190 /* 16-bit instructions. */
3191 case MIPS_INSN16_SIZE
:
3192 switch (micromips_op (insn
))
3194 case 0x3: /* MOVE: bits 000011 */
3195 sreg
= b0s5_reg (insn
);
3196 dreg
= b5s5_reg (insn
);
3197 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3200 else if ((sreg
& 0x1c) != 0x4)
3201 /* MOVE reg, $a0-$a3 */
3202 this_non_prologue_insn
= 1;
3205 case 0x11: /* POOL16C: bits 010001 */
3206 if (b6s4_op (insn
) == 0x5)
3207 /* SWM: bits 010001 0101 */
3209 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3210 reglist
= b4s2_regl (insn
);
3211 for (i
= 0; i
<= reglist
; i
++)
3212 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3213 set_reg_offset (gdbarch
, this_cache
,
3214 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3217 this_non_prologue_insn
= 1;
3220 case 0x13: /* POOL16D: bits 010011 */
3221 if ((insn
& 0x1) == 0x1)
3222 /* ADDIUSP: bits 010011 1 */
3223 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3224 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3225 /* ADDIUS5: bits 010011 0 */
3226 /* ADDIUS5 $sp, imm */
3227 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3229 this_non_prologue_insn
= 1;
3232 case 0x32: /* SWSP: bits 110010 */
3233 offset
= b0s5_imm (insn
) << 2;
3234 sreg
= b5s5_reg (insn
);
3235 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3239 /* The instruction in the delay slot can be a part
3240 of the prologue, so move forward once more. */
3241 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3244 this_non_prologue_insn
= 1;
3250 frame_offset
-= sp_adj
;
3252 non_prologue_insns
+= this_non_prologue_insn
;
3254 /* A jump or branch, enough non-prologue insns seen or positive
3255 stack adjustment? If so, then we must have reached the end
3256 of the prologue by now. */
3257 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3258 || micromips_instruction_is_compact_branch (insn
))
3261 prev_non_prologue_insn
= this_non_prologue_insn
;
3262 prev_delay_slot
= in_delay_slot
;
3266 if (this_cache
!= NULL
)
3269 (get_frame_register_signed (this_frame
,
3270 gdbarch_num_regs (gdbarch
) + frame_reg
)
3271 + frame_offset
- frame_adjust
);
3272 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3273 be able to get rid of the assignment below, evetually. But it's
3274 still needed for now. */
3275 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3276 + mips_regnum (gdbarch
)->pc
]
3277 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3280 /* Set end_prologue_addr to the address of the instruction immediately
3281 after the last one we scanned. Unless the last one looked like a
3282 non-prologue instruction (and we looked ahead), in which case use
3283 its address instead. */
3285 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3287 return end_prologue_addr
;
3290 /* Heuristic unwinder for procedures using microMIPS instructions.
3291 Procedures that use the 32-bit instruction set are handled by the
3292 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3294 static struct mips_frame_cache
*
3295 mips_micro_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3297 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3298 struct mips_frame_cache
*cache
;
3300 if ((*this_cache
) != NULL
)
3301 return (struct mips_frame_cache
*) (*this_cache
);
3303 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3304 (*this_cache
) = cache
;
3305 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3307 /* Analyze the function prologue. */
3309 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3310 CORE_ADDR start_addr
;
3312 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3313 if (start_addr
== 0)
3314 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3315 /* We can't analyze the prologue if we couldn't find the begining
3317 if (start_addr
== 0)
3320 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3321 (struct mips_frame_cache
*) *this_cache
);
3324 /* gdbarch_sp_regnum contains the value and not the address. */
3325 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3326 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3328 return (struct mips_frame_cache
*) (*this_cache
);
3332 mips_micro_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3333 struct frame_id
*this_id
)
3335 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3337 /* This marks the outermost frame. */
3338 if (info
->base
== 0)
3340 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3343 static struct value
*
3344 mips_micro_frame_prev_register (frame_info_ptr this_frame
,
3345 void **this_cache
, int regnum
)
3347 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3349 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3353 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3354 frame_info_ptr this_frame
, void **this_cache
)
3356 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3357 CORE_ADDR pc
= get_frame_pc (this_frame
);
3359 if (mips_pc_is_micromips (gdbarch
, pc
))
3364 static const struct frame_unwind mips_micro_frame_unwind
=
3366 "mips micro prologue",
3368 default_frame_unwind_stop_reason
,
3369 mips_micro_frame_this_id
,
3370 mips_micro_frame_prev_register
,
3372 mips_micro_frame_sniffer
3376 mips_micro_frame_base_address (frame_info_ptr this_frame
,
3379 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3384 static const struct frame_base mips_micro_frame_base
=
3386 &mips_micro_frame_unwind
,
3387 mips_micro_frame_base_address
,
3388 mips_micro_frame_base_address
,
3389 mips_micro_frame_base_address
3392 static const struct frame_base
*
3393 mips_micro_frame_base_sniffer (frame_info_ptr this_frame
)
3395 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3396 CORE_ADDR pc
= get_frame_pc (this_frame
);
3398 if (mips_pc_is_micromips (gdbarch
, pc
))
3399 return &mips_micro_frame_base
;
3404 /* Mark all the registers as unset in the saved_regs array
3405 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3408 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3410 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3414 const int num_regs
= gdbarch_num_regs (gdbarch
);
3417 /* Reset the register values to their default state. Register i's value
3418 is in register i. */
3419 for (i
= 0; i
< num_regs
; i
++)
3420 this_cache
->saved_regs
[i
].set_realreg (i
);
3424 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3425 the associated FRAME_CACHE if not null.
3426 Return the address of the first instruction past the prologue. */
3429 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3430 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3431 frame_info_ptr this_frame
,
3432 struct mips_frame_cache
*this_cache
)
3434 int prev_non_prologue_insn
;
3435 int this_non_prologue_insn
;
3436 int non_prologue_insns
;
3437 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3439 int prev_delay_slot
;
3444 int frame_reg
= MIPS_SP_REGNUM
;
3446 CORE_ADDR end_prologue_addr
;
3447 int seen_sp_adjust
= 0;
3448 int load_immediate_bytes
= 0;
3450 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3452 /* Can be called when there's no process, and hence when there's no
3454 if (this_frame
!= NULL
)
3455 sp
= get_frame_register_signed (this_frame
,
3456 gdbarch_num_regs (gdbarch
)
3461 if (limit_pc
> start_pc
+ 200)
3462 limit_pc
= start_pc
+ 200;
3465 prev_non_prologue_insn
= 0;
3466 non_prologue_insns
= 0;
3467 prev_delay_slot
= 0;
3470 /* Permit at most one non-prologue non-control-transfer instruction
3471 in the middle which may have been reordered by the compiler for
3474 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3476 unsigned long inst
, high_word
;
3480 this_non_prologue_insn
= 0;
3483 /* Fetch the instruction. */
3484 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3487 /* Save some code by pre-extracting some useful fields. */
3488 high_word
= (inst
>> 16) & 0xffff;
3489 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3490 reg
= high_word
& 0x1f;
3492 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3493 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3494 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3496 if (offset
< 0) /* Negative stack adjustment? */
3497 frame_offset
-= offset
;
3499 /* Exit loop if a positive stack adjustment is found, which
3500 usually means that the stack cleanup code in the function
3501 epilogue is reached. */
3505 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3506 && !regsize_is_64_bits
)
3508 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3510 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3511 && regsize_is_64_bits
)
3513 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3514 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3516 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3518 /* Old gcc frame, r30 is virtual frame pointer. */
3519 if (offset
!= frame_offset
)
3520 frame_addr
= sp
+ offset
;
3521 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3523 unsigned alloca_adjust
;
3526 frame_addr
= get_frame_register_signed
3527 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3530 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3531 if (alloca_adjust
> 0)
3533 /* FP > SP + frame_size. This may be because of
3534 an alloca or somethings similar. Fix sp to
3535 "pre-alloca" value, and try again. */
3536 sp
+= alloca_adjust
;
3537 /* Need to reset the status of all registers. Otherwise,
3538 we will hit a guard that prevents the new address
3539 for each register to be recomputed during the second
3541 reset_saved_regs (gdbarch
, this_cache
);
3546 /* move $30,$sp. With different versions of gas this will be either
3547 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3548 Accept any one of these. */
3549 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3551 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3552 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3554 unsigned alloca_adjust
;
3557 frame_addr
= get_frame_register_signed
3558 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3560 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3561 if (alloca_adjust
> 0)
3563 /* FP > SP + frame_size. This may be because of
3564 an alloca or somethings similar. Fix sp to
3565 "pre-alloca" value, and try again. */
3567 /* Need to reset the status of all registers. Otherwise,
3568 we will hit a guard that prevents the new address
3569 for each register to be recomputed during the second
3571 reset_saved_regs (gdbarch
, this_cache
);
3576 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3577 && !regsize_is_64_bits
)
3579 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3581 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3582 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3583 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3584 || high_word
== 0x3c1c /* lui $gp,n */
3585 || high_word
== 0x279c /* addiu $gp,$gp,n */
3586 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3587 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3588 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3589 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3590 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3593 /* These instructions are part of the prologue, but we don't
3594 need to do anything special to handle them. */
3596 /* The instructions below load $at or $t0 with an immediate
3597 value in preparation for a stack adjustment via
3598 subu $sp,$sp,[$at,$t0]. These instructions could also
3599 initialize a local variable, so we accept them only before
3600 a stack adjustment instruction was seen. */
3601 else if (!seen_sp_adjust
3603 && (high_word
== 0x3c01 /* lui $at,n */
3604 || high_word
== 0x3c08 /* lui $t0,n */
3605 || high_word
== 0x3421 /* ori $at,$at,n */
3606 || high_word
== 0x3508 /* ori $t0,$t0,n */
3607 || high_word
== 0x3401 /* ori $at,$zero,n */
3608 || high_word
== 0x3408 /* ori $t0,$zero,n */
3611 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3613 /* Check for branches and jumps. The instruction in the delay
3614 slot can be a part of the prologue, so move forward once more. */
3615 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3619 /* This instruction is not an instruction typically found
3620 in a prologue, so we must have reached the end of the
3624 this_non_prologue_insn
= 1;
3627 non_prologue_insns
+= this_non_prologue_insn
;
3629 /* A jump or branch, or enough non-prologue insns seen? If so,
3630 then we must have reached the end of the prologue by now. */
3631 if (prev_delay_slot
|| non_prologue_insns
> 1)
3634 prev_non_prologue_insn
= this_non_prologue_insn
;
3635 prev_delay_slot
= in_delay_slot
;
3639 if (this_cache
!= NULL
)
3642 (get_frame_register_signed (this_frame
,
3643 gdbarch_num_regs (gdbarch
) + frame_reg
)
3645 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3646 this assignment below, eventually. But it's still needed
3648 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3649 + mips_regnum (gdbarch
)->pc
]
3650 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3654 /* Set end_prologue_addr to the address of the instruction immediately
3655 after the last one we scanned. Unless the last one looked like a
3656 non-prologue instruction (and we looked ahead), in which case use
3657 its address instead. */
3659 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3661 /* In a frameless function, we might have incorrectly
3662 skipped some load immediate instructions. Undo the skipping
3663 if the load immediate was not followed by a stack adjustment. */
3664 if (load_immediate_bytes
&& !seen_sp_adjust
)
3665 end_prologue_addr
-= load_immediate_bytes
;
3667 return end_prologue_addr
;
3670 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3671 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3672 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3673 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3675 static struct mips_frame_cache
*
3676 mips_insn32_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3678 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3679 struct mips_frame_cache
*cache
;
3681 if ((*this_cache
) != NULL
)
3682 return (struct mips_frame_cache
*) (*this_cache
);
3684 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3685 (*this_cache
) = cache
;
3686 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3688 /* Analyze the function prologue. */
3690 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3691 CORE_ADDR start_addr
;
3693 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3694 if (start_addr
== 0)
3695 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3696 /* We can't analyze the prologue if we couldn't find the begining
3698 if (start_addr
== 0)
3701 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3702 (struct mips_frame_cache
*) *this_cache
);
3705 /* gdbarch_sp_regnum contains the value and not the address. */
3706 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3707 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3709 return (struct mips_frame_cache
*) (*this_cache
);
3713 mips_insn32_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3714 struct frame_id
*this_id
)
3716 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3718 /* This marks the outermost frame. */
3719 if (info
->base
== 0)
3721 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3724 static struct value
*
3725 mips_insn32_frame_prev_register (frame_info_ptr this_frame
,
3726 void **this_cache
, int regnum
)
3728 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3730 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3734 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3735 frame_info_ptr this_frame
, void **this_cache
)
3737 CORE_ADDR pc
= get_frame_pc (this_frame
);
3738 if (mips_pc_is_mips (pc
))
3743 static const struct frame_unwind mips_insn32_frame_unwind
=
3745 "mips insn32 prologue",
3747 default_frame_unwind_stop_reason
,
3748 mips_insn32_frame_this_id
,
3749 mips_insn32_frame_prev_register
,
3751 mips_insn32_frame_sniffer
3755 mips_insn32_frame_base_address (frame_info_ptr this_frame
,
3758 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3763 static const struct frame_base mips_insn32_frame_base
=
3765 &mips_insn32_frame_unwind
,
3766 mips_insn32_frame_base_address
,
3767 mips_insn32_frame_base_address
,
3768 mips_insn32_frame_base_address
3771 static const struct frame_base
*
3772 mips_insn32_frame_base_sniffer (frame_info_ptr this_frame
)
3774 CORE_ADDR pc
= get_frame_pc (this_frame
);
3775 if (mips_pc_is_mips (pc
))
3776 return &mips_insn32_frame_base
;
3781 static struct trad_frame_cache
*
3782 mips_stub_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3785 CORE_ADDR start_addr
;
3786 CORE_ADDR stack_addr
;
3787 struct trad_frame_cache
*this_trad_cache
;
3788 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3789 int num_regs
= gdbarch_num_regs (gdbarch
);
3791 if ((*this_cache
) != NULL
)
3792 return (struct trad_frame_cache
*) (*this_cache
);
3793 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3794 (*this_cache
) = this_trad_cache
;
3796 /* The return address is in the link register. */
3797 trad_frame_set_reg_realreg (this_trad_cache
,
3798 gdbarch_pc_regnum (gdbarch
),
3799 num_regs
+ MIPS_RA_REGNUM
);
3801 /* Frame ID, since it's a frameless / stackless function, no stack
3802 space is allocated and SP on entry is the current SP. */
3803 pc
= get_frame_pc (this_frame
);
3804 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3805 stack_addr
= get_frame_register_signed (this_frame
,
3806 num_regs
+ MIPS_SP_REGNUM
);
3807 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3809 /* Assume that the frame's base is the same as the
3811 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3813 return this_trad_cache
;
3817 mips_stub_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3818 struct frame_id
*this_id
)
3820 struct trad_frame_cache
*this_trad_cache
3821 = mips_stub_frame_cache (this_frame
, this_cache
);
3822 trad_frame_get_id (this_trad_cache
, this_id
);
3825 static struct value
*
3826 mips_stub_frame_prev_register (frame_info_ptr this_frame
,
3827 void **this_cache
, int regnum
)
3829 struct trad_frame_cache
*this_trad_cache
3830 = mips_stub_frame_cache (this_frame
, this_cache
);
3831 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3835 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3836 frame_info_ptr this_frame
, void **this_cache
)
3839 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3840 struct bound_minimal_symbol msym
;
3842 /* Use the stub unwinder for unreadable code. */
3843 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3846 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3849 /* Calling a PIC function from a non-PIC function passes through a
3850 stub. The stub for foo is named ".pic.foo". */
3851 msym
= lookup_minimal_symbol_by_pc (pc
);
3852 if (msym
.minsym
!= NULL
3853 && msym
.minsym
->linkage_name () != NULL
3854 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3860 static const struct frame_unwind mips_stub_frame_unwind
=
3864 default_frame_unwind_stop_reason
,
3865 mips_stub_frame_this_id
,
3866 mips_stub_frame_prev_register
,
3868 mips_stub_frame_sniffer
3872 mips_stub_frame_base_address (frame_info_ptr this_frame
,
3875 struct trad_frame_cache
*this_trad_cache
3876 = mips_stub_frame_cache (this_frame
, this_cache
);
3877 return trad_frame_get_this_base (this_trad_cache
);
3880 static const struct frame_base mips_stub_frame_base
=
3882 &mips_stub_frame_unwind
,
3883 mips_stub_frame_base_address
,
3884 mips_stub_frame_base_address
,
3885 mips_stub_frame_base_address
3888 static const struct frame_base
*
3889 mips_stub_frame_base_sniffer (frame_info_ptr this_frame
)
3891 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3892 return &mips_stub_frame_base
;
3897 /* mips_addr_bits_remove - remove useless address bits */
3900 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3902 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
3904 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3905 /* This hack is a work-around for existing boards using PMON, the
3906 simulator, and any other 64-bit targets that doesn't have true
3907 64-bit addressing. On these targets, the upper 32 bits of
3908 addresses are ignored by the hardware. Thus, the PC or SP are
3909 likely to have been sign extended to all 1s by instruction
3910 sequences that load 32-bit addresses. For example, a typical
3911 piece of code that loads an address is this:
3913 lui $r2, <upper 16 bits>
3914 ori $r2, <lower 16 bits>
3916 But the lui sign-extends the value such that the upper 32 bits
3917 may be all 1s. The workaround is simply to mask off these
3918 bits. In the future, gcc may be changed to support true 64-bit
3919 addressing, and this masking will have to be disabled. */
3920 return addr
&= 0xffffffffUL
;
3926 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3927 instruction and ending with a SC/SCD instruction. If such a sequence
3928 is found, attempt to step through it. A breakpoint is placed at the end of
3931 /* Instructions used during single-stepping of atomic sequences, standard
3933 #define LL_OPCODE 0x30
3934 #define LLD_OPCODE 0x34
3935 #define SC_OPCODE 0x38
3936 #define SCD_OPCODE 0x3c
3938 static std::vector
<CORE_ADDR
>
3939 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3941 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3943 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3947 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3948 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3950 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3951 /* Assume all atomic sequences start with a ll/lld instruction. */
3952 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3955 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3957 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3960 loc
+= MIPS_INSN32_SIZE
;
3961 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3963 /* Assume that there is at most one branch in the atomic
3964 sequence. If a branch is found, put a breakpoint in its
3965 destination address. */
3966 switch (itype_op (insn
))
3968 case 0: /* SPECIAL */
3969 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3970 return {}; /* fallback to the standard single-step code. */
3972 case 1: /* REGIMM */
3973 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3974 || ((itype_rt (insn
) & 0x1e) == 0
3975 && itype_rs (insn
) == 0)); /* BPOSGE* */
3979 return {}; /* fallback to the standard single-step code. */
3986 case 22: /* BLEZL */
3987 case 23: /* BGTTL */
3991 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3992 && (itype_rt (insn
) & 0x2) == 0);
3993 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3998 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4003 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4004 if (last_breakpoint
>= 1)
4005 return {}; /* More than one branch found, fallback to the
4006 standard single-step code. */
4007 breaks
[1] = branch_bp
;
4011 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4015 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4016 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4019 loc
+= MIPS_INSN32_SIZE
;
4021 /* Insert a breakpoint right after the end of the atomic sequence. */
4024 /* Check for duplicated breakpoints. Check also for a breakpoint
4025 placed (branch instruction's destination) in the atomic sequence. */
4026 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4027 last_breakpoint
= 0;
4029 std::vector
<CORE_ADDR
> next_pcs
;
4031 /* Effectively inserts the breakpoints. */
4032 for (index
= 0; index
<= last_breakpoint
; index
++)
4033 next_pcs
.push_back (breaks
[index
]);
4038 static std::vector
<CORE_ADDR
>
4039 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4042 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4043 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4044 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4045 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4053 /* Assume all atomic sequences start with a ll/lld instruction. */
4054 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4055 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4057 loc
+= MIPS_INSN16_SIZE
;
4059 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4060 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4062 loc
+= MIPS_INSN16_SIZE
;
4064 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4065 that no atomic sequence is longer than "atomic_sequence_length"
4067 for (insn_count
= 0;
4068 !sc_found
&& insn_count
< atomic_sequence_length
;
4073 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4074 loc
+= MIPS_INSN16_SIZE
;
4076 /* Assume that there is at most one conditional branch in the
4077 atomic sequence. If a branch is found, put a breakpoint in
4078 its destination address. */
4079 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4081 /* 32-bit instructions. */
4082 case 2 * MIPS_INSN16_SIZE
:
4083 switch (micromips_op (insn
))
4085 case 0x10: /* POOL32I: bits 010000 */
4086 if ((b5s5_op (insn
) & 0x18) != 0x0
4087 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4088 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4089 && (b5s5_op (insn
) & 0x1d) != 0x11
4090 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4091 && ((b5s5_op (insn
) & 0x1e) != 0x14
4092 || (insn
& 0x3) != 0x0)
4093 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4094 && (b5s5_op (insn
) & 0x1e) != 0x1a
4095 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4096 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4097 || (insn
& 0x3) != 0x0)
4098 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4099 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4100 || (insn
& 0x3) != 0x1))
4101 /* BC1ANY*: bits 010000 111xx xxx01 */
4105 case 0x25: /* BEQ: bits 100101 */
4106 case 0x2d: /* BNE: bits 101101 */
4108 insn
|= mips_fetch_instruction (gdbarch
,
4109 ISA_MICROMIPS
, loc
, NULL
);
4110 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4111 + micromips_relative_offset16 (insn
));
4115 case 0x00: /* POOL32A: bits 000000 */
4117 insn
|= mips_fetch_instruction (gdbarch
,
4118 ISA_MICROMIPS
, loc
, NULL
);
4119 if (b0s6_op (insn
) != 0x3c
4120 /* POOL32Axf: bits 000000 ... 111100 */
4121 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4122 /* JALR, JALR.HB: 000000 000x111100 111100 */
4123 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4127 case 0x1d: /* JALS: bits 011101 */
4128 case 0x35: /* J: bits 110101 */
4129 case 0x3d: /* JAL: bits 111101 */
4130 case 0x3c: /* JALX: bits 111100 */
4131 return {}; /* Fall back to the standard single-step code. */
4133 case 0x18: /* POOL32C: bits 011000 */
4134 if ((b12s4_op (insn
) & 0xb) == 0xb)
4135 /* SC, SCD: bits 011000 1x11 */
4139 loc
+= MIPS_INSN16_SIZE
;
4142 /* 16-bit instructions. */
4143 case MIPS_INSN16_SIZE
:
4144 switch (micromips_op (insn
))
4146 case 0x23: /* BEQZ16: bits 100011 */
4147 case 0x2b: /* BNEZ16: bits 101011 */
4148 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4152 case 0x11: /* POOL16C: bits 010001 */
4153 if ((b5s5_op (insn
) & 0x1c) != 0xc
4154 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4155 && b5s5_op (insn
) != 0x18)
4156 /* JRADDIUSP: bits 010001 11000 */
4158 return {}; /* Fall back to the standard single-step code. */
4160 case 0x33: /* B16: bits 110011 */
4161 return {}; /* Fall back to the standard single-step code. */
4167 if (last_breakpoint
>= 1)
4168 return {}; /* More than one branch found, fallback to the
4169 standard single-step code. */
4170 breaks
[1] = branch_bp
;
4177 /* Insert a breakpoint right after the end of the atomic sequence. */
4180 /* Check for duplicated breakpoints. Check also for a breakpoint
4181 placed (branch instruction's destination) in the atomic sequence */
4182 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4183 last_breakpoint
= 0;
4185 std::vector
<CORE_ADDR
> next_pcs
;
4187 /* Effectively inserts the breakpoints. */
4188 for (index
= 0; index
<= last_breakpoint
; index
++)
4189 next_pcs
.push_back (breaks
[index
]);
4194 static std::vector
<CORE_ADDR
>
4195 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4197 if (mips_pc_is_mips (pc
))
4198 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4199 else if (mips_pc_is_micromips (gdbarch
, pc
))
4200 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4205 /* mips_software_single_step() is called just before we want to resume
4206 the inferior, if we want to single-step it but there is no hardware
4207 or kernel single-step support (MIPS on GNU/Linux for example). We find
4208 the target of the coming instruction and breakpoint it. */
4210 std::vector
<CORE_ADDR
>
4211 mips_software_single_step (struct regcache
*regcache
)
4213 struct gdbarch
*gdbarch
= regcache
->arch ();
4214 CORE_ADDR pc
, next_pc
;
4216 pc
= regcache_read_pc (regcache
);
4217 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4219 if (!next_pcs
.empty ())
4222 next_pc
= mips_next_pc (regcache
, pc
);
4227 /* Test whether the PC points to the return instruction at the
4228 end of a function. */
4231 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4236 /* This used to check for MIPS16, but this piece of code is never
4237 called for MIPS16 functions. And likewise microMIPS ones. */
4238 gdb_assert (mips_pc_is_mips (pc
));
4240 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4242 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4246 /* This fencepost looks highly suspicious to me. Removing it also
4247 seems suspicious as it could affect remote debugging across serial
4251 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4257 struct inferior
*inf
;
4259 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4261 fence
= start_pc
- heuristic_fence_post
;
4265 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4266 fence
= VM_MIN_ADDRESS
;
4268 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4270 inf
= current_inferior ();
4272 /* Search back for previous return. */
4273 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4274 if (start_pc
< fence
)
4276 /* It's not clear to me why we reach this point when
4277 stop_soon, but with this test, at least we
4278 don't print out warnings for every child forked (eg, on
4279 decstation). 22apr93 rich@cygnus.com. */
4280 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4282 static int blurb_printed
= 0;
4284 warning (_("GDB can't find the start of the function at %s."),
4285 paddress (gdbarch
, pc
));
4289 /* This actually happens frequently in embedded
4290 development, when you first connect to a board
4291 and your stack pointer and pc are nowhere in
4292 particular. This message needs to give people
4293 in that situation enough information to
4294 determine that it's no big deal. */
4296 GDB is unable to find the start of the function at %s\n\
4297 and thus can't determine the size of that function's stack frame.\n\
4298 This means that GDB may be unable to access that stack frame, or\n\
4299 the frames below it.\n\
4300 This problem is most likely caused by an invalid program counter or\n\
4302 However, if you think GDB should simply search farther back\n\
4303 from %s for code which looks like the beginning of a\n\
4304 function, you can increase the range of the search using the `set\n\
4305 heuristic-fence-post' command.\n",
4306 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4313 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4315 unsigned short inst
;
4317 /* On MIPS16, any one of the following is likely to be the
4318 start of a function:
4324 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4325 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4326 if ((inst
& 0xff80) == 0x6480) /* save */
4328 if (start_pc
- instlen
>= fence
)
4330 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4331 start_pc
- instlen
, NULL
);
4332 if ((inst
& 0xf800) == 0xf000) /* extend */
4333 start_pc
-= instlen
;
4337 else if (((inst
& 0xf81f) == 0xe809
4338 && (inst
& 0x700) != 0x700) /* entry */
4339 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4340 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4341 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4343 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4344 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4349 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4357 /* On microMIPS, any one of the following is likely to be the
4358 start of a function:
4362 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4363 switch (micromips_op (insn
))
4365 case 0xc: /* ADDIU: bits 001100 */
4366 case 0x17: /* DADDIU: bits 010111 */
4367 sreg
= b0s5_reg (insn
);
4368 dreg
= b5s5_reg (insn
);
4370 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4371 pc
+ MIPS_INSN16_SIZE
, NULL
);
4372 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4373 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4374 /* (D)ADDIU $sp, imm */
4379 case 0x10: /* POOL32I: bits 010000 */
4380 if (b5s5_op (insn
) == 0xd
4381 /* LUI: bits 010000 001101 */
4382 && b0s5_reg (insn
>> 16) == 28)
4387 case 0x13: /* POOL16D: bits 010011 */
4388 if ((insn
& 0x1) == 0x1)
4389 /* ADDIUSP: bits 010011 1 */
4391 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4397 /* ADDIUS5: bits 010011 0 */
4399 dreg
= b5s5_reg (insn
);
4400 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4401 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4402 /* ADDIUS5 $sp, -imm */
4410 else if (mips_about_to_return (gdbarch
, start_pc
))
4412 /* Skip return and its delay slot. */
4413 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4420 struct mips_objfile_private
4426 /* According to the current ABI, should the type be passed in a
4427 floating-point register (assuming that there is space)? When there
4428 is no FPU, FP are not even considered as possible candidates for
4429 FP registers and, consequently this returns false - forces FP
4430 arguments into integer registers. */
4433 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4434 struct type
*arg_type
)
4436 return ((typecode
== TYPE_CODE_FLT
4437 || (mips_eabi (gdbarch
)
4438 && (typecode
== TYPE_CODE_STRUCT
4439 || typecode
== TYPE_CODE_UNION
)
4440 && arg_type
->num_fields () == 1
4441 && check_typedef (arg_type
->field (0).type ())->code ()
4443 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4446 /* On o32, argument passing in GPRs depends on the alignment of the type being
4447 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4450 mips_type_needs_double_align (struct type
*type
)
4452 enum type_code typecode
= type
->code ();
4454 if (typecode
== TYPE_CODE_FLT
&& type
->length () == 8)
4456 else if (typecode
== TYPE_CODE_STRUCT
)
4458 if (type
->num_fields () < 1)
4460 return mips_type_needs_double_align (type
->field (0).type ());
4462 else if (typecode
== TYPE_CODE_UNION
)
4466 n
= type
->num_fields ();
4467 for (i
= 0; i
< n
; i
++)
4468 if (mips_type_needs_double_align (type
->field (i
).type ()))
4475 /* Adjust the address downward (direction of stack growth) so that it
4476 is correctly aligned for a new stack frame. */
4478 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4480 return align_down (addr
, 16);
4483 /* Implement the "push_dummy_code" gdbarch method. */
4486 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4487 CORE_ADDR funaddr
, struct value
**args
,
4488 int nargs
, struct type
*value_type
,
4489 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4490 struct regcache
*regcache
)
4492 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4496 /* Reserve enough room on the stack for our breakpoint instruction. */
4497 bp_slot
= sp
- sizeof (nop_insn
);
4499 /* Return to microMIPS mode if calling microMIPS code to avoid
4500 triggering an address error exception on processors that only
4501 support microMIPS execution. */
4502 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4503 ? make_compact_addr (bp_slot
) : bp_slot
);
4505 /* The breakpoint layer automatically adjusts the address of
4506 breakpoints inserted in a branch delay slot. With enough
4507 bad luck, the 4 bytes located just before our breakpoint
4508 instruction could look like a branch instruction, and thus
4509 trigger the adjustement, and break the function call entirely.
4510 So, we reserve those 4 bytes and write a nop instruction
4511 to prevent that from happening. */
4512 nop_addr
= bp_slot
- sizeof (nop_insn
);
4513 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4514 sp
= mips_frame_align (gdbarch
, nop_addr
);
4516 /* Inferior resumes at the function entry point. */
4523 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4524 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4525 int nargs
, struct value
**args
, CORE_ADDR sp
,
4526 function_call_return_method return_method
,
4527 CORE_ADDR struct_addr
)
4533 int stack_offset
= 0;
4534 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4535 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4536 int abi_regsize
= mips_abi_regsize (gdbarch
);
4538 /* For shared libraries, "t9" needs to point at the function
4540 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4542 /* Set the return address register to point to the entry point of
4543 the program, where a breakpoint lies in wait. */
4544 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4546 /* First ensure that the stack and structure return address (if any)
4547 are properly aligned. The stack has to be at least 64-bit
4548 aligned even on 32-bit machines, because doubles must be 64-bit
4549 aligned. For n32 and n64, stack frames need to be 128-bit
4550 aligned, so we round to this widest known alignment. */
4552 sp
= align_down (sp
, 16);
4553 struct_addr
= align_down (struct_addr
, 16);
4555 /* Now make space on the stack for the args. We allocate more
4556 than necessary for EABI, because the first few arguments are
4557 passed in registers, but that's OK. */
4558 for (argnum
= 0; argnum
< nargs
; argnum
++)
4559 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4561 sp
-= align_up (arg_space
, 16);
4564 gdb_printf (gdb_stdlog
,
4565 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4566 paddress (gdbarch
, sp
),
4567 (long) align_up (arg_space
, 16));
4569 /* Initialize the integer and float register pointers. */
4570 argreg
= MIPS_A0_REGNUM
;
4571 float_argreg
= mips_fpa0_regnum (gdbarch
);
4573 /* The struct_return pointer occupies the first parameter-passing reg. */
4574 if (return_method
== return_method_struct
)
4577 gdb_printf (gdb_stdlog
,
4578 "mips_eabi_push_dummy_call: "
4579 "struct_return reg=%d %s\n",
4580 argreg
, paddress (gdbarch
, struct_addr
));
4581 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4584 /* Now load as many as possible of the first arguments into
4585 registers, and push the rest onto the stack. Loop thru args
4586 from first to last. */
4587 for (argnum
= 0; argnum
< nargs
; argnum
++)
4589 const gdb_byte
*val
;
4590 /* This holds the address of structures that are passed by
4592 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4593 struct value
*arg
= args
[argnum
];
4594 struct type
*arg_type
= check_typedef (arg
->type ());
4595 int len
= arg_type
->length ();
4596 enum type_code typecode
= arg_type
->code ();
4599 gdb_printf (gdb_stdlog
,
4600 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4601 argnum
+ 1, len
, (int) typecode
);
4603 /* The EABI passes structures that do not fit in a register by
4605 if (len
> abi_regsize
4606 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4608 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4609 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4611 typecode
= TYPE_CODE_PTR
;
4615 gdb_printf (gdb_stdlog
, " push");
4618 val
= arg
->contents ().data ();
4620 /* 32-bit ABIs always start floating point arguments in an
4621 even-numbered floating point register. Round the FP register
4622 up before the check to see if there are any FP registers
4623 left. Non MIPS_EABI targets also pass the FP in the integer
4624 registers so also round up normal registers. */
4625 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4627 if ((float_argreg
& 1))
4631 /* Floating point arguments passed in registers have to be
4632 treated specially. On 32-bit architectures, doubles
4633 are passed in register pairs; the even register gets
4634 the low word, and the odd register gets the high word.
4635 On non-EABI processors, the first two floating point arguments are
4636 also copied to general registers, because MIPS16 functions
4637 don't use float registers for arguments. This duplication of
4638 arguments in general registers can't hurt non-MIPS16 functions
4639 because those registers are normally skipped. */
4640 /* MIPS_EABI squeezes a struct that contains a single floating
4641 point value into an FP register instead of pushing it onto the
4643 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4644 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4646 /* EABI32 will pass doubles in consecutive registers, even on
4647 64-bit cores. At one time, we used to check the size of
4648 `float_argreg' to determine whether or not to pass doubles
4649 in consecutive registers, but this is not sufficient for
4650 making the ABI determination. */
4651 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4653 int low_offset
= gdbarch_byte_order (gdbarch
)
4654 == BFD_ENDIAN_BIG
? 4 : 0;
4657 /* Write the low word of the double to the even register(s). */
4658 regval
= extract_signed_integer (val
+ low_offset
,
4661 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4662 float_argreg
, phex (regval
, 4));
4663 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4665 /* Write the high word of the double to the odd register(s). */
4666 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4669 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4670 float_argreg
, phex (regval
, 4));
4671 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4675 /* This is a floating point value that fits entirely
4676 in a single register. */
4677 /* On 32 bit ABI's the float_argreg is further adjusted
4678 above to ensure that it is even register aligned. */
4679 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4681 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4682 float_argreg
, phex (regval
, len
));
4683 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4688 /* Copy the argument to general registers or the stack in
4689 register-sized pieces. Large arguments are split between
4690 registers and stack. */
4691 /* Note: structs whose size is not a multiple of abi_regsize
4692 are treated specially: Irix cc passes
4693 them in registers where gcc sometimes puts them on the
4694 stack. For maximum compatibility, we will put them in
4696 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4698 /* Note: Floating-point values that didn't fit into an FP
4699 register are only written to memory. */
4702 /* Remember if the argument was written to the stack. */
4703 int stack_used_p
= 0;
4704 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4707 gdb_printf (gdb_stdlog
, " -- partial=%d",
4710 /* Write this portion of the argument to the stack. */
4711 if (argreg
> mips_last_arg_regnum (gdbarch
)
4713 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4715 /* Should shorter than int integer values be
4716 promoted to int before being stored? */
4717 int longword_offset
= 0;
4720 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4722 if (abi_regsize
== 8
4723 && (typecode
== TYPE_CODE_INT
4724 || typecode
== TYPE_CODE_PTR
4725 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4726 longword_offset
= abi_regsize
- len
;
4727 else if ((typecode
== TYPE_CODE_STRUCT
4728 || typecode
== TYPE_CODE_UNION
)
4729 && arg_type
->length () < abi_regsize
)
4730 longword_offset
= abi_regsize
- len
;
4735 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4736 paddress (gdbarch
, stack_offset
));
4737 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4738 paddress (gdbarch
, longword_offset
));
4741 addr
= sp
+ stack_offset
+ longword_offset
;
4746 gdb_printf (gdb_stdlog
, " @%s ",
4747 paddress (gdbarch
, addr
));
4748 for (i
= 0; i
< partial_len
; i
++)
4750 gdb_printf (gdb_stdlog
, "%02x",
4754 write_memory (addr
, val
, partial_len
);
4757 /* Note!!! This is NOT an else clause. Odd sized
4758 structs may go thru BOTH paths. Floating point
4759 arguments will not. */
4760 /* Write this portion of the argument to a general
4761 purpose register. */
4762 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4763 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4766 extract_signed_integer (val
, partial_len
, byte_order
);
4769 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4771 phex (regval
, abi_regsize
));
4772 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4779 /* Compute the offset into the stack at which we will
4780 copy the next parameter.
4782 In the new EABI (and the NABI32), the stack_offset
4783 only needs to be adjusted when it has been used. */
4786 stack_offset
+= align_up (partial_len
, abi_regsize
);
4790 gdb_printf (gdb_stdlog
, "\n");
4793 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4795 /* Return adjusted stack pointer. */
4799 /* Determine the return value convention being used. */
4801 static enum return_value_convention
4802 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4803 struct type
*type
, struct regcache
*regcache
,
4804 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4806 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
4807 int fp_return_type
= 0;
4808 int offset
, regnum
, xfer
;
4810 if (type
->length () > 2 * mips_abi_regsize (gdbarch
))
4811 return RETURN_VALUE_STRUCT_CONVENTION
;
4813 /* Floating point type? */
4814 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4816 if (type
->code () == TYPE_CODE_FLT
)
4818 /* Structs with a single field of float type
4819 are returned in a floating point register. */
4820 if ((type
->code () == TYPE_CODE_STRUCT
4821 || type
->code () == TYPE_CODE_UNION
)
4822 && type
->num_fields () == 1)
4824 struct type
*fieldtype
= type
->field (0).type ();
4826 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4833 /* A floating-point value belongs in the least significant part
4836 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4837 regnum
= mips_regnum (gdbarch
)->fp0
;
4841 /* An integer value goes in V0/V1. */
4843 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4844 regnum
= MIPS_V0_REGNUM
;
4847 offset
< type
->length ();
4848 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4850 xfer
= mips_abi_regsize (gdbarch
);
4851 if (offset
+ xfer
> type
->length ())
4852 xfer
= type
->length () - offset
;
4853 mips_xfer_register (gdbarch
, regcache
,
4854 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4855 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4859 return RETURN_VALUE_REGISTER_CONVENTION
;
4863 /* N32/N64 ABI stuff. */
4865 /* Search for a naturally aligned double at OFFSET inside a struct
4866 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4870 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4875 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4878 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4881 if (arg_type
->length () < offset
+ MIPS64_REGSIZE
)
4884 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4887 struct type
*field_type
;
4889 /* We're only looking at normal fields. */
4890 if (arg_type
->field (i
).is_static ()
4891 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4894 /* If we have gone past the offset, there is no double to pass. */
4895 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4899 field_type
= check_typedef (arg_type
->field (i
).type ());
4901 /* If this field is entirely before the requested offset, go
4902 on to the next one. */
4903 if (pos
+ field_type
->length () <= offset
)
4906 /* If this is our special aligned double, we can stop. */
4907 if (field_type
->code () == TYPE_CODE_FLT
4908 && field_type
->length () == MIPS64_REGSIZE
)
4911 /* This field starts at or before the requested offset, and
4912 overlaps it. If it is a structure, recurse inwards. */
4913 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4920 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4921 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4922 int nargs
, struct value
**args
, CORE_ADDR sp
,
4923 function_call_return_method return_method
,
4924 CORE_ADDR struct_addr
)
4930 int stack_offset
= 0;
4931 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4932 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4934 /* For shared libraries, "t9" needs to point at the function
4936 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4938 /* Set the return address register to point to the entry point of
4939 the program, where a breakpoint lies in wait. */
4940 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4942 /* First ensure that the stack and structure return address (if any)
4943 are properly aligned. The stack has to be at least 64-bit
4944 aligned even on 32-bit machines, because doubles must be 64-bit
4945 aligned. For n32 and n64, stack frames need to be 128-bit
4946 aligned, so we round to this widest known alignment. */
4948 sp
= align_down (sp
, 16);
4949 struct_addr
= align_down (struct_addr
, 16);
4951 /* Now make space on the stack for the args. */
4952 for (argnum
= 0; argnum
< nargs
; argnum
++)
4953 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4955 sp
-= align_up (arg_space
, 16);
4958 gdb_printf (gdb_stdlog
,
4959 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4960 paddress (gdbarch
, sp
),
4961 (long) align_up (arg_space
, 16));
4963 /* Initialize the integer and float register pointers. */
4964 argreg
= MIPS_A0_REGNUM
;
4965 float_argreg
= mips_fpa0_regnum (gdbarch
);
4967 /* The struct_return pointer occupies the first parameter-passing reg. */
4968 if (return_method
== return_method_struct
)
4971 gdb_printf (gdb_stdlog
,
4972 "mips_n32n64_push_dummy_call: "
4973 "struct_return reg=%d %s\n",
4974 argreg
, paddress (gdbarch
, struct_addr
));
4975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4978 /* Now load as many as possible of the first arguments into
4979 registers, and push the rest onto the stack. Loop thru args
4980 from first to last. */
4981 for (argnum
= 0; argnum
< nargs
; argnum
++)
4983 const gdb_byte
*val
;
4984 struct value
*arg
= args
[argnum
];
4985 struct type
*arg_type
= check_typedef (arg
->type ());
4986 int len
= arg_type
->length ();
4987 enum type_code typecode
= arg_type
->code ();
4990 gdb_printf (gdb_stdlog
,
4991 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4992 argnum
+ 1, len
, (int) typecode
);
4994 val
= arg
->contents ().data ();
4996 /* A 128-bit long double value requires an even-odd pair of
4997 floating-point registers. */
4999 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5000 && (float_argreg
& 1))
5006 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5007 && argreg
<= mips_last_arg_regnum (gdbarch
))
5009 /* This is a floating point value that fits entirely
5010 in a single register or a pair of registers. */
5011 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5012 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5014 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5015 float_argreg
, phex (regval
, reglen
));
5016 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5019 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5020 argreg
, phex (regval
, reglen
));
5021 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5026 regval
= extract_unsigned_integer (val
+ reglen
,
5027 reglen
, byte_order
);
5029 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5030 float_argreg
, phex (regval
, reglen
));
5031 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5034 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5035 argreg
, phex (regval
, reglen
));
5036 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5043 /* Copy the argument to general registers or the stack in
5044 register-sized pieces. Large arguments are split between
5045 registers and stack. */
5046 /* For N32/N64, structs, unions, or other composite types are
5047 treated as a sequence of doublewords, and are passed in integer
5048 or floating point registers as though they were simple scalar
5049 parameters to the extent that they fit, with any excess on the
5050 stack packed according to the normal memory layout of the
5052 The caller does not reserve space for the register arguments;
5053 the callee is responsible for reserving it if required. */
5054 /* Note: Floating-point values that didn't fit into an FP
5055 register are only written to memory. */
5058 /* Remember if the argument was written to the stack. */
5059 int stack_used_p
= 0;
5060 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5063 gdb_printf (gdb_stdlog
, " -- partial=%d",
5066 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5067 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5069 /* Write this portion of the argument to the stack. */
5070 if (argreg
> mips_last_arg_regnum (gdbarch
))
5072 /* Should shorter than int integer values be
5073 promoted to int before being stored? */
5074 int longword_offset
= 0;
5077 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5079 if ((typecode
== TYPE_CODE_INT
5080 || typecode
== TYPE_CODE_PTR
)
5082 longword_offset
= MIPS64_REGSIZE
- len
;
5087 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5088 paddress (gdbarch
, stack_offset
));
5089 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5090 paddress (gdbarch
, longword_offset
));
5093 addr
= sp
+ stack_offset
+ longword_offset
;
5098 gdb_printf (gdb_stdlog
, " @%s ",
5099 paddress (gdbarch
, addr
));
5100 for (i
= 0; i
< partial_len
; i
++)
5102 gdb_printf (gdb_stdlog
, "%02x",
5106 write_memory (addr
, val
, partial_len
);
5109 /* Note!!! This is NOT an else clause. Odd sized
5110 structs may go thru BOTH paths. */
5111 /* Write this portion of the argument to a general
5112 purpose register. */
5113 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5117 /* Sign extend pointers, 32-bit integers and signed
5118 16-bit and 8-bit integers; everything else is taken
5121 if ((partial_len
== 4
5122 && (typecode
== TYPE_CODE_PTR
5123 || typecode
== TYPE_CODE_INT
))
5125 && typecode
== TYPE_CODE_INT
5126 && !arg_type
->is_unsigned ()))
5127 regval
= extract_signed_integer (val
, partial_len
,
5130 regval
= extract_unsigned_integer (val
, partial_len
,
5133 /* A non-floating-point argument being passed in a
5134 general register. If a struct or union, and if
5135 the remaining length is smaller than the register
5136 size, we have to adjust the register value on
5139 It does not seem to be necessary to do the
5140 same for integral types. */
5142 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5143 && partial_len
< MIPS64_REGSIZE
5144 && (typecode
== TYPE_CODE_STRUCT
5145 || typecode
== TYPE_CODE_UNION
))
5146 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5150 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5152 phex (regval
, MIPS64_REGSIZE
));
5153 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5155 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5156 arg_type
->length () - len
))
5159 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5161 phex (regval
, MIPS64_REGSIZE
));
5162 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5173 /* Compute the offset into the stack at which we will
5174 copy the next parameter.
5176 In N32 (N64?), the stack_offset only needs to be
5177 adjusted when it has been used. */
5180 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5184 gdb_printf (gdb_stdlog
, "\n");
5187 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5189 /* Return adjusted stack pointer. */
5193 static enum return_value_convention
5194 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5195 struct type
*type
, struct regcache
*regcache
,
5196 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5198 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5200 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5202 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5203 if needed), as appropriate for the type. Composite results (struct,
5204 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5207 * A struct with only one or two floating point fields is returned in $f0
5208 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5211 * Any other composite results of at most 128 bits are returned in
5212 $2 (first 64 bits) and $3 (remainder, if necessary).
5214 * Larger composite results are handled by converting the function to a
5215 procedure with an implicit first parameter, which is a pointer to an area
5216 reserved by the caller to receive the result. [The o32-bit ABI requires
5217 that all composite results be handled by conversion to implicit first
5218 parameters. The MIPS/SGI Fortran implementation has always made a
5219 specific exception to return COMPLEX results in the floating point
5222 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5227 Name fgregdef.h) Use and Linkage
5228 -----------------------------------------------------------------
5229 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5230 ($f0) and complex type function ($f0 has the
5231 real part, $f2 has the imaginary part.) */
5233 if (type
->length () > 2 * MIPS64_REGSIZE
)
5234 return RETURN_VALUE_STRUCT_CONVENTION
;
5235 else if ((type
->code () == TYPE_CODE_COMPLEX
5236 || (type
->code () == TYPE_CODE_FLT
&& type
->length () == 16))
5237 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5239 /* A complex value of up to 128 bits in width as well as a 128-bit
5240 floating-point value goes in both $f0 and $f2. A single complex
5241 value is held in the lower halves only of the respective registers.
5242 The two registers are used in the same as memory order, so the
5243 bytes with the lower memory address are in $f0. */
5245 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5246 mips_xfer_register (gdbarch
, regcache
,
5247 (gdbarch_num_regs (gdbarch
)
5248 + mips_regnum (gdbarch
)->fp0
),
5249 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5250 readbuf
, writebuf
, 0);
5251 mips_xfer_register (gdbarch
, regcache
,
5252 (gdbarch_num_regs (gdbarch
)
5253 + mips_regnum (gdbarch
)->fp0
+ 2),
5254 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5255 readbuf
? readbuf
+ type
->length () / 2 : readbuf
,
5257 ? writebuf
+ type
->length () / 2 : writebuf
), 0);
5258 return RETURN_VALUE_REGISTER_CONVENTION
;
5260 else if (type
->code () == TYPE_CODE_FLT
5261 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5263 /* A single or double floating-point value that fits in FP0. */
5265 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5266 mips_xfer_register (gdbarch
, regcache
,
5267 (gdbarch_num_regs (gdbarch
)
5268 + mips_regnum (gdbarch
)->fp0
),
5270 gdbarch_byte_order (gdbarch
),
5271 readbuf
, writebuf
, 0);
5272 return RETURN_VALUE_REGISTER_CONVENTION
;
5274 else if (type
->code () == TYPE_CODE_STRUCT
5275 && type
->num_fields () <= 2
5276 && type
->num_fields () >= 1
5277 && ((type
->num_fields () == 1
5278 && (check_typedef (type
->field (0).type ())->code ()
5280 || (type
->num_fields () == 2
5281 && (check_typedef (type
->field (0).type ())->code ()
5283 && (check_typedef (type
->field (1).type ())->code ()
5284 == TYPE_CODE_FLT
))))
5286 /* A struct that contains one or two floats. Each value is part
5287 in the least significant part of their floating point
5288 register (or GPR, for soft float). */
5291 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5292 ? mips_regnum (gdbarch
)->fp0
5294 field
< type
->num_fields (); field
++, regnum
+= 2)
5296 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5298 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5300 if (type
->field (field
).type ()->length () == 16)
5302 /* A 16-byte long double field goes in two consecutive
5304 mips_xfer_register (gdbarch
, regcache
,
5305 gdbarch_num_regs (gdbarch
) + regnum
,
5307 gdbarch_byte_order (gdbarch
),
5308 readbuf
, writebuf
, offset
);
5309 mips_xfer_register (gdbarch
, regcache
,
5310 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5312 gdbarch_byte_order (gdbarch
),
5313 readbuf
, writebuf
, offset
+ 8);
5316 mips_xfer_register (gdbarch
, regcache
,
5317 gdbarch_num_regs (gdbarch
) + regnum
,
5318 type
->field (field
).type ()->length (),
5319 gdbarch_byte_order (gdbarch
),
5320 readbuf
, writebuf
, offset
);
5322 return RETURN_VALUE_REGISTER_CONVENTION
;
5324 else if (type
->code () == TYPE_CODE_STRUCT
5325 || type
->code () == TYPE_CODE_UNION
5326 || type
->code () == TYPE_CODE_ARRAY
)
5328 /* A composite type. Extract the left justified value,
5329 regardless of the byte order. I.e. DO NOT USE
5333 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5334 offset
< type
->length ();
5335 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5337 int xfer
= register_size (gdbarch
, regnum
);
5338 if (offset
+ xfer
> type
->length ())
5339 xfer
= type
->length () - offset
;
5341 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5342 offset
, xfer
, regnum
);
5343 mips_xfer_register (gdbarch
, regcache
,
5344 gdbarch_num_regs (gdbarch
) + regnum
,
5345 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5348 return RETURN_VALUE_REGISTER_CONVENTION
;
5352 /* A scalar extract each part but least-significant-byte
5356 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5357 offset
< type
->length ();
5358 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5360 int xfer
= register_size (gdbarch
, regnum
);
5361 if (offset
+ xfer
> type
->length ())
5362 xfer
= type
->length () - offset
;
5364 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5365 offset
, xfer
, regnum
);
5366 mips_xfer_register (gdbarch
, regcache
,
5367 gdbarch_num_regs (gdbarch
) + regnum
,
5368 xfer
, gdbarch_byte_order (gdbarch
),
5369 readbuf
, writebuf
, offset
);
5371 return RETURN_VALUE_REGISTER_CONVENTION
;
5375 /* Which registers to use for passing floating-point values between
5376 function calls, one of floating-point, general and both kinds of
5377 registers. O32 and O64 use different register kinds for standard
5378 MIPS and MIPS16 code; to make the handling of cases where we may
5379 not know what kind of code is being used (e.g. no debug information)
5380 easier we sometimes use both kinds. */
5389 /* O32 ABI stuff. */
5392 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5393 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5394 int nargs
, struct value
**args
, CORE_ADDR sp
,
5395 function_call_return_method return_method
,
5396 CORE_ADDR struct_addr
)
5402 int stack_offset
= 0;
5403 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5404 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5406 /* For shared libraries, "t9" needs to point at the function
5408 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5410 /* Set the return address register to point to the entry point of
5411 the program, where a breakpoint lies in wait. */
5412 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5414 /* First ensure that the stack and structure return address (if any)
5415 are properly aligned. The stack has to be at least 64-bit
5416 aligned even on 32-bit machines, because doubles must be 64-bit
5417 aligned. For n32 and n64, stack frames need to be 128-bit
5418 aligned, so we round to this widest known alignment. */
5420 sp
= align_down (sp
, 16);
5421 struct_addr
= align_down (struct_addr
, 16);
5423 /* Now make space on the stack for the args. */
5424 for (argnum
= 0; argnum
< nargs
; argnum
++)
5426 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5428 /* Align to double-word if necessary. */
5429 if (mips_type_needs_double_align (arg_type
))
5430 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5431 /* Allocate space on the stack. */
5432 arg_space
+= align_up (arg_type
->length (), MIPS32_REGSIZE
);
5434 sp
-= align_up (arg_space
, 16);
5437 gdb_printf (gdb_stdlog
,
5438 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5439 paddress (gdbarch
, sp
),
5440 (long) align_up (arg_space
, 16));
5442 /* Initialize the integer and float register pointers. */
5443 argreg
= MIPS_A0_REGNUM
;
5444 float_argreg
= mips_fpa0_regnum (gdbarch
);
5446 /* The struct_return pointer occupies the first parameter-passing reg. */
5447 if (return_method
== return_method_struct
)
5450 gdb_printf (gdb_stdlog
,
5451 "mips_o32_push_dummy_call: "
5452 "struct_return reg=%d %s\n",
5453 argreg
, paddress (gdbarch
, struct_addr
));
5454 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5455 stack_offset
+= MIPS32_REGSIZE
;
5458 /* Now load as many as possible of the first arguments into
5459 registers, and push the rest onto the stack. Loop thru args
5460 from first to last. */
5461 for (argnum
= 0; argnum
< nargs
; argnum
++)
5463 const gdb_byte
*val
;
5464 struct value
*arg
= args
[argnum
];
5465 struct type
*arg_type
= check_typedef (arg
->type ());
5466 int len
= arg_type
->length ();
5467 enum type_code typecode
= arg_type
->code ();
5470 gdb_printf (gdb_stdlog
,
5471 "mips_o32_push_dummy_call: %d len=%d type=%d",
5472 argnum
+ 1, len
, (int) typecode
);
5474 val
= arg
->contents ().data ();
5476 /* 32-bit ABIs always start floating point arguments in an
5477 even-numbered floating point register. Round the FP register
5478 up before the check to see if there are any FP registers
5479 left. O32 targets also pass the FP in the integer registers
5480 so also round up normal registers. */
5481 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5483 if ((float_argreg
& 1))
5487 /* Floating point arguments passed in registers have to be
5488 treated specially. On 32-bit architectures, doubles are
5489 passed in register pairs; the even FP register gets the
5490 low word, and the odd FP register gets the high word.
5491 On O32, the first two floating point arguments are also
5492 copied to general registers, following their memory order,
5493 because MIPS16 functions don't use float registers for
5494 arguments. This duplication of arguments in general
5495 registers can't hurt non-MIPS16 functions, because those
5496 registers are normally skipped. */
5498 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5499 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5501 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5503 int freg_offset
= gdbarch_byte_order (gdbarch
)
5504 == BFD_ENDIAN_BIG
? 1 : 0;
5505 unsigned long regval
;
5508 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5510 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5511 float_argreg
+ freg_offset
,
5513 regcache_cooked_write_unsigned (regcache
,
5514 float_argreg
++ + freg_offset
,
5517 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5518 argreg
, phex (regval
, 4));
5519 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5522 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5524 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5525 float_argreg
- freg_offset
,
5527 regcache_cooked_write_unsigned (regcache
,
5528 float_argreg
++ - freg_offset
,
5531 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5532 argreg
, phex (regval
, 4));
5533 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5537 /* This is a floating point value that fits entirely
5538 in a single register. */
5539 /* On 32 bit ABI's the float_argreg is further adjusted
5540 above to ensure that it is even register aligned. */
5541 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5543 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5544 float_argreg
, phex (regval
, len
));
5545 regcache_cooked_write_unsigned (regcache
,
5546 float_argreg
++, regval
);
5547 /* Although two FP registers are reserved for each
5548 argument, only one corresponding integer register is
5551 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5552 argreg
, phex (regval
, len
));
5553 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5555 /* Reserve space for the FP register. */
5556 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5560 /* Copy the argument to general registers or the stack in
5561 register-sized pieces. Large arguments are split between
5562 registers and stack. */
5563 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5564 are treated specially: Irix cc passes
5565 them in registers where gcc sometimes puts them on the
5566 stack. For maximum compatibility, we will put them in
5568 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5569 && len
% MIPS32_REGSIZE
!= 0);
5570 /* Structures should be aligned to eight bytes (even arg registers)
5571 on MIPS_ABI_O32, if their first member has double precision. */
5572 if (mips_type_needs_double_align (arg_type
))
5577 stack_offset
+= MIPS32_REGSIZE
;
5582 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5585 gdb_printf (gdb_stdlog
, " -- partial=%d",
5588 /* Write this portion of the argument to the stack. */
5589 if (argreg
> mips_last_arg_regnum (gdbarch
)
5590 || odd_sized_struct
)
5592 /* Should shorter than int integer values be
5593 promoted to int before being stored? */
5594 int longword_offset
= 0;
5599 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5600 paddress (gdbarch
, stack_offset
));
5601 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5602 paddress (gdbarch
, longword_offset
));
5605 addr
= sp
+ stack_offset
+ longword_offset
;
5610 gdb_printf (gdb_stdlog
, " @%s ",
5611 paddress (gdbarch
, addr
));
5612 for (i
= 0; i
< partial_len
; i
++)
5614 gdb_printf (gdb_stdlog
, "%02x",
5618 write_memory (addr
, val
, partial_len
);
5621 /* Note!!! This is NOT an else clause. Odd sized
5622 structs may go thru BOTH paths. */
5623 /* Write this portion of the argument to a general
5624 purpose register. */
5625 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5627 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5629 /* Value may need to be sign extended, because
5630 mips_isa_regsize() != mips_abi_regsize(). */
5632 /* A non-floating-point argument being passed in a
5633 general register. If a struct or union, and if
5634 the remaining length is smaller than the register
5635 size, we have to adjust the register value on
5638 It does not seem to be necessary to do the
5639 same for integral types.
5641 Also don't do this adjustment on O64 binaries.
5643 cagney/2001-07-23: gdb/179: Also, GCC, when
5644 outputting LE O32 with sizeof (struct) <
5645 mips_abi_regsize(), generates a left shift
5646 as part of storing the argument in a register
5647 (the left shift isn't generated when
5648 sizeof (struct) >= mips_abi_regsize()). Since
5649 it is quite possible that this is GCC
5650 contradicting the LE/O32 ABI, GDB has not been
5651 adjusted to accommodate this. Either someone
5652 needs to demonstrate that the LE/O32 ABI
5653 specifies such a left shift OR this new ABI gets
5654 identified as such and GDB gets tweaked
5657 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5658 && partial_len
< MIPS32_REGSIZE
5659 && (typecode
== TYPE_CODE_STRUCT
5660 || typecode
== TYPE_CODE_UNION
))
5661 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5665 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5667 phex (regval
, MIPS32_REGSIZE
));
5668 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5671 /* Prevent subsequent floating point arguments from
5672 being passed in floating point registers. */
5673 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5679 /* Compute the offset into the stack at which we will
5680 copy the next parameter.
5682 In older ABIs, the caller reserved space for
5683 registers that contained arguments. This was loosely
5684 referred to as their "home". Consequently, space is
5685 always allocated. */
5687 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5691 gdb_printf (gdb_stdlog
, "\n");
5694 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5696 /* Return adjusted stack pointer. */
5700 static enum return_value_convention
5701 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5702 struct type
*type
, struct regcache
*regcache
,
5703 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5705 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5706 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5707 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5708 enum mips_fval_reg fval_reg
;
5710 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5711 if (type
->code () == TYPE_CODE_STRUCT
5712 || type
->code () == TYPE_CODE_UNION
5713 || type
->code () == TYPE_CODE_ARRAY
)
5714 return RETURN_VALUE_STRUCT_CONVENTION
;
5715 else if (type
->code () == TYPE_CODE_FLT
5716 && type
->length () == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5718 /* A single-precision floating-point value. If reading in or copying,
5719 then we get it from/put it to FP0 for standard MIPS code or GPR2
5720 for MIPS16 code. If writing out only, then we put it to both FP0
5721 and GPR2. We do not support reading in with no function known, if
5722 this safety check ever triggers, then we'll have to try harder. */
5723 gdb_assert (function
|| !readbuf
);
5728 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5731 gdb_printf (gdb_stderr
, "Return float in $2\n");
5733 case mips_fval_both
:
5734 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5737 if (fval_reg
!= mips_fval_gpr
)
5738 mips_xfer_register (gdbarch
, regcache
,
5739 (gdbarch_num_regs (gdbarch
)
5740 + mips_regnum (gdbarch
)->fp0
),
5742 gdbarch_byte_order (gdbarch
),
5743 readbuf
, writebuf
, 0);
5744 if (fval_reg
!= mips_fval_fpr
)
5745 mips_xfer_register (gdbarch
, regcache
,
5746 gdbarch_num_regs (gdbarch
) + 2,
5748 gdbarch_byte_order (gdbarch
),
5749 readbuf
, writebuf
, 0);
5750 return RETURN_VALUE_REGISTER_CONVENTION
;
5752 else if (type
->code () == TYPE_CODE_FLT
5753 && type
->length () == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5755 /* A double-precision floating-point value. If reading in or copying,
5756 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5757 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5758 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5759 no function known, if this safety check ever triggers, then we'll
5760 have to try harder. */
5761 gdb_assert (function
|| !readbuf
);
5766 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5769 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5771 case mips_fval_both
:
5772 gdb_printf (gdb_stderr
,
5773 "Return float in $fp1/$fp0 and $2/$3\n");
5776 if (fval_reg
!= mips_fval_gpr
)
5778 /* The most significant part goes in FP1, and the least significant
5780 switch (gdbarch_byte_order (gdbarch
))
5782 case BFD_ENDIAN_LITTLE
:
5783 mips_xfer_register (gdbarch
, regcache
,
5784 (gdbarch_num_regs (gdbarch
)
5785 + mips_regnum (gdbarch
)->fp0
+ 0),
5786 4, gdbarch_byte_order (gdbarch
),
5787 readbuf
, writebuf
, 0);
5788 mips_xfer_register (gdbarch
, regcache
,
5789 (gdbarch_num_regs (gdbarch
)
5790 + mips_regnum (gdbarch
)->fp0
+ 1),
5791 4, gdbarch_byte_order (gdbarch
),
5792 readbuf
, writebuf
, 4);
5794 case BFD_ENDIAN_BIG
:
5795 mips_xfer_register (gdbarch
, regcache
,
5796 (gdbarch_num_regs (gdbarch
)
5797 + mips_regnum (gdbarch
)->fp0
+ 1),
5798 4, gdbarch_byte_order (gdbarch
),
5799 readbuf
, writebuf
, 0);
5800 mips_xfer_register (gdbarch
, regcache
,
5801 (gdbarch_num_regs (gdbarch
)
5802 + mips_regnum (gdbarch
)->fp0
+ 0),
5803 4, gdbarch_byte_order (gdbarch
),
5804 readbuf
, writebuf
, 4);
5807 internal_error (_("bad switch"));
5810 if (fval_reg
!= mips_fval_fpr
)
5812 /* The two 32-bit parts are always placed in GPR2 and GPR3
5813 following these registers' memory order. */
5814 mips_xfer_register (gdbarch
, regcache
,
5815 gdbarch_num_regs (gdbarch
) + 2,
5816 4, gdbarch_byte_order (gdbarch
),
5817 readbuf
, writebuf
, 0);
5818 mips_xfer_register (gdbarch
, regcache
,
5819 gdbarch_num_regs (gdbarch
) + 3,
5820 4, gdbarch_byte_order (gdbarch
),
5821 readbuf
, writebuf
, 4);
5823 return RETURN_VALUE_REGISTER_CONVENTION
;
5826 else if (type
->code () == TYPE_CODE_STRUCT
5827 && type
->num_fields () <= 2
5828 && type
->num_fields () >= 1
5829 && ((type
->num_fields () == 1
5830 && (TYPE_CODE (type
->field (0).type ())
5832 || (type
->num_fields () == 2
5833 && (TYPE_CODE (type
->field (0).type ())
5835 && (TYPE_CODE (type
->field (1).type ())
5837 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5839 /* A struct that contains one or two floats. Each value is part
5840 in the least significant part of their floating point
5844 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5845 field
< type
->num_fields (); field
++, regnum
+= 2)
5847 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5849 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5851 mips_xfer_register (gdbarch
, regcache
,
5852 gdbarch_num_regs (gdbarch
) + regnum
,
5853 TYPE_LENGTH (type
->field (field
).type ()),
5854 gdbarch_byte_order (gdbarch
),
5855 readbuf
, writebuf
, offset
);
5857 return RETURN_VALUE_REGISTER_CONVENTION
;
5861 else if (type
->code () == TYPE_CODE_STRUCT
5862 || type
->code () == TYPE_CODE_UNION
)
5864 /* A structure or union. Extract the left justified value,
5865 regardless of the byte order. I.e. DO NOT USE
5869 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5870 offset
< type
->length ();
5871 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5873 int xfer
= register_size (gdbarch
, regnum
);
5874 if (offset
+ xfer
> type
->length ())
5875 xfer
= type
->length () - offset
;
5877 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5878 offset
, xfer
, regnum
);
5879 mips_xfer_register (gdbarch
, regcache
,
5880 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5881 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5883 return RETURN_VALUE_REGISTER_CONVENTION
;
5888 /* A scalar extract each part but least-significant-byte
5889 justified. o32 thinks registers are 4 byte, regardless of
5893 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5894 offset
< type
->length ();
5895 offset
+= MIPS32_REGSIZE
, regnum
++)
5897 int xfer
= MIPS32_REGSIZE
;
5898 if (offset
+ xfer
> type
->length ())
5899 xfer
= type
->length () - offset
;
5901 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5902 offset
, xfer
, regnum
);
5903 mips_xfer_register (gdbarch
, regcache
,
5904 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5905 gdbarch_byte_order (gdbarch
),
5906 readbuf
, writebuf
, offset
);
5908 return RETURN_VALUE_REGISTER_CONVENTION
;
5912 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5916 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5917 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5919 struct value
**args
, CORE_ADDR sp
,
5920 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5926 int stack_offset
= 0;
5927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5928 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5930 /* For shared libraries, "t9" needs to point at the function
5932 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5934 /* Set the return address register to point to the entry point of
5935 the program, where a breakpoint lies in wait. */
5936 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5938 /* First ensure that the stack and structure return address (if any)
5939 are properly aligned. The stack has to be at least 64-bit
5940 aligned even on 32-bit machines, because doubles must be 64-bit
5941 aligned. For n32 and n64, stack frames need to be 128-bit
5942 aligned, so we round to this widest known alignment. */
5944 sp
= align_down (sp
, 16);
5945 struct_addr
= align_down (struct_addr
, 16);
5947 /* Now make space on the stack for the args. */
5948 for (argnum
= 0; argnum
< nargs
; argnum
++)
5950 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5952 /* Allocate space on the stack. */
5953 arg_space
+= align_up (arg_type
->length (), MIPS64_REGSIZE
);
5955 sp
-= align_up (arg_space
, 16);
5958 gdb_printf (gdb_stdlog
,
5959 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5960 paddress (gdbarch
, sp
),
5961 (long) align_up (arg_space
, 16));
5963 /* Initialize the integer and float register pointers. */
5964 argreg
= MIPS_A0_REGNUM
;
5965 float_argreg
= mips_fpa0_regnum (gdbarch
);
5967 /* The struct_return pointer occupies the first parameter-passing reg. */
5968 if (return_method
== return_method_struct
)
5971 gdb_printf (gdb_stdlog
,
5972 "mips_o64_push_dummy_call: "
5973 "struct_return reg=%d %s\n",
5974 argreg
, paddress (gdbarch
, struct_addr
));
5975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5976 stack_offset
+= MIPS64_REGSIZE
;
5979 /* Now load as many as possible of the first arguments into
5980 registers, and push the rest onto the stack. Loop thru args
5981 from first to last. */
5982 for (argnum
= 0; argnum
< nargs
; argnum
++)
5984 const gdb_byte
*val
;
5985 struct value
*arg
= args
[argnum
];
5986 struct type
*arg_type
= check_typedef (arg
->type ());
5987 int len
= arg_type
->length ();
5988 enum type_code typecode
= arg_type
->code ();
5991 gdb_printf (gdb_stdlog
,
5992 "mips_o64_push_dummy_call: %d len=%d type=%d",
5993 argnum
+ 1, len
, (int) typecode
);
5995 val
= arg
->contents ().data ();
5997 /* Floating point arguments passed in registers have to be
5998 treated specially. On 32-bit architectures, doubles are
5999 passed in register pairs; the even FP register gets the
6000 low word, and the odd FP register gets the high word.
6001 On O64, the first two floating point arguments are also
6002 copied to general registers, because MIPS16 functions
6003 don't use float registers for arguments. This duplication
6004 of arguments in general registers can't hurt non-MIPS16
6005 functions because those registers are normally skipped. */
6007 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6008 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6010 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6012 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6013 float_argreg
, phex (regval
, len
));
6014 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6016 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6017 argreg
, phex (regval
, len
));
6018 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6020 /* Reserve space for the FP register. */
6021 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6025 /* Copy the argument to general registers or the stack in
6026 register-sized pieces. Large arguments are split between
6027 registers and stack. */
6028 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6029 are treated specially: Irix cc passes them in registers
6030 where gcc sometimes puts them on the stack. For maximum
6031 compatibility, we will put them in both places. */
6032 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6033 && len
% MIPS64_REGSIZE
!= 0);
6036 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6039 gdb_printf (gdb_stdlog
, " -- partial=%d",
6042 /* Write this portion of the argument to the stack. */
6043 if (argreg
> mips_last_arg_regnum (gdbarch
)
6044 || odd_sized_struct
)
6046 /* Should shorter than int integer values be
6047 promoted to int before being stored? */
6048 int longword_offset
= 0;
6050 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6052 if ((typecode
== TYPE_CODE_INT
6053 || typecode
== TYPE_CODE_PTR
6054 || typecode
== TYPE_CODE_FLT
)
6056 longword_offset
= MIPS64_REGSIZE
- len
;
6061 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6062 paddress (gdbarch
, stack_offset
));
6063 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6064 paddress (gdbarch
, longword_offset
));
6067 addr
= sp
+ stack_offset
+ longword_offset
;
6072 gdb_printf (gdb_stdlog
, " @%s ",
6073 paddress (gdbarch
, addr
));
6074 for (i
= 0; i
< partial_len
; i
++)
6076 gdb_printf (gdb_stdlog
, "%02x",
6080 write_memory (addr
, val
, partial_len
);
6083 /* Note!!! This is NOT an else clause. Odd sized
6084 structs may go thru BOTH paths. */
6085 /* Write this portion of the argument to a general
6086 purpose register. */
6087 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6089 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6091 /* Value may need to be sign extended, because
6092 mips_isa_regsize() != mips_abi_regsize(). */
6094 /* A non-floating-point argument being passed in a
6095 general register. If a struct or union, and if
6096 the remaining length is smaller than the register
6097 size, we have to adjust the register value on
6100 It does not seem to be necessary to do the
6101 same for integral types. */
6103 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6104 && partial_len
< MIPS64_REGSIZE
6105 && (typecode
== TYPE_CODE_STRUCT
6106 || typecode
== TYPE_CODE_UNION
))
6107 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6111 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6113 phex (regval
, MIPS64_REGSIZE
));
6114 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6117 /* Prevent subsequent floating point arguments from
6118 being passed in floating point registers. */
6119 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6125 /* Compute the offset into the stack at which we will
6126 copy the next parameter.
6128 In older ABIs, the caller reserved space for
6129 registers that contained arguments. This was loosely
6130 referred to as their "home". Consequently, space is
6131 always allocated. */
6133 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6137 gdb_printf (gdb_stdlog
, "\n");
6140 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6142 /* Return adjusted stack pointer. */
6146 static enum return_value_convention
6147 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6148 struct type
*type
, struct regcache
*regcache
,
6149 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6151 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6152 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6153 enum mips_fval_reg fval_reg
;
6155 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6156 if (type
->code () == TYPE_CODE_STRUCT
6157 || type
->code () == TYPE_CODE_UNION
6158 || type
->code () == TYPE_CODE_ARRAY
)
6159 return RETURN_VALUE_STRUCT_CONVENTION
;
6160 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6162 /* A floating-point value. If reading in or copying, then we get it
6163 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6164 If writing out only, then we put it to both FP0 and GPR2. We do
6165 not support reading in with no function known, if this safety
6166 check ever triggers, then we'll have to try harder. */
6167 gdb_assert (function
|| !readbuf
);
6172 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6175 gdb_printf (gdb_stderr
, "Return float in $2\n");
6177 case mips_fval_both
:
6178 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6181 if (fval_reg
!= mips_fval_gpr
)
6182 mips_xfer_register (gdbarch
, regcache
,
6183 (gdbarch_num_regs (gdbarch
)
6184 + mips_regnum (gdbarch
)->fp0
),
6186 gdbarch_byte_order (gdbarch
),
6187 readbuf
, writebuf
, 0);
6188 if (fval_reg
!= mips_fval_fpr
)
6189 mips_xfer_register (gdbarch
, regcache
,
6190 gdbarch_num_regs (gdbarch
) + 2,
6192 gdbarch_byte_order (gdbarch
),
6193 readbuf
, writebuf
, 0);
6194 return RETURN_VALUE_REGISTER_CONVENTION
;
6198 /* A scalar extract each part but least-significant-byte
6202 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6203 offset
< type
->length ();
6204 offset
+= MIPS64_REGSIZE
, regnum
++)
6206 int xfer
= MIPS64_REGSIZE
;
6207 if (offset
+ xfer
> type
->length ())
6208 xfer
= type
->length () - offset
;
6210 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6211 offset
, xfer
, regnum
);
6212 mips_xfer_register (gdbarch
, regcache
,
6213 gdbarch_num_regs (gdbarch
) + regnum
,
6214 xfer
, gdbarch_byte_order (gdbarch
),
6215 readbuf
, writebuf
, offset
);
6217 return RETURN_VALUE_REGISTER_CONVENTION
;
6221 /* Floating point register management.
6223 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6224 64bit operations, these early MIPS cpus treat fp register pairs
6225 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6226 registers and offer a compatibility mode that emulates the MIPS2 fp
6227 model. When operating in MIPS2 fp compat mode, later cpu's split
6228 double precision floats into two 32-bit chunks and store them in
6229 consecutive fp regs. To display 64-bit floats stored in this
6230 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6231 Throw in user-configurable endianness and you have a real mess.
6233 The way this works is:
6234 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6235 double-precision value will be split across two logical registers.
6236 The lower-numbered logical register will hold the low-order bits,
6237 regardless of the processor's endianness.
6238 - If we are on a 64-bit processor, and we are looking for a
6239 single-precision value, it will be in the low ordered bits
6240 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6241 save slot in memory.
6242 - If we are in 64-bit mode, everything is straightforward.
6244 Note that this code only deals with "live" registers at the top of the
6245 stack. We will attempt to deal with saved registers later, when
6246 the raw/cooked register interface is in place. (We need a general
6247 interface that can deal with dynamic saved register sizes -- fp
6248 regs could be 32 bits wide in one frame and 64 on the frame above
6251 /* Copy a 32-bit single-precision value from the current frame
6252 into rare_buffer. */
6255 mips_read_fp_register_single (frame_info_ptr frame
, int regno
,
6256 gdb_byte
*rare_buffer
)
6258 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6259 int raw_size
= register_size (gdbarch
, regno
);
6260 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6262 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6263 error (_("can't read register %d (%s)"),
6264 regno
, gdbarch_register_name (gdbarch
, regno
));
6267 /* We have a 64-bit value for this register. Find the low-order
6271 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6276 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6280 memcpy (rare_buffer
, raw_buffer
, 4);
6284 /* Copy a 64-bit double-precision value from the current frame into
6285 rare_buffer. This may include getting half of it from the next
6289 mips_read_fp_register_double (frame_info_ptr frame
, int regno
,
6290 gdb_byte
*rare_buffer
)
6292 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6293 int raw_size
= register_size (gdbarch
, regno
);
6295 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6297 /* We have a 64-bit value for this register, and we should use
6299 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6300 error (_("can't read register %d (%s)"),
6301 regno
, gdbarch_register_name (gdbarch
, regno
));
6305 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6307 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6308 internal_error (_("mips_read_fp_register_double: bad access to "
6309 "odd-numbered FP register"));
6311 /* mips_read_fp_register_single will find the correct 32 bits from
6313 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6315 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6316 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6320 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6321 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6327 mips_print_fp_register (struct ui_file
*file
, frame_info_ptr frame
,
6329 { /* Do values for FP (float) regs. */
6330 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6331 gdb_byte
*raw_buffer
;
6332 std::string flt_str
, dbl_str
;
6334 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6335 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6339 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6341 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6342 gdb_printf (file
, "%*s",
6343 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6346 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6348 struct value_print_options opts
;
6350 /* 4-byte registers: Print hex and floating. Also print even
6351 numbered registers as doubles. */
6352 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6353 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6355 get_formatted_print_options (&opts
, 'x');
6356 print_scalar_formatted (raw_buffer
,
6357 builtin_type (gdbarch
)->builtin_uint32
,
6360 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6362 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6364 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6365 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6367 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6372 struct value_print_options opts
;
6374 /* Eight byte registers: print each one as hex, float and double. */
6375 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6376 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6378 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6379 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6381 get_formatted_print_options (&opts
, 'x');
6382 print_scalar_formatted (raw_buffer
,
6383 builtin_type (gdbarch
)->builtin_uint64
,
6386 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6387 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6392 mips_print_register (struct ui_file
*file
, frame_info_ptr frame
,
6395 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6396 struct value_print_options opts
;
6399 if (mips_float_register_p (gdbarch
, regnum
))
6401 mips_print_fp_register (file
, frame
, regnum
);
6405 val
= get_frame_register_value (frame
, regnum
);
6407 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6409 /* The problem with printing numeric register names (r26, etc.) is that
6410 the user can't use them on input. Probably the best solution is to
6411 fix it so that either the numeric or the funky (a2, etc.) names
6412 are accepted on input. */
6413 if (regnum
< MIPS_NUMREGS
)
6414 gdb_printf (file
, "(r%d): ", regnum
);
6416 gdb_printf (file
, ": ");
6418 get_formatted_print_options (&opts
, 'x');
6419 value_print_scalar_formatted (val
, &opts
, 0, file
);
6422 /* Print IEEE exception condition bits in FLAGS. */
6425 print_fpu_flags (struct ui_file
*file
, int flags
)
6427 if (flags
& (1 << 0))
6428 gdb_puts (" inexact", file
);
6429 if (flags
& (1 << 1))
6430 gdb_puts (" uflow", file
);
6431 if (flags
& (1 << 2))
6432 gdb_puts (" oflow", file
);
6433 if (flags
& (1 << 3))
6434 gdb_puts (" div0", file
);
6435 if (flags
& (1 << 4))
6436 gdb_puts (" inval", file
);
6437 if (flags
& (1 << 5))
6438 gdb_puts (" unimp", file
);
6439 gdb_putc ('\n', file
);
6442 /* Print interesting information about the floating point processor
6443 (if present) or emulator. */
6446 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6447 frame_info_ptr frame
, const char *args
)
6449 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6450 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6454 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6455 type
= MIPS_FPU_NONE
;
6457 gdb_printf (file
, "fpu type: %s\n",
6458 type
== MIPS_FPU_DOUBLE
? "double-precision"
6459 : type
== MIPS_FPU_SINGLE
? "single-precision"
6462 if (type
== MIPS_FPU_NONE
)
6465 gdb_printf (file
, "reg size: %d bits\n",
6466 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6468 gdb_puts ("cond :", file
);
6469 if (fcs
& (1 << 23))
6470 gdb_puts (" 0", file
);
6471 for (i
= 1; i
<= 7; i
++)
6472 if (fcs
& (1 << (24 + i
)))
6473 gdb_printf (file
, " %d", i
);
6474 gdb_putc ('\n', file
);
6476 gdb_puts ("cause :", file
);
6477 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6478 fputs ("mask :", stdout
);
6479 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6480 fputs ("flags :", stdout
);
6481 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6483 gdb_puts ("rounding: ", file
);
6486 case 0: gdb_puts ("nearest\n", file
); break;
6487 case 1: gdb_puts ("zero\n", file
); break;
6488 case 2: gdb_puts ("+inf\n", file
); break;
6489 case 3: gdb_puts ("-inf\n", file
); break;
6492 gdb_puts ("flush :", file
);
6493 if (fcs
& (1 << 21))
6494 gdb_puts (" nearest", file
);
6495 if (fcs
& (1 << 22))
6496 gdb_puts (" override", file
);
6497 if (fcs
& (1 << 24))
6498 gdb_puts (" zero", file
);
6499 if ((fcs
& (0xb << 21)) == 0)
6500 gdb_puts (" no", file
);
6501 gdb_putc ('\n', file
);
6503 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6504 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6505 gdb_putc ('\n', file
);
6507 default_print_float_info (gdbarch
, file
, frame
, args
);
6510 /* Replacement for generic do_registers_info.
6511 Print regs in pretty columns. */
6514 print_fp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6517 gdb_printf (file
, " ");
6518 mips_print_fp_register (file
, frame
, regnum
);
6519 gdb_printf (file
, "\n");
6524 /* Print a row's worth of GP (int) registers, with name labels above. */
6527 print_gp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6530 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6531 /* Do values for GP (int) regs. */
6532 const gdb_byte
*raw_buffer
;
6533 struct value
*value
;
6534 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6539 /* For GP registers, we print a separate row of names above the vals. */
6540 for (col
= 0, regnum
= start_regnum
;
6541 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6544 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6545 continue; /* unused register */
6546 if (mips_float_register_p (gdbarch
, regnum
))
6547 break; /* End the row: reached FP register. */
6548 /* Large registers are handled separately. */
6549 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6552 break; /* End the row before this register. */
6554 /* Print this register on a row by itself. */
6555 mips_print_register (file
, frame
, regnum
);
6556 gdb_printf (file
, "\n");
6560 gdb_printf (file
, " ");
6562 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6563 gdbarch_register_name (gdbarch
, regnum
));
6570 /* Print the R0 to R31 names. */
6571 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6572 gdb_printf (file
, "\n R%-4d",
6573 start_regnum
% gdbarch_num_regs (gdbarch
));
6575 gdb_printf (file
, "\n ");
6577 /* Now print the values in hex, 4 or 8 to the row. */
6578 for (col
= 0, regnum
= start_regnum
;
6579 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6582 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6583 continue; /* unused register */
6584 if (mips_float_register_p (gdbarch
, regnum
))
6585 break; /* End row: reached FP register. */
6586 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6587 break; /* End row: large register. */
6589 /* OK: get the data in raw format. */
6590 value
= get_frame_register_value (frame
, regnum
);
6591 if (value
->optimized_out ()
6592 || !value
->entirely_available ())
6594 gdb_printf (file
, "%*s ",
6595 (int) mips_abi_regsize (gdbarch
) * 2,
6596 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6597 : "<unavailable>"));
6601 raw_buffer
= value
->contents_all ().data ();
6602 /* pad small registers */
6604 byte
< (mips_abi_regsize (gdbarch
)
6605 - register_size (gdbarch
, regnum
)); byte
++)
6606 gdb_printf (file
, " ");
6607 /* Now print the register value in hex, endian order. */
6608 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6610 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6611 byte
< register_size (gdbarch
, regnum
); byte
++)
6612 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6614 for (byte
= register_size (gdbarch
, regnum
) - 1;
6616 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6617 gdb_printf (file
, " ");
6620 if (col
> 0) /* ie. if we actually printed anything... */
6621 gdb_printf (file
, "\n");
6626 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6629 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6630 frame_info_ptr frame
, int regnum
, int all
)
6632 if (regnum
!= -1) /* Do one specified register. */
6634 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6635 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6636 error (_("Not a valid register for the current processor type"));
6638 mips_print_register (file
, frame
, regnum
);
6639 gdb_printf (file
, "\n");
6642 /* Do all (or most) registers. */
6644 regnum
= gdbarch_num_regs (gdbarch
);
6645 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6647 if (mips_float_register_p (gdbarch
, regnum
))
6649 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6650 regnum
= print_fp_register_row (file
, frame
, regnum
);
6652 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6655 regnum
= print_gp_register_row (file
, frame
, regnum
);
6661 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6662 frame_info_ptr frame
)
6664 CORE_ADDR pc
= get_frame_pc (frame
);
6669 if ((mips_pc_is_mips (pc
)
6670 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6671 || (mips_pc_is_micromips (gdbarch
, pc
)
6672 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6673 || (mips_pc_is_mips16 (gdbarch
, pc
)
6674 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6677 isa
= mips_pc_isa (gdbarch
, pc
);
6678 /* _has_delay_slot above will have validated the read. */
6679 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6680 size
= mips_insn_size (isa
, insn
);
6682 const address_space
*aspace
= get_frame_address_space (frame
);
6684 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6687 /* To skip prologues, I use this predicate. Returns either PC itself
6688 if the code at PC does not look like a function prologue; otherwise
6689 returns an address that (if we're lucky) follows the prologue. If
6690 LENIENT, then we must skip everything which is involved in setting
6691 up the frame (it's OK to skip more, just so long as we don't skip
6692 anything which might clobber the registers which are being saved.
6693 We must skip more in the case where part of the prologue is in the
6694 delay slot of a non-prologue instruction). */
6697 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6700 CORE_ADDR func_addr
;
6702 /* See if we can determine the end of the prologue via the symbol table.
6703 If so, then return either PC, or the PC after the prologue, whichever
6705 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6707 CORE_ADDR post_prologue_pc
6708 = skip_prologue_using_sal (gdbarch
, func_addr
);
6709 if (post_prologue_pc
!= 0)
6710 return std::max (pc
, post_prologue_pc
);
6713 /* Can't determine prologue from the symbol table, need to examine
6716 /* Find an upper limit on the function prologue using the debug
6717 information. If the debug information could not be used to provide
6718 that bound, then use an arbitrary large number as the upper bound. */
6719 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6721 limit_pc
= pc
+ 100; /* Magic. */
6723 if (mips_pc_is_mips16 (gdbarch
, pc
))
6724 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6725 else if (mips_pc_is_micromips (gdbarch
, pc
))
6726 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6728 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6731 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6732 This is a helper function for mips_stack_frame_destroyed_p. */
6735 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6737 CORE_ADDR func_addr
= 0, func_end
= 0;
6739 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6741 /* The MIPS epilogue is max. 12 bytes long. */
6742 CORE_ADDR addr
= func_end
- 12;
6744 if (addr
< func_addr
+ 4)
6745 addr
= func_addr
+ 4;
6749 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6751 unsigned long high_word
;
6754 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6755 high_word
= (inst
>> 16) & 0xffff;
6757 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6758 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6759 && inst
!= 0x03e00008 /* jr $ra */
6760 && inst
!= 0x00000000) /* nop */
6770 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6771 This is a helper function for mips_stack_frame_destroyed_p. */
6774 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6776 CORE_ADDR func_addr
= 0;
6777 CORE_ADDR func_end
= 0;
6785 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6788 /* The microMIPS epilogue is max. 12 bytes long. */
6789 addr
= func_end
- 12;
6791 if (addr
< func_addr
+ 2)
6792 addr
= func_addr
+ 2;
6796 for (; pc
< func_end
; pc
+= loc
)
6799 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6800 loc
+= MIPS_INSN16_SIZE
;
6801 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6803 /* 32-bit instructions. */
6804 case 2 * MIPS_INSN16_SIZE
:
6806 insn
|= mips_fetch_instruction (gdbarch
,
6807 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6808 loc
+= MIPS_INSN16_SIZE
;
6809 switch (micromips_op (insn
>> 16))
6811 case 0xc: /* ADDIU: bits 001100 */
6812 case 0x17: /* DADDIU: bits 010111 */
6813 sreg
= b0s5_reg (insn
>> 16);
6814 dreg
= b5s5_reg (insn
>> 16);
6815 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6816 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6817 /* (D)ADDIU $sp, imm */
6827 /* 16-bit instructions. */
6828 case MIPS_INSN16_SIZE
:
6829 switch (micromips_op (insn
))
6831 case 0x3: /* MOVE: bits 000011 */
6832 sreg
= b0s5_reg (insn
);
6833 dreg
= b5s5_reg (insn
);
6834 if (sreg
== 0 && dreg
== 0)
6835 /* MOVE $zero, $zero aka NOP */
6839 case 0x11: /* POOL16C: bits 010001 */
6840 if (b5s5_op (insn
) == 0x18
6841 /* JRADDIUSP: bits 010011 11000 */
6842 || (b5s5_op (insn
) == 0xd
6843 /* JRC: bits 010011 01101 */
6844 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6849 case 0x13: /* POOL16D: bits 010011 */
6850 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6851 if ((insn
& 0x1) == 0x1
6852 /* ADDIUSP: bits 010011 1 */
6866 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6867 This is a helper function for mips_stack_frame_destroyed_p. */
6870 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6872 CORE_ADDR func_addr
= 0, func_end
= 0;
6874 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6876 /* The MIPS epilogue is max. 12 bytes long. */
6877 CORE_ADDR addr
= func_end
- 12;
6879 if (addr
< func_addr
+ 4)
6880 addr
= func_addr
+ 4;
6884 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6886 unsigned short inst
;
6888 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6890 if ((inst
& 0xf800) == 0xf000) /* extend */
6893 if (inst
!= 0x6300 /* addiu $sp,offset */
6894 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6895 && inst
!= 0xe820 /* jr $ra */
6896 && inst
!= 0xe8a0 /* jrc $ra */
6897 && inst
!= 0x6500) /* nop */
6907 /* Implement the stack_frame_destroyed_p gdbarch method.
6909 The epilogue is defined here as the area at the end of a function,
6910 after an instruction which destroys the function's stack frame. */
6913 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6915 if (mips_pc_is_mips16 (gdbarch
, pc
))
6916 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6917 else if (mips_pc_is_micromips (gdbarch
, pc
))
6918 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6920 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6923 /* Commands to show/set the MIPS FPU type. */
6926 show_mipsfpu_command (const char *args
, int from_tty
)
6930 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
6934 ("The MIPS floating-point coprocessor is unknown "
6935 "because the current architecture is not MIPS.\n");
6939 switch (mips_get_fpu_type (current_inferior ()->arch ()))
6941 case MIPS_FPU_SINGLE
:
6942 fpu
= "single-precision";
6944 case MIPS_FPU_DOUBLE
:
6945 fpu
= "double-precision";
6948 fpu
= "absent (none)";
6951 internal_error (_("bad switch"));
6953 if (mips_fpu_type_auto
)
6954 gdb_printf ("The MIPS floating-point coprocessor "
6955 "is set automatically (currently %s)\n",
6959 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6964 set_mipsfpu_single_command (const char *args
, int from_tty
)
6966 struct gdbarch_info info
;
6967 mips_fpu_type
= MIPS_FPU_SINGLE
;
6968 mips_fpu_type_auto
= 0;
6969 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6970 instead of relying on globals. Doing that would let generic code
6971 handle the search for this specific architecture. */
6972 if (!gdbarch_update_p (info
))
6973 internal_error (_("set mipsfpu failed"));
6977 set_mipsfpu_double_command (const char *args
, int from_tty
)
6979 struct gdbarch_info info
;
6980 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6981 mips_fpu_type_auto
= 0;
6982 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6983 instead of relying on globals. Doing that would let generic code
6984 handle the search for this specific architecture. */
6985 if (!gdbarch_update_p (info
))
6986 internal_error (_("set mipsfpu failed"));
6990 set_mipsfpu_none_command (const char *args
, int from_tty
)
6992 struct gdbarch_info info
;
6993 mips_fpu_type
= MIPS_FPU_NONE
;
6994 mips_fpu_type_auto
= 0;
6995 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6996 instead of relying on globals. Doing that would let generic code
6997 handle the search for this specific architecture. */
6998 if (!gdbarch_update_p (info
))
6999 internal_error (_("set mipsfpu failed"));
7003 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7005 mips_fpu_type_auto
= 1;
7008 /* Just like reinit_frame_cache, but with the right arguments to be
7009 callable as an sfunc. */
7012 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7013 struct cmd_list_element
*c
)
7015 reinit_frame_cache ();
7019 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7021 gdb_disassemble_info
*di
7022 = static_cast<gdb_disassemble_info
*> (info
->application_data
);
7023 struct gdbarch
*gdbarch
= di
->arch ();
7025 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7026 disassembler needs to be able to locally determine the ISA, and
7027 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7029 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7030 info
->mach
= bfd_mach_mips16
;
7031 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7032 info
->mach
= bfd_mach_mips_micromips
;
7034 /* Round down the instruction address to the appropriate boundary. */
7035 memaddr
&= (info
->mach
== bfd_mach_mips16
7036 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7038 return default_print_insn (memaddr
, info
);
7041 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7044 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7046 CORE_ADDR pc
= *pcptr
;
7048 if (mips_pc_is_mips16 (gdbarch
, pc
))
7050 *pcptr
= unmake_compact_addr (pc
);
7051 return MIPS_BP_KIND_MIPS16
;
7053 else if (mips_pc_is_micromips (gdbarch
, pc
))
7058 *pcptr
= unmake_compact_addr (pc
);
7059 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7060 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7061 return MIPS_BP_KIND_MICROMIPS16
;
7063 return MIPS_BP_KIND_MICROMIPS32
;
7066 return MIPS_BP_KIND_MIPS32
;
7069 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7071 static const gdb_byte
*
7072 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7074 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7078 case MIPS_BP_KIND_MIPS16
:
7080 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7081 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7084 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7085 return mips16_big_breakpoint
;
7087 return mips16_little_breakpoint
;
7089 case MIPS_BP_KIND_MICROMIPS16
:
7091 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7092 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7096 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7097 return micromips16_big_breakpoint
;
7099 return micromips16_little_breakpoint
;
7101 case MIPS_BP_KIND_MICROMIPS32
:
7103 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7104 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7107 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7108 return micromips32_big_breakpoint
;
7110 return micromips32_little_breakpoint
;
7112 case MIPS_BP_KIND_MIPS32
:
7114 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7115 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7118 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7119 return big_breakpoint
;
7121 return little_breakpoint
;
7124 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7128 /* Return non-zero if the standard MIPS instruction INST has a branch
7129 delay slot (i.e. it is a jump or branch instruction). This function
7130 is based on mips32_next_pc. */
7133 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7139 op
= itype_op (inst
);
7140 if ((inst
& 0xe0000000) != 0)
7142 rs
= itype_rs (inst
);
7143 rt
= itype_rt (inst
);
7144 return (is_octeon_bbit_op (op
, gdbarch
)
7145 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7146 || op
== 29 /* JALX: bits 011101 */
7149 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7150 || (rs
== 9 && (rt
& 0x2) == 0)
7151 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7152 || (rs
== 10 && (rt
& 0x2) == 0))));
7153 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7156 switch (op
& 0x07) /* extract bits 28,27,26 */
7158 case 0: /* SPECIAL */
7159 op
= rtype_funct (inst
);
7160 return (op
== 8 /* JR */
7161 || op
== 9); /* JALR */
7162 break; /* end SPECIAL */
7163 case 1: /* REGIMM */
7164 rs
= itype_rs (inst
);
7165 rt
= itype_rt (inst
); /* branch condition */
7166 return ((rt
& 0xc) == 0
7167 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7168 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7169 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7170 /* BPOSGE32, BPOSGE64: bits 1110x */
7171 break; /* end REGIMM */
7172 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7178 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7179 delay slot (i.e. it is a jump or branch instruction). */
7182 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7187 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7191 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7194 /* Return non-zero if the microMIPS instruction INSN, comprising the
7195 16-bit major opcode word in the high 16 bits and any second word
7196 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7197 jump or branch instruction). The instruction must be 32-bit if
7198 MUSTBE32 is set or can be any instruction otherwise. */
7201 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7203 ULONGEST major
= insn
>> 16;
7205 switch (micromips_op (major
))
7207 /* 16-bit instructions. */
7208 case 0x33: /* B16: bits 110011 */
7209 case 0x2b: /* BNEZ16: bits 101011 */
7210 case 0x23: /* BEQZ16: bits 100011 */
7212 case 0x11: /* POOL16C: bits 010001 */
7214 && ((b5s5_op (major
) == 0xc
7215 /* JR16: bits 010001 01100 */
7216 || (b5s5_op (major
) & 0x1e) == 0xe)));
7217 /* JALR16, JALRS16: bits 010001 0111x */
7218 /* 32-bit instructions. */
7219 case 0x3d: /* JAL: bits 111101 */
7220 case 0x3c: /* JALX: bits 111100 */
7221 case 0x35: /* J: bits 110101 */
7222 case 0x2d: /* BNE: bits 101101 */
7223 case 0x25: /* BEQ: bits 100101 */
7224 case 0x1d: /* JALS: bits 011101 */
7226 case 0x10: /* POOL32I: bits 010000 */
7227 return ((b5s5_op (major
) & 0x1c) == 0x0
7228 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7229 || (b5s5_op (major
) & 0x1d) == 0x4
7230 /* BLEZ, BGTZ: bits 010000 001x0 */
7231 || (b5s5_op (major
) & 0x1d) == 0x11
7232 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7233 || ((b5s5_op (major
) & 0x1e) == 0x14
7234 && (major
& 0x3) == 0x0)
7235 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7236 || (b5s5_op (major
) & 0x1e) == 0x1a
7237 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7238 || ((b5s5_op (major
) & 0x1e) == 0x1c
7239 && (major
& 0x3) == 0x0)
7240 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7241 || ((b5s5_op (major
) & 0x1c) == 0x1c
7242 && (major
& 0x3) == 0x1));
7243 /* BC1ANY*: bits 010000 111xx xxx01 */
7244 case 0x0: /* POOL32A: bits 000000 */
7245 return (b0s6_op (insn
) == 0x3c
7246 /* POOL32Axf: bits 000000 ... 111100 */
7247 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7248 /* JALR, JALR.HB: 000000 000x111100 111100 */
7249 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7255 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7256 slot (i.e. it is a non-compact jump instruction). The instruction
7257 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7260 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7261 CORE_ADDR addr
, int mustbe32
)
7267 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7270 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7272 if (size
== 2 * MIPS_INSN16_SIZE
)
7274 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7279 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7282 /* Return non-zero if the MIPS16 instruction INST, which must be
7283 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7284 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7285 instruction). This function is based on mips16_next_pc. */
7288 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7290 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7292 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7295 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7296 slot (i.e. it is a non-compact jump instruction). The instruction
7297 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7300 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7301 CORE_ADDR addr
, int mustbe32
)
7303 unsigned short insn
;
7306 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7310 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7313 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7314 This assumes KSSEG exists. */
7317 mips_segment_boundary (CORE_ADDR bpaddr
)
7319 CORE_ADDR mask
= CORE_ADDR_MAX
;
7322 if (sizeof (CORE_ADDR
) == 8)
7323 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7324 a compiler warning produced where CORE_ADDR is a 32-bit type even
7325 though in that case this is dead code). */
7326 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7329 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7330 segsize
= 29; /* 32-bit compatibility segment */
7332 segsize
= 62; /* xkseg */
7334 case 2: /* xkphys */
7337 default: /* xksseg (1), xkuseg/kuseg (0) */
7341 else if (bpaddr
& 0x80000000) /* kernel segment */
7344 segsize
= 31; /* user segment */
7346 return bpaddr
& mask
;
7349 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7350 it backwards if necessary. Return the address of the new location. */
7353 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7355 CORE_ADDR prev_addr
;
7357 CORE_ADDR func_addr
;
7359 /* If a breakpoint is set on the instruction in a branch delay slot,
7360 GDB gets confused. When the breakpoint is hit, the PC isn't on
7361 the instruction in the branch delay slot, the PC will point to
7362 the branch instruction. Since the PC doesn't match any known
7363 breakpoints, GDB reports a trap exception.
7365 There are two possible fixes for this problem.
7367 1) When the breakpoint gets hit, see if the BD bit is set in the
7368 Cause register (which indicates the last exception occurred in a
7369 branch delay slot). If the BD bit is set, fix the PC to point to
7370 the instruction in the branch delay slot.
7372 2) When the user sets the breakpoint, don't allow him to set the
7373 breakpoint on the instruction in the branch delay slot. Instead
7374 move the breakpoint to the branch instruction (which will have
7377 The problem with the first solution is that if the user then
7378 single-steps the processor, the branch instruction will get
7379 skipped (since GDB thinks the PC is on the instruction in the
7382 So, we'll use the second solution. To do this we need to know if
7383 the instruction we're trying to set the breakpoint on is in the
7384 branch delay slot. */
7386 boundary
= mips_segment_boundary (bpaddr
);
7388 /* Make sure we don't scan back before the beginning of the current
7389 function, since we may fetch constant data or insns that look like
7390 a jump. Of course we might do that anyway if the compiler has
7391 moved constants inline. :-( */
7392 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7393 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7394 boundary
= func_addr
;
7396 if (mips_pc_is_mips (bpaddr
))
7398 if (bpaddr
== boundary
)
7401 /* If the previous instruction has a branch delay slot, we have
7402 to move the breakpoint to the branch instruction. */
7403 prev_addr
= bpaddr
- 4;
7404 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7409 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7410 CORE_ADDR addr
, jmpaddr
;
7413 boundary
= unmake_compact_addr (boundary
);
7415 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7416 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7417 so try for that first, then try the 2 byte JALR/JR.
7418 The microMIPS ASE has a whole range of jumps and branches
7419 with delay slots, some of which take 4 bytes and some take
7420 2 bytes, so the idea is the same.
7421 FIXME: We have to assume that bpaddr is not the second half
7422 of an extended instruction. */
7423 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7424 ? micromips_insn_at_pc_has_delay_slot
7425 : mips16_insn_at_pc_has_delay_slot
);
7429 for (i
= 1; i
< 4; i
++)
7431 if (unmake_compact_addr (addr
) == boundary
)
7433 addr
-= MIPS_INSN16_SIZE
;
7434 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7435 /* Looks like a JR/JALR at [target-1], but it could be
7436 the second word of a previous JAL/JALX, so record it
7437 and check back one more. */
7439 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7442 /* Looks like a JAL/JALX at [target-2], but it could also
7443 be the second word of a previous JAL/JALX, record it,
7444 and check back one more. */
7447 /* Looks like a JAL/JALX at [target-3], so any previously
7448 recorded JAL/JALX or JR/JALR must be wrong, because:
7451 -2: JAL-ext (can't be JAL/JALX)
7452 -1: bdslot (can't be JR/JALR)
7455 Of course it could be another JAL-ext which looks
7456 like a JAL, but in that case we'd have broken out
7457 of this loop at [target-2]:
7461 -2: bdslot (can't be jmp)
7468 /* Not a jump instruction: if we're at [target-1] this
7469 could be the second word of a JAL/JALX, so continue;
7470 otherwise we're done. */
7483 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7484 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7487 mips_is_stub_suffix (const char *suffix
, int zero
)
7492 return zero
&& suffix
[1] == '\0';
7494 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7499 return suffix
[1] == '\0';
7505 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7506 call stubs, one of sf, df, sc, or dc. */
7509 mips_is_stub_mode (const char *mode
)
7511 return ((mode
[0] == 's' || mode
[0] == 'd')
7512 && (mode
[1] == 'f' || mode
[1] == 'c'));
7515 /* Code at PC is a compiler-generated stub. Such a stub for a function
7516 bar might have a name like __fn_stub_bar, and might look like this:
7523 followed by (or interspersed with):
7530 addiu $25, $25, %lo(bar)
7533 ($1 may be used in old code; for robustness we accept any register)
7536 lui $28, %hi(_gp_disp)
7537 addiu $28, $28, %lo(_gp_disp)
7540 addiu $25, $25, %lo(bar)
7543 In the case of a __call_stub_bar stub, the sequence to set up
7544 arguments might look like this:
7551 followed by (or interspersed with) one of the jump sequences above.
7553 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7554 of J or JR, respectively, followed by:
7560 We are at the beginning of the stub here, and scan down and extract
7561 the target address from the jump immediate instruction or, if a jump
7562 register instruction is used, from the register referred. Return
7563 the value of PC calculated or 0 if inconclusive.
7565 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7568 mips_get_mips16_fn_stub_pc (frame_info_ptr frame
, CORE_ADDR pc
)
7570 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7571 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7572 int addrreg
= MIPS_ZERO_REGNUM
;
7573 CORE_ADDR start_pc
= pc
;
7574 CORE_ADDR target_pc
= 0;
7581 status
== 0 && target_pc
== 0 && i
< 20;
7582 i
++, pc
+= MIPS_INSN32_SIZE
)
7584 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7590 switch (itype_op (inst
))
7592 case 0: /* SPECIAL */
7593 switch (rtype_funct (inst
))
7597 rs
= rtype_rs (inst
);
7598 if (rs
== MIPS_GP_REGNUM
)
7599 target_pc
= gp
; /* Hmm... */
7600 else if (rs
== addrreg
)
7604 case 0x21: /* ADDU */
7605 rt
= rtype_rt (inst
);
7606 rs
= rtype_rs (inst
);
7607 rd
= rtype_rd (inst
);
7608 if (rd
== MIPS_GP_REGNUM
7609 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7610 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7618 target_pc
= jtype_target (inst
) << 2;
7619 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7623 rt
= itype_rt (inst
);
7624 rs
= itype_rs (inst
);
7627 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7628 if (rt
== MIPS_GP_REGNUM
)
7630 else if (rt
== addrreg
)
7636 rt
= itype_rt (inst
);
7637 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7638 if (rt
== MIPS_GP_REGNUM
)
7640 else if (rt
!= MIPS_ZERO_REGNUM
)
7648 rt
= itype_rt (inst
);
7649 rs
= itype_rs (inst
);
7650 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7651 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7655 memset (buf
, 0, sizeof (buf
));
7656 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7658 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7667 /* If PC is in a MIPS16 call or return stub, return the address of the
7668 target PC, which is either the callee or the caller. There are several
7669 cases which must be handled:
7671 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7672 and the target PC is in $31 ($ra).
7673 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7674 and the target PC is in $2.
7675 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7676 i.e. before the JALR instruction, this is effectively a call stub
7677 and the target PC is in $2. Otherwise this is effectively
7678 a return stub and the target PC is in $18.
7679 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7680 JAL or JALR instruction, this is effectively a call stub and the
7681 target PC is buried in the instruction stream. Otherwise this
7682 is effectively a return stub and the target PC is in $18.
7683 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7684 stub and the target PC is buried in the instruction stream.
7686 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7687 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7691 mips_skip_mips16_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7693 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7694 CORE_ADDR start_addr
;
7698 /* Find the starting address and name of the function containing the PC. */
7699 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7702 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7703 and the target PC is in $31 ($ra). */
7704 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7705 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7706 && mips_is_stub_mode (name
+ prefixlen
)
7707 && name
[prefixlen
+ 2] == '\0')
7708 return get_frame_register_signed
7709 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7711 /* If the PC is in __mips16_call_stub_*, this is one of the call
7712 call/return stubs. */
7713 prefixlen
= strlen (mips_str_mips16_call_stub
);
7714 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7716 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7717 and the target PC is in $2. */
7718 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7719 return get_frame_register_signed
7720 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7722 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7723 i.e. before the JALR instruction, this is effectively a call stub
7724 and the target PC is in $2. Otherwise this is effectively
7725 a return stub and the target PC is in $18. */
7726 else if (mips_is_stub_mode (name
+ prefixlen
)
7727 && name
[prefixlen
+ 2] == '_'
7728 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7730 if (pc
== start_addr
)
7731 /* This is the 'call' part of a call stub. The return
7732 address is in $2. */
7733 return get_frame_register_signed
7734 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7736 /* This is the 'return' part of a call stub. The return
7737 address is in $18. */
7738 return get_frame_register_signed
7739 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7742 return 0; /* Not a stub. */
7745 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7746 compiler-generated call or call/return stubs. */
7747 if (startswith (name
, mips_str_fn_stub
)
7748 || startswith (name
, mips_str_call_stub
))
7750 if (pc
== start_addr
)
7751 /* This is the 'call' part of a call stub. Call this helper
7752 to scan through this code for interesting instructions
7753 and determine the final PC. */
7754 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7756 /* This is the 'return' part of a call stub. The return address
7758 return get_frame_register_signed
7759 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7762 return 0; /* Not a stub. */
7765 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7766 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7769 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7771 CORE_ADDR start_addr
;
7774 /* Find the starting address of the function containing the PC. */
7775 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7778 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7779 the start, i.e. after the JALR instruction, this is effectively
7781 prefixlen
= strlen (mips_str_mips16_call_stub
);
7782 if (pc
!= start_addr
7783 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7784 && mips_is_stub_mode (name
+ prefixlen
)
7785 && name
[prefixlen
+ 2] == '_'
7786 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7789 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7790 the JAL or JALR instruction, this is effectively a return stub. */
7791 prefixlen
= strlen (mips_str_call_fp_stub
);
7792 if (pc
!= start_addr
7793 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7796 /* Consume the .pic. prefix of any PIC stub, this function must return
7797 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7798 or the call stub path will trigger in handle_inferior_event causing
7800 prefixlen
= strlen (mips_str_pic
);
7801 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7804 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7805 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7806 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7807 && mips_is_stub_mode (name
+ prefixlen
)
7808 && name
[prefixlen
+ 2] == '\0')
7811 return 0; /* Not a stub. */
7814 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7815 PC of the stub target. The stub just loads $t9 and jumps to it,
7816 so that $t9 has the correct value at function entry. */
7819 mips_skip_pic_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7821 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7823 struct bound_minimal_symbol msym
;
7825 gdb_byte stub_code
[16];
7826 int32_t stub_words
[4];
7828 /* The stub for foo is named ".pic.foo", and is either two
7829 instructions inserted before foo or a three instruction sequence
7830 which jumps to foo. */
7831 msym
= lookup_minimal_symbol_by_pc (pc
);
7832 if (msym
.minsym
== NULL
7833 || msym
.value_address () != pc
7834 || msym
.minsym
->linkage_name () == NULL
7835 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7838 /* A two-instruction header. */
7839 if (msym
.minsym
->size () == 8)
7842 /* A three-instruction (plus delay slot) trampoline. */
7843 if (msym
.minsym
->size () == 16)
7845 if (target_read_memory (pc
, stub_code
, 16) != 0)
7847 for (i
= 0; i
< 4; i
++)
7848 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7851 /* A stub contains these instructions:
7854 addiu t9, t9, %lo(target)
7857 This works even for N64, since stubs are only generated with
7859 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7860 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7861 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7862 && stub_words
[3] == 0x00000000)
7863 return ((((stub_words
[0] & 0x0000ffff) << 16)
7864 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7867 /* Not a recognized stub. */
7872 mips_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7874 CORE_ADDR requested_pc
= pc
;
7875 CORE_ADDR target_pc
;
7882 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7886 new_pc
= find_solib_trampoline_target (frame
, pc
);
7890 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7894 while (pc
!= target_pc
);
7896 return pc
!= requested_pc
? pc
: 0;
7899 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7900 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7903 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7906 if (num
>= 0 && num
< 32)
7908 else if (num
>= 38 && num
< 70)
7909 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7911 regnum
= mips_regnum (gdbarch
)->hi
;
7913 regnum
= mips_regnum (gdbarch
)->lo
;
7914 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7915 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7918 return gdbarch_num_regs (gdbarch
) + regnum
;
7922 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7923 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7926 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7929 if (num
>= 0 && num
< 32)
7931 else if (num
>= 32 && num
< 64)
7932 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7934 regnum
= mips_regnum (gdbarch
)->hi
;
7936 regnum
= mips_regnum (gdbarch
)->lo
;
7937 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7938 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7941 return gdbarch_num_regs (gdbarch
) + regnum
;
7945 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7947 /* Only makes sense to supply raw registers. */
7948 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7949 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7950 decide if it is valid. Should instead define a standard sim/gdb
7951 register numbering scheme. */
7952 if (gdbarch_register_name (gdbarch
,
7953 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
7956 return LEGACY_SIM_REGNO_IGNORE
;
7960 /* Convert an integer into an address. Extracting the value signed
7961 guarantees a correctly sign extended address. */
7964 mips_integer_to_address (struct gdbarch
*gdbarch
,
7965 struct type
*type
, const gdb_byte
*buf
)
7967 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7968 return extract_signed_integer (buf
, type
->length (), byte_order
);
7971 /* Dummy virtual frame pointer method. This is no more or less accurate
7972 than most other architectures; we just need to be explicit about it,
7973 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7974 an assertion failure. */
7977 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7978 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7980 *reg
= MIPS_SP_REGNUM
;
7985 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7987 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7988 const char *name
= bfd_section_name (sect
);
7990 if (*abip
!= MIPS_ABI_UNKNOWN
)
7993 if (!startswith (name
, ".mdebug."))
7996 if (strcmp (name
, ".mdebug.abi32") == 0)
7997 *abip
= MIPS_ABI_O32
;
7998 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7999 *abip
= MIPS_ABI_N32
;
8000 else if (strcmp (name
, ".mdebug.abi64") == 0)
8001 *abip
= MIPS_ABI_N64
;
8002 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8003 *abip
= MIPS_ABI_O64
;
8004 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8005 *abip
= MIPS_ABI_EABI32
;
8006 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8007 *abip
= MIPS_ABI_EABI64
;
8009 warning (_("unsupported ABI %s."), name
+ 8);
8013 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8015 int *lbp
= (int *) obj
;
8016 const char *name
= bfd_section_name (sect
);
8018 if (startswith (name
, ".gcc_compiled_long32"))
8020 else if (startswith (name
, ".gcc_compiled_long64"))
8022 else if (startswith (name
, ".gcc_compiled_long"))
8023 warning (_("unrecognized .gcc_compiled_longXX"));
8026 static enum mips_abi
8027 global_mips_abi (void)
8031 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8032 if (mips_abi_strings
[i
] == mips_abi_string
)
8033 return (enum mips_abi
) i
;
8035 internal_error (_("unknown ABI string"));
8038 /* Return the default compressed instruction set, either of MIPS16
8039 or microMIPS, selected when none could have been determined from
8040 the ELF header of the binary being executed (or no binary has been
8043 static enum mips_isa
8044 global_mips_compression (void)
8048 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8049 if (mips_compression_strings
[i
] == mips_compression_string
)
8050 return (enum mips_isa
) i
;
8052 internal_error (_("unknown compressed ISA string"));
8056 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8058 /* If the size matches the set of 32-bit or 64-bit integer registers,
8059 assume that's what we've got. */
8060 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8061 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8063 /* If the size matches the full set of registers GDB traditionally
8064 knows about, including floating point, for either 32-bit or
8065 64-bit, assume that's what we've got. */
8066 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8067 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8069 /* Otherwise we don't have a useful guess. */
8072 static struct value
*
8073 value_of_mips_user_reg (frame_info_ptr frame
, const void *baton
)
8075 const int *reg_p
= (const int *) baton
;
8076 return value_of_register (*reg_p
, frame
);
8079 static struct gdbarch
*
8080 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8083 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8085 enum mips_fpu_type fpu_type
;
8086 tdesc_arch_data_up tdesc_data
;
8087 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8088 const char * const *reg_names
;
8089 struct mips_regnum mips_regnum
, *regnum
;
8090 enum mips_isa mips_isa
;
8094 /* First of all, extract the elf_flags, if available. */
8095 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8096 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8097 else if (arches
!= NULL
)
8099 mips_gdbarch_tdep
*tdep
8100 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8101 elf_flags
= tdep
->elf_flags
;
8106 gdb_printf (gdb_stdlog
,
8107 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8109 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8110 switch ((elf_flags
& EF_MIPS_ABI
))
8112 case E_MIPS_ABI_O32
:
8113 found_abi
= MIPS_ABI_O32
;
8115 case E_MIPS_ABI_O64
:
8116 found_abi
= MIPS_ABI_O64
;
8118 case E_MIPS_ABI_EABI32
:
8119 found_abi
= MIPS_ABI_EABI32
;
8121 case E_MIPS_ABI_EABI64
:
8122 found_abi
= MIPS_ABI_EABI64
;
8125 if ((elf_flags
& EF_MIPS_ABI2
))
8126 found_abi
= MIPS_ABI_N32
;
8128 found_abi
= MIPS_ABI_UNKNOWN
;
8132 /* GCC creates a pseudo-section whose name describes the ABI. */
8133 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8134 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8136 /* If we have no useful BFD information, use the ABI from the last
8137 MIPS architecture (if there is one). */
8138 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8140 mips_gdbarch_tdep
*tdep
8141 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8142 found_abi
= tdep
->found_abi
;
8145 /* Try the architecture for any hint of the correct ABI. */
8146 if (found_abi
== MIPS_ABI_UNKNOWN
8147 && info
.bfd_arch_info
!= NULL
8148 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8150 switch (info
.bfd_arch_info
->mach
)
8152 case bfd_mach_mips3900
:
8153 found_abi
= MIPS_ABI_EABI32
;
8155 case bfd_mach_mips4100
:
8156 case bfd_mach_mips5000
:
8157 found_abi
= MIPS_ABI_EABI64
;
8159 case bfd_mach_mips8000
:
8160 case bfd_mach_mips10000
:
8161 /* On Irix, ELF64 executables use the N64 ABI. The
8162 pseudo-sections which describe the ABI aren't present
8163 on IRIX. (Even for executables created by gcc.) */
8164 if (info
.abfd
!= NULL
8165 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8166 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8167 found_abi
= MIPS_ABI_N64
;
8169 found_abi
= MIPS_ABI_N32
;
8174 /* Default 64-bit objects to N64 instead of O32. */
8175 if (found_abi
== MIPS_ABI_UNKNOWN
8176 && info
.abfd
!= NULL
8177 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8178 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8179 found_abi
= MIPS_ABI_N64
;
8182 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8185 /* What has the user specified from the command line? */
8186 wanted_abi
= global_mips_abi ();
8188 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8191 /* Now that we have found what the ABI for this binary would be,
8192 check whether the user is overriding it. */
8193 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8194 mips_abi
= wanted_abi
;
8195 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8196 mips_abi
= found_abi
;
8198 mips_abi
= MIPS_ABI_O32
;
8200 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8203 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8204 if (mips_abi
!= MIPS_ABI_EABI32
8205 && mips_abi
!= MIPS_ABI_O32
8206 && info
.bfd_arch_info
!= NULL
8207 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8208 && info
.bfd_arch_info
->bits_per_word
< 64)
8209 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8211 /* Determine the default compressed ISA. */
8212 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8213 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8214 mips_isa
= ISA_MICROMIPS
;
8215 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8216 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8217 mips_isa
= ISA_MIPS16
;
8219 mips_isa
= global_mips_compression ();
8220 mips_compression_string
= mips_compression_strings
[mips_isa
];
8222 /* Also used when doing an architecture lookup. */
8224 gdb_printf (gdb_stdlog
,
8225 "mips_gdbarch_init: "
8226 "mips64_transfers_32bit_regs_p = %d\n",
8227 mips64_transfers_32bit_regs_p
);
8229 /* Determine the MIPS FPU type. */
8232 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8233 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8234 Tag_GNU_MIPS_ABI_FP
);
8235 #endif /* HAVE_ELF */
8237 if (!mips_fpu_type_auto
)
8238 fpu_type
= mips_fpu_type
;
8239 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8241 switch (elf_fpu_type
)
8243 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8244 fpu_type
= MIPS_FPU_DOUBLE
;
8246 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8247 fpu_type
= MIPS_FPU_SINGLE
;
8249 case Val_GNU_MIPS_ABI_FP_SOFT
:
8251 /* Soft float or unknown. */
8252 fpu_type
= MIPS_FPU_NONE
;
8256 else if (info
.bfd_arch_info
!= NULL
8257 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8258 switch (info
.bfd_arch_info
->mach
)
8260 case bfd_mach_mips3900
:
8261 case bfd_mach_mips4100
:
8262 case bfd_mach_mips4111
:
8263 case bfd_mach_mips4120
:
8264 fpu_type
= MIPS_FPU_NONE
;
8266 case bfd_mach_mips4650
:
8267 fpu_type
= MIPS_FPU_SINGLE
;
8270 fpu_type
= MIPS_FPU_DOUBLE
;
8273 else if (arches
!= NULL
)
8274 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8276 fpu_type
= MIPS_FPU_DOUBLE
;
8278 gdb_printf (gdb_stdlog
,
8279 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8281 /* Check for blatant incompatibilities. */
8283 /* If we have only 32-bit registers, then we can't debug a 64-bit
8285 if (info
.target_desc
8286 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8287 && mips_abi
!= MIPS_ABI_EABI32
8288 && mips_abi
!= MIPS_ABI_O32
)
8291 /* Fill in the OS dependent register numbers and names. */
8292 if (info
.osabi
== GDB_OSABI_LINUX
)
8294 mips_regnum
.fp0
= 38;
8295 mips_regnum
.pc
= 37;
8296 mips_regnum
.cause
= 36;
8297 mips_regnum
.badvaddr
= 35;
8298 mips_regnum
.hi
= 34;
8299 mips_regnum
.lo
= 33;
8300 mips_regnum
.fp_control_status
= 70;
8301 mips_regnum
.fp_implementation_revision
= 71;
8302 mips_regnum
.dspacc
= -1;
8303 mips_regnum
.dspctl
= -1;
8307 reg_names
= mips_linux_reg_names
;
8311 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8312 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8313 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8314 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8315 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8316 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8317 mips_regnum
.fp_control_status
= 70;
8318 mips_regnum
.fp_implementation_revision
= 71;
8319 mips_regnum
.dspacc
= dspacc
= -1;
8320 mips_regnum
.dspctl
= dspctl
= -1;
8321 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8322 if (info
.bfd_arch_info
!= NULL
8323 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8324 reg_names
= mips_tx39_reg_names
;
8326 reg_names
= mips_generic_reg_names
;
8329 /* Check any target description for validity. */
8330 if (tdesc_has_registers (info
.target_desc
))
8332 static const char *const mips_gprs
[] = {
8333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8335 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8336 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8338 static const char *const mips_fprs
[] = {
8339 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8340 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8341 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8342 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8345 const struct tdesc_feature
*feature
;
8348 feature
= tdesc_find_feature (info
.target_desc
,
8349 "org.gnu.gdb.mips.cpu");
8350 if (feature
== NULL
)
8353 tdesc_data
= tdesc_data_alloc ();
8356 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8357 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8361 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8362 mips_regnum
.lo
, "lo");
8363 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8364 mips_regnum
.hi
, "hi");
8365 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8366 mips_regnum
.pc
, "pc");
8371 feature
= tdesc_find_feature (info
.target_desc
,
8372 "org.gnu.gdb.mips.cp0");
8373 if (feature
== NULL
)
8377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8378 mips_regnum
.badvaddr
, "badvaddr");
8379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8380 MIPS_PS_REGNUM
, "status");
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 mips_regnum
.cause
, "cause");
8387 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8388 backend is not prepared for that, though. */
8389 feature
= tdesc_find_feature (info
.target_desc
,
8390 "org.gnu.gdb.mips.fpu");
8391 if (feature
== NULL
)
8395 for (i
= 0; i
< 32; i
++)
8396 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8397 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8399 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8400 mips_regnum
.fp_control_status
,
8403 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8404 mips_regnum
.fp_implementation_revision
,
8410 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8414 feature
= tdesc_find_feature (info
.target_desc
,
8415 "org.gnu.gdb.mips.dsp");
8416 /* The DSP registers are optional; it's OK if they are absent. */
8417 if (feature
!= NULL
)
8421 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8422 dspacc
+ i
++, "hi1");
8423 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8424 dspacc
+ i
++, "lo1");
8425 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8426 dspacc
+ i
++, "hi2");
8427 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8428 dspacc
+ i
++, "lo2");
8429 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 dspacc
+ i
++, "hi3");
8431 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8432 dspacc
+ i
++, "lo3");
8434 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8440 mips_regnum
.dspacc
= dspacc
;
8441 mips_regnum
.dspctl
= dspctl
;
8443 num_regs
= mips_regnum
.dspctl
+ 1;
8447 /* It would be nice to detect an attempt to use a 64-bit ABI
8448 when only 32-bit registers are provided. */
8452 /* Try to find a pre-existing architecture. */
8453 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8455 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8457 mips_gdbarch_tdep
*tdep
8458 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8460 /* MIPS needs to be pedantic about which ABI and the compressed
8461 ISA variation the object is using. */
8462 if (tdep
->elf_flags
!= elf_flags
)
8464 if (tdep
->mips_abi
!= mips_abi
)
8466 if (tdep
->mips_isa
!= mips_isa
)
8468 /* Need to be pedantic about which register virtual size is
8470 if (tdep
->mips64_transfers_32bit_regs_p
8471 != mips64_transfers_32bit_regs_p
)
8473 /* Be pedantic about which FPU is selected. */
8474 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8477 return arches
->gdbarch
;
8480 /* Need a new architecture. Fill in a target specific vector. */
8482 = gdbarch_alloc (&info
, gdbarch_tdep_up (new mips_gdbarch_tdep
));
8483 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8485 tdep
->elf_flags
= elf_flags
;
8486 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8487 tdep
->found_abi
= found_abi
;
8488 tdep
->mips_abi
= mips_abi
;
8489 tdep
->mips_isa
= mips_isa
;
8490 tdep
->mips_fpu_type
= fpu_type
;
8491 tdep
->register_size_valid_p
= 0;
8492 tdep
->register_size
= 0;
8494 if (info
.target_desc
)
8496 /* Some useful properties can be inferred from the target. */
8497 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8499 tdep
->register_size_valid_p
= 1;
8500 tdep
->register_size
= 4;
8502 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8504 tdep
->register_size_valid_p
= 1;
8505 tdep
->register_size
= 8;
8509 /* Initially set everything according to the default ABI/ISA. */
8510 set_gdbarch_short_bit (gdbarch
, 16);
8511 set_gdbarch_int_bit (gdbarch
, 32);
8512 set_gdbarch_float_bit (gdbarch
, 32);
8513 set_gdbarch_double_bit (gdbarch
, 64);
8514 set_gdbarch_long_double_bit (gdbarch
, 64);
8515 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8516 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8517 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8519 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8520 mips_ax_pseudo_register_collect
);
8521 set_gdbarch_ax_pseudo_register_push_stack
8522 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8524 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8525 mips_elf_make_msymbol_special
);
8526 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8527 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8528 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8530 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8531 *regnum
= mips_regnum
;
8532 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8533 set_gdbarch_num_regs (gdbarch
, num_regs
);
8534 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8535 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8536 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8537 tdep
->mips_processor_reg_names
= reg_names
;
8538 tdep
->regnum
= regnum
;
8543 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8544 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8545 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8546 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8547 tdep
->default_mask_address_p
= 0;
8548 set_gdbarch_long_bit (gdbarch
, 32);
8549 set_gdbarch_ptr_bit (gdbarch
, 32);
8550 set_gdbarch_long_long_bit (gdbarch
, 64);
8553 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8554 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8555 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8556 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8557 tdep
->default_mask_address_p
= 0;
8558 set_gdbarch_long_bit (gdbarch
, 32);
8559 set_gdbarch_ptr_bit (gdbarch
, 32);
8560 set_gdbarch_long_long_bit (gdbarch
, 64);
8562 case MIPS_ABI_EABI32
:
8563 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8564 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8565 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8566 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8567 tdep
->default_mask_address_p
= 0;
8568 set_gdbarch_long_bit (gdbarch
, 32);
8569 set_gdbarch_ptr_bit (gdbarch
, 32);
8570 set_gdbarch_long_long_bit (gdbarch
, 64);
8572 case MIPS_ABI_EABI64
:
8573 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8574 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8575 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8576 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8577 tdep
->default_mask_address_p
= 0;
8578 set_gdbarch_long_bit (gdbarch
, 64);
8579 set_gdbarch_ptr_bit (gdbarch
, 64);
8580 set_gdbarch_long_long_bit (gdbarch
, 64);
8583 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8584 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8585 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8586 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8587 tdep
->default_mask_address_p
= 0;
8588 set_gdbarch_long_bit (gdbarch
, 32);
8589 set_gdbarch_ptr_bit (gdbarch
, 32);
8590 set_gdbarch_long_long_bit (gdbarch
, 64);
8591 set_gdbarch_long_double_bit (gdbarch
, 128);
8592 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8595 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8596 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8597 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8598 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8599 tdep
->default_mask_address_p
= 0;
8600 set_gdbarch_long_bit (gdbarch
, 64);
8601 set_gdbarch_ptr_bit (gdbarch
, 64);
8602 set_gdbarch_long_long_bit (gdbarch
, 64);
8603 set_gdbarch_long_double_bit (gdbarch
, 128);
8604 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8607 internal_error (_("unknown ABI in switch"));
8610 /* GCC creates a pseudo-section whose name specifies the size of
8611 longs, since -mlong32 or -mlong64 may be used independent of
8612 other options. How those options affect pointer sizes is ABI and
8613 architecture dependent, so use them to override the default sizes
8614 set by the ABI. This table shows the relationship between ABI,
8615 -mlongXX, and size of pointers:
8617 ABI -mlongXX ptr bits
8618 --- -------- --------
8632 Note that for o32 and eabi32, pointers are always 32 bits
8633 regardless of any -mlongXX option. For all others, pointers and
8634 longs are the same, as set by -mlongXX or set by defaults. */
8636 if (info
.abfd
!= NULL
)
8640 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8643 set_gdbarch_long_bit (gdbarch
, long_bit
);
8647 case MIPS_ABI_EABI32
:
8652 case MIPS_ABI_EABI64
:
8653 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8656 internal_error (_("unknown ABI in switch"));
8661 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8662 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8665 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8666 flag in object files because to do so would make it impossible to
8667 link with libraries compiled without "-gp32". This is
8668 unnecessarily restrictive.
8670 We could solve this problem by adding "-gp32" multilibs to gcc,
8671 but to set this flag before gcc is built with such multilibs will
8672 break too many systems.''
8674 But even more unhelpfully, the default linker output target for
8675 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8676 for 64-bit programs - you need to change the ABI to change this,
8677 and not all gcc targets support that currently. Therefore using
8678 this flag to detect 32-bit mode would do the wrong thing given
8679 the current gcc - it would make GDB treat these 64-bit programs
8680 as 32-bit programs by default. */
8682 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8683 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8685 /* Add/remove bits from an address. The MIPS needs be careful to
8686 ensure that all 32 bit addresses are sign extended to 64 bits. */
8687 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8689 /* Unwind the frame. */
8690 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8691 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8692 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8694 /* Map debug register numbers onto internal register numbers. */
8695 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8696 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8697 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8698 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8699 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8700 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8702 /* MIPS version of CALL_DUMMY. */
8704 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8705 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8706 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8708 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8710 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8711 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8712 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8714 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8715 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8716 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8717 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8718 mips_adjust_breakpoint_address
);
8720 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8722 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8724 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8725 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8726 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8728 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8730 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8732 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8733 if (mips_abi
== MIPS_ABI_N64
)
8734 set_gdbarch_disassembler_options_implicit
8735 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8736 else if (mips_abi
== MIPS_ABI_N32
)
8737 set_gdbarch_disassembler_options_implicit
8738 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8740 set_gdbarch_disassembler_options_implicit
8741 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8742 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8743 set_gdbarch_valid_disassembler_options (gdbarch
,
8744 disassembler_options_mips ());
8746 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8747 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8748 need to all be folded into the target vector. Since they are
8749 being used as guards for target_stopped_by_watchpoint, why not have
8750 target_stopped_by_watchpoint return the type of watchpoint that the code
8752 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8754 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8756 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8757 to support MIPS16. This is a bad thing. Make sure not to do it
8758 if we have an OS ABI that actually supports shared libraries, since
8759 shared library support is more important. If we have an OS someday
8760 that supports both shared libraries and MIPS16, we'll have to find
8761 a better place for these.
8762 macro/2012-04-25: But that applies to return trampolines only and
8763 currently no MIPS OS ABI uses shared libraries that have them. */
8764 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8766 set_gdbarch_single_step_through_delay (gdbarch
,
8767 mips_single_step_through_delay
);
8769 /* Virtual tables. */
8770 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8772 mips_register_g_packet_guesses (gdbarch
);
8774 /* Hook in OS ABI-specific overrides, if they have been registered. */
8775 info
.tdesc_data
= tdesc_data
.get ();
8776 gdbarch_init_osabi (info
, gdbarch
);
8778 /* The hook may have adjusted num_regs, fetch the final value and
8779 set pc_regnum and sp_regnum now that it has been fixed. */
8780 num_regs
= gdbarch_num_regs (gdbarch
);
8781 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8782 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8784 /* Unwind the frame. */
8785 dwarf2_append_unwinders (gdbarch
);
8786 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8787 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8788 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8789 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8790 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8791 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8792 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8793 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8794 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8796 if (tdesc_data
!= nullptr)
8798 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8799 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8801 /* Override the normal target description methods to handle our
8802 dual real and pseudo registers. */
8803 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8804 set_gdbarch_register_reggroup_p (gdbarch
,
8805 mips_tdesc_register_reggroup_p
);
8807 num_regs
= gdbarch_num_regs (gdbarch
);
8808 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8809 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8810 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8813 /* Add ABI-specific aliases for the registers. */
8814 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8815 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8816 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8817 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8819 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8820 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8821 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8823 /* Add some other standard aliases. */
8824 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8825 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8826 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8828 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8829 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8830 value_of_mips_user_reg
,
8831 &mips_numeric_register_aliases
[i
].regnum
);
8837 mips_abi_update (const char *ignore_args
,
8838 int from_tty
, struct cmd_list_element
*c
)
8840 struct gdbarch_info info
;
8842 /* Force the architecture to update, and (if it's a MIPS architecture)
8843 mips_gdbarch_init will take care of the rest. */
8844 gdbarch_update_p (info
);
8847 /* Print out which MIPS ABI is in use. */
8850 show_mips_abi (struct ui_file
*file
,
8852 struct cmd_list_element
*ignored_cmd
,
8853 const char *ignored_value
)
8855 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
8859 "The MIPS ABI is unknown because the current architecture "
8863 enum mips_abi global_abi
= global_mips_abi ();
8864 enum mips_abi actual_abi
= mips_abi (current_inferior ()->arch ());
8865 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8867 if (global_abi
== MIPS_ABI_UNKNOWN
)
8870 "The MIPS ABI is set automatically (currently \"%s\").\n",
8872 else if (global_abi
== actual_abi
)
8875 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8879 /* Probably shouldn't happen... */
8881 "The (auto detected) MIPS ABI \"%s\" is in use "
8882 "even though the user setting was \"%s\".\n",
8883 actual_abi_str
, mips_abi_strings
[global_abi
]);
8888 /* Print out which MIPS compressed ISA encoding is used. */
8891 show_mips_compression (struct ui_file
*file
, int from_tty
,
8892 struct cmd_list_element
*c
, const char *value
)
8894 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8898 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8901 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8907 case MIPS_FPU_SINGLE
:
8909 case MIPS_FPU_DOUBLE
:
8917 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8919 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8923 int ef_mips_32bitmode
;
8924 /* Determine the ISA. */
8925 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8943 /* Determine the size of a pointer. */
8944 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8946 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8949 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8952 "mips_dump_tdep: ef_mips_arch = %d\n",
8955 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8956 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8959 "mips_mask_address_p() %d (default %d)\n",
8960 mips_mask_address_p (tdep
),
8961 tdep
->default_mask_address_p
);
8964 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8965 MIPS_DEFAULT_FPU_TYPE
,
8966 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8967 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8968 mips_eabi (gdbarch
));
8970 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8971 mips_get_fpu_type (gdbarch
),
8972 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8975 void _initialize_mips_tdep ();
8977 _initialize_mips_tdep ()
8979 static struct cmd_list_element
*mipsfpulist
= NULL
;
8981 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8982 if (MIPS_ABI_LAST
+ 1
8983 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8984 internal_error (_("mips_abi_strings out of sync"));
8986 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8988 /* Create feature sets with the appropriate properties. The values
8989 are not important. */
8990 mips_tdesc_gp32
= allocate_target_description ().release ();
8991 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8993 mips_tdesc_gp64
= allocate_target_description ().release ();
8994 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8996 /* Add root prefix command for all "set mips"/"show mips" commands. */
8997 add_setshow_prefix_cmd ("mips", no_class
,
8998 _("Various MIPS specific commands."),
8999 _("Various MIPS specific commands."),
9000 &setmipscmdlist
, &showmipscmdlist
,
9001 &setlist
, &showlist
);
9003 /* Allow the user to override the ABI. */
9004 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9005 &mips_abi_string
, _("\
9006 Set the MIPS ABI used by this program."), _("\
9007 Show the MIPS ABI used by this program."), _("\
9008 This option can be set to one of:\n\
9009 auto - the default ABI associated with the current binary\n\
9018 &setmipscmdlist
, &showmipscmdlist
);
9020 /* Allow the user to set the ISA to assume for compressed code if ELF
9021 file flags don't tell or there is no program file selected. This
9022 setting is updated whenever unambiguous ELF file flags are interpreted,
9023 and carried over to subsequent sessions. */
9024 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9025 &mips_compression_string
, _("\
9026 Set the compressed ISA encoding used by MIPS code."), _("\
9027 Show the compressed ISA encoding used by MIPS code."), _("\
9028 Select the compressed ISA encoding used in functions that have no symbol\n\
9029 information available. The encoding can be set to either of:\n\
9032 and is updated automatically from ELF file flags if available."),
9034 show_mips_compression
,
9035 &setmipscmdlist
, &showmipscmdlist
);
9037 /* Let the user turn off floating point and set the fence post for
9038 heuristic_proc_start. */
9040 add_basic_prefix_cmd ("mipsfpu", class_support
,
9041 _("Set use of MIPS floating-point coprocessor."),
9042 &mipsfpulist
, 0, &setlist
);
9043 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9044 _("Select single-precision MIPS floating-point coprocessor."),
9046 cmd_list_element
*set_mipsfpu_double_cmd
9047 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9048 _("Select double-precision MIPS floating-point coprocessor."),
9050 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9051 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9052 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9054 cmd_list_element
*set_mipsfpu_none_cmd
9055 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9056 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9057 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9058 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9059 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9060 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9061 _("Select MIPS floating-point coprocessor automatically."),
9063 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9064 _("Show current use of MIPS floating-point coprocessor target."),
9067 /* We really would like to have both "0" and "unlimited" work, but
9068 command.c doesn't deal with that. So make it a var_zinteger
9069 because the user can always use "999999" or some such for unlimited. */
9070 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9071 &heuristic_fence_post
, _("\
9072 Set the distance searched for the start of a function."), _("\
9073 Show the distance searched for the start of a function."), _("\
9074 If you are debugging a stripped executable, GDB needs to search through the\n\
9075 program for the start of a function. This command sets the distance of the\n\
9076 search. The only need to set it is when debugging a stripped executable."),
9077 reinit_frame_cache_sfunc
,
9078 NULL
, /* FIXME: i18n: The distance searched for
9079 the start of a function is %s. */
9080 &setlist
, &showlist
);
9082 /* Allow the user to control whether the upper bits of 64-bit
9083 addresses should be zeroed. */
9084 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9085 &mask_address_var
, _("\
9086 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9087 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9088 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9089 allow GDB to determine the correct value."),
9090 NULL
, show_mask_address
,
9091 &setmipscmdlist
, &showmipscmdlist
);
9093 /* Allow the user to control the size of 32 bit registers within the
9094 raw remote packet. */
9095 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9096 &mips64_transfers_32bit_regs_p
, _("\
9097 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9099 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9101 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9102 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9103 64 bits for others. Use \"off\" to disable compatibility mode"),
9104 set_mips64_transfers_32bit_regs
,
9105 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9106 MIPS target that transfers 32-bit
9107 quantities is %s. */
9108 &setlist
, &showlist
);
9110 /* Debug this files internals. */
9111 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9113 Set mips debugging."), _("\
9114 Show mips debugging."), _("\
9115 When non-zero, mips specific debugging is enabled."),
9117 NULL
, /* FIXME: i18n: Mips debugging is
9119 &setdebuglist
, &showdebuglist
);