1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "sim/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h"
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 static const registry
<inferior
>::key
<ppc_inferior_data
> ppc_inferior_data_key
;
160 /* Get the per-inferior PowerPC data for INF. */
163 get_ppc_per_inferior (inferior
*inf
)
165 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
167 if (per_inf
== nullptr)
168 per_inf
= ppc_inferior_data_key
.emplace (inf
);
173 /* To be used by skip_prologue. */
175 struct rs6000_framedata
177 int offset
; /* total size of frame --- the distance
178 by which we decrement sp to allocate
180 int saved_gpr
; /* smallest # of saved gpr */
181 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
182 int saved_fpr
; /* smallest # of saved fpr */
183 int saved_vr
; /* smallest # of saved vr */
184 int saved_ev
; /* smallest # of saved ev */
185 int alloca_reg
; /* alloca register number (frame ptr) */
186 char frameless
; /* true if frameless functions. */
187 char nosavedpc
; /* true if pc not saved. */
188 char used_bl
; /* true if link register clobbered */
189 int gpr_offset
; /* offset of saved gprs from prev sp */
190 int fpr_offset
; /* offset of saved fprs from prev sp */
191 int vr_offset
; /* offset of saved vrs from prev sp */
192 int ev_offset
; /* offset of saved evs from prev sp */
193 int lr_offset
; /* offset of saved lr */
194 int lr_register
; /* register of saved lr, if trustworthy */
195 int cr_offset
; /* offset of saved cr */
196 int vrsave_offset
; /* offset of saved vrsave register */
200 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
202 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
204 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
205 if (tdep
->ppc_vsr0_regnum
< 0)
208 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
209 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
212 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
214 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
216 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
217 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
220 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
224 /* Return true if REGNO is an SPE register, false otherwise. */
226 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
228 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
230 /* Is it a reference to EV0 -- EV31, and do we have those? */
231 if (IS_SPE_PSEUDOREG (tdep
, regno
))
234 /* Is it a reference to one of the raw upper GPR halves? */
235 if (tdep
->ppc_ev0_upper_regnum
>= 0
236 && tdep
->ppc_ev0_upper_regnum
<= regno
237 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
240 /* Is it a reference to the 64-bit accumulator, and do we have that? */
241 if (tdep
->ppc_acc_regnum
>= 0
242 && tdep
->ppc_acc_regnum
== regno
)
245 /* Is it a reference to the SPE floating-point status and control register,
246 and do we have that? */
247 if (tdep
->ppc_spefscr_regnum
>= 0
248 && tdep
->ppc_spefscr_regnum
== regno
)
255 /* Return non-zero if the architecture described by GDBARCH has
256 floating-point registers (f0 --- f31 and fpscr). */
258 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
260 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
262 return (tdep
->ppc_fp0_regnum
>= 0
263 && tdep
->ppc_fpscr_regnum
>= 0);
266 /* Return non-zero if the architecture described by GDBARCH has
267 Altivec registers (vr0 --- vr31, vrsave and vscr). */
269 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
271 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
273 return (tdep
->ppc_vr0_regnum
>= 0
274 && tdep
->ppc_vrsave_regnum
>= 0);
277 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
280 This is a helper function for init_sim_regno_table, constructing
281 the table mapping GDB register numbers to sim register numbers; we
282 initialize every element in that table to -1 before we start
285 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
287 /* Make sure we don't try to assign any given GDB register a sim
288 register number more than once. */
289 gdb_assert (table
[gdb_regno
] == -1);
290 table
[gdb_regno
] = sim_regno
;
294 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
295 numbers to simulator register numbers, based on the values placed
296 in the ARCH->tdep->ppc_foo_regnum members. */
298 init_sim_regno_table (struct gdbarch
*arch
)
300 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
301 int total_regs
= gdbarch_num_regs (arch
);
302 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
304 static const char *const segment_regs
[] = {
305 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
306 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
309 /* Presume that all registers not explicitly mentioned below are
310 unavailable from the sim. */
311 for (i
= 0; i
< total_regs
; i
++)
314 /* General-purpose registers. */
315 for (i
= 0; i
< ppc_num_gprs
; i
++)
316 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
318 /* Floating-point registers. */
319 if (tdep
->ppc_fp0_regnum
>= 0)
320 for (i
= 0; i
< ppc_num_fprs
; i
++)
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_fp0_regnum
+ i
,
323 sim_ppc_f0_regnum
+ i
);
324 if (tdep
->ppc_fpscr_regnum
>= 0)
325 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
327 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
328 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
329 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
331 /* Segment registers. */
332 for (i
= 0; i
< ppc_num_srs
; i
++)
336 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
338 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
341 /* Altivec registers. */
342 if (tdep
->ppc_vr0_regnum
>= 0)
344 for (i
= 0; i
< ppc_num_vrs
; i
++)
345 set_sim_regno (sim_regno
,
346 tdep
->ppc_vr0_regnum
+ i
,
347 sim_ppc_vr0_regnum
+ i
);
349 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
350 we can treat this more like the other cases. */
351 set_sim_regno (sim_regno
,
352 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
353 sim_ppc_vscr_regnum
);
355 /* vsave is a special-purpose register, so the code below handles it. */
357 /* SPE APU (E500) registers. */
358 if (tdep
->ppc_ev0_upper_regnum
>= 0)
359 for (i
= 0; i
< ppc_num_gprs
; i
++)
360 set_sim_regno (sim_regno
,
361 tdep
->ppc_ev0_upper_regnum
+ i
,
362 sim_ppc_rh0_regnum
+ i
);
363 if (tdep
->ppc_acc_regnum
>= 0)
364 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
365 /* spefscr is a special-purpose register, so the code below handles it. */
368 /* Now handle all special-purpose registers. Verify that they
369 haven't mistakenly been assigned numbers by any of the above
371 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
373 const char *spr_name
= sim_spr_register_name (i
);
376 if (spr_name
!= NULL
)
377 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
380 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
384 /* Drop the initialized array into place. */
385 tdep
->sim_regno
= sim_regno
;
389 /* Given a GDB register number REG, return the corresponding SIM
392 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
394 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
397 if (tdep
->sim_regno
== NULL
)
398 init_sim_regno_table (gdbarch
);
400 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
401 sim_regno
= tdep
->sim_regno
[reg
];
406 return LEGACY_SIM_REGNO_IGNORE
;
411 /* Register set support functions. */
413 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
414 Write the register to REGCACHE. */
417 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
418 const gdb_byte
*regs
, size_t offset
, int regsize
)
420 if (regnum
!= -1 && offset
!= -1)
424 struct gdbarch
*gdbarch
= regcache
->arch ();
425 int gdb_regsize
= register_size (gdbarch
, regnum
);
426 if (gdb_regsize
< regsize
427 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
428 offset
+= regsize
- gdb_regsize
;
430 regcache
->raw_supply (regnum
, regs
+ offset
);
434 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
435 in a field REGSIZE wide. Zero pad as necessary. */
438 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
439 gdb_byte
*regs
, size_t offset
, int regsize
)
441 if (regnum
!= -1 && offset
!= -1)
445 struct gdbarch
*gdbarch
= regcache
->arch ();
446 int gdb_regsize
= register_size (gdbarch
, regnum
);
447 if (gdb_regsize
< regsize
)
449 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
451 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
452 offset
+= regsize
- gdb_regsize
;
455 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
456 regsize
- gdb_regsize
);
459 regcache
->raw_collect (regnum
, regs
+ offset
);
464 ppc_greg_offset (struct gdbarch
*gdbarch
,
465 ppc_gdbarch_tdep
*tdep
,
466 const struct ppc_reg_offsets
*offsets
,
470 *regsize
= offsets
->gpr_size
;
471 if (regnum
>= tdep
->ppc_gp0_regnum
472 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
473 return (offsets
->r0_offset
474 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
476 if (regnum
== gdbarch_pc_regnum (gdbarch
))
477 return offsets
->pc_offset
;
479 if (regnum
== tdep
->ppc_ps_regnum
)
480 return offsets
->ps_offset
;
482 if (regnum
== tdep
->ppc_lr_regnum
)
483 return offsets
->lr_offset
;
485 if (regnum
== tdep
->ppc_ctr_regnum
)
486 return offsets
->ctr_offset
;
488 *regsize
= offsets
->xr_size
;
489 if (regnum
== tdep
->ppc_cr_regnum
)
490 return offsets
->cr_offset
;
492 if (regnum
== tdep
->ppc_xer_regnum
)
493 return offsets
->xer_offset
;
495 if (regnum
== tdep
->ppc_mq_regnum
)
496 return offsets
->mq_offset
;
502 ppc_fpreg_offset (ppc_gdbarch_tdep
*tdep
,
503 const struct ppc_reg_offsets
*offsets
,
506 if (regnum
>= tdep
->ppc_fp0_regnum
507 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
508 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
510 if (regnum
== tdep
->ppc_fpscr_regnum
)
511 return offsets
->fpscr_offset
;
516 /* Supply register REGNUM in the general-purpose register set REGSET
517 from the buffer specified by GREGS and LEN to register cache
518 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
521 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
522 int regnum
, const void *gregs
, size_t len
)
524 struct gdbarch
*gdbarch
= regcache
->arch ();
525 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
526 const struct ppc_reg_offsets
*offsets
527 = (const struct ppc_reg_offsets
*) regset
->regmap
;
534 int gpr_size
= offsets
->gpr_size
;
536 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
537 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
538 i
++, offset
+= gpr_size
)
539 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
542 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
543 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
544 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
545 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
546 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
548 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
549 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
550 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
551 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
553 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
554 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
556 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
562 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
563 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
566 /* Supply register REGNUM in the floating-point register set REGSET
567 from the buffer specified by FPREGS and LEN to register cache
568 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
571 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
572 int regnum
, const void *fpregs
, size_t len
)
574 struct gdbarch
*gdbarch
= regcache
->arch ();
575 const struct ppc_reg_offsets
*offsets
;
578 if (!ppc_floating_point_unit_p (gdbarch
))
581 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
582 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
587 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
588 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
590 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
592 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
593 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
594 offsets
->fpscr_size
);
598 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
599 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
600 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
603 /* Collect register REGNUM in the general-purpose register set
604 REGSET from register cache REGCACHE into the buffer specified by
605 GREGS and LEN. If REGNUM is -1, do this for all registers in
609 ppc_collect_gregset (const struct regset
*regset
,
610 const struct regcache
*regcache
,
611 int regnum
, void *gregs
, size_t len
)
613 struct gdbarch
*gdbarch
= regcache
->arch ();
614 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
615 const struct ppc_reg_offsets
*offsets
616 = (const struct ppc_reg_offsets
*) regset
->regmap
;
623 int gpr_size
= offsets
->gpr_size
;
625 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
626 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
627 i
++, offset
+= gpr_size
)
628 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
630 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
631 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
632 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
633 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
634 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
635 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
636 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
637 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
638 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
639 (gdb_byte
*) gregs
, offsets
->cr_offset
,
641 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
642 (gdb_byte
*) gregs
, offsets
->xer_offset
,
644 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
645 (gdb_byte
*) gregs
, offsets
->mq_offset
,
650 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
651 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
654 /* Collect register REGNUM in the floating-point register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 FPREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_fpregset (const struct regset
*regset
,
661 const struct regcache
*regcache
,
662 int regnum
, void *fpregs
, size_t len
)
664 struct gdbarch
*gdbarch
= regcache
->arch ();
665 const struct ppc_reg_offsets
*offsets
;
668 if (!ppc_floating_point_unit_p (gdbarch
))
671 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
672 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
677 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
678 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
680 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
682 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
683 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
684 offsets
->fpscr_size
);
688 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
689 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
690 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
694 insn_changes_sp_or_jumps (unsigned long insn
)
696 int opcode
= (insn
>> 26) & 0x03f;
697 int sd
= (insn
>> 21) & 0x01f;
698 int a
= (insn
>> 16) & 0x01f;
699 int subcode
= (insn
>> 1) & 0x3ff;
701 /* Changes the stack pointer. */
703 /* NOTE: There are many ways to change the value of a given register.
704 The ways below are those used when the register is R1, the SP,
705 in a funtion's epilogue. */
707 if (opcode
== 31 && subcode
== 444 && a
== 1)
708 return 1; /* mr R1,Rn */
709 if (opcode
== 14 && sd
== 1)
710 return 1; /* addi R1,Rn,simm */
711 if (opcode
== 58 && sd
== 1)
712 return 1; /* ld R1,ds(Rn) */
714 /* Transfers control. */
720 if (opcode
== 19 && subcode
== 16)
722 if (opcode
== 19 && subcode
== 528)
723 return 1; /* bcctr */
728 /* Return true if we are in the function's epilogue, i.e. after the
729 instruction that destroyed the function's stack frame.
731 1) scan forward from the point of execution:
732 a) If you find an instruction that modifies the stack pointer
733 or transfers control (except a return), execution is not in
735 b) Stop scanning if you find a return instruction or reach the
736 end of the function or reach the hard limit for the size of
738 2) scan backward from the point of execution:
739 a) If you find an instruction that modifies the stack pointer,
740 execution *is* in an epilogue, return.
741 b) Stop scanning if you reach an instruction that transfers
742 control or the beginning of the function or reach the hard
743 limit for the size of an epilogue. */
746 rs6000_in_function_epilogue_frame_p (frame_info_ptr curfrm
,
747 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
749 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
750 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
751 bfd_byte insn_buf
[PPC_INSN_SIZE
];
752 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
755 /* Find the search limits based on function boundaries and hard limit. */
757 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
760 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
761 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
763 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
764 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
766 /* Scan forward until next 'blr'. */
768 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
770 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
771 {insn_buf
, PPC_INSN_SIZE
}))
773 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
774 if (insn
== 0x4e800020)
776 /* Assume a bctr is a tail call unless it points strictly within
778 if (insn
== 0x4e800420)
780 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
781 tdep
->ppc_ctr_regnum
);
782 if (ctr
> func_start
&& ctr
< func_end
)
787 if (insn_changes_sp_or_jumps (insn
))
791 /* Scan backward until adjustment to stack pointer (R1). */
793 for (scan_pc
= pc
- PPC_INSN_SIZE
;
794 scan_pc
>= epilogue_start
;
795 scan_pc
-= PPC_INSN_SIZE
)
797 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
798 {insn_buf
, PPC_INSN_SIZE
}))
800 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
801 if (insn_changes_sp_or_jumps (insn
))
808 /* Implement the stack_frame_destroyed_p gdbarch method. */
811 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
813 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
817 /* Get the ith function argument for the current function. */
819 rs6000_fetch_pointer_argument (frame_info_ptr frame
, int argi
,
822 return get_frame_register_unsigned (frame
, 3 + argi
);
825 /* Sequence of bytes for breakpoint instruction. */
827 constexpr gdb_byte big_breakpoint
[] = { 0x7f, 0xe0, 0x00, 0x08 };
828 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x00, 0xe0, 0x7f };
830 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
833 /* Instruction masks for displaced stepping. */
834 #define OP_MASK 0xfc000000
835 #define BP_MASK 0xFC0007FE
836 #define B_INSN 0x48000000
837 #define BC_INSN 0x40000000
838 #define BXL_INSN 0x4c000000
839 #define BP_INSN 0x7C000008
841 /* Instruction masks used during single-stepping of atomic
843 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
844 #define LWARX_INSTRUCTION 0x7c000028
845 #define LDARX_INSTRUCTION 0x7c0000A8
846 #define LBARX_INSTRUCTION 0x7c000068
847 #define LHARX_INSTRUCTION 0x7c0000e8
848 #define LQARX_INSTRUCTION 0x7c000228
849 #define STORE_CONDITIONAL_MASK 0xfc0007ff
850 #define STWCX_INSTRUCTION 0x7c00012d
851 #define STDCX_INSTRUCTION 0x7c0001ad
852 #define STBCX_INSTRUCTION 0x7c00056d
853 #define STHCX_INSTRUCTION 0x7c0005ad
854 #define STQCX_INSTRUCTION 0x7c00016d
856 /* Instruction masks for single-stepping of addpcis/lnia. */
857 #define ADDPCIS_INSN 0x4c000004
858 #define ADDPCIS_INSN_MASK 0xfc00003e
859 #define ADDPCIS_TARGET_REGISTER 0x03F00000
860 #define ADDPCIS_INSN_REGSHIFT 21
862 #define PNOP_MASK 0xfff3ffff
863 #define PNOP_INSN 0x07000000
864 #define R_MASK 0x00100000
865 #define R_ZERO 0x00000000
867 /* Check if insn is one of the Load And Reserve instructions used for atomic
869 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
871 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
872 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
873 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
874 /* Check if insn is one of the Store Conditional instructions used for atomic
876 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
878 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
879 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
880 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
882 typedef buf_displaced_step_copy_insn_closure
883 ppc_displaced_step_copy_insn_closure
;
885 /* We can't displaced step atomic sequences. */
887 static displaced_step_copy_insn_closure_up
888 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
889 CORE_ADDR from
, CORE_ADDR to
,
890 struct regcache
*regs
)
892 size_t len
= gdbarch_displaced_step_buffer_length (gdbarch
);
893 gdb_assert (len
> PPC_INSN_SIZE
);
894 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
895 (new ppc_displaced_step_copy_insn_closure (len
));
896 gdb_byte
*buf
= closure
->buf
.data ();
897 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
900 len
= target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY
, NULL
,
902 if ((ssize_t
) len
< PPC_INSN_SIZE
)
903 memory_error (TARGET_XFER_E_IO
, from
);
905 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
907 /* Check for PNOP and for prefixed instructions with R=0. Those
908 instructions are safe to displace. Prefixed instructions with R=1
909 will read/write data to/from locations relative to the current PC.
910 We would not be able to fixup after an instruction has written data
911 into a displaced location, so decline to displace those instructions. */
912 if ((insn
& OP_MASK
) == 1 << 26)
914 if (((insn
& PNOP_MASK
) != PNOP_INSN
)
915 && ((insn
& R_MASK
) != R_ZERO
))
917 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
918 insn
, paddress (gdbarch
, from
));
923 /* Non-prefixed instructions.. */
925 /* Set the instruction length to 4 to match the actual instruction
930 /* Assume all atomic sequences start with a Load and Reserve instruction. */
931 if (IS_LOAD_AND_RESERVE_INSN (insn
))
933 displaced_debug_printf ("can't displaced step atomic sequence at %s",
934 paddress (gdbarch
, from
));
939 write_memory (to
, buf
, len
);
941 displaced_debug_printf ("copy %s->%s: %s",
942 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
943 bytes_to_string (buf
, len
).c_str ());
945 /* This is a work around for a problem with g++ 4.8. */
946 return displaced_step_copy_insn_closure_up (closure
.release ());
949 /* Fix up the state of registers and memory after having single-stepped
950 a displaced instruction. */
952 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
953 struct displaced_step_copy_insn_closure
*closure_
,
954 CORE_ADDR from
, CORE_ADDR to
,
955 struct regcache
*regs
, bool completed_p
)
957 /* If the displaced instruction didn't complete successfully then all we
958 need to do is restore the program counter. */
961 CORE_ADDR pc
= regcache_read_pc (regs
);
962 pc
= from
+ (pc
- to
);
963 regcache_write_pc (regs
, pc
);
967 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
968 /* Our closure is a copy of the instruction. */
969 ppc_displaced_step_copy_insn_closure
*closure
970 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
971 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
972 PPC_INSN_SIZE
, byte_order
);
974 /* Offset for non PC-relative instructions. */
977 opcode
= insn
& OP_MASK
;
979 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
980 if ((opcode
) == 1 << 26)
981 offset
= 2 * PPC_INSN_SIZE
;
983 offset
= PPC_INSN_SIZE
;
985 displaced_debug_printf ("(ppc) fixup (%s, %s)",
986 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
988 /* Handle the addpcis/lnia instruction. */
989 if ((insn
& ADDPCIS_INSN_MASK
) == ADDPCIS_INSN
)
991 LONGEST displaced_offset
;
992 ULONGEST current_val
;
993 /* Measure the displacement. */
994 displaced_offset
= from
- to
;
995 /* Identify the target register that was updated by the instruction. */
996 int regnum
= (insn
& ADDPCIS_TARGET_REGISTER
) >> ADDPCIS_INSN_REGSHIFT
;
997 /* Read and update the target value. */
998 regcache_cooked_read_unsigned (regs
, regnum
, ¤t_val
);
999 displaced_debug_printf ("addpcis target regnum %d was %s now %s",
1000 regnum
, paddress (gdbarch
, current_val
),
1001 paddress (gdbarch
, current_val
1002 + displaced_offset
));
1003 regcache_cooked_write_unsigned (regs
, regnum
,
1004 current_val
+ displaced_offset
);
1005 /* point the PC back at the non-displaced instruction. */
1006 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1009 /* Handle PC-relative branch instructions. */
1010 else if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1012 ULONGEST current_pc
;
1014 /* Read the current PC value after the instruction has been executed
1015 in a displaced location. Calculate the offset to be applied to the
1016 original PC value before the displaced stepping. */
1017 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1019 offset
= current_pc
- to
;
1021 if (opcode
!= BXL_INSN
)
1023 /* Check for AA bit indicating whether this is an absolute
1024 addressing or PC-relative (1: absolute, 0: relative). */
1027 /* PC-relative addressing is being used in the branch. */
1028 displaced_debug_printf ("(ppc) branch instruction: %s",
1029 paddress (gdbarch
, insn
));
1030 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
1031 paddress (gdbarch
, current_pc
),
1032 paddress (gdbarch
, from
+ offset
));
1034 regcache_cooked_write_unsigned (regs
,
1035 gdbarch_pc_regnum (gdbarch
),
1041 /* If we're here, it means we have a branch to LR or CTR. If the
1042 branch was taken, the offset is probably greater than 4 (the next
1043 instruction), so it's safe to assume that an offset of 4 means we
1044 did not take the branch. */
1045 if (offset
== PPC_INSN_SIZE
)
1046 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1047 from
+ PPC_INSN_SIZE
);
1050 /* Check for LK bit indicating whether we should set the link
1051 register to point to the next instruction
1052 (1: Set, 0: Don't set). */
1055 /* Link register needs to be set to the next instruction's PC. */
1056 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1057 regcache_cooked_write_unsigned (regs
,
1058 tdep
->ppc_lr_regnum
,
1059 from
+ PPC_INSN_SIZE
);
1060 displaced_debug_printf ("(ppc) adjusted LR to %s",
1061 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1065 /* Check for breakpoints in the inferior. If we've found one, place the PC
1066 right at the breakpoint instruction. */
1067 else if ((insn
& BP_MASK
) == BP_INSN
)
1068 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1071 /* Handle any other instructions that do not fit in the categories
1073 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1078 /* Implementation of gdbarch_displaced_step_prepare. */
1080 static displaced_step_prepare_status
1081 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1082 CORE_ADDR
&displaced_pc
)
1084 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1086 if (!per_inferior
->disp_step_buf
.has_value ())
1088 /* Figure out where the displaced step buffer is. */
1089 CORE_ADDR disp_step_buf_addr
1090 = displaced_step_at_entry_point (thread
->inf
->arch ());
1092 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1095 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1098 /* Implementation of gdbarch_displaced_step_finish. */
1100 static displaced_step_finish_status
1101 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1102 const target_waitstatus
&status
)
1104 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1106 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1108 return per_inferior
->disp_step_buf
->finish (arch
, thread
, status
);
1111 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1114 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1116 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1118 if (per_inferior
== nullptr
1119 || !per_inferior
->disp_step_buf
.has_value ())
1122 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1125 /* Always use hardware single-stepping to execute the
1126 displaced instruction. */
1128 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1133 /* Checks for an atomic sequence of instructions beginning with a
1134 Load And Reserve instruction and ending with a Store Conditional
1135 instruction. If such a sequence is found, attempt to step through it.
1136 A breakpoint is placed at the end of the sequence. */
1137 std::vector
<CORE_ADDR
>
1138 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1140 struct gdbarch
*gdbarch
= regcache
->arch ();
1141 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1142 CORE_ADDR pc
= regcache_read_pc (regcache
);
1143 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1145 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1146 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1149 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1150 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1151 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1153 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1154 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1157 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1159 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1161 if ((insn
& OP_MASK
) == 1 << 26)
1162 loc
+= 2 * PPC_INSN_SIZE
;
1164 loc
+= PPC_INSN_SIZE
;
1165 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1167 /* Assume that there is at most one conditional branch in the atomic
1168 sequence. If a conditional branch is found, put a breakpoint in
1169 its destination address. */
1170 if ((insn
& OP_MASK
) == BC_INSN
)
1172 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1173 int absolute
= insn
& 2;
1175 if (bc_insn_count
>= 1)
1176 return {}; /* More than one conditional branch found, fallback
1177 to the standard single-step code. */
1180 breaks
[1] = immediate
;
1182 breaks
[1] = loc
+ immediate
;
1188 if (IS_STORE_CONDITIONAL_INSN (insn
))
1192 /* Assume that the atomic sequence ends with a Store Conditional
1194 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1198 loc
+= PPC_INSN_SIZE
;
1200 /* Insert a breakpoint right after the end of the atomic sequence. */
1203 /* Check for duplicated breakpoints. Check also for a breakpoint
1204 placed (branch instruction's destination) anywhere in sequence. */
1206 && (breaks
[1] == breaks
[0]
1207 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1208 last_breakpoint
= 0;
1210 std::vector
<CORE_ADDR
> next_pcs
;
1212 for (index
= 0; index
<= last_breakpoint
; index
++)
1213 next_pcs
.push_back (breaks
[index
]);
1219 #define SIGNED_SHORT(x) \
1220 ((sizeof (short) == 2) \
1221 ? ((int)(short)(x)) \
1222 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1224 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1226 /* Limit the number of skipped non-prologue instructions, as the examining
1227 of the prologue is expensive. */
1228 static int max_skip_non_prologue_insns
= 10;
1230 /* Return nonzero if the given instruction OP can be part of the prologue
1231 of a function and saves a parameter on the stack. FRAMEP should be
1232 set if one of the previous instructions in the function has set the
1236 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1238 /* Move parameters from argument registers to temporary register. */
1239 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1241 /* Rx must be scratch register r0. */
1242 const int rx_regno
= (op
>> 16) & 31;
1243 /* Ry: Only r3 - r10 are used for parameter passing. */
1244 const int ry_regno
= GET_SRC_REG (op
);
1246 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1248 *r0_contains_arg
= 1;
1255 /* Save a General Purpose Register on stack. */
1257 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1258 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1260 /* Rx: Only r3 - r10 are used for parameter passing. */
1261 const int rx_regno
= GET_SRC_REG (op
);
1263 return (rx_regno
>= 3 && rx_regno
<= 10);
1266 /* Save a General Purpose Register on stack via the Frame Pointer. */
1269 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1270 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1271 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1273 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1274 However, the compiler sometimes uses r0 to hold an argument. */
1275 const int rx_regno
= GET_SRC_REG (op
);
1277 return ((rx_regno
>= 3 && rx_regno
<= 10)
1278 || (rx_regno
== 0 && *r0_contains_arg
));
1281 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1283 /* Only f2 - f8 are used for parameter passing. */
1284 const int src_regno
= GET_SRC_REG (op
);
1286 return (src_regno
>= 2 && src_regno
<= 8);
1289 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1291 /* Only f2 - f8 are used for parameter passing. */
1292 const int src_regno
= GET_SRC_REG (op
);
1294 return (src_regno
>= 2 && src_regno
<= 8);
1297 /* Not an insn that saves a parameter on stack. */
1301 /* Assuming that INSN is a "bl" instruction located at PC, return
1302 nonzero if the destination of the branch is a "blrl" instruction.
1304 This sequence is sometimes found in certain function prologues.
1305 It allows the function to load the LR register with a value that
1306 they can use to access PIC data using PC-relative offsets. */
1309 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1316 absolute
= (int) ((insn
>> 1) & 1);
1317 immediate
= ((insn
& ~3) << 6) >> 6;
1321 dest
= pc
+ immediate
;
1323 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1324 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1330 /* Return true if OP is a stw or std instruction with
1331 register operands RS and RA and any immediate offset.
1333 If WITH_UPDATE is true, also return true if OP is
1334 a stwu or stdu instruction with the same operands.
1336 Return false otherwise.
1339 store_insn_p (unsigned long op
, unsigned long rs
,
1340 unsigned long ra
, bool with_update
)
1345 if (/* std RS, SIMM(RA) */
1346 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1347 /* stw RS, SIMM(RA) */
1348 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1353 if (/* stdu RS, SIMM(RA) */
1354 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1355 /* stwu RS, SIMM(RA) */
1356 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1363 /* Masks for decoding a branch-and-link (bl) instruction.
1365 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1366 The former is anded with the opcode in question; if the result of
1367 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1368 question is a ``bl'' instruction.
1370 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1371 the branch displacement. */
1373 #define BL_MASK 0xfc000001
1374 #define BL_INSTRUCTION 0x48000001
1375 #define BL_DISPLACEMENT_MASK 0x03fffffc
1377 static unsigned long
1378 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1380 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1384 /* Fetch the instruction and convert it to an integer. */
1385 if (target_read_memory (pc
, buf
, 4))
1387 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1392 /* GCC generates several well-known sequences of instructions at the begining
1393 of each function prologue when compiling with -fstack-check. If one of
1394 such sequences starts at START_PC, then return the address of the
1395 instruction immediately past this sequence. Otherwise, return START_PC. */
1398 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1400 CORE_ADDR pc
= start_pc
;
1401 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1403 /* First possible sequence: A small number of probes.
1404 stw 0, -<some immediate>(1)
1405 [repeat this instruction any (small) number of times]. */
1407 if ((op
& 0xffff0000) == 0x90010000)
1409 while ((op
& 0xffff0000) == 0x90010000)
1412 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1417 /* Second sequence: A probing loop.
1418 addi 12,1,-<some immediate>
1419 lis 0,-<some immediate>
1420 [possibly ori 0,0,<some immediate>]
1424 addi 12,12,-<some immediate>
1427 [possibly one last probe: stw 0,<some immediate>(12)]. */
1431 /* addi 12,1,-<some immediate> */
1432 if ((op
& 0xffff0000) != 0x39810000)
1435 /* lis 0,-<some immediate> */
1437 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1438 if ((op
& 0xffff0000) != 0x3c000000)
1442 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1443 /* [possibly ori 0,0,<some immediate>] */
1444 if ((op
& 0xffff0000) == 0x60000000)
1447 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1450 if (op
!= 0x7c0c0214)
1455 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1456 if (op
!= 0x7c0c0000)
1461 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1462 if ((op
& 0xff9f0001) != 0x41820000)
1465 /* addi 12,12,-<some immediate> */
1467 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 if ((op
& 0xffff0000) != 0x398c0000)
1473 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1474 if (op
!= 0x900c0000)
1479 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1480 if ((op
& 0xfc000001) != 0x48000000)
1483 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1485 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1486 if ((op
& 0xffff0000) == 0x900c0000)
1489 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1492 /* We found a valid stack-check sequence, return the new PC. */
1496 /* Third sequence: No probe; instead, a comparison between the stack size
1497 limit (saved in a run-time global variable) and the current stack
1500 addi 0,1,-<some immediate>
1501 lis 12,__gnat_stack_limit@ha
1502 lwz 12,__gnat_stack_limit@l(12)
1505 or, with a small variant in the case of a bigger stack frame:
1506 addis 0,1,<some immediate>
1507 addic 0,0,-<some immediate>
1508 lis 12,__gnat_stack_limit@ha
1509 lwz 12,__gnat_stack_limit@l(12)
1514 /* addi 0,1,-<some immediate> */
1515 if ((op
& 0xffff0000) != 0x38010000)
1517 /* small stack frame variant not recognized; try the
1518 big stack frame variant: */
1520 /* addis 0,1,<some immediate> */
1521 if ((op
& 0xffff0000) != 0x3c010000)
1524 /* addic 0,0,-<some immediate> */
1526 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1527 if ((op
& 0xffff0000) != 0x30000000)
1531 /* lis 12,<some immediate> */
1533 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1534 if ((op
& 0xffff0000) != 0x3d800000)
1537 /* lwz 12,<some immediate>(12) */
1539 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1540 if ((op
& 0xffff0000) != 0x818c0000)
1545 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1546 if ((op
& 0xfffffffe) != 0x7c406008)
1549 /* We found a valid stack-check sequence, return the new PC. */
1553 /* No stack check code in our prologue, return the start_pc. */
1557 /* return pc value after skipping a function prologue and also return
1558 information about a function frame.
1560 in struct rs6000_framedata fdata:
1561 - frameless is TRUE, if function does not have a frame.
1562 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1563 - offset is the initial size of this stack frame --- the amount by
1564 which we decrement the sp to allocate the frame.
1565 - saved_gpr is the number of the first saved gpr.
1566 - saved_fpr is the number of the first saved fpr.
1567 - saved_vr is the number of the first saved vr.
1568 - saved_ev is the number of the first saved ev.
1569 - alloca_reg is the number of the register used for alloca() handling.
1571 - gpr_offset is the offset of the first saved gpr from the previous frame.
1572 - fpr_offset is the offset of the first saved fpr from the previous frame.
1573 - vr_offset is the offset of the first saved vr from the previous frame.
1574 - ev_offset is the offset of the first saved ev from the previous frame.
1575 - lr_offset is the offset of the saved lr
1576 - cr_offset is the offset of the saved cr
1577 - vrsave_offset is the offset of the saved vrsave register. */
1580 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1581 struct rs6000_framedata
*fdata
)
1583 CORE_ADDR orig_pc
= pc
;
1584 CORE_ADDR last_prologue_pc
= pc
;
1585 CORE_ADDR li_found_pc
= 0;
1589 long alloca_reg_offset
= 0;
1590 long vr_saved_offset
= 0;
1596 int vrsave_reg
= -1;
1599 int minimal_toc_loaded
= 0;
1600 int prev_insn_was_prologue_insn
= 1;
1601 int num_skip_non_prologue_insns
= 0;
1602 int r0_contains_arg
= 0;
1603 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1604 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1605 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1607 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1608 fdata
->saved_gpr
= -1;
1609 fdata
->saved_fpr
= -1;
1610 fdata
->saved_vr
= -1;
1611 fdata
->saved_ev
= -1;
1612 fdata
->alloca_reg
= -1;
1613 fdata
->frameless
= 1;
1614 fdata
->nosavedpc
= 1;
1615 fdata
->lr_register
= -1;
1617 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1623 /* Sometimes it isn't clear if an instruction is a prologue
1624 instruction or not. When we encounter one of these ambiguous
1625 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1626 Otherwise, we'll assume that it really is a prologue instruction. */
1627 if (prev_insn_was_prologue_insn
)
1628 last_prologue_pc
= pc
;
1630 /* Stop scanning if we've hit the limit. */
1634 prev_insn_was_prologue_insn
= 1;
1636 /* Fetch the instruction and convert it to an integer. */
1637 if (target_read_memory (pc
, buf
, 4))
1639 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1641 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1643 /* Since shared library / PIC code, which needs to get its
1644 address at runtime, can appear to save more than one link
1656 remember just the first one, but skip over additional
1659 lr_reg
= (op
& 0x03e00000) >> 21;
1661 r0_contains_arg
= 0;
1664 else if ((op
& 0xfc1fffff) == 0x7c000026)
1666 cr_reg
= (op
& 0x03e00000) >> 21;
1668 r0_contains_arg
= 0;
1672 else if ((op
& 0xfc1f0000) == 0xd8010000)
1673 { /* stfd Rx,NUM(r1) */
1674 reg
= GET_SRC_REG (op
);
1675 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1677 fdata
->saved_fpr
= reg
;
1678 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1683 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1684 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1685 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1686 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1689 reg
= GET_SRC_REG (op
);
1690 if ((op
& 0xfc1f0000) == 0xbc010000)
1691 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1693 fdata
->gpr_mask
|= 1U << reg
;
1694 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1696 fdata
->saved_gpr
= reg
;
1697 if ((op
& 0xfc1f0003) == 0xf8010000)
1699 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1704 else if ((op
& 0xffff0000) == 0x3c4c0000
1705 || (op
& 0xffff0000) == 0x3c400000
1706 || (op
& 0xffff0000) == 0x38420000)
1708 /* . 0: addis 2,12,.TOC.-0b@ha
1709 . addi 2,2,.TOC.-0b@l
1713 used by ELFv2 global entry points to set up r2. */
1716 else if (op
== 0x60000000)
1719 /* Allow nops in the prologue, but do not consider them to
1720 be part of the prologue unless followed by other prologue
1722 prev_insn_was_prologue_insn
= 0;
1726 else if ((op
& 0xffff0000) == 0x3c000000)
1727 { /* addis 0,0,NUM, used for >= 32k frames */
1728 fdata
->offset
= (op
& 0x0000ffff) << 16;
1729 fdata
->frameless
= 0;
1730 r0_contains_arg
= 0;
1734 else if ((op
& 0xffff0000) == 0x60000000)
1735 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1736 fdata
->offset
|= (op
& 0x0000ffff);
1737 fdata
->frameless
= 0;
1738 r0_contains_arg
= 0;
1742 else if (lr_reg
>= 0 &&
1743 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1745 (store_insn_p (op
, lr_reg
,
1746 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1749 if (store_insn_p (op
, lr_reg
, 1, true))
1750 fdata
->lr_offset
= offset
;
1751 else /* LR save through frame pointer. */
1752 fdata
->lr_offset
= alloca_reg_offset
;
1754 fdata
->nosavedpc
= 0;
1755 /* Invalidate lr_reg, but don't set it to -1.
1756 That would mean that it had never been set. */
1758 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1759 (op
& 0xfc000000) == 0x90000000) /* stw */
1761 /* Does not update r1, so add displacement to lr_offset. */
1762 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1767 else if (cr_reg
>= 0 &&
1768 (store_insn_p (op
, cr_reg
, 1, true)))
1770 fdata
->cr_offset
= offset
;
1771 /* Invalidate cr_reg, but don't set it to -1.
1772 That would mean that it had never been set. */
1774 if ((op
& 0xfc000003) == 0xf8000000 ||
1775 (op
& 0xfc000000) == 0x90000000)
1777 /* Does not update r1, so add displacement to cr_offset. */
1778 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1783 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1785 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1786 prediction bits. If the LR has already been saved, we can
1790 else if (op
== 0x48000005)
1797 else if (op
== 0x48000004)
1802 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1803 in V.4 -mminimal-toc */
1804 (op
& 0xffff0000) == 0x3bde0000)
1805 { /* addi 30,30,foo@l */
1809 else if ((op
& 0xfc000001) == 0x48000001)
1813 fdata
->frameless
= 0;
1815 /* If the return address has already been saved, we can skip
1816 calls to blrl (for PIC). */
1817 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1823 /* Don't skip over the subroutine call if it is not within
1824 the first three instructions of the prologue and either
1825 we have no line table information or the line info tells
1826 us that the subroutine call is not part of the line
1827 associated with the prologue. */
1828 if ((pc
- orig_pc
) > 8)
1830 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1831 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1833 if ((prologue_sal
.line
== 0)
1834 || (prologue_sal
.line
!= this_sal
.line
))
1838 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1840 /* At this point, make sure this is not a trampoline
1841 function (a function that simply calls another functions,
1842 and nothing else). If the next is not a nop, this branch
1843 was part of the function prologue. */
1845 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1846 break; /* Don't skip over
1852 /* update stack pointer */
1853 else if ((op
& 0xfc1f0000) == 0x94010000)
1854 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1855 fdata
->frameless
= 0;
1856 fdata
->offset
= SIGNED_SHORT (op
);
1857 offset
= fdata
->offset
;
1860 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1861 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1862 /* No way to figure out what r1 is going to be. */
1863 fdata
->frameless
= 0;
1864 offset
= fdata
->offset
;
1867 else if ((op
& 0xfc1f0003) == 0xf8010001)
1868 { /* stdu rX,NUM(r1) */
1869 fdata
->frameless
= 0;
1870 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1871 offset
= fdata
->offset
;
1874 else if ((op
& 0xffff0000) == 0x38210000)
1875 { /* addi r1,r1,SIMM */
1876 fdata
->frameless
= 0;
1877 fdata
->offset
+= SIGNED_SHORT (op
);
1878 offset
= fdata
->offset
;
1881 /* Load up minimal toc pointer. Do not treat an epilogue restore
1882 of r31 as a minimal TOC load. */
1883 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1884 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1886 && !minimal_toc_loaded
)
1888 minimal_toc_loaded
= 1;
1891 /* move parameters from argument registers to local variable
1894 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1895 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1896 (((op
>> 21) & 31) <= 10) &&
1897 ((long) ((op
>> 16) & 31)
1898 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1902 /* store parameters in stack */
1904 /* Move parameters from argument registers to temporary register. */
1905 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1909 /* Set up frame pointer */
1911 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1913 fdata
->frameless
= 0;
1915 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1916 alloca_reg_offset
= offset
;
1919 /* Another way to set up the frame pointer. */
1921 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1922 || op
== 0x7c3f0b78)
1924 fdata
->frameless
= 0;
1926 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1927 alloca_reg_offset
= offset
;
1930 /* Another way to set up the frame pointer. */
1932 else if ((op
& 0xfc1fffff) == 0x38010000)
1933 { /* addi rX, r1, 0x0 */
1934 fdata
->frameless
= 0;
1936 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1937 + ((op
& ~0x38010000) >> 21));
1938 alloca_reg_offset
= offset
;
1941 /* AltiVec related instructions. */
1942 /* Store the vrsave register (spr 256) in another register for
1943 later manipulation, or load a register into the vrsave
1944 register. 2 instructions are used: mfvrsave and
1945 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1946 and mtspr SPR256, Rn. */
1947 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1948 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1949 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1951 vrsave_reg
= GET_SRC_REG (op
);
1954 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1958 /* Store the register where vrsave was saved to onto the stack:
1959 rS is the register where vrsave was stored in a previous
1961 /* 100100 sssss 00001 dddddddd dddddddd */
1962 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1964 if (vrsave_reg
== GET_SRC_REG (op
))
1966 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1971 /* Compute the new value of vrsave, by modifying the register
1972 where vrsave was saved to. */
1973 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1974 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1978 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1979 in a pair of insns to save the vector registers on the
1981 /* 001110 00000 00000 iiii iiii iiii iiii */
1982 /* 001110 01110 00000 iiii iiii iiii iiii */
1983 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1984 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1986 if ((op
& 0xffff0000) == 0x38000000)
1987 r0_contains_arg
= 0;
1989 vr_saved_offset
= SIGNED_SHORT (op
);
1991 /* This insn by itself is not part of the prologue, unless
1992 if part of the pair of insns mentioned above. So do not
1993 record this insn as part of the prologue yet. */
1994 prev_insn_was_prologue_insn
= 0;
1996 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1997 /* 011111 sssss 11111 00000 00111001110 */
1998 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2000 if (pc
== (li_found_pc
+ 4))
2002 vr_reg
= GET_SRC_REG (op
);
2003 /* If this is the first vector reg to be saved, or if
2004 it has a lower number than others previously seen,
2005 reupdate the frame info. */
2006 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2008 fdata
->saved_vr
= vr_reg
;
2009 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2011 vr_saved_offset
= -1;
2016 /* End AltiVec related instructions. */
2018 /* Start BookE related instructions. */
2019 /* Store gen register S at (r31+uimm).
2020 Any register less than r13 is volatile, so we don't care. */
2021 /* 000100 sssss 11111 iiiii 01100100001 */
2022 else if (arch_info
->mach
== bfd_mach_ppc_e500
2023 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2025 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2028 ev_reg
= GET_SRC_REG (op
);
2029 imm
= (op
>> 11) & 0x1f;
2030 ev_offset
= imm
* 8;
2031 /* If this is the first vector reg to be saved, or if
2032 it has a lower number than others previously seen,
2033 reupdate the frame info. */
2034 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2036 fdata
->saved_ev
= ev_reg
;
2037 fdata
->ev_offset
= ev_offset
+ offset
;
2042 /* Store gen register rS at (r1+rB). */
2043 /* 000100 sssss 00001 bbbbb 01100100000 */
2044 else if (arch_info
->mach
== bfd_mach_ppc_e500
2045 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2047 if (pc
== (li_found_pc
+ 4))
2049 ev_reg
= GET_SRC_REG (op
);
2050 /* If this is the first vector reg to be saved, or if
2051 it has a lower number than others previously seen,
2052 reupdate the frame info. */
2053 /* We know the contents of rB from the previous instruction. */
2054 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2056 fdata
->saved_ev
= ev_reg
;
2057 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2059 vr_saved_offset
= -1;
2065 /* Store gen register r31 at (rA+uimm). */
2066 /* 000100 11111 aaaaa iiiii 01100100001 */
2067 else if (arch_info
->mach
== bfd_mach_ppc_e500
2068 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2070 /* Wwe know that the source register is 31 already, but
2071 it can't hurt to compute it. */
2072 ev_reg
= GET_SRC_REG (op
);
2073 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2074 /* If this is the first vector reg to be saved, or if
2075 it has a lower number than others previously seen,
2076 reupdate the frame info. */
2077 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2079 fdata
->saved_ev
= ev_reg
;
2080 fdata
->ev_offset
= ev_offset
+ offset
;
2085 /* Store gen register S at (r31+r0).
2086 Store param on stack when offset from SP bigger than 4 bytes. */
2087 /* 000100 sssss 11111 00000 01100100000 */
2088 else if (arch_info
->mach
== bfd_mach_ppc_e500
2089 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2091 if (pc
== (li_found_pc
+ 4))
2093 if ((op
& 0x03e00000) >= 0x01a00000)
2095 ev_reg
= GET_SRC_REG (op
);
2096 /* If this is the first vector reg to be saved, or if
2097 it has a lower number than others previously seen,
2098 reupdate the frame info. */
2099 /* We know the contents of r0 from the previous
2101 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2103 fdata
->saved_ev
= ev_reg
;
2104 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2108 vr_saved_offset
= -1;
2113 /* End BookE related instructions. */
2117 /* Not a recognized prologue instruction.
2118 Handle optimizer code motions into the prologue by continuing
2119 the search if we have no valid frame yet or if the return
2120 address is not yet saved in the frame. Also skip instructions
2121 if some of the GPRs expected to be saved are not yet saved. */
2122 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2123 && fdata
->saved_gpr
!= -1)
2125 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2127 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2131 if (op
== 0x4e800020 /* blr */
2132 || op
== 0x4e800420) /* bctr */
2133 /* Do not scan past epilogue in frameless functions or
2136 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2137 /* Never skip branches. */
2140 /* Test based on opcode and mask values of
2141 powerpc_opcodes[svc..svcla] in opcodes/ppc-opc.c. */
2142 if ((op
& 0xffff0000) == 0x44000000)
2143 /* Never skip system calls. */
2146 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2147 /* Do not scan too many insns, scanning insns is expensive with
2151 /* Continue scanning. */
2152 prev_insn_was_prologue_insn
= 0;
2158 /* I have problems with skipping over __main() that I need to address
2159 * sometime. Previously, I used to use misc_function_vector which
2160 * didn't work as well as I wanted to be. -MGO */
2162 /* If the first thing after skipping a prolog is a branch to a function,
2163 this might be a call to an initializer in main(), introduced by gcc2.
2164 We'd like to skip over it as well. Fortunately, xlc does some extra
2165 work before calling a function right after a prologue, thus we can
2166 single out such gcc2 behaviour. */
2169 if ((op
& 0xfc000001) == 0x48000001)
2170 { /* bl foo, an initializer function? */
2171 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2173 if (op
== 0x4def7b82)
2174 { /* cror 0xf, 0xf, 0xf (nop) */
2176 /* Check and see if we are in main. If so, skip over this
2177 initializer function as well. */
2179 tmp
= find_pc_misc_function (pc
);
2181 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2187 if (pc
== lim_pc
&& lr_reg
>= 0)
2188 fdata
->lr_register
= lr_reg
;
2190 fdata
->offset
= -fdata
->offset
;
2191 return last_prologue_pc
;
2195 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2197 struct rs6000_framedata frame
;
2198 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2200 /* See if we can determine the end of the prologue via the symbol table.
2201 If so, then return either PC, or the PC after the prologue, whichever
2203 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2205 CORE_ADDR post_prologue_pc
2206 = skip_prologue_using_sal (gdbarch
, func_addr
);
2207 if (post_prologue_pc
!= 0)
2208 return std::max (pc
, post_prologue_pc
);
2211 /* Can't determine prologue from the symbol table, need to examine
2214 /* Find an upper limit on the function prologue using the debug
2215 information. If the debug information could not be used to provide
2216 that bound, then use an arbitrary large number as the upper bound. */
2217 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2219 limit_pc
= pc
+ 100; /* Magic. */
2221 /* Do not allow limit_pc to be past the function end, if we know
2222 where that end is... */
2223 if (func_end_addr
&& limit_pc
> func_end_addr
)
2224 limit_pc
= func_end_addr
;
2226 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2230 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2231 in the prologue of main().
2233 The function below examines the code pointed at by PC and checks to
2234 see if it corresponds to a call to __eabi. If so, it returns the
2235 address of the instruction following that call. Otherwise, it simply
2239 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2241 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2245 if (target_read_memory (pc
, buf
, 4))
2247 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2249 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2251 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2252 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2253 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2255 /* We check for ___eabi (three leading underscores) in addition
2256 to __eabi in case the GCC option "-fleading-underscore" was
2257 used to compile the program. */
2258 if (s
.minsym
!= NULL
2259 && s
.minsym
->linkage_name () != NULL
2260 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2261 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2267 /* All the ABI's require 16 byte alignment. */
2269 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2271 return (addr
& -16);
2274 /* Return whether handle_inferior_event() should proceed through code
2275 starting at PC in function NAME when stepping.
2277 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2278 handle memory references that are too distant to fit in instructions
2279 generated by the compiler. For example, if 'foo' in the following
2284 is greater than 32767, the linker might replace the lwz with a branch to
2285 somewhere in @FIX1 that does the load in 2 instructions and then branches
2286 back to where execution should continue.
2288 GDB should silently step over @FIX code, just like AIX dbx does.
2289 Unfortunately, the linker uses the "b" instruction for the
2290 branches, meaning that the link register doesn't get set.
2291 Therefore, GDB's usual step_over_function () mechanism won't work.
2293 Instead, use the gdbarch_skip_trampoline_code and
2294 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2298 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2299 CORE_ADDR pc
, const char *name
)
2301 return name
&& startswith (name
, "@FIX");
2304 /* Skip code that the user doesn't want to see when stepping:
2306 1. Indirect function calls use a piece of trampoline code to do context
2307 switching, i.e. to set the new TOC table. Skip such code if we are on
2308 its first instruction (as when we have single-stepped to here).
2310 2. Skip shared library trampoline code (which is different from
2311 indirect function call trampolines).
2313 3. Skip bigtoc fixup code.
2315 Result is desired PC to step until, or NULL if we are not in
2316 code that should be skipped. */
2319 rs6000_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
2321 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2322 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2323 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2324 unsigned int ii
, op
;
2326 CORE_ADDR solib_target_pc
;
2327 struct bound_minimal_symbol msymbol
;
2329 static unsigned trampoline_code
[] =
2331 0x800b0000, /* l r0,0x0(r11) */
2332 0x90410014, /* st r2,0x14(r1) */
2333 0x7c0903a6, /* mtctr r0 */
2334 0x804b0004, /* l r2,0x4(r11) */
2335 0x816b0008, /* l r11,0x8(r11) */
2336 0x4e800420, /* bctr */
2337 0x4e800020, /* br */
2341 /* Check for bigtoc fixup code. */
2342 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2344 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2345 msymbol
.minsym
->linkage_name ()))
2347 /* Double-check that the third instruction from PC is relative "b". */
2348 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2349 if ((op
& 0xfc000003) == 0x48000000)
2351 /* Extract bits 6-29 as a signed 24-bit relative word address and
2352 add it to the containing PC. */
2353 rel
= ((int)(op
<< 6) >> 6);
2354 return pc
+ 8 + rel
;
2358 /* If pc is in a shared library trampoline, return its target. */
2359 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2360 if (solib_target_pc
)
2361 return solib_target_pc
;
2363 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2365 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2366 if (op
!= trampoline_code
[ii
])
2369 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2371 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2375 /* ISA-specific vector types. */
2377 static struct type
*
2378 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2380 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2382 if (!tdep
->ppc_builtin_type_vec64
)
2384 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2386 /* The type we're building is this: */
2388 union __gdb_builtin_type_vec64
2392 int32_t v2_int32
[2];
2393 int16_t v4_int16
[4];
2400 t
= arch_composite_type (gdbarch
,
2401 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2402 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2403 append_composite_type_field (t
, "v2_float",
2404 init_vector_type (bt
->builtin_float
, 2));
2405 append_composite_type_field (t
, "v2_int32",
2406 init_vector_type (bt
->builtin_int32
, 2));
2407 append_composite_type_field (t
, "v4_int16",
2408 init_vector_type (bt
->builtin_int16
, 4));
2409 append_composite_type_field (t
, "v8_int8",
2410 init_vector_type (bt
->builtin_int8
, 8));
2412 t
->set_is_vector (true);
2413 t
->set_name ("ppc_builtin_type_vec64");
2414 tdep
->ppc_builtin_type_vec64
= t
;
2417 return tdep
->ppc_builtin_type_vec64
;
2420 /* Vector 128 type. */
2422 static struct type
*
2423 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2425 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2427 if (!tdep
->ppc_builtin_type_vec128
)
2429 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2431 /* The type we're building is this
2433 type = union __ppc_builtin_type_vec128 {
2434 float128_t float128;
2436 double v2_double[2];
2438 int32_t v4_int32[4];
2439 int16_t v8_int16[8];
2440 int8_t v16_int8[16];
2444 /* PPC specific type for IEEE 128-bit float field */
2445 type_allocator
alloc (gdbarch
);
2446 struct type
*t_float128
2447 = init_float_type (alloc
, 128, "float128_t", floatformats_ieee_quad
);
2451 t
= arch_composite_type (gdbarch
,
2452 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2453 append_composite_type_field (t
, "float128", t_float128
);
2454 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2455 append_composite_type_field (t
, "v2_double",
2456 init_vector_type (bt
->builtin_double
, 2));
2457 append_composite_type_field (t
, "v4_float",
2458 init_vector_type (bt
->builtin_float
, 4));
2459 append_composite_type_field (t
, "v4_int32",
2460 init_vector_type (bt
->builtin_int32
, 4));
2461 append_composite_type_field (t
, "v8_int16",
2462 init_vector_type (bt
->builtin_int16
, 8));
2463 append_composite_type_field (t
, "v16_int8",
2464 init_vector_type (bt
->builtin_int8
, 16));
2466 t
->set_is_vector (true);
2467 t
->set_name ("ppc_builtin_type_vec128");
2468 tdep
->ppc_builtin_type_vec128
= t
;
2471 return tdep
->ppc_builtin_type_vec128
;
2474 /* Return the name of register number REGNO, or the empty string if it
2475 is an anonymous register. */
2478 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2480 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2482 /* The upper half "registers" have names in the XML description,
2483 but we present only the low GPRs and the full 64-bit registers
2485 if (tdep
->ppc_ev0_upper_regnum
>= 0
2486 && tdep
->ppc_ev0_upper_regnum
<= regno
2487 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2490 /* Hide the upper halves of the vs0~vs31 registers. */
2491 if (tdep
->ppc_vsr0_regnum
>= 0
2492 && tdep
->ppc_vsr0_upper_regnum
<= regno
2493 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2496 /* Hide the upper halves of the cvs0~cvs31 registers. */
2497 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2498 && regno
< (to_underlying (PPC_CVSR0_UPPER_REGNUM
)
2499 + to_underlying (ppc_num_gprs
)))
2502 /* Check if the SPE pseudo registers are available. */
2503 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2505 static const char *const spe_regnames
[] = {
2506 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2507 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2508 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2509 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2511 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2514 /* Check if the decimal128 pseudo-registers are available. */
2515 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2517 static const char *const dfp128_regnames
[] = {
2518 "dl0", "dl1", "dl2", "dl3",
2519 "dl4", "dl5", "dl6", "dl7",
2520 "dl8", "dl9", "dl10", "dl11",
2521 "dl12", "dl13", "dl14", "dl15"
2523 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2526 /* Check if this is a vX alias for a raw vrX vector register. */
2527 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2529 static const char *const vector_alias_regnames
[] = {
2530 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2531 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2532 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2533 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2535 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2538 /* Check if this is a VSX pseudo-register. */
2539 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2541 static const char *const vsx_regnames
[] = {
2542 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2543 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2544 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2545 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2546 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2547 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2548 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2549 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2550 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2552 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2555 /* Check if the this is a Extended FP pseudo-register. */
2556 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2558 static const char *const efpr_regnames
[] = {
2559 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2560 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2561 "f46", "f47", "f48", "f49", "f50", "f51",
2562 "f52", "f53", "f54", "f55", "f56", "f57",
2563 "f58", "f59", "f60", "f61", "f62", "f63"
2565 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2568 /* Check if this is a Checkpointed DFP pseudo-register. */
2569 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2571 static const char *const cdfp128_regnames
[] = {
2572 "cdl0", "cdl1", "cdl2", "cdl3",
2573 "cdl4", "cdl5", "cdl6", "cdl7",
2574 "cdl8", "cdl9", "cdl10", "cdl11",
2575 "cdl12", "cdl13", "cdl14", "cdl15"
2577 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2580 /* Check if this is a Checkpointed VSX pseudo-register. */
2581 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2583 static const char *const cvsx_regnames
[] = {
2584 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2585 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2586 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2587 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2588 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2589 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2590 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2591 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2592 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2594 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2597 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2598 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2600 static const char *const cefpr_regnames
[] = {
2601 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2602 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2603 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2604 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2605 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2607 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2610 return tdesc_register_name (gdbarch
, regno
);
2613 /* Return the GDB type object for the "standard" data type of data in
2616 static struct type
*
2617 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2619 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2621 /* These are the e500 pseudo-registers. */
2622 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2623 return rs6000_builtin_type_vec64 (gdbarch
);
2624 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2625 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2626 /* PPC decimal128 pseudo-registers. */
2627 return builtin_type (gdbarch
)->builtin_declong
;
2628 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2629 return gdbarch_register_type (gdbarch
,
2630 tdep
->ppc_vr0_regnum
2632 - tdep
->ppc_v0_alias_regnum
));
2633 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2634 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2635 /* POWER7 VSX pseudo-registers. */
2636 return rs6000_builtin_type_vec128 (gdbarch
);
2637 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2638 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2639 /* POWER7 Extended FP pseudo-registers. */
2640 return builtin_type (gdbarch
)->builtin_double
;
2642 internal_error (_("rs6000_pseudo_register_type: "
2643 "called on unexpected register '%s' (%d)"),
2644 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2647 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2648 the vX aliases for the vector registers by always returning false
2649 to avoid duplicated information in "info register vector/all",
2650 since the raw vrX registers will already show in these cases. For
2651 other pseudo-registers we use the default membership function. */
2654 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2655 const struct reggroup
*group
)
2657 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2659 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2662 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2665 /* The register format for RS/6000 floating point registers is always
2666 double, we need a conversion if the memory format is float. */
2669 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2672 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2674 return (tdep
->ppc_fp0_regnum
>= 0
2675 && regnum
>= tdep
->ppc_fp0_regnum
2676 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2677 && type
->code () == TYPE_CODE_FLT
2679 == builtin_type (gdbarch
)->builtin_float
->length ()));
2683 ieee_128_float_regnum_adjust (struct gdbarch
*gdbarch
, struct type
*type
,
2686 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2688 /* If we have the an IEEE 128-bit floating point value, need to map the
2689 register number to the corresponding VSR. */
2690 if (tdep
->ppc_vsr0_regnum
!= -1
2691 && regnum
>= tdep
->ppc_fp0_regnum
2692 && regnum
< (tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
2693 && (gdbarch_long_double_format (gdbarch
) == floatformats_ieee_quad
)
2694 && (type
->length() == 16))
2695 regnum
= regnum
- tdep
->ppc_fp0_regnum
+ tdep
->ppc_vsr0_regnum
;
2701 rs6000_register_to_value (frame_info_ptr frame
,
2705 int *optimizedp
, int *unavailablep
)
2707 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2708 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2710 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2712 /* We have an IEEE 128-bit float -- need to change regnum mapping from
2714 regnum
= ieee_128_float_regnum_adjust (gdbarch
, type
, regnum
);
2716 if (!get_frame_register_bytes (frame
, regnum
, 0,
2717 gdb::make_array_view (from
,
2718 register_size (gdbarch
,
2720 optimizedp
, unavailablep
))
2723 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2725 *optimizedp
= *unavailablep
= 0;
2730 rs6000_value_to_register (frame_info_ptr frame
,
2733 const gdb_byte
*from
)
2735 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2736 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2738 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2740 /* We have an IEEE 128-bit float -- need to change regnum mapping from
2742 regnum
= ieee_128_float_regnum_adjust (gdbarch
, type
, regnum
);
2744 target_float_convert (from
, type
,
2745 to
, builtin_type (gdbarch
)->builtin_double
);
2746 put_frame_register (frame
, regnum
, to
);
2749 static struct value
*
2750 rs6000_value_from_register (struct gdbarch
*gdbarch
, struct type
*type
,
2751 int regnum
, struct frame_id frame_id
)
2753 int len
= type
->length ();
2754 struct value
*value
= value::allocate (type
);
2756 /* We have an IEEE 128-bit float -- need to change regnum mapping from
2758 regnum
= ieee_128_float_regnum_adjust (gdbarch
, type
, regnum
);
2760 value
->set_lval (lval_register
);
2761 frame_info_ptr frame
= frame_find_by_id (frame_id
);
2764 frame_id
= null_frame_id
;
2766 frame_id
= get_frame_id (get_next_frame_sentinel_okay (frame
));
2768 VALUE_NEXT_FRAME_ID (value
) = frame_id
;
2769 VALUE_REGNUM (value
) = regnum
;
2771 /* Any structure stored in more than one register will always be
2772 an integral number of registers. Otherwise, you need to do
2773 some fiddling with the last register copied here for little
2775 if (type_byte_order (type
) == BFD_ENDIAN_BIG
2776 && len
< register_size (gdbarch
, regnum
))
2777 /* Big-endian, and we want less than full size. */
2778 value
->set_offset (register_size (gdbarch
, regnum
) - len
);
2780 value
->set_offset (0);
2785 /* The type of a function that moves the value of REG between CACHE
2786 or BUF --- in either direction. */
2787 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2790 /* Move SPE vector register values between a 64-bit buffer and the two
2791 32-bit raw register halves in a regcache. This function handles
2792 both splitting a 64-bit value into two 32-bit halves, and joining
2793 two halves into a whole 64-bit value, depending on the function
2794 passed as the MOVE argument.
2796 EV_REG must be the number of an SPE evN vector register --- a
2797 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2800 Call MOVE once for each 32-bit half of that register, passing
2801 REGCACHE, the number of the raw register corresponding to that
2802 half, and the address of the appropriate half of BUFFER.
2804 For example, passing 'regcache_raw_read' as the MOVE function will
2805 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2806 'regcache_raw_supply' will supply the contents of BUFFER to the
2807 appropriate pair of raw registers in REGCACHE.
2809 You may need to cast away some 'const' qualifiers when passing
2810 MOVE, since this function can't tell at compile-time which of
2811 REGCACHE or BUFFER is acting as the source of the data. If C had
2812 co-variant type qualifiers, ... */
2814 static enum register_status
2815 e500_move_ev_register (move_ev_register_func move
,
2816 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2818 struct gdbarch
*arch
= regcache
->arch ();
2819 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
2821 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2822 enum register_status status
;
2824 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2826 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2828 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2830 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2832 if (status
== REG_VALID
)
2833 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2838 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2839 if (status
== REG_VALID
)
2840 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2847 static enum register_status
2848 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2850 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2855 static enum register_status
2856 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2857 int ev_reg
, gdb_byte
*buffer
)
2859 struct gdbarch
*arch
= regcache
->arch ();
2860 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2862 enum register_status status
;
2864 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2866 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2868 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2870 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2872 if (status
== REG_VALID
)
2873 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2878 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2879 if (status
== REG_VALID
)
2880 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2889 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2890 int reg_nr
, const gdb_byte
*buffer
)
2892 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2893 reg_nr
, (void *) buffer
);
2896 /* Read method for DFP pseudo-registers. */
2897 static enum register_status
2898 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2899 int reg_nr
, gdb_byte
*buffer
)
2901 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2903 enum register_status status
;
2905 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2907 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2908 fp0
= PPC_F0_REGNUM
;
2912 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2914 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2915 fp0
= PPC_CF0_REGNUM
;
2918 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2920 /* Read two FP registers to form a whole dl register. */
2921 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2922 if (status
== REG_VALID
)
2923 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2928 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2929 if (status
== REG_VALID
)
2930 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2936 /* Write method for DFP pseudo-registers. */
2938 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2939 int reg_nr
, const gdb_byte
*buffer
)
2941 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2944 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2946 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2947 fp0
= PPC_F0_REGNUM
;
2951 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2953 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2954 fp0
= PPC_CF0_REGNUM
;
2957 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2959 /* Write each half of the dl register into a separate
2961 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2962 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2966 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2967 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2971 /* Read method for the vX aliases for the raw vrX registers. */
2973 static enum register_status
2974 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2975 readable_regcache
*regcache
, int reg_nr
,
2978 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2979 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2981 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2982 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2986 /* Write method for the vX aliases for the raw vrX registers. */
2989 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2990 struct regcache
*regcache
,
2991 int reg_nr
, const gdb_byte
*buffer
)
2993 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2994 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2996 regcache
->raw_write (tdep
->ppc_vr0_regnum
2997 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
3000 /* Read method for POWER7 VSX pseudo-registers. */
3001 static enum register_status
3002 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3003 int reg_nr
, gdb_byte
*buffer
)
3005 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3006 int reg_index
, vr0
, fp0
, vsr0_upper
;
3007 enum register_status status
;
3009 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3011 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3012 vr0
= PPC_VR0_REGNUM
;
3013 fp0
= PPC_F0_REGNUM
;
3014 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3018 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3020 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3021 vr0
= PPC_CVR0_REGNUM
;
3022 fp0
= PPC_CF0_REGNUM
;
3023 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3026 /* Read the portion that overlaps the VMX registers. */
3028 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
3030 /* Read the portion that overlaps the FPR registers. */
3031 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3033 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
3034 if (status
== REG_VALID
)
3035 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
3040 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
3041 if (status
== REG_VALID
)
3042 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
3048 /* Write method for POWER7 VSX pseudo-registers. */
3050 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3051 int reg_nr
, const gdb_byte
*buffer
)
3053 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3054 int reg_index
, vr0
, fp0
, vsr0_upper
;
3056 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3058 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3059 vr0
= PPC_VR0_REGNUM
;
3060 fp0
= PPC_F0_REGNUM
;
3061 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3065 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3067 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3068 vr0
= PPC_CVR0_REGNUM
;
3069 fp0
= PPC_CF0_REGNUM
;
3070 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3073 /* Write the portion that overlaps the VMX registers. */
3075 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
3077 /* Write the portion that overlaps the FPR registers. */
3078 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3080 regcache
->raw_write (fp0
+ reg_index
, buffer
);
3081 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
3085 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
3086 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
3090 /* Read method for POWER7 Extended FP pseudo-registers. */
3091 static enum register_status
3092 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3093 int reg_nr
, gdb_byte
*buffer
)
3095 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3098 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3100 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3101 vr0
= PPC_VR0_REGNUM
;
3105 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3107 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3108 vr0
= PPC_CVR0_REGNUM
;
3111 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3113 /* Read the portion that overlaps the VMX register. */
3114 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
3115 register_size (gdbarch
, reg_nr
),
3119 /* Write method for POWER7 Extended FP pseudo-registers. */
3121 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3122 int reg_nr
, const gdb_byte
*buffer
)
3124 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3126 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3128 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3130 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3131 vr0
= PPC_VR0_REGNUM
;
3135 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3137 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3138 vr0
= PPC_CVR0_REGNUM
;
3140 /* The call to raw_write_part fails silently if the initial read
3141 of the read-update-write sequence returns an invalid status,
3142 so we check this manually and throw an error if needed. */
3143 regcache
->raw_update (vr0
+ reg_index
);
3144 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3145 error (_("Cannot write to the checkpointed EFP register, "
3146 "the corresponding vector register is unavailable."));
3149 /* Write the portion that overlaps the VMX register. */
3150 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3151 register_size (gdbarch
, reg_nr
), buffer
);
3154 static enum register_status
3155 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3156 readable_regcache
*regcache
,
3157 int reg_nr
, gdb_byte
*buffer
)
3159 struct gdbarch
*regcache_arch
= regcache
->arch ();
3160 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3162 gdb_assert (regcache_arch
== gdbarch
);
3164 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3165 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3166 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3167 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3168 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3169 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3170 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3172 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3173 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3174 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3175 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3176 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3177 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3179 internal_error (_("rs6000_pseudo_register_read: "
3180 "called on unexpected register '%s' (%d)"),
3181 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3185 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3186 struct regcache
*regcache
,
3187 int reg_nr
, const gdb_byte
*buffer
)
3189 struct gdbarch
*regcache_arch
= regcache
->arch ();
3190 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3192 gdb_assert (regcache_arch
== gdbarch
);
3194 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3195 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3196 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3197 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3198 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3199 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3200 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3201 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3202 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3203 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3204 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3205 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3206 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3208 internal_error (_("rs6000_pseudo_register_write: "
3209 "called on unexpected register '%s' (%d)"),
3210 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3213 /* Set the register mask in AX with the registers that form the DFP or
3214 checkpointed DFP pseudo-register REG_NR. */
3217 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3218 struct agent_expr
*ax
, int reg_nr
)
3220 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3223 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3225 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3226 fp0
= PPC_F0_REGNUM
;
3230 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3232 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3233 fp0
= PPC_CF0_REGNUM
;
3236 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3237 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3240 /* Set the register mask in AX with the raw vector register that
3241 corresponds to its REG_NR alias. */
3244 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3245 struct agent_expr
*ax
, int reg_nr
)
3247 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3248 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3250 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3251 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3254 /* Set the register mask in AX with the registers that form the VSX or
3255 checkpointed VSX pseudo-register REG_NR. */
3258 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3259 struct agent_expr
*ax
, int reg_nr
)
3261 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3262 int reg_index
, vr0
, fp0
, vsr0_upper
;
3264 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3266 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3267 vr0
= PPC_VR0_REGNUM
;
3268 fp0
= PPC_F0_REGNUM
;
3269 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3273 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3275 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3276 vr0
= PPC_CVR0_REGNUM
;
3277 fp0
= PPC_CF0_REGNUM
;
3278 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3283 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3287 ax_reg_mask (ax
, fp0
+ reg_index
);
3288 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3292 /* Set the register mask in AX with the register that corresponds to
3293 the EFP or checkpointed EFP pseudo-register REG_NR. */
3296 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3297 struct agent_expr
*ax
, int reg_nr
)
3299 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3302 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3304 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3305 vr0
= PPC_VR0_REGNUM
;
3309 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3311 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3312 vr0
= PPC_CVR0_REGNUM
;
3315 ax_reg_mask (ax
, vr0
+ reg_index
);
3319 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3320 struct agent_expr
*ax
, int reg_nr
)
3322 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3323 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3325 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3326 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3327 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3329 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3330 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3332 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3334 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3336 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3338 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3339 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3341 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3343 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3344 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3346 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3349 internal_error (_("rs6000_pseudo_register_collect: "
3350 "called on unexpected register '%s' (%d)"),
3351 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3357 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3358 struct agent_expr
*ax
, struct axs_value
*value
,
3361 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3362 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3363 value
->kind
= axs_lvalue_register
;
3364 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3368 /* Convert a DBX STABS register number to a GDB register number. */
3370 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3372 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3374 if (0 <= num
&& num
<= 31)
3375 return tdep
->ppc_gp0_regnum
+ num
;
3376 else if (32 <= num
&& num
<= 63)
3377 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3378 specifies registers the architecture doesn't have? Our
3379 callers don't check the value we return. */
3380 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3381 else if (77 <= num
&& num
<= 108)
3382 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3383 else if (1200 <= num
&& num
< 1200 + 32)
3384 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3389 return tdep
->ppc_mq_regnum
;
3391 return tdep
->ppc_lr_regnum
;
3393 return tdep
->ppc_ctr_regnum
;
3395 return tdep
->ppc_xer_regnum
;
3397 return tdep
->ppc_vrsave_regnum
;
3399 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3401 return tdep
->ppc_acc_regnum
;
3403 return tdep
->ppc_spefscr_regnum
;
3410 /* Convert a Dwarf 2 register number to a GDB register number. */
3412 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3414 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3416 if (0 <= num
&& num
<= 31)
3417 return tdep
->ppc_gp0_regnum
+ num
;
3418 else if (32 <= num
&& num
<= 63)
3419 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3420 specifies registers the architecture doesn't have? Our
3421 callers don't check the value we return. */
3422 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3423 else if (1124 <= num
&& num
< 1124 + 32)
3424 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3425 else if (1200 <= num
&& num
< 1200 + 32)
3426 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3431 return tdep
->ppc_cr_regnum
;
3433 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3435 return tdep
->ppc_acc_regnum
;
3437 return tdep
->ppc_mq_regnum
;
3439 return tdep
->ppc_xer_regnum
;
3441 return tdep
->ppc_lr_regnum
;
3443 return tdep
->ppc_ctr_regnum
;
3445 return tdep
->ppc_vrsave_regnum
;
3447 return tdep
->ppc_spefscr_regnum
;
3450 /* Unknown DWARF register number. */
3454 /* Translate a .eh_frame register to DWARF register, or adjust a
3455 .debug_frame register. */
3458 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3460 /* GCC releases before 3.4 use GCC internal register numbering in
3461 .debug_frame (and .debug_info, et cetera). The numbering is
3462 different from the standard SysV numbering for everything except
3463 for GPRs and FPRs. We can not detect this problem in most cases
3464 - to get accurate debug info for variables living in lr, ctr, v0,
3465 et cetera, use a newer version of GCC. But we must detect
3466 one important case - lr is in column 65 in .debug_frame output,
3469 GCC 3.4, and the "hammer" branch, have a related problem. They
3470 record lr register saves in .debug_frame as 108, but still record
3471 the return column as 65. We fix that up too.
3473 We can do this because 65 is assigned to fpsr, and GCC never
3474 generates debug info referring to it. To add support for
3475 handwritten debug info that restores fpsr, we would need to add a
3476 producer version check to this. */
3485 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3486 internal register numbering; translate that to the standard DWARF2
3487 register numbering. */
3488 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3490 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3491 return num
- 68 + 86;
3492 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3493 return num
- 77 + 1124;
3505 case 109: /* vrsave */
3507 case 110: /* vscr */
3509 case 111: /* spe_acc */
3511 case 112: /* spefscr */
3519 /* Handling the various POWER/PowerPC variants. */
3521 /* Information about a particular processor variant. */
3525 /* Name of this variant. */
3528 /* English description of the variant. */
3529 const char *description
;
3531 /* bfd_arch_info.arch corresponding to variant. */
3532 enum bfd_architecture arch
;
3534 /* bfd_arch_info.mach corresponding to variant. */
3537 /* Target description for this variant. */
3538 const struct target_desc
**tdesc
;
3541 static struct ppc_variant variants
[] =
3543 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3544 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3545 {"power", "POWER user-level", bfd_arch_rs6000
,
3546 bfd_mach_rs6k
, &tdesc_rs6000
},
3547 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3548 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3549 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3550 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3551 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3552 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3553 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3554 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3555 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3556 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3557 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3558 604, &tdesc_powerpc_604
},
3559 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3560 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3561 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3562 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3563 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3564 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3565 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3566 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3567 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3568 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3569 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3570 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3573 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3574 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3575 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3576 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3577 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3578 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3579 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3580 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3581 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3582 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3583 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3584 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3586 /* FIXME: I haven't checked the register sets of the following. */
3587 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3588 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3589 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3590 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3591 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3592 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3594 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3597 /* Return the variant corresponding to architecture ARCH and machine number
3598 MACH. If no such variant exists, return null. */
3600 static const struct ppc_variant
*
3601 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3603 const struct ppc_variant
*v
;
3605 for (v
= variants
; v
->name
; v
++)
3606 if (arch
== v
->arch
&& mach
== v
->mach
)
3614 struct rs6000_frame_cache
3617 CORE_ADDR initial_sp
;
3618 trad_frame_saved_reg
*saved_regs
;
3620 /* Set BASE_P to true if this frame cache is properly initialized.
3621 Otherwise set to false because some registers or memory cannot
3624 /* Cache PC for building unavailable frame. */
3628 static struct rs6000_frame_cache
*
3629 rs6000_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3631 struct rs6000_frame_cache
*cache
;
3632 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3633 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3634 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3635 struct rs6000_framedata fdata
;
3636 int wordsize
= tdep
->wordsize
;
3637 CORE_ADDR func
= 0, pc
= 0;
3639 if ((*this_cache
) != NULL
)
3640 return (struct rs6000_frame_cache
*) (*this_cache
);
3641 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3642 (*this_cache
) = cache
;
3644 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3648 func
= get_frame_func (this_frame
);
3650 pc
= get_frame_pc (this_frame
);
3651 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3653 /* Figure out the parent's stack pointer. */
3655 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3656 address of the current frame. Things might be easier if the
3657 ->frame pointed to the outer-most address of the frame. In
3658 the mean time, the address of the prev frame is used as the
3659 base address of this frame. */
3660 cache
->base
= get_frame_register_unsigned
3661 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3663 catch (const gdb_exception_error
&ex
)
3665 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3667 return (struct rs6000_frame_cache
*) (*this_cache
);
3670 /* If the function appears to be frameless, check a couple of likely
3671 indicators that we have simply failed to find the frame setup.
3672 Two common cases of this are missing symbols (i.e.
3673 get_frame_func returns the wrong address or 0), and assembly
3674 stubs which have a fast exit path but set up a frame on the slow
3677 If the LR appears to return to this function, then presume that
3678 we have an ABI compliant frame that we failed to find. */
3679 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3684 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3685 if (func
== 0 && saved_lr
== pc
)
3689 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3690 if (func
== saved_func
)
3696 fdata
.frameless
= 0;
3697 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3701 if (!fdata
.frameless
)
3703 /* Frameless really means stackless. */
3706 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3707 byte_order
, &backchain
))
3708 cache
->base
= (CORE_ADDR
) backchain
;
3711 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3713 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3714 All fpr's from saved_fpr to fp31 are saved. */
3716 if (fdata
.saved_fpr
>= 0)
3719 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3721 /* If skip_prologue says floating-point registers were saved,
3722 but the current architecture has no floating-point registers,
3723 then that's strange. But we have no indices to even record
3724 the addresses under, so we just ignore it. */
3725 if (ppc_floating_point_unit_p (gdbarch
))
3726 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3728 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3733 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3734 All gpr's from saved_gpr to gpr31 are saved (except during the
3737 if (fdata
.saved_gpr
>= 0)
3740 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3741 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3743 if (fdata
.gpr_mask
& (1U << i
))
3744 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3745 gpr_addr
+= wordsize
;
3749 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3750 All vr's from saved_vr to vr31 are saved. */
3751 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3753 if (fdata
.saved_vr
>= 0)
3756 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3757 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3759 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3760 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3765 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3766 All vr's from saved_ev to ev31 are saved. ????? */
3767 if (tdep
->ppc_ev0_regnum
!= -1)
3769 if (fdata
.saved_ev
>= 0)
3772 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3773 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3775 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3777 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3778 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3780 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3785 /* If != 0, fdata.cr_offset is the offset from the frame that
3787 if (fdata
.cr_offset
!= 0)
3788 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3791 /* If != 0, fdata.lr_offset is the offset from the frame that
3793 if (fdata
.lr_offset
!= 0)
3794 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3796 else if (fdata
.lr_register
!= -1)
3797 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3798 /* The PC is found in the link register. */
3799 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3800 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3802 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3803 holds the VRSAVE. */
3804 if (fdata
.vrsave_offset
!= 0)
3805 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3806 + fdata
.vrsave_offset
);
3808 if (fdata
.alloca_reg
< 0)
3809 /* If no alloca register used, then fi->frame is the value of the
3810 %sp for this frame, and it is good enough. */
3812 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3815 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3822 rs6000_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3823 struct frame_id
*this_id
)
3825 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3830 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3834 /* This marks the outermost frame. */
3835 if (info
->base
== 0)
3838 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3841 static struct value
*
3842 rs6000_frame_prev_register (frame_info_ptr this_frame
,
3843 void **this_cache
, int regnum
)
3845 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3847 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3850 static const struct frame_unwind rs6000_frame_unwind
=
3854 default_frame_unwind_stop_reason
,
3855 rs6000_frame_this_id
,
3856 rs6000_frame_prev_register
,
3858 default_frame_sniffer
3861 /* Allocate and initialize a frame cache for an epilogue frame.
3862 SP is restored and prev-PC is stored in LR. */
3864 static struct rs6000_frame_cache
*
3865 rs6000_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3867 struct rs6000_frame_cache
*cache
;
3868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3869 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3872 return (struct rs6000_frame_cache
*) *this_cache
;
3874 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3875 (*this_cache
) = cache
;
3876 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3880 /* At this point the stack looks as if we just entered the
3881 function, and the return address is stored in LR. */
3884 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3885 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3888 cache
->initial_sp
= sp
;
3890 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3892 catch (const gdb_exception_error
&ex
)
3894 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3901 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3902 Return the frame ID of an epilogue frame. */
3905 rs6000_epilogue_frame_this_id (frame_info_ptr this_frame
,
3906 void **this_cache
, struct frame_id
*this_id
)
3909 struct rs6000_frame_cache
*info
=
3910 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3912 pc
= get_frame_func (this_frame
);
3913 if (info
->base
== 0)
3914 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3916 (*this_id
) = frame_id_build (info
->base
, pc
);
3919 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3920 Return the register value of REGNUM in previous frame. */
3922 static struct value
*
3923 rs6000_epilogue_frame_prev_register (frame_info_ptr this_frame
,
3924 void **this_cache
, int regnum
)
3926 struct rs6000_frame_cache
*info
=
3927 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3928 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3931 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3932 Check whether this an epilogue frame. */
3935 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3936 frame_info_ptr this_frame
,
3937 void **this_prologue_cache
)
3939 if (frame_relative_level (this_frame
) == 0)
3940 return rs6000_in_function_epilogue_frame_p (this_frame
,
3941 get_frame_arch (this_frame
),
3942 get_frame_pc (this_frame
));
3947 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3948 a function without debug information. */
3950 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3954 default_frame_unwind_stop_reason
,
3955 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3957 rs6000_epilogue_frame_sniffer
3962 rs6000_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
3964 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3966 return info
->initial_sp
;
3969 static const struct frame_base rs6000_frame_base
= {
3970 &rs6000_frame_unwind
,
3971 rs6000_frame_base_address
,
3972 rs6000_frame_base_address
,
3973 rs6000_frame_base_address
3976 static const struct frame_base
*
3977 rs6000_frame_base_sniffer (frame_info_ptr this_frame
)
3979 return &rs6000_frame_base
;
3982 /* DWARF-2 frame support. Used to handle the detection of
3983 clobbered registers during function calls. */
3986 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3987 struct dwarf2_frame_state_reg
*reg
,
3988 frame_info_ptr this_frame
)
3990 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3992 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3993 non-volatile registers. We will use the same code for both. */
3995 /* Call-saved GP registers. */
3996 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3997 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3998 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3999 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
4001 /* Call-clobbered GP registers. */
4002 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
4003 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
4004 || (regnum
== tdep
->ppc_gp0_regnum
))
4005 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
4007 /* Deal with FP registers, if supported. */
4008 if (tdep
->ppc_fp0_regnum
>= 0)
4010 /* Call-saved FP registers. */
4011 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
4012 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
4013 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
4015 /* Call-clobbered FP registers. */
4016 if ((regnum
>= tdep
->ppc_fp0_regnum
4017 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
4018 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
4021 /* Deal with ALTIVEC registers, if supported. */
4022 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
4024 /* Call-saved Altivec registers. */
4025 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
4026 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
4027 || regnum
== tdep
->ppc_vrsave_regnum
)
4028 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
4030 /* Call-clobbered Altivec registers. */
4031 if ((regnum
>= tdep
->ppc_vr0_regnum
4032 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
4033 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
4036 /* Handle PC register and Stack Pointer correctly. */
4037 if (regnum
== gdbarch_pc_regnum (gdbarch
))
4038 reg
->how
= DWARF2_FRAME_REG_RA
;
4039 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
4040 reg
->how
= DWARF2_FRAME_REG_CFA
;
4044 /* Return true if a .gnu_attributes section exists in BFD and it
4045 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
4046 section exists in BFD and it indicates that SPE extensions are in
4047 use. Check the .gnu.attributes section first, as the binary might be
4048 compiled for SPE, but not actually using SPE instructions. */
4051 bfd_uses_spe_extensions (bfd
*abfd
)
4054 gdb_byte
*contents
= NULL
;
4063 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
4064 could be using the SPE vector abi without actually using any spe
4065 bits whatsoever. But it's close enough for now. */
4066 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
4067 Tag_GNU_Power_ABI_Vector
);
4068 if (vector_abi
== 3)
4072 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
4076 size
= bfd_section_size (sect
);
4077 contents
= (gdb_byte
*) xmalloc (size
);
4078 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
4084 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
4090 char name[name_len rounded up to 4-byte alignment];
4091 char data[data_len];
4094 Technically, there's only supposed to be one such structure in a
4095 given apuinfo section, but the linker is not always vigilant about
4096 merging apuinfo sections from input files. Just go ahead and parse
4097 them all, exiting early when we discover the binary uses SPE
4100 It's not specified in what endianness the information in this
4101 section is stored. Assume that it's the endianness of the BFD. */
4105 unsigned int name_len
;
4106 unsigned int data_len
;
4109 /* If we can't read the first three fields, we're done. */
4113 name_len
= bfd_get_32 (abfd
, ptr
);
4114 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
4115 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
4116 type
= bfd_get_32 (abfd
, ptr
+ 8);
4119 /* The name must be "APUinfo\0". */
4121 && strcmp ((const char *) ptr
, "APUinfo") != 0)
4125 /* The type must be 2. */
4129 /* The data is stored as a series of uint32. The upper half of
4130 each uint32 indicates the particular APU used and the lower
4131 half indicates the revision of that APU. We just care about
4134 /* Not 4-byte quantities. */
4140 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
4141 unsigned int apu
= apuinfo
>> 16;
4145 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4147 if (apu
== 0x100 || apu
== 0x101)
4162 /* These are macros for parsing instruction fields (I.1.6.28) */
4164 #define PPC_FIELD(value, from, len) \
4165 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4166 #define PPC_SEXT(v, bs) \
4167 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4168 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4169 - ((CORE_ADDR) 1 << ((bs) - 1)))
4170 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4171 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4172 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4173 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4174 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4175 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4176 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4177 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4178 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4179 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4180 | (PPC_FIELD (insn, 16, 5) << 5))
4181 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4182 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4183 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4184 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4185 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4186 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4187 #define PPC_OE(insn) PPC_BIT (insn, 21)
4188 #define PPC_RC(insn) PPC_BIT (insn, 31)
4189 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4190 #define PPC_LK(insn) PPC_BIT (insn, 31)
4191 #define PPC_TX(insn) PPC_BIT (insn, 31)
4192 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4194 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4195 #define PPC_XTp(insn) ((PPC_BIT (insn, 10) << 5) \
4196 | PPC_FIELD (insn, 6, 4) << 1)
4197 #define PPC_XSp(insn) ((PPC_BIT (insn, 10) << 5) \
4198 | PPC_FIELD (insn, 6, 4) << 1)
4199 #define PPC_XER_NB(xer) (xer & 0x7f)
4201 /* The following macros are for the prefixed instructions. */
4202 #define P_PPC_D(insn_prefix, insn_suffix) \
4203 PPC_SEXT (PPC_FIELD (insn_prefix, 14, 18) << 16 \
4204 | PPC_FIELD (insn_suffix, 16, 16), 34)
4205 #define P_PPC_TX5(insn_sufix) PPC_BIT (insn_suffix, 5)
4206 #define P_PPC_TX15(insn_suffix) PPC_BIT (insn_suffix, 15)
4207 #define P_PPC_XT(insn_suffix) ((PPC_TX (insn_suffix) << 5) \
4208 | PPC_T (insn_suffix))
4209 #define P_PPC_XT5(insn_suffix) ((P_PPC_TX5 (insn_suffix) << 5) \
4210 | PPC_T (insn_suffix))
4211 #define P_PPC_XT15(insn_suffix) \
4212 ((P_PPC_TX15 (insn_suffix) << 5) | PPC_T (insn_suffix))
4214 /* Record Vector-Scalar Registers.
4215 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4216 Otherwise, it's just a VR register. Record them accordingly. */
4219 ppc_record_vsr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
, int vsr
)
4221 if (vsr
< 0 || vsr
>= 64)
4226 if (tdep
->ppc_vr0_regnum
>= 0)
4227 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4231 if (tdep
->ppc_fp0_regnum
>= 0)
4232 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4233 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4234 record_full_arch_list_add_reg (regcache
,
4235 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4241 /* The ppc_record_ACC_fpscr() records the changes to the VSR registers
4242 modified by a floating point instruction. The ENTRY argument selects which
4243 of the eight AT entries needs to be recorded. The boolean SAVE_FPSCR
4244 argument is set to TRUE to indicate the FPSCR also needs to be recorded.
4245 The function returns 0 on success. */
4248 ppc_record_ACC_fpscr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
,
4249 int entry
, bool save_fpscr
)
4252 if (entry
< 0 || entry
>= 8)
4255 /* The ACC register file consists of 8 register entries, each register
4256 entry consist of four 128-bit rows.
4258 The ACC rows map to specific VSR registers.
4264 ACC[7][0] -> VSR[28]
4265 ACC[7][1] -> VSR[29]
4266 ACC[7][2] -> VSR[30]
4267 ACC[7][3] -> VSR[31]
4270 In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31].
4272 In the future, the ACC may be implemented as an independent register file
4273 rather than mapping on top of the VSRs. This will then require the ACC to
4274 be assigned its own register number and the ptrace interface to be able
4275 access the ACC. Note the ptrace interface for the ACC will also need to
4278 /* ACC maps over the same VSR space as the fp registers. */
4279 for (i
= 0; i
< 4; i
++)
4281 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
4283 record_full_arch_list_add_reg (regcache
,
4284 tdep
->ppc_vsr0_upper_regnum
4289 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4294 /* Parse and record instructions primary opcode-4 at ADDR.
4295 Return 0 if successful. */
4298 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4299 CORE_ADDR addr
, uint32_t insn
)
4301 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4302 int ext
= PPC_FIELD (insn
, 21, 11);
4303 int vra
= PPC_FIELD (insn
, 11, 5);
4307 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4308 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4309 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4310 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4311 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4313 case 20: /* Move To VSR Byte Mask Immediate opcode, b2 = 0,
4315 case 21: /* Move To VSR Byte Mask Immediate opcode, b2 = 1,
4317 case 23: /* Vector Multiply-Sum & write Carry-out Unsigned
4319 case 24: /* Vector Extract Double Unsigned Byte to VSR
4320 using GPR-specified Left-Index */
4321 case 25: /* Vector Extract Double Unsigned Byte to VSR
4322 using GPR-specified Right-Index */
4323 case 26: /* Vector Extract Double Unsigned Halfword to VSR
4324 using GPR-specified Left-Index */
4325 case 27: /* Vector Extract Double Unsigned Halfword to VSR
4326 using GPR-specified Right-Index */
4327 case 28: /* Vector Extract Double Unsigned Word to VSR
4328 using GPR-specified Left-Index */
4329 case 29: /* Vector Extract Double Unsigned Word to VSR
4330 using GPR-specified Right-Index */
4331 case 30: /* Vector Extract Double Unsigned Doubleword to VSR
4332 using GPR-specified Left-Index */
4333 case 31: /* Vector Extract Double Unsigned Doubleword to VSR
4334 using GPR-specified Right-Index */
4335 case 42: /* Vector Select */
4336 case 43: /* Vector Permute */
4337 case 59: /* Vector Permute Right-indexed */
4338 case 22: /* Vector Shift
4339 Left Double by Bit Immediate if insn[21] = 0
4340 Right Double by Bit Immediate if insn[21] = 1 */
4341 case 44: /* Vector Shift Left Double by Octet Immediate */
4342 case 45: /* Vector Permute and Exclusive-OR */
4343 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4344 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4345 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4346 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4347 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4348 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4349 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4350 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4351 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4352 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4353 case 46: /* Vector Multiply-Add Single-Precision */
4354 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4355 record_full_arch_list_add_reg (regcache
,
4356 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4359 case 48: /* Multiply-Add High Doubleword */
4360 case 49: /* Multiply-Add High Doubleword Unsigned */
4361 case 51: /* Multiply-Add Low Doubleword */
4362 record_full_arch_list_add_reg (regcache
,
4363 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4367 switch ((ext
& 0x1ff))
4370 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4371 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4372 && vra
!= 4 /* Decimal Convert To Zoned */
4373 && vra
!= 5 /* Decimal Convert To National */
4374 && vra
!= 6 /* Decimal Convert From Zoned */
4375 && vra
!= 7 /* Decimal Convert From National */
4376 && vra
!= 31) /* Decimal Set Sign */
4379 /* 5.16 Decimal Integer Arithmetic Instructions */
4380 case 1: /* Decimal Add Modulo */
4381 case 65: /* Decimal Subtract Modulo */
4383 case 193: /* Decimal Shift */
4384 case 129: /* Decimal Unsigned Shift */
4385 case 449: /* Decimal Shift and Round */
4387 case 257: /* Decimal Truncate */
4388 case 321: /* Decimal Unsigned Truncate */
4390 /* Bit-21 should be set. */
4391 if (!PPC_BIT (insn
, 21))
4394 record_full_arch_list_add_reg (regcache
,
4395 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4396 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4400 /* Bit-21 is used for RC */
4401 switch (ext
& 0x3ff)
4403 case 5: /* Vector Rotate Left Quadword */
4404 case 69: /* Vector Rotate Left Quadword then Mask Insert */
4405 case 325: /* Vector Rotate Left Quadword then AND with Mask */
4406 case 6: /* Vector Compare Equal To Unsigned Byte */
4407 case 70: /* Vector Compare Equal To Unsigned Halfword */
4408 case 134: /* Vector Compare Equal To Unsigned Word */
4409 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4410 case 774: /* Vector Compare Greater Than Signed Byte */
4411 case 838: /* Vector Compare Greater Than Signed Halfword */
4412 case 902: /* Vector Compare Greater Than Signed Word */
4413 case 967: /* Vector Compare Greater Than Signed Doubleword */
4414 case 903: /* Vector Compare Greater Than Signed Quadword */
4415 case 518: /* Vector Compare Greater Than Unsigned Byte */
4416 case 646: /* Vector Compare Greater Than Unsigned Word */
4417 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4418 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4419 case 647: /* Vector Compare Greater Than Unsigned Quadword */
4420 case 966: /* Vector Compare Bounds Single-Precision */
4421 case 198: /* Vector Compare Equal To Single-Precision */
4422 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4423 case 455: /* Vector Compare Equal Quadword */
4424 case 710: /* Vector Compare Greater Than Single-Precision */
4425 case 7: /* Vector Compare Not Equal Byte */
4426 case 71: /* Vector Compare Not Equal Halfword */
4427 case 135: /* Vector Compare Not Equal Word */
4428 case 263: /* Vector Compare Not Equal or Zero Byte */
4429 case 327: /* Vector Compare Not Equal or Zero Halfword */
4430 case 391: /* Vector Compare Not Equal or Zero Word */
4432 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4433 record_full_arch_list_add_reg (regcache
,
4434 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4438 switch (vra
) /* Bit-21 is used for RC */
4440 case 0: /* Vector String Isolate Byte Left-justified */
4441 case 1: /* Vector String Isolate Byte Right-justified */
4442 case 2: /* Vector String Isolate Halfword Left-justified */
4443 case 3: /* Vector String Isolate Halfword Right-justified */
4445 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4446 record_full_arch_list_add_reg (regcache
,
4447 tdep
->ppc_vr0_regnum
4457 case 0: /* Vector Count Leading Zero Least-Significant Bits
4459 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4461 record_full_arch_list_add_reg (regcache
,
4462 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4465 case 6: /* Vector Negate Word */
4466 case 7: /* Vector Negate Doubleword */
4467 case 8: /* Vector Parity Byte Word */
4468 case 9: /* Vector Parity Byte Doubleword */
4469 case 10: /* Vector Parity Byte Quadword */
4470 case 16: /* Vector Extend Sign Byte To Word */
4471 case 17: /* Vector Extend Sign Halfword To Word */
4472 case 24: /* Vector Extend Sign Byte To Doubleword */
4473 case 25: /* Vector Extend Sign Halfword To Doubleword */
4474 case 26: /* Vector Extend Sign Word To Doubleword */
4475 case 27: /* Vector Extend Sign Doubleword To Quadword */
4476 case 28: /* Vector Count Trailing Zeros Byte */
4477 case 29: /* Vector Count Trailing Zeros Halfword */
4478 case 30: /* Vector Count Trailing Zeros Word */
4479 case 31: /* Vector Count Trailing Zeros Doubleword */
4480 record_full_arch_list_add_reg (regcache
,
4481 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4490 case 0: /* Vector Expand Byte Mask */
4491 case 1: /* Vector Expand Halfword Mask */
4492 case 2: /* Vector Expand Word Mask */
4493 case 3: /* Vector Expand Doubleword Mask */
4494 case 4: /* Vector Expand Quadword Mask */
4495 case 16: /* Move to VSR Byte Mask */
4496 case 17: /* Move to VSR Halfword Mask */
4497 case 18: /* Move to VSR Word Mask */
4498 case 19: /* Move to VSR Doubleword Mask */
4499 case 20: /* Move to VSR Quadword Mask */
4500 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
4503 case 8: /* Vector Extract Byte Mask */
4504 case 9: /* Vector Extract Halfword Mask */
4505 case 10: /* Vector Extract Word Mask */
4506 case 11: /* Vector Extract Doubleword Mask */
4507 case 12: /* Vector Extract Quadword Mask */
4509 /* Ignore the MP bit in the LSB position of the vra value. */
4510 case 24: /* Vector Count Mask Bits Byte, MP = 0 */
4511 case 25: /* Vector Count Mask Bits Byte, MP = 1 */
4512 case 26: /* Vector Count Mask Bits Halfword, MP = 0 */
4513 case 27: /* Vector Count Mask Bits Halfword, MP = 1 */
4514 case 28: /* Vector Count Mask Bits Word, MP = 0 */
4515 case 29: /* Vector Count Mask Bits Word, MP = 1 */
4516 case 30: /* Vector Count Mask Bits Doubleword, MP = 0 */
4517 case 31: /* Vector Count Mask Bits Doubleword, MP = 1 */
4518 record_full_arch_list_add_reg (regcache
,
4519 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4520 record_full_arch_list_add_reg (regcache
,
4521 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4529 case 257: /* Vector Compare Unsigned Quadword */
4530 case 321: /* Vector Compare Signed Quadword */
4531 /* Comparison tests that always set CR field BF */
4532 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4533 record_full_arch_list_add_reg (regcache
,
4534 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4537 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4538 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4539 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4540 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4541 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4542 case 462: /* Vector Pack Signed Word Signed Saturate */
4543 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4544 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4545 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4546 case 512: /* Vector Add Unsigned Byte Saturate */
4547 case 576: /* Vector Add Unsigned Halfword Saturate */
4548 case 640: /* Vector Add Unsigned Word Saturate */
4549 case 768: /* Vector Add Signed Byte Saturate */
4550 case 832: /* Vector Add Signed Halfword Saturate */
4551 case 896: /* Vector Add Signed Word Saturate */
4552 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4553 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4554 case 1664: /* Vector Subtract Unsigned Word Saturate */
4555 case 1792: /* Vector Subtract Signed Byte Saturate */
4556 case 1856: /* Vector Subtract Signed Halfword Saturate */
4557 case 1920: /* Vector Subtract Signed Word Saturate */
4559 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4560 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4561 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4562 case 1672: /* Vector Sum across Half Signed Word Saturate */
4563 case 1928: /* Vector Sum across Signed Word Saturate */
4564 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4565 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4566 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4568 case 12: /* Vector Merge High Byte */
4569 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4570 case 76: /* Vector Merge High Halfword */
4571 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4572 case 140: /* Vector Merge High Word */
4573 case 268: /* Vector Merge Low Byte */
4574 case 332: /* Vector Merge Low Halfword */
4575 case 396: /* Vector Merge Low Word */
4576 case 397: /* Vector Clear Leftmost Bytes */
4577 case 461: /* Vector Clear Rightmost Bytes */
4578 case 526: /* Vector Unpack High Signed Byte */
4579 case 590: /* Vector Unpack High Signed Halfword */
4580 case 654: /* Vector Unpack Low Signed Byte */
4581 case 718: /* Vector Unpack Low Signed Halfword */
4582 case 782: /* Vector Pack Pixel */
4583 case 846: /* Vector Unpack High Pixel */
4584 case 974: /* Vector Unpack Low Pixel */
4585 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4586 case 1614: /* Vector Unpack High Signed Word */
4587 case 1676: /* Vector Merge Odd Word */
4588 case 1742: /* Vector Unpack Low Signed Word */
4589 case 1932: /* Vector Merge Even Word */
4590 case 524: /* Vector Splat Byte */
4591 case 588: /* Vector Splat Halfword */
4592 case 652: /* Vector Splat Word */
4593 case 780: /* Vector Splat Immediate Signed Byte */
4594 case 844: /* Vector Splat Immediate Signed Halfword */
4595 case 908: /* Vector Splat Immediate Signed Word */
4596 case 261: /* Vector Shift Left Quadword */
4597 case 452: /* Vector Shift Left */
4598 case 517: /* Vector Shift Right Quadword */
4599 case 708: /* Vector Shift Right */
4600 case 773: /* Vector Shift Right Algebraic Quadword */
4601 case 1036: /* Vector Shift Left by Octet */
4602 case 1100: /* Vector Shift Right by Octet */
4603 case 0: /* Vector Add Unsigned Byte Modulo */
4604 case 64: /* Vector Add Unsigned Halfword Modulo */
4605 case 128: /* Vector Add Unsigned Word Modulo */
4606 case 192: /* Vector Add Unsigned Doubleword Modulo */
4607 case 256: /* Vector Add Unsigned Quadword Modulo */
4608 case 320: /* Vector Add & write Carry Unsigned Quadword */
4609 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4610 case 8: /* Vector Multiply Odd Unsigned Byte */
4611 case 72: /* Vector Multiply Odd Unsigned Halfword */
4612 case 136: /* Vector Multiply Odd Unsigned Word */
4613 case 200: /* Vector Multiply Odd Unsigned Doubleword */
4614 case 264: /* Vector Multiply Odd Signed Byte */
4615 case 328: /* Vector Multiply Odd Signed Halfword */
4616 case 392: /* Vector Multiply Odd Signed Word */
4617 case 456: /* Vector Multiply Odd Signed Doubleword */
4618 case 520: /* Vector Multiply Even Unsigned Byte */
4619 case 584: /* Vector Multiply Even Unsigned Halfword */
4620 case 648: /* Vector Multiply Even Unsigned Word */
4621 case 712: /* Vector Multiply Even Unsigned Doubleword */
4622 case 776: /* Vector Multiply Even Signed Byte */
4623 case 840: /* Vector Multiply Even Signed Halfword */
4624 case 904: /* Vector Multiply Even Signed Word */
4625 case 968: /* Vector Multiply Even Signed Doubleword */
4626 case 457: /* Vector Multiply Low Doubleword */
4627 case 649: /* Vector Multiply High Unsigned Word */
4628 case 713: /* Vector Multiply High Unsigned Doubleword */
4629 case 905: /* Vector Multiply High Signed Word */
4630 case 969: /* Vector Multiply High Signed Doubleword */
4631 case 11: /* Vector Divide Unsigned Quadword */
4632 case 203: /* Vector Divide Unsigned Doubleword */
4633 case 139: /* Vector Divide Unsigned Word */
4634 case 267: /* Vector Divide Signed Quadword */
4635 case 459: /* Vector Divide Signed Doubleword */
4636 case 395: /* Vector Divide Signed Word */
4637 case 523: /* Vector Divide Extended Unsigned Quadword */
4638 case 715: /* Vector Divide Extended Unsigned Doubleword */
4639 case 651: /* Vector Divide Extended Unsigned Word */
4640 case 779: /* Vector Divide Extended Signed Quadword */
4641 case 971: /* Vector Divide Extended Signed Doubleword */
4642 case 907: /* Vector Divide Extended Unsigned Word */
4643 case 1547: /* Vector Modulo Unsigned Quadword */
4644 case 1675: /* Vector Modulo Unsigned Word */
4645 case 1739: /* Vector Modulo Unsigned Doubleword */
4646 case 1803: /* Vector Modulo Signed Quadword */
4647 case 1931: /* Vector Modulo Signed Word */
4648 case 1995: /* Vector Modulo Signed Doubleword */
4650 case 137: /* Vector Multiply Unsigned Word Modulo */
4651 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4652 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4653 case 1152: /* Vector Subtract Unsigned Word Modulo */
4654 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4655 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4656 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4657 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4658 case 1282: /* Vector Average Signed Byte */
4659 case 1346: /* Vector Average Signed Halfword */
4660 case 1410: /* Vector Average Signed Word */
4661 case 1026: /* Vector Average Unsigned Byte */
4662 case 1090: /* Vector Average Unsigned Halfword */
4663 case 1154: /* Vector Average Unsigned Word */
4664 case 258: /* Vector Maximum Signed Byte */
4665 case 322: /* Vector Maximum Signed Halfword */
4666 case 386: /* Vector Maximum Signed Word */
4667 case 450: /* Vector Maximum Signed Doubleword */
4668 case 2: /* Vector Maximum Unsigned Byte */
4669 case 66: /* Vector Maximum Unsigned Halfword */
4670 case 130: /* Vector Maximum Unsigned Word */
4671 case 194: /* Vector Maximum Unsigned Doubleword */
4672 case 770: /* Vector Minimum Signed Byte */
4673 case 834: /* Vector Minimum Signed Halfword */
4674 case 898: /* Vector Minimum Signed Word */
4675 case 962: /* Vector Minimum Signed Doubleword */
4676 case 514: /* Vector Minimum Unsigned Byte */
4677 case 578: /* Vector Minimum Unsigned Halfword */
4678 case 642: /* Vector Minimum Unsigned Word */
4679 case 706: /* Vector Minimum Unsigned Doubleword */
4680 case 1028: /* Vector Logical AND */
4681 case 1668: /* Vector Logical Equivalent */
4682 case 1092: /* Vector Logical AND with Complement */
4683 case 1412: /* Vector Logical NAND */
4684 case 1348: /* Vector Logical OR with Complement */
4685 case 1156: /* Vector Logical OR */
4686 case 1284: /* Vector Logical NOR */
4687 case 1220: /* Vector Logical XOR */
4688 case 4: /* Vector Rotate Left Byte */
4689 case 132: /* Vector Rotate Left Word VX-form */
4690 case 68: /* Vector Rotate Left Halfword */
4691 case 196: /* Vector Rotate Left Doubleword */
4692 case 260: /* Vector Shift Left Byte */
4693 case 388: /* Vector Shift Left Word */
4694 case 324: /* Vector Shift Left Halfword */
4695 case 1476: /* Vector Shift Left Doubleword */
4696 case 516: /* Vector Shift Right Byte */
4697 case 644: /* Vector Shift Right Word */
4698 case 580: /* Vector Shift Right Halfword */
4699 case 1732: /* Vector Shift Right Doubleword */
4700 case 772: /* Vector Shift Right Algebraic Byte */
4701 case 900: /* Vector Shift Right Algebraic Word */
4702 case 836: /* Vector Shift Right Algebraic Halfword */
4703 case 964: /* Vector Shift Right Algebraic Doubleword */
4704 case 10: /* Vector Add Single-Precision */
4705 case 74: /* Vector Subtract Single-Precision */
4706 case 1034: /* Vector Maximum Single-Precision */
4707 case 1098: /* Vector Minimum Single-Precision */
4708 case 842: /* Vector Convert From Signed Fixed-Point Word */
4709 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4710 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4711 case 522: /* Vector Round to Single-Precision Integer Nearest */
4712 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4713 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4714 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4715 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4716 case 266: /* Vector Reciprocal Estimate Single-Precision */
4717 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4718 case 1288: /* Vector AES Cipher */
4719 case 1289: /* Vector AES Cipher Last */
4720 case 1352: /* Vector AES Inverse Cipher */
4721 case 1353: /* Vector AES Inverse Cipher Last */
4722 case 1480: /* Vector AES SubBytes */
4723 case 1730: /* Vector SHA-512 Sigma Doubleword */
4724 case 1666: /* Vector SHA-256 Sigma Word */
4725 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4726 case 1160: /* Vector Polynomial Multiply-Sum Word */
4727 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4728 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4729 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4730 case 1794: /* Vector Count Leading Zeros Byte */
4731 case 1858: /* Vector Count Leading Zeros Halfword */
4732 case 1922: /* Vector Count Leading Zeros Word */
4733 case 1924: /* Vector Count Leading Zeros Doubleword under
4735 case 1986: /* Vector Count Leading Zeros Doubleword */
4736 case 1988: /* Vector Count Trailing Zeros Doubleword under bit
4738 case 1795: /* Vector Population Count Byte */
4739 case 1859: /* Vector Population Count Halfword */
4740 case 1923: /* Vector Population Count Word */
4741 case 1987: /* Vector Population Count Doubleword */
4742 case 1356: /* Vector Bit Permute Quadword */
4743 case 1484: /* Vector Bit Permute Doubleword */
4744 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4745 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4747 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4748 case 65: /* Vector Multiply-by-10 Extended & write Carry
4749 Unsigned Quadword */
4750 case 1027: /* Vector Absolute Difference Unsigned Byte */
4751 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4752 case 1155: /* Vector Absolute Difference Unsigned Word */
4753 case 1796: /* Vector Shift Right Variable */
4754 case 1860: /* Vector Shift Left Variable */
4755 case 133: /* Vector Rotate Left Word then Mask Insert */
4756 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4757 case 389: /* Vector Rotate Left Word then AND with Mask */
4758 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4759 case 525: /* Vector Extract Unsigned Byte */
4760 case 589: /* Vector Extract Unsigned Halfword */
4761 case 653: /* Vector Extract Unsigned Word */
4762 case 717: /* Vector Extract Doubleword */
4763 case 15: /* Vector Insert Byte from VSR using GPR-specified
4765 case 79: /* Vector Insert Halfword from VSR using GPR-specified
4767 case 143: /* Vector Insert Word from VSR using GPR-specified
4769 case 207: /* Vector Insert Word from GPR using
4770 immediate-specified index */
4771 case 463: /* Vector Insert Doubleword from GPR using
4772 immediate-specified index */
4773 case 271: /* Vector Insert Byte from VSR using GPR-specified
4775 case 335: /* Vector Insert Halfword from VSR using GPR-specified
4777 case 399: /* Vector Insert Word from VSR using GPR-specified
4779 case 527: /* Vector Insert Byte from GPR using GPR-specified
4781 case 591: /* Vector Insert Halfword from GPR using GPR-specified
4783 case 655: /* Vector Insert Word from GPR using GPR-specified
4785 case 719: /* Vector Insert Doubleword from GPR using
4786 GPR-specified Left-Index */
4787 case 783: /* Vector Insert Byte from GPR using GPR-specified
4789 case 847: /* Vector Insert Halfword from GPR using GPR-specified
4791 case 911: /* Vector Insert Word from GPR using GPR-specified
4793 case 975: /* Vector Insert Doubleword from GPR using
4794 GPR-specified Right-Index */
4795 case 781: /* Vector Insert Byte */
4796 case 845: /* Vector Insert Halfword */
4797 case 909: /* Vector Insert Word */
4798 case 973: /* Vector Insert Doubleword */
4799 case 1357: /* Vector Centrifuge Doubleword */
4800 case 1421: /* Vector Parallel Bits Extract Doubleword */
4801 case 1485: /* Vector Parallel Bits Deposit Doubleword */
4802 record_full_arch_list_add_reg (regcache
,
4803 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4806 case 1228: /* Vector Gather every Nth Bit */
4807 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4808 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4809 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4810 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4811 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4812 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4813 record_full_arch_list_add_reg (regcache
,
4814 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4817 case 1604: /* Move To Vector Status and Control Register */
4818 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4820 case 1540: /* Move From Vector Status and Control Register */
4821 record_full_arch_list_add_reg (regcache
,
4822 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4824 case 833: /* Decimal Copy Sign */
4825 record_full_arch_list_add_reg (regcache
,
4826 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4827 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4831 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4832 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4836 /* Parse and record instructions of primary opcode 6 at ADDR.
4837 Return 0 if successful. */
4840 ppc_process_record_op6 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4841 CORE_ADDR addr
, uint32_t insn
)
4843 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4844 int subtype
= PPC_FIELD (insn
, 28, 4);
4849 case 0: /* Load VSX Vector Paired */
4850 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
4851 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
4853 case 1: /* Store VSX Vector Paired */
4854 if (PPC_RA (insn
) != 0)
4855 regcache_raw_read_unsigned (regcache
,
4856 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ea
);
4857 ea
+= PPC_DQ (insn
) << 4;
4858 record_full_arch_list_add_mem (ea
, 32);
4864 /* Parse and record instructions of primary opcode-19 at ADDR.
4865 Return 0 if successful. */
4868 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4869 CORE_ADDR addr
, uint32_t insn
)
4871 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4872 int ext
= PPC_EXTOP (insn
);
4874 switch (ext
& 0x01f)
4876 case 2: /* Add PC Immediate Shifted */
4877 record_full_arch_list_add_reg (regcache
,
4878 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4884 case 0: /* Move Condition Register Field */
4885 case 33: /* Condition Register NOR */
4886 case 129: /* Condition Register AND with Complement */
4887 case 193: /* Condition Register XOR */
4888 case 225: /* Condition Register NAND */
4889 case 257: /* Condition Register AND */
4890 case 289: /* Condition Register Equivalent */
4891 case 417: /* Condition Register OR with Complement */
4892 case 449: /* Condition Register OR */
4893 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4896 case 16: /* Branch Conditional */
4897 case 560: /* Branch Conditional to Branch Target Address Register */
4898 if ((PPC_BO (insn
) & 0x4) == 0)
4899 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4901 case 528: /* Branch Conditional to Count Register */
4903 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4906 case 150: /* Instruction Synchronize */
4911 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4912 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4916 /* Parse and record instructions of primary opcode-31 with the extended opcode
4917 177. The argument is the word instruction (insn). Return 0 if successful.
4921 ppc_process_record_op31_177 (struct gdbarch
*gdbarch
,
4922 struct regcache
*regcache
,
4925 int RA_opcode
= PPC_RA(insn
);
4926 int as
= PPC_FIELD (insn
, 6, 3);
4927 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4931 case 0: /* VSX Move From Accumulator, xxmfacc */
4932 case 1: /* VSX Move To Accumulator, xxmtacc */
4933 case 3: /* VSX Set Accumulator to Zero, xxsetaccz */
4934 ppc_record_ACC_fpscr (regcache
, tdep
, as
, false);
4940 /* Parse and record instructions of primary opcode-31 at ADDR.
4941 Return 0 if successful. */
4944 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4945 CORE_ADDR addr
, uint32_t insn
)
4947 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4948 int ext
= PPC_EXTOP (insn
);
4949 int tmp
, nr
, nb
= 0, i
;
4950 CORE_ADDR at_dcsz
, ea
= 0;
4951 ULONGEST rb
, ra
, xer
;
4954 /* These instructions have OE bit. */
4955 switch (ext
& 0x1ff)
4957 /* These write RT and XER. Update CR if RC is set. */
4958 case 8: /* Subtract from carrying */
4959 case 10: /* Add carrying */
4960 case 136: /* Subtract from extended */
4961 case 138: /* Add extended */
4962 case 200: /* Subtract from zero extended */
4963 case 202: /* Add to zero extended */
4964 case 232: /* Subtract from minus one extended */
4965 case 234: /* Add to minus one extended */
4966 /* CA is always altered, but SO/OV are only altered when OE=1.
4967 In any case, XER is always altered. */
4968 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4970 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4971 record_full_arch_list_add_reg (regcache
,
4972 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4975 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4976 case 40: /* Subtract from */
4977 case 104: /* Negate */
4978 case 233: /* Multiply low doubleword */
4979 case 235: /* Multiply low word */
4981 case 393: /* Divide Doubleword Extended Unsigned */
4982 case 395: /* Divide Word Extended Unsigned */
4983 case 425: /* Divide Doubleword Extended */
4984 case 427: /* Divide Word Extended */
4985 case 457: /* Divide Doubleword Unsigned */
4986 case 459: /* Divide Word Unsigned */
4987 case 489: /* Divide Doubleword */
4988 case 491: /* Divide Word */
4990 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4992 case 9: /* Multiply High Doubleword Unsigned */
4993 case 11: /* Multiply High Word Unsigned */
4994 case 73: /* Multiply High Doubleword */
4995 case 75: /* Multiply High Word */
4997 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4998 record_full_arch_list_add_reg (regcache
,
4999 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5003 if ((ext
& 0x1f) == 15)
5005 /* Integer Select. bit[16:20] is used for BC. */
5006 record_full_arch_list_add_reg (regcache
,
5007 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5011 if ((ext
& 0xff) == 170)
5013 /* Add Extended using alternate carry bits */
5014 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5015 record_full_arch_list_add_reg (regcache
,
5016 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5022 case 78: /* Determine Leftmost Zero Byte */
5024 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5025 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5026 record_full_arch_list_add_reg (regcache
,
5027 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5030 /* These only write RT. */
5031 case 19: /* Move from condition register */
5032 /* Move From One Condition Register Field */
5033 case 74: /* Add and Generate Sixes */
5034 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
5035 case 302: /* Move From Branch History Rolling Buffer */
5036 case 339: /* Move From Special Purpose Register */
5037 case 371: /* Move From Time Base [Phased-Out] */
5038 case 309: /* Load Doubleword Monitored Indexed */
5039 case 128: /* Set Boolean */
5040 case 384: /* Set Boolean Condition */
5041 case 416: /* Set Boolean Condition Reverse */
5042 case 448: /* Set Negative Boolean Condition */
5043 case 480: /* Set Negative Boolean Condition Reverse */
5044 case 755: /* Deliver A Random Number */
5045 record_full_arch_list_add_reg (regcache
,
5046 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5049 /* These only write to RA. */
5050 case 51: /* Move From VSR Doubleword */
5051 case 59: /* Count Leading Zeros Doubleword under bit Mask */
5052 case 115: /* Move From VSR Word and Zero */
5053 case 122: /* Population count bytes */
5054 case 155: /* Byte-Reverse Word */
5055 case 156: /* Parallel Bits Deposit Doubleword */
5056 case 187: /* Byte-Reverse Doubleword */
5057 case 188: /* Parallel Bits Extract Doubleword */
5058 case 219: /* Byte-Reverse Halfword */
5059 case 220: /* Centrifuge Doubleword */
5060 case 378: /* Population count words */
5061 case 506: /* Population count doublewords */
5062 case 154: /* Parity Word */
5063 case 186: /* Parity Doubleword */
5064 case 252: /* Bit Permute Doubleword */
5065 case 282: /* Convert Declets To Binary Coded Decimal */
5066 case 314: /* Convert Binary Coded Decimal To Declets */
5067 case 508: /* Compare bytes */
5068 case 307: /* Move From VSR Lower Doubleword */
5069 case 571: /* Count Trailing Zeros Doubleword under bit Mask */
5070 record_full_arch_list_add_reg (regcache
,
5071 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5074 /* These write CR and optional RA. */
5075 case 792: /* Shift Right Algebraic Word */
5076 case 794: /* Shift Right Algebraic Doubleword */
5077 case 824: /* Shift Right Algebraic Word Immediate */
5078 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
5079 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
5080 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5081 record_full_arch_list_add_reg (regcache
,
5082 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5084 case 0: /* Compare */
5085 case 32: /* Compare logical */
5086 case 144: /* Move To Condition Register Fields */
5087 /* Move To One Condition Register Field */
5088 case 192: /* Compare Ranged Byte */
5089 case 224: /* Compare Equal Byte */
5090 case 576: /* Move XER to CR Extended */
5091 case 902: /* Paste (should always fail due to single-stepping and
5092 the memory location might not be accessible, so
5094 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5097 /* These write to RT. Update RA if 'update indexed.' */
5098 case 53: /* Load Doubleword with Update Indexed */
5099 case 119: /* Load Byte and Zero with Update Indexed */
5100 case 311: /* Load Halfword and Zero with Update Indexed */
5101 case 55: /* Load Word and Zero with Update Indexed */
5102 case 375: /* Load Halfword Algebraic with Update Indexed */
5103 case 373: /* Load Word Algebraic with Update Indexed */
5104 record_full_arch_list_add_reg (regcache
,
5105 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5107 case 21: /* Load Doubleword Indexed */
5108 case 52: /* Load Byte And Reserve Indexed */
5109 case 116: /* Load Halfword And Reserve Indexed */
5110 case 20: /* Load Word And Reserve Indexed */
5111 case 84: /* Load Doubleword And Reserve Indexed */
5112 case 87: /* Load Byte and Zero Indexed */
5113 case 279: /* Load Halfword and Zero Indexed */
5114 case 23: /* Load Word and Zero Indexed */
5115 case 343: /* Load Halfword Algebraic Indexed */
5116 case 341: /* Load Word Algebraic Indexed */
5117 case 790: /* Load Halfword Byte-Reverse Indexed */
5118 case 534: /* Load Word Byte-Reverse Indexed */
5119 case 532: /* Load Doubleword Byte-Reverse Indexed */
5120 case 582: /* Load Word Atomic */
5121 case 614: /* Load Doubleword Atomic */
5122 case 265: /* Modulo Unsigned Doubleword */
5123 case 777: /* Modulo Signed Doubleword */
5124 case 267: /* Modulo Unsigned Word */
5125 case 779: /* Modulo Signed Word */
5126 record_full_arch_list_add_reg (regcache
,
5127 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5130 case 597: /* Load String Word Immediate */
5131 case 533: /* Load String Word Indexed */
5140 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5141 nr
= PPC_XER_NB (xer
);
5146 /* If n=0, the contents of register RT are undefined. */
5150 for (i
= 0; i
< nr
; i
++)
5151 record_full_arch_list_add_reg (regcache
,
5152 tdep
->ppc_gp0_regnum
5153 + ((PPC_RT (insn
) + i
) & 0x1f));
5156 case 276: /* Load Quadword And Reserve Indexed */
5157 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5158 record_full_arch_list_add_reg (regcache
, tmp
);
5159 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5162 /* These write VRT. */
5163 case 6: /* Load Vector for Shift Left Indexed */
5164 case 38: /* Load Vector for Shift Right Indexed */
5165 case 7: /* Load Vector Element Byte Indexed */
5166 case 39: /* Load Vector Element Halfword Indexed */
5167 case 71: /* Load Vector Element Word Indexed */
5168 case 103: /* Load Vector Indexed */
5169 case 359: /* Load Vector Indexed LRU */
5170 record_full_arch_list_add_reg (regcache
,
5171 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
5174 /* These write FRT. Update RA if 'update indexed.' */
5175 case 567: /* Load Floating-Point Single with Update Indexed */
5176 case 631: /* Load Floating-Point Double with Update Indexed */
5177 record_full_arch_list_add_reg (regcache
,
5178 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5180 case 535: /* Load Floating-Point Single Indexed */
5181 case 599: /* Load Floating-Point Double Indexed */
5182 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
5183 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
5184 record_full_arch_list_add_reg (regcache
,
5185 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5188 case 791: /* Load Floating-Point Double Pair Indexed */
5189 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5190 record_full_arch_list_add_reg (regcache
, tmp
);
5191 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5194 /* These write to destination register PPC_XT. */
5195 case 179: /* Move To VSR Doubleword */
5196 case 211: /* Move To VSR Word Algebraic */
5197 case 243: /* Move To VSR Word and Zero */
5198 case 588: /* Load VSX Scalar Doubleword Indexed */
5199 case 524: /* Load VSX Scalar Single-Precision Indexed */
5200 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
5201 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
5202 case 13: /* Load VSX Vector Rightmost Byte Indexed */
5203 case 45: /* Load VSX Vector Rightmost Halfword Indexed */
5204 case 77: /* Load VSX Vector Rightmost Word Indexed */
5205 case 109: /* Load VSX Vector Rightmost Doubleword Indexed */
5206 case 844: /* Load VSX Vector Doubleword*2 Indexed */
5207 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
5208 case 780: /* Load VSX Vector Word*4 Indexed */
5209 case 268: /* Load VSX Vector Indexed */
5210 case 364: /* Load VSX Vector Word & Splat Indexed */
5211 case 812: /* Load VSX Vector Halfword*8 Indexed */
5212 case 876: /* Load VSX Vector Byte*16 Indexed */
5213 case 269: /* Load VSX Vector with Length */
5214 case 301: /* Load VSX Vector Left-justified with Length */
5215 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
5216 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
5217 case 403: /* Move To VSR Word & Splat */
5218 case 435: /* Move To VSR Double Doubleword */
5219 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5222 case 333: /* Load VSX Vector Paired Indexed */
5223 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
5224 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
5227 /* These write RA. Update CR if RC is set. */
5228 case 24: /* Shift Left Word */
5229 case 26: /* Count Leading Zeros Word */
5230 case 27: /* Shift Left Doubleword */
5232 case 58: /* Count Leading Zeros Doubleword */
5233 case 60: /* AND with Complement */
5235 case 284: /* Equivalent */
5237 case 476: /* NAND */
5238 case 412: /* OR with Complement */
5240 case 536: /* Shift Right Word */
5241 case 539: /* Shift Right Doubleword */
5242 case 922: /* Extend Sign Halfword */
5243 case 954: /* Extend Sign Byte */
5244 case 986: /* Extend Sign Word */
5245 case 538: /* Count Trailing Zeros Word */
5246 case 570: /* Count Trailing Zeros Doubleword */
5247 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
5248 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
5250 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
5251 && (PPC_RS (insn
) == PPC_RA (insn
))
5252 && (PPC_RA (insn
) == PPC_RB (insn
))
5255 /* or Rx,Rx,Rx alters PRI in PPR. */
5256 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5261 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5262 record_full_arch_list_add_reg (regcache
,
5263 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5267 case 181: /* Store Doubleword with Update Indexed */
5268 case 183: /* Store Word with Update Indexed */
5269 case 247: /* Store Byte with Update Indexed */
5270 case 439: /* Store Half Word with Update Indexed */
5271 case 695: /* Store Floating-Point Single with Update Indexed */
5272 case 759: /* Store Floating-Point Double with Update Indexed */
5273 record_full_arch_list_add_reg (regcache
,
5274 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5276 case 135: /* Store Vector Element Byte Indexed */
5277 case 167: /* Store Vector Element Halfword Indexed */
5278 case 199: /* Store Vector Element Word Indexed */
5279 case 231: /* Store Vector Indexed */
5280 case 487: /* Store Vector Indexed LRU */
5281 case 716: /* Store VSX Scalar Doubleword Indexed */
5282 case 140: /* Store VSX Scalar as Integer Word Indexed */
5283 case 652: /* Store VSX Scalar Single-Precision Indexed */
5284 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5285 case 908: /* Store VSX Vector Word*4 Indexed */
5286 case 149: /* Store Doubleword Indexed */
5287 case 151: /* Store Word Indexed */
5288 case 215: /* Store Byte Indexed */
5289 case 407: /* Store Half Word Indexed */
5290 case 694: /* Store Byte Conditional Indexed */
5291 case 726: /* Store Halfword Conditional Indexed */
5292 case 150: /* Store Word Conditional Indexed */
5293 case 214: /* Store Doubleword Conditional Indexed */
5294 case 182: /* Store Quadword Conditional Indexed */
5295 case 662: /* Store Word Byte-Reverse Indexed */
5296 case 918: /* Store Halfword Byte-Reverse Indexed */
5297 case 660: /* Store Doubleword Byte-Reverse Indexed */
5298 case 663: /* Store Floating-Point Single Indexed */
5299 case 727: /* Store Floating-Point Double Indexed */
5300 case 919: /* Store Floating-Point Double Pair Indexed */
5301 case 983: /* Store Floating-Point as Integer Word Indexed */
5302 case 396: /* Store VSX Vector Indexed */
5303 case 940: /* Store VSX Vector Halfword*8 Indexed */
5304 case 1004: /* Store VSX Vector Byte*16 Indexed */
5305 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5306 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5307 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
5308 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5311 if (PPC_RA (insn
) != 0)
5312 regcache_raw_read_unsigned (regcache
,
5313 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5314 regcache_raw_read_unsigned (regcache
,
5315 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5320 case 183: /* Store Word with Update Indexed */
5321 case 199: /* Store Vector Element Word Indexed */
5322 case 140: /* Store VSX Scalar as Integer Word Indexed */
5323 case 652: /* Store VSX Scalar Single-Precision Indexed */
5324 case 151: /* Store Word Indexed */
5325 case 150: /* Store Word Conditional Indexed */
5326 case 662: /* Store Word Byte-Reverse Indexed */
5327 case 663: /* Store Floating-Point Single Indexed */
5328 case 695: /* Store Floating-Point Single with Update Indexed */
5329 case 983: /* Store Floating-Point as Integer Word Indexed */
5332 case 247: /* Store Byte with Update Indexed */
5333 case 135: /* Store Vector Element Byte Indexed */
5334 case 215: /* Store Byte Indexed */
5335 case 694: /* Store Byte Conditional Indexed */
5336 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5339 case 439: /* Store Halfword with Update Indexed */
5340 case 167: /* Store Vector Element Halfword Indexed */
5341 case 407: /* Store Halfword Indexed */
5342 case 726: /* Store Halfword Conditional Indexed */
5343 case 918: /* Store Halfword Byte-Reverse Indexed */
5344 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5347 case 181: /* Store Doubleword with Update Indexed */
5348 case 716: /* Store VSX Scalar Doubleword Indexed */
5349 case 149: /* Store Doubleword Indexed */
5350 case 214: /* Store Doubleword Conditional Indexed */
5351 case 660: /* Store Doubleword Byte-Reverse Indexed */
5352 case 727: /* Store Floating-Point Double Indexed */
5353 case 759: /* Store Floating-Point Double with Update Indexed */
5356 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5357 case 908: /* Store VSX Vector Word*4 Indexed */
5358 case 182: /* Store Quadword Conditional Indexed */
5359 case 231: /* Store Vector Indexed */
5360 case 487: /* Store Vector Indexed LRU */
5361 case 919: /* Store Floating-Point Double Pair Indexed */
5362 case 396: /* Store VSX Vector Indexed */
5363 case 940: /* Store VSX Vector Halfword*8 Indexed */
5364 case 1004: /* Store VSX Vector Byte*16 Indexed */
5371 /* Align address for Store Vector instructions. */
5374 case 167: /* Store Vector Element Halfword Indexed */
5378 case 199: /* Store Vector Element Word Indexed */
5382 case 231: /* Store Vector Indexed */
5383 case 487: /* Store Vector Indexed LRU */
5388 record_full_arch_list_add_mem (ea
, size
);
5391 case 141: /* Store VSX Vector Rightmost Byte Indexed */
5392 case 173: /* Store VSX Vector Rightmost Halfword Indexed */
5393 case 205: /* Store VSX Vector Rightmost Word Indexed */
5394 case 237: /* Store VSX Vector Rightmost Doubleword Indexed */
5407 if (PPC_RA (insn
) != 0)
5408 regcache_raw_read_unsigned (regcache
,
5409 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5410 regcache_raw_read_unsigned (regcache
,
5411 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5413 record_full_arch_list_add_mem (ea
, nb
);
5416 case 397: /* Store VSX Vector with Length */
5417 case 429: /* Store VSX Vector Left-justified with Length */
5419 if (PPC_RA (insn
) != 0)
5420 regcache_raw_read_unsigned (regcache
,
5421 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5423 regcache_raw_read_unsigned (regcache
,
5424 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5425 /* Store up to 16 bytes. */
5426 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
5428 record_full_arch_list_add_mem (ea
, nb
);
5431 case 461: /* Store VSX Vector Paired Indexed */
5433 if (PPC_RA (insn
) != 0)
5434 regcache_raw_read_unsigned (regcache
,
5435 tdep
->ppc_gp0_regnum
5436 + PPC_RA (insn
), &ea
);
5437 regcache_raw_read_unsigned (regcache
,
5438 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5440 record_full_arch_list_add_mem (ea
, 32);
5444 case 710: /* Store Word Atomic */
5445 case 742: /* Store Doubleword Atomic */
5447 if (PPC_RA (insn
) != 0)
5448 regcache_raw_read_unsigned (regcache
,
5449 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5453 case 710: /* Store Word Atomic */
5456 case 742: /* Store Doubleword Atomic */
5462 record_full_arch_list_add_mem (ea
, size
);
5465 case 725: /* Store String Word Immediate */
5467 if (PPC_RA (insn
) != 0)
5468 regcache_raw_read_unsigned (regcache
,
5469 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5476 record_full_arch_list_add_mem (ea
, nb
);
5480 case 661: /* Store String Word Indexed */
5482 if (PPC_RA (insn
) != 0)
5483 regcache_raw_read_unsigned (regcache
,
5484 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5487 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5488 nb
= PPC_XER_NB (xer
);
5492 regcache_raw_read_unsigned (regcache
,
5493 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5496 record_full_arch_list_add_mem (ea
, nb
);
5501 case 467: /* Move To Special Purpose Register */
5502 switch (PPC_SPR (insn
))
5505 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5508 if (tdep
->ppc_dscr_regnum
>= 0)
5509 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5512 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5515 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5517 case 256: /* VRSAVE */
5518 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5521 if (tdep
->ppc_tar_regnum
>= 0)
5522 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5526 if (tdep
->ppc_ppr_regnum
>= 0)
5527 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5533 case 147: /* Move To Split Little Endian */
5534 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5537 case 512: /* Move to Condition Register from XER */
5538 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5539 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5542 case 4: /* Trap Word */
5543 case 68: /* Trap Doubleword */
5544 case 430: /* Clear BHRB */
5545 case 598: /* Synchronize */
5546 case 62: /* Wait for Interrupt */
5548 case 22: /* Instruction Cache Block Touch */
5549 case 854: /* Enforce In-order Execution of I/O */
5550 case 246: /* Data Cache Block Touch for Store */
5551 case 54: /* Data Cache Block Store */
5552 case 86: /* Data Cache Block Flush */
5553 case 278: /* Data Cache Block Touch */
5554 case 758: /* Data Cache Block Allocate */
5555 case 982: /* Instruction Cache Block Invalidate */
5556 case 774: /* Copy */
5557 case 838: /* CP_Abort */
5560 case 654: /* Transaction Begin */
5561 case 686: /* Transaction End */
5562 case 750: /* Transaction Suspend or Resume */
5563 case 782: /* Transaction Abort Word Conditional */
5564 case 814: /* Transaction Abort Doubleword Conditional */
5565 case 846: /* Transaction Abort Word Conditional Immediate */
5566 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5567 case 910: /* Transaction Abort */
5568 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5570 case 718: /* Transaction Check */
5571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5574 case 1014: /* Data Cache Block set to Zero */
5575 if (target_auxv_search (AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5577 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5580 if (PPC_RA (insn
) != 0)
5581 regcache_raw_read_unsigned (regcache
,
5582 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5583 regcache_raw_read_unsigned (regcache
,
5584 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5585 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5586 record_full_arch_list_add_mem (ea
, at_dcsz
);
5590 if (ppc_process_record_op31_177 (gdbarch
, regcache
, insn
) == 0)
5595 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5596 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5600 /* Parse and record instructions of primary opcode-59 at ADDR.
5601 Return 0 if successful. */
5604 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5605 CORE_ADDR addr
, uint32_t insn
)
5607 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5608 int ext
= PPC_EXTOP (insn
);
5609 int at
= PPC_FIELD (insn
, 6, 3);
5611 /* Note the mnemonics for the pmxvf64ger* instructions were officially
5612 changed to pmdmxvf64ger*. The old mnemonics are still supported as
5613 extended mnemonics. */
5617 case 18: /* Floating Divide */
5618 case 20: /* Floating Subtract */
5619 case 21: /* Floating Add */
5620 case 22: /* Floating Square Root */
5621 case 24: /* Floating Reciprocal Estimate */
5622 case 25: /* Floating Multiply */
5623 case 26: /* Floating Reciprocal Square Root Estimate */
5624 case 28: /* Floating Multiply-Subtract */
5625 case 29: /* Floating Multiply-Add */
5626 case 30: /* Floating Negative Multiply-Subtract */
5627 case 31: /* Floating Negative Multiply-Add */
5628 record_full_arch_list_add_reg (regcache
,
5629 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5631 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5632 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5637 /* MMA instructions, keep looking. */
5638 switch (ext
>> 2) /* Additional opcode field is upper 8-bits of ext */
5640 case 3: /* VSX Vector 8-bit Signed/Unsigned Integer GER, xvi8ger4 */
5641 case 2: /* VSX Vector 8-bit Signed/Unsigned Integer GER Positive
5642 multiply, Positive accumulate, xvi8ger4pp */
5644 case 99: /* VSX Vector 8-bit Signed/Unsigned Integer GER with
5645 Saturate Positive multiply, Positive accumulate,
5648 case 35: /* VSX Vector 4-bit Signed Integer GER, xvi4ger8 */
5649 case 34: /* VSX Vector 4-bit Signed Integer GER Positive multiply,
5650 Positive accumulate, xvi4ger8pp */
5652 case 75: /* VSX Vector 16-bit Signed Integer GER, xvi16ger2 */
5653 case 107: /* VSX Vector 16-bit Signed Integer GER Positive multiply,
5654 Positive accumulate, xvi16ger2pp */
5656 case 43: /* VSX Vector 16-bit Signed Integer GER with Saturation,
5658 case 42: /* VSX Vector 16-bit Signed Integer GER with Saturation
5659 Positive multiply, Positive accumulate, xvi16ger2spp */
5660 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
5663 case 19: /* VSX Vector 16-bit Floating-Point GER, xvf16ger2 */
5664 case 18: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5665 Positive accumulate, xvf16ger2pp */
5666 case 146: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5667 Negative accumulate, xvf16ger2pn */
5668 case 82: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5669 Positive accumulate, xvf16ger2np */
5670 case 210: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5671 Negative accumulate, xvf16ger2nn */
5673 case 27: /* VSX Vector 32-bit Floating-Point GER, xvf32ger */
5674 case 26: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5675 Positive accumulate, xvf32gerpp */
5676 case 154: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5677 Negative accumulate, xvf32gerpn */
5678 case 90: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5679 Positive accumulate, xvf32gernp */
5680 case 218: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5681 Negative accumulate, xvf32gernn */
5683 case 59: /* VSX Vector 64-bit Floating-Point GER, pmdmxvf64ger
5685 case 58: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5686 Positive accumulate, xvf64gerpp */
5687 case 186: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5688 Negative accumulate, xvf64gerpn */
5689 case 122: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5690 Positive accumulate, xvf64gernp */
5691 case 250: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5692 Negative accumulate, pmdmxvf64gernn (pmxvf64gernn) */
5694 case 51: /* VSX Vector bfloat16 GER, xvbf16ger2 */
5695 case 50: /* VSX Vector bfloat16 GER Positive multiply,
5696 Positive accumulate, xvbf16ger2pp */
5697 case 178: /* VSX Vector bfloat16 GER Positive multiply,
5698 Negative accumulate, xvbf16ger2pn */
5699 case 114: /* VSX Vector bfloat16 GER Negative multiply,
5700 Positive accumulate, xvbf16ger2np */
5701 case 242: /* VSX Vector bfloat16 GER Negative multiply,
5702 Negative accumulate, xvbf16ger2nn */
5703 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
5709 case 2: /* DFP Add */
5710 case 3: /* DFP Quantize */
5711 case 34: /* DFP Multiply */
5712 case 35: /* DFP Reround */
5713 case 67: /* DFP Quantize Immediate */
5714 case 99: /* DFP Round To FP Integer With Inexact */
5715 case 227: /* DFP Round To FP Integer Without Inexact */
5716 case 258: /* DFP Convert To DFP Long! */
5717 case 290: /* DFP Convert To Fixed */
5718 case 514: /* DFP Subtract */
5719 case 546: /* DFP Divide */
5720 case 770: /* DFP Round To DFP Short! */
5721 case 802: /* DFP Convert From Fixed */
5722 case 834: /* DFP Encode BCD To DPD */
5724 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5725 record_full_arch_list_add_reg (regcache
,
5726 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5727 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5730 case 130: /* DFP Compare Ordered */
5731 case 162: /* DFP Test Exponent */
5732 case 194: /* DFP Test Data Class */
5733 case 226: /* DFP Test Data Group */
5734 case 642: /* DFP Compare Unordered */
5735 case 674: /* DFP Test Significance */
5736 case 675: /* DFP Test Significance Immediate */
5737 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5738 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5741 case 66: /* DFP Shift Significand Left Immediate */
5742 case 98: /* DFP Shift Significand Right Immediate */
5743 case 322: /* DFP Decode DPD To BCD */
5744 case 354: /* DFP Extract Biased Exponent */
5745 case 866: /* DFP Insert Biased Exponent */
5746 record_full_arch_list_add_reg (regcache
,
5747 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5749 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5752 case 846: /* Floating Convert From Integer Doubleword Single */
5753 case 974: /* Floating Convert From Integer Doubleword Unsigned
5755 record_full_arch_list_add_reg (regcache
,
5756 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5758 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5759 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5764 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5765 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5769 /* Parse and record an XX2-Form instruction with opcode 60 at ADDR. The
5770 word instruction is an argument insn. Return 0 if successful. */
5773 ppc_process_record_op60_XX2 (struct gdbarch
*gdbarch
,
5774 struct regcache
*regcache
,
5775 CORE_ADDR addr
, uint32_t insn
)
5777 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5778 int RA_opcode
= PPC_RA(insn
);
5782 case 2: /* VSX Vector Test Least-Significant Bit by Byte */
5783 case 25: /* VSX Vector round and Convert Single-Precision format
5784 to Half-Precision format. Only changes the CR
5786 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5788 case 17: /* VSX Vector Convert with round Single-Precision
5789 to bfloat16 format */
5790 case 24: /* VSX Vector Convert Half-Precision format to
5791 Single-Precision format */
5792 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5794 case 0: /* VSX Vector Extract Exponent Double-Precision */
5795 case 1: /* VSX Vector Extract Significand Double-Precision */
5796 case 7: /* VSX Vector Byte-Reverse Halfword */
5797 case 8: /* VSX Vector Extract Exponent Single-Precision */
5798 case 9: /* VSX Vector Extract Significand Single-Precision */
5799 case 15: /* VSX Vector Byte-Reverse Word */
5800 case 16: /* VSX Vector Convert bfloat16 to Single-Precision
5801 format Non-signaling */
5802 case 23: /* VSX Vector Byte-Reverse Doubleword */
5803 case 31: /* VSX Vector Byte-Reverse Quadword */
5804 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5811 /* Parse and record instructions of primary opcode-60 at ADDR.
5812 Return 0 if successful. */
5815 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5816 CORE_ADDR addr
, uint32_t insn
)
5818 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5819 int ext
= PPC_EXTOP (insn
);
5823 case 0: /* VSX Scalar Add Single-Precision */
5824 case 32: /* VSX Scalar Add Double-Precision */
5825 case 24: /* VSX Scalar Divide Single-Precision */
5826 case 56: /* VSX Scalar Divide Double-Precision */
5827 case 176: /* VSX Scalar Copy Sign Double-Precision */
5828 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5829 case 41: /* ditto */
5830 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5832 case 160: /* VSX Scalar Maximum Double-Precision */
5833 case 168: /* VSX Scalar Minimum Double-Precision */
5834 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5835 case 57: /* ditto */
5836 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5837 case 25: /* ditto */
5838 case 48: /* VSX Scalar Multiply Double-Precision */
5839 case 16: /* VSX Scalar Multiply Single-Precision */
5840 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5841 case 169: /* ditto */
5842 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5843 case 137: /* ditto */
5844 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5845 case 185: /* ditto */
5846 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5847 case 153: /* ditto */
5848 case 40: /* VSX Scalar Subtract Double-Precision */
5849 case 8: /* VSX Scalar Subtract Single-Precision */
5850 case 96: /* VSX Vector Add Double-Precision */
5851 case 64: /* VSX Vector Add Single-Precision */
5852 case 120: /* VSX Vector Divide Double-Precision */
5853 case 88: /* VSX Vector Divide Single-Precision */
5854 case 97: /* VSX Vector Multiply-Add Double-Precision */
5855 case 105: /* ditto */
5856 case 65: /* VSX Vector Multiply-Add Single-Precision */
5857 case 73: /* ditto */
5858 case 224: /* VSX Vector Maximum Double-Precision */
5859 case 192: /* VSX Vector Maximum Single-Precision */
5860 case 232: /* VSX Vector Minimum Double-Precision */
5861 case 200: /* VSX Vector Minimum Single-Precision */
5862 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5863 case 121: /* ditto */
5864 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5865 case 89: /* ditto */
5866 case 112: /* VSX Vector Multiply Double-Precision */
5867 case 80: /* VSX Vector Multiply Single-Precision */
5868 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5869 case 233: /* ditto */
5870 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5871 case 201: /* ditto */
5872 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5873 case 249: /* ditto */
5874 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5875 case 217: /* ditto */
5876 case 104: /* VSX Vector Subtract Double-Precision */
5877 case 72: /* VSX Vector Subtract Single-Precision */
5878 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5879 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5880 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5881 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5882 case 3: /* VSX Scalar Compare Equal Double-Precision */
5883 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5884 case 19: /* VSX Scalar Compare Greater Than or Equal
5886 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5888 case 240: /* VSX Vector Copy Sign Double-Precision */
5889 case 208: /* VSX Vector Copy Sign Single-Precision */
5890 case 130: /* VSX Logical AND */
5891 case 138: /* VSX Logical AND with Complement */
5892 case 186: /* VSX Logical Equivalence */
5893 case 178: /* VSX Logical NAND */
5894 case 170: /* VSX Logical OR with Complement */
5895 case 162: /* VSX Logical NOR */
5896 case 146: /* VSX Logical OR */
5897 case 154: /* VSX Logical XOR */
5898 case 18: /* VSX Merge High Word */
5899 case 50: /* VSX Merge Low Word */
5900 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5901 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5902 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5903 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5904 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5905 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5906 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5907 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5908 case 216: /* VSX Vector Insert Exponent Single-Precision */
5909 case 248: /* VSX Vector Insert Exponent Double-Precision */
5910 case 26: /* VSX Vector Permute */
5911 case 58: /* VSX Vector Permute Right-indexed */
5912 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5913 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5914 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5915 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5916 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5919 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5920 case 125: /* VSX Vector Test for software Divide Double-Precision */
5921 case 93: /* VSX Vector Test for software Divide Single-Precision */
5922 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5925 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5926 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5927 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5928 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5929 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5933 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5935 case 99: /* VSX Vector Compare Equal To Double-Precision */
5936 case 67: /* VSX Vector Compare Equal To Single-Precision */
5937 case 115: /* VSX Vector Compare Greater Than or
5938 Equal To Double-Precision */
5939 case 83: /* VSX Vector Compare Greater Than or
5940 Equal To Single-Precision */
5941 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5942 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5944 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5945 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5946 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5952 case 265: /* VSX Scalar round Double-Precision to
5953 Single-Precision and Convert to
5954 Single-Precision format */
5955 case 344: /* VSX Scalar truncate Double-Precision to
5956 Integer and Convert to Signed Integer
5957 Doubleword format with Saturate */
5958 case 88: /* VSX Scalar truncate Double-Precision to
5959 Integer and Convert to Signed Integer Word
5960 Format with Saturate */
5961 case 328: /* VSX Scalar truncate Double-Precision integer
5962 and Convert to Unsigned Integer Doubleword
5963 Format with Saturate */
5964 case 72: /* VSX Scalar truncate Double-Precision to
5965 Integer and Convert to Unsigned Integer Word
5966 Format with Saturate */
5967 case 329: /* VSX Scalar Convert Single-Precision to
5968 Double-Precision format */
5969 case 376: /* VSX Scalar Convert Signed Integer
5970 Doubleword to floating-point format and
5971 Round to Double-Precision format */
5972 case 312: /* VSX Scalar Convert Signed Integer
5973 Doubleword to floating-point format and
5974 round to Single-Precision */
5975 case 360: /* VSX Scalar Convert Unsigned Integer
5976 Doubleword to floating-point format and
5977 Round to Double-Precision format */
5978 case 296: /* VSX Scalar Convert Unsigned Integer
5979 Doubleword to floating-point format and
5980 Round to Single-Precision */
5981 case 73: /* VSX Scalar Round to Double-Precision Integer
5982 Using Round to Nearest Away */
5983 case 107: /* VSX Scalar Round to Double-Precision Integer
5984 Exact using Current rounding mode */
5985 case 121: /* VSX Scalar Round to Double-Precision Integer
5986 Using Round toward -Infinity */
5987 case 105: /* VSX Scalar Round to Double-Precision Integer
5988 Using Round toward +Infinity */
5989 case 89: /* VSX Scalar Round to Double-Precision Integer
5990 Using Round toward Zero */
5991 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5992 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5993 case 281: /* VSX Scalar Round to Single-Precision */
5994 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5996 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5998 case 75: /* VSX Scalar Square Root Double-Precision */
5999 case 11: /* VSX Scalar Square Root Single-Precision */
6000 case 393: /* VSX Vector round Double-Precision to
6001 Single-Precision and Convert to
6002 Single-Precision format */
6003 case 472: /* VSX Vector truncate Double-Precision to
6004 Integer and Convert to Signed Integer
6005 Doubleword format with Saturate */
6006 case 216: /* VSX Vector truncate Double-Precision to
6007 Integer and Convert to Signed Integer Word
6008 Format with Saturate */
6009 case 456: /* VSX Vector truncate Double-Precision to
6010 Integer and Convert to Unsigned Integer
6011 Doubleword format with Saturate */
6012 case 200: /* VSX Vector truncate Double-Precision to
6013 Integer and Convert to Unsigned Integer Word
6014 Format with Saturate */
6015 case 457: /* VSX Vector Convert Single-Precision to
6016 Double-Precision format */
6017 case 408: /* VSX Vector truncate Single-Precision to
6018 Integer and Convert to Signed Integer
6019 Doubleword format with Saturate */
6020 case 152: /* VSX Vector truncate Single-Precision to
6021 Integer and Convert to Signed Integer Word
6022 Format with Saturate */
6023 case 392: /* VSX Vector truncate Single-Precision to
6024 Integer and Convert to Unsigned Integer
6025 Doubleword format with Saturate */
6026 case 136: /* VSX Vector truncate Single-Precision to
6027 Integer and Convert to Unsigned Integer Word
6028 Format with Saturate */
6029 case 504: /* VSX Vector Convert and round Signed Integer
6030 Doubleword to Double-Precision format */
6031 case 440: /* VSX Vector Convert and round Signed Integer
6032 Doubleword to Single-Precision format */
6033 case 248: /* VSX Vector Convert Signed Integer Word to
6034 Double-Precision format */
6035 case 184: /* VSX Vector Convert and round Signed Integer
6036 Word to Single-Precision format */
6037 case 488: /* VSX Vector Convert and round Unsigned
6038 Integer Doubleword to Double-Precision format */
6039 case 424: /* VSX Vector Convert and round Unsigned
6040 Integer Doubleword to Single-Precision format */
6041 case 232: /* VSX Vector Convert and round Unsigned
6042 Integer Word to Double-Precision format */
6043 case 168: /* VSX Vector Convert and round Unsigned
6044 Integer Word to Single-Precision format */
6045 case 201: /* VSX Vector Round to Double-Precision
6046 Integer using round to Nearest Away */
6047 case 235: /* VSX Vector Round to Double-Precision
6048 Integer Exact using Current rounding mode */
6049 case 249: /* VSX Vector Round to Double-Precision
6050 Integer using round toward -Infinity */
6051 case 233: /* VSX Vector Round to Double-Precision
6052 Integer using round toward +Infinity */
6053 case 217: /* VSX Vector Round to Double-Precision
6054 Integer using round toward Zero */
6055 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
6056 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
6057 case 137: /* VSX Vector Round to Single-Precision Integer
6058 Using Round to Nearest Away */
6059 case 171: /* VSX Vector Round to Single-Precision Integer
6060 Exact Using Current rounding mode */
6061 case 185: /* VSX Vector Round to Single-Precision Integer
6062 Using Round toward -Infinity */
6063 case 169: /* VSX Vector Round to Single-Precision Integer
6064 Using Round toward +Infinity */
6065 case 153: /* VSX Vector Round to Single-Precision Integer
6066 Using round toward Zero */
6067 case 202: /* VSX Vector Reciprocal Square Root Estimate
6069 case 138: /* VSX Vector Reciprocal Square Root Estimate
6071 case 203: /* VSX Vector Square Root Double-Precision */
6072 case 139: /* VSX Vector Square Root Single-Precision */
6073 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6075 case 345: /* VSX Scalar Absolute Value Double-Precision */
6076 case 267: /* VSX Scalar Convert Scalar Single-Precision to
6077 Vector Single-Precision format Non-signalling */
6078 case 331: /* VSX Scalar Convert Single-Precision to
6079 Double-Precision format Non-signalling */
6080 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
6081 case 377: /* VSX Scalar Negate Double-Precision */
6082 case 473: /* VSX Vector Absolute Value Double-Precision */
6083 case 409: /* VSX Vector Absolute Value Single-Precision */
6084 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
6085 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
6086 case 505: /* VSX Vector Negate Double-Precision */
6087 case 441: /* VSX Vector Negate Single-Precision */
6088 case 164: /* VSX Splat Word */
6089 case 165: /* VSX Vector Extract Unsigned Word */
6090 case 181: /* VSX Vector Insert Word */
6091 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6094 case 298: /* VSX Scalar Test Data Class Single-Precision */
6095 case 362: /* VSX Scalar Test Data Class Double-Precision */
6096 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6098 case 106: /* VSX Scalar Test for software Square Root
6100 case 234: /* VSX Vector Test for software Square Root
6102 case 170: /* VSX Vector Test for software Square Root
6104 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6108 switch (PPC_FIELD (insn
, 11, 5))
6110 case 0: /* VSX Scalar Extract Exponent Double-Precision */
6111 case 1: /* VSX Scalar Extract Significand Double-Precision */
6112 record_full_arch_list_add_reg (regcache
,
6113 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6115 case 16: /* VSX Scalar Convert Half-Precision format to
6116 Double-Precision format */
6117 case 17: /* VSX Scalar round & Convert Double-Precision format
6118 to Half-Precision format */
6119 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6120 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6126 if (ppc_process_record_op60_XX2 (gdbarch
, regcache
, addr
, insn
) != 0)
6134 if (PPC_FIELD (insn
, 11, 2) == 0) /* VSX Vector Splat Immediate Byte */
6136 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6139 if (PPC_FIELD (insn
, 11, 5) == 31) /* Load VSX Vector Special Value
6142 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6146 case 916: /* VSX Vector Generate PCV from Byte Mask */
6147 case 917: /* VSX Vector Generate PCV from Halfword Mask */
6148 case 948: /* VSX Vector Generate PCV from Word Mask */
6149 case 949: /* VSX Vector Generate PCV from Doubleword Mask */
6150 case 918: /* VSX Scalar Insert Exponent Double-Precision */
6151 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6155 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
6157 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6161 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6162 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6166 /* Parse and record instructions of primary opcode-61 at ADDR.
6167 Return 0 if successful. */
6170 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6171 CORE_ADDR addr
, uint32_t insn
)
6173 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6179 case 0: /* Store Floating-Point Double Pair */
6180 case 2: /* Store VSX Scalar Doubleword */
6181 case 3: /* Store VSX Scalar Single */
6182 if (PPC_RA (insn
) != 0)
6183 regcache_raw_read_unsigned (regcache
,
6184 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6186 ea
+= PPC_DS (insn
) << 2;
6189 case 0: /* Store Floating-Point Double Pair */
6192 case 2: /* Store VSX Scalar Doubleword */
6195 case 3: /* Store VSX Scalar Single */
6201 record_full_arch_list_add_mem (ea
, size
);
6207 case 1: /* Load VSX Vector */
6208 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6210 case 5: /* Store VSX Vector */
6211 if (PPC_RA (insn
) != 0)
6212 regcache_raw_read_unsigned (regcache
,
6213 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6215 ea
+= PPC_DQ (insn
) << 4;
6216 record_full_arch_list_add_mem (ea
, 16);
6220 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6221 "at %s.\n", insn
, paddress (gdbarch
, addr
));
6225 /* Parse and record instructions of primary opcode-63 at ADDR.
6226 Return 0 if successful. */
6229 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6230 CORE_ADDR addr
, uint32_t insn
)
6232 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6233 int ext
= PPC_EXTOP (insn
);
6238 case 18: /* Floating Divide */
6239 case 20: /* Floating Subtract */
6240 case 21: /* Floating Add */
6241 case 22: /* Floating Square Root */
6242 case 24: /* Floating Reciprocal Estimate */
6243 case 25: /* Floating Multiply */
6244 case 26: /* Floating Reciprocal Square Root Estimate */
6245 case 28: /* Floating Multiply-Subtract */
6246 case 29: /* Floating Multiply-Add */
6247 case 30: /* Floating Negative Multiply-Subtract */
6248 case 31: /* Floating Negative Multiply-Add */
6249 record_full_arch_list_add_reg (regcache
,
6250 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6252 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6253 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6256 case 23: /* Floating Select */
6257 record_full_arch_list_add_reg (regcache
,
6258 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6260 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6266 case 5: /* VSX Scalar Round to Quad-Precision Integer */
6267 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
6269 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6270 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6276 case 2: /* DFP Add Quad */
6277 case 3: /* DFP Quantize Quad */
6278 case 34: /* DFP Multiply Quad */
6279 case 35: /* DFP Reround Quad */
6280 case 67: /* DFP Quantize Immediate Quad */
6281 case 99: /* DFP Round To FP Integer With Inexact Quad */
6282 case 227: /* DFP Round To FP Integer Without Inexact Quad */
6283 case 258: /* DFP Convert To DFP Extended Quad */
6284 case 514: /* DFP Subtract Quad */
6285 case 546: /* DFP Divide Quad */
6286 case 770: /* DFP Round To DFP Long Quad */
6287 case 802: /* DFP Convert From Fixed Quad */
6288 case 834: /* DFP Encode BCD To DPD Quad */
6290 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6291 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6292 record_full_arch_list_add_reg (regcache
, tmp
);
6293 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6294 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6297 case 130: /* DFP Compare Ordered Quad */
6298 case 162: /* DFP Test Exponent Quad */
6299 case 194: /* DFP Test Data Class Quad */
6300 case 226: /* DFP Test Data Group Quad */
6301 case 642: /* DFP Compare Unordered Quad */
6302 case 674: /* DFP Test Significance Quad */
6303 case 675: /* DFP Test Significance Immediate Quad */
6304 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6305 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6308 case 66: /* DFP Shift Significand Left Immediate Quad */
6309 case 98: /* DFP Shift Significand Right Immediate Quad */
6310 case 322: /* DFP Decode DPD To BCD Quad */
6311 case 866: /* DFP Insert Biased Exponent Quad */
6312 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6313 record_full_arch_list_add_reg (regcache
, tmp
);
6314 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6316 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6319 case 290: /* DFP Convert To Fixed Quad */
6320 record_full_arch_list_add_reg (regcache
,
6321 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6323 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6324 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6327 case 354: /* DFP Extract Biased Exponent Quad */
6328 record_full_arch_list_add_reg (regcache
,
6329 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6331 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6334 case 12: /* Floating Round to Single-Precision */
6335 case 14: /* Floating Convert To Integer Word */
6336 case 15: /* Floating Convert To Integer Word
6337 with round toward Zero */
6338 case 142: /* Floating Convert To Integer Word Unsigned */
6339 case 143: /* Floating Convert To Integer Word Unsigned
6340 with round toward Zero */
6341 case 392: /* Floating Round to Integer Nearest */
6342 case 424: /* Floating Round to Integer Toward Zero */
6343 case 456: /* Floating Round to Integer Plus */
6344 case 488: /* Floating Round to Integer Minus */
6345 case 814: /* Floating Convert To Integer Doubleword */
6346 case 815: /* Floating Convert To Integer Doubleword
6347 with round toward Zero */
6348 case 846: /* Floating Convert From Integer Doubleword */
6349 case 942: /* Floating Convert To Integer Doubleword Unsigned */
6350 case 943: /* Floating Convert To Integer Doubleword Unsigned
6351 with round toward Zero */
6352 case 974: /* Floating Convert From Integer Doubleword Unsigned */
6353 record_full_arch_list_add_reg (regcache
,
6354 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6356 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6357 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6361 switch (PPC_FIELD (insn
, 11, 5))
6363 case 1: /* Move From FPSCR & Clear Enables */
6364 case 20: /* Move From FPSCR Control & set DRN */
6365 case 21: /* Move From FPSCR Control & set DRN Immediate */
6366 case 22: /* Move From FPSCR Control & set RN */
6367 case 23: /* Move From FPSCR Control & set RN Immediate */
6368 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6370 case 0: /* Move From FPSCR */
6371 case 24: /* Move From FPSCR Lightweight */
6372 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
6373 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6374 record_full_arch_list_add_reg (regcache
,
6375 tdep
->ppc_fp0_regnum
6381 case 8: /* Floating Copy Sign */
6382 case 40: /* Floating Negate */
6383 case 72: /* Floating Move Register */
6384 case 136: /* Floating Negative Absolute Value */
6385 case 264: /* Floating Absolute Value */
6386 record_full_arch_list_add_reg (regcache
,
6387 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6389 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6392 case 838: /* Floating Merge Odd Word */
6393 case 966: /* Floating Merge Even Word */
6394 record_full_arch_list_add_reg (regcache
,
6395 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6398 case 38: /* Move To FPSCR Bit 1 */
6399 case 70: /* Move To FPSCR Bit 0 */
6400 case 134: /* Move To FPSCR Field Immediate */
6401 case 711: /* Move To FPSCR Fields */
6403 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6404 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6407 case 0: /* Floating Compare Unordered */
6408 case 32: /* Floating Compare Ordered */
6409 case 64: /* Move to Condition Register from FPSCR */
6410 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
6411 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
6412 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
6413 case 708: /* VSX Scalar Test Data Class Quad-Precision */
6414 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6416 case 128: /* Floating Test for software Divide */
6417 case 160: /* Floating Test for software Square Root */
6418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6421 case 4: /* VSX Scalar Add Quad-Precision */
6422 case 36: /* VSX Scalar Multiply Quad-Precision */
6423 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
6424 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
6425 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
6426 case 484: /* VSX Scalar Negative Multiply-Subtract
6428 case 516: /* VSX Scalar Subtract Quad-Precision */
6429 case 548: /* VSX Scalar Divide Quad-Precision */
6432 switch (PPC_FIELD (insn
, 11, 5))
6434 case 0: /* DFP Convert From Fixed Quadword Quad */
6435 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6437 record_full_arch_list_add_reg (regcache
,
6438 tdep
->ppc_fp0_regnum
6440 record_full_arch_list_add_reg (regcache
,
6441 tdep
->ppc_fp0_regnum
6442 + PPC_FRT (insn
) + 1);
6444 case 1: /* DFP Convert To Fixed Quadword Quad */
6445 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6446 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6451 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6453 case 68: /* VSX Scalar Compare Equal Quad-Precision */
6454 case 196: /* VSX Scalar Compare Greater Than or Equal
6456 case 228: /* VSX Scalar Compare Greater Than Quad-Precision */
6457 case 676: /* VSX Scalar Maximum Type-C Quad-Precision */
6458 case 740: /* VSX Scalar Minimum Type-C Quad-Precision */
6459 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6461 case 100: /* VSX Scalar Copy Sign Quad-Precision */
6462 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
6463 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6467 switch (PPC_FIELD (insn
, 11, 5))
6469 case 27: /* VSX Scalar Square Root Quad-Precision */
6470 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6472 case 0: /* VSX Scalar Absolute Quad-Precision */
6473 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
6474 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
6475 case 16: /* VSX Scalar Negate Quad-Precision */
6476 case 18: /* VSX Scalar Extract Significand Quad-Precision */
6477 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6483 switch (PPC_FIELD (insn
, 11, 5))
6485 case 0: /* VSX Scalar Convert with round to zero
6486 Quad-Precision to Unsigned Quadword */
6487 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
6488 to Unsigned Word format */
6489 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
6490 Quad-Precision format */
6491 case 3: /* VSX Scalar Convert with round
6492 Unsigned Quadword to Quad-Precision */
6493 case 8: /* VSX Scalar Convert with round to zero
6494 Quad-Precision to Signed Quadword */
6495 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
6496 to Signed Word format */
6497 case 10: /* VSX Scalar Convert Signed Doubleword format to
6498 Quad-Precision format */
6499 case 11: /* VSX Scalar Convert with round
6500 Signed Quadword to Quad-Precision */
6501 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
6502 to Unsigned Doubleword format */
6503 case 20: /* VSX Scalar round & Convert Quad-Precision format to
6504 Double-Precision format */
6505 case 22: /* VSX Scalar Convert Double-Precision format to
6506 Quad-Precision format */
6507 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
6508 to Signed Doubleword format */
6509 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6510 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6515 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6516 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6520 /* Record the prefixed instructions with primary opcode 32. The arguments are
6521 the first 32-bits of the instruction (insn_prefix), and the second 32-bits
6522 of the instruction (insn_suffix). Return 0 on success. */
6525 ppc_process_record_prefix_op42 (struct gdbarch
*gdbarch
,
6526 struct regcache
*regcache
,
6527 uint32_t insn_prefix
, uint32_t insn_suffix
)
6529 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6530 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6531 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6538 case 0: /* Prefixed Load VSX Scalar Doubleword, plxsd */
6539 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
6541 case 2: /* Prefixed Load Halfword Algebraic, plha */
6542 record_full_arch_list_add_reg (regcache
,
6543 tdep
->ppc_gp0_regnum
6544 + PPC_RT (insn_suffix
));
6552 /* Record the prefixed XX3-Form instructions with primary opcode 59. The
6553 arguments are the first 32-bits of the instruction (insn_prefix), and the
6554 second 32-bits of the instruction (insn_suffix). Return 0 on success. */
6557 ppc_process_record_prefix_op59_XX3 (struct gdbarch
*gdbarch
,
6558 struct regcache
*regcache
,
6559 uint32_t insn_prefix
, uint32_t insn_suffix
)
6561 int opcode
= PPC_FIELD (insn_suffix
, 21, 8);
6562 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6563 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6564 int at
= PPC_FIELD (insn_suffix
, 6, 3);
6565 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6567 /* Note, the mnemonics for the pmxvf16ger*, pmxvf32ger*,pmxvf64ger*,
6568 pmxvi4ger8*, pmxvi8ger4* pmxvi16ger2* instructions were officially
6569 changed to pmdmxbf16ger*, pmdmxvf32ger*, pmdmxvf64ger*, pmdmxvi4ger8*,
6570 pmdmxvi8ger4*, pmdmxvi16ger* respectively. The old mnemonics are still
6571 supported by the assembler as extended mnemonics. The disassembler
6572 generates the new mnemonics. */
6578 case 35: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6579 MMIRR, pmdmxvi4ger8 (pmxvi4ger8) */
6580 case 34: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6581 MMIRR, pmdmxvi4ger8pp (pmxvi4ger8pp) */
6583 case 99: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6584 Integer GER with Saturate Positive multiply,
6585 Positive accumulate, xvi8ger4spp */
6587 case 3: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6588 Integer GER MMIRR, pmdmxvi8ger4 (pmxvi8ger4) */
6589 case 2: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6590 Integer GER Positive multiply, Positive accumulate
6591 MMIRR, pmdmxvi8ger4pp (pmxvi8ger4pp) */
6593 case 75: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6594 GER MMIRR, pmdmxvi16ger2 (pmxvi16ger2) */
6595 case 107: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6596 GER Positive multiply, Positive accumulate,
6597 pmdmxvi16ger2pp (pmxvi16ger2pp) */
6599 case 43: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6600 GER with Saturation MMIRR, pmdmxvi16ger2s
6602 case 42: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6603 GER with Saturation Positive multiply, Positive
6604 accumulate MMIRR, pmdmxvi16ger2spp (pmxvi16ger2spp)
6606 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
6609 case 19: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6610 GER MMIRR, pmdmxvf16ger2 (pmxvf16ger2) */
6611 case 18: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6612 GER Positive multiply, Positive accumulate MMIRR,
6613 pmdmxvf16ger2pp (pmxvf16ger2pp) */
6614 case 146: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6615 GER Positive multiply, Negative accumulate MMIRR,
6616 pmdmxvf16ger2pn (pmxvf16ger2pn) */
6617 case 82: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6618 GER Negative multiply, Positive accumulate MMIRR,
6619 pmdmxvf16ger2np (pmxvf16ger2np) */
6620 case 210: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6621 GER Negative multiply, Negative accumulate MMIRR,
6622 pmdmxvf16ger2nn (pmxvf16ger2nn) */
6624 case 27: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6625 GER MMIRR, pmdmxvf32ger (pmxvf32ger) */
6626 case 26: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6627 GER Positive multiply, Positive accumulate MMIRR,
6628 pmdmxvf32gerpp (pmxvf32gerpp) */
6629 case 154: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6630 GER Positive multiply, Negative accumulate MMIRR,
6631 pmdmxvf32gerpn (pmxvf32gerpn) */
6632 case 90: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6633 GER Negative multiply, Positive accumulate MMIRR,
6634 pmdmxvf32gernp (pmxvf32gernp )*/
6635 case 218: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6636 GER Negative multiply, Negative accumulate MMIRR,
6637 pmdmxvf32gernn (pmxvf32gernn) */
6639 case 59: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6640 GER MMIRR, pmdmxvf64ger (pmxvf64ger) */
6641 case 58: /* Floating-Point GER Positive multiply, Positive
6642 accumulate MMIRR, pmdmxvf64gerpp (pmxvf64gerpp) */
6643 case 186: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6644 GER Positive multiply, Negative accumulate MMIRR,
6645 pmdmxvf64gerpn (pmxvf64gerpn) */
6646 case 122: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6647 GER Negative multiply, Positive accumulate MMIRR,
6648 pmdmxvf64gernp (pmxvf64gernp) */
6649 case 250: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6650 GER Negative multiply, Negative accumulate MMIRR,
6651 pmdmxvf64gernn (pmxvf64gernn) */
6653 case 51: /* Prefixed Masked VSX Vector bfloat16 GER MMIRR,
6654 pmdmxvbf16ger2 (pmxvbf16ger2) */
6655 case 50: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6656 multiply, Positive accumulate MMIRR,
6657 pmdmxvbf16ger2pp (pmxvbf16ger2pp) */
6658 case 178: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6659 multiply, Negative accumulate MMIRR,
6660 pmdmxvbf16ger2pn (pmxvbf16ger2pn) */
6661 case 114: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6662 multiply, Positive accumulate MMIRR,
6663 pmdmxvbf16ger2np (pmxvbf16ger2np) */
6664 case 242: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6665 multiply, Negative accumulate MMIRR,
6666 pmdmxvbf16ger2nn (pmxvbf16ger2nn) */
6667 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
6677 /* Record the prefixed store instructions. The arguments are the instruction
6678 address, the first 32-bits of the instruction(insn_prefix) and the following
6679 32-bits of the instruction (insn_suffix). Return 0 on success. */
6682 ppc_process_record_prefix_store (struct gdbarch
*gdbarch
,
6683 struct regcache
*regcache
,
6684 CORE_ADDR addr
, uint32_t insn_prefix
,
6685 uint32_t insn_suffix
)
6687 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6690 int R
= PPC_BIT (insn_prefix
, 11);
6691 int op6
= PPC_OP6 (insn_suffix
);
6695 if (PPC_RA (insn_suffix
) != 0)
6696 regcache_raw_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
6697 + PPC_RA (insn_suffix
), &iaddr
);
6701 iaddr
= addr
; /* PC relative */
6707 size
= 1; /* store byte, pstb */
6710 size
= 2; /* store halfword, psth */
6714 size
= 4; /* store word, pstw, pstfs */
6718 size
= 8; /* store double word, pstd, pstfd */
6721 size
= 16; /* store quadword, pstq */
6726 iaddr
+= P_PPC_D (insn_prefix
, insn_suffix
);
6727 record_full_arch_list_add_mem (iaddr
, size
);
6731 /* Record the prefixed instructions with primary op code 32. The arguments
6732 are the first 32-bits of the instruction (insn_prefix) and the following
6733 32-bits of the instruction (insn_suffix). Return 0 on success. */
6736 ppc_process_record_prefix_op32 (struct gdbarch
*gdbarch
,
6737 struct regcache
*regcache
,
6738 uint32_t insn_prefix
, uint32_t insn_suffix
)
6740 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6741 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6742 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6743 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6749 switch (PPC_FIELD (insn_suffix
, 11, 3))
6751 case 0: /* VSX Vector Splat Immediate Word 8RR, xxsplti32dx */
6752 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6756 switch (PPC_FIELD (insn_suffix
, 11, 4))
6758 case 2: /* VSX Vector Splat Immediate Double-Precision
6760 case 3: /* VSX Vector Splat Immediate Word 8RR, xxspltiw */
6761 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6773 if (ST1
== 0) /* Prefixed Load Word and Zero, plwz */
6774 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
6775 + PPC_RT (insn_suffix
));
6786 /* Record the prefixed instructions with primary op code 33. The arguments
6787 are the first 32-bits of the instruction(insn_prefix) and the following
6788 32-bits of the instruction (insn_suffix). Return 0 on success. */
6791 ppc_process_record_prefix_op33 (struct gdbarch
*gdbarch
,
6792 struct regcache
*regcache
,
6793 uint32_t insn_prefix
, uint32_t insn_suffix
)
6795 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6796 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6797 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6802 switch (PPC_FIELD (insn_suffix
, 26, 2))
6804 case 0: /* VSX Vector Blend Variable Byte 8RR, xxblendvb */
6805 case 1: /* VSX Vector Blend Variable Halfword, xxblendvh */
6806 case 2: /* VSX Vector Blend Variable Word, xxblendvw */
6807 case 3: /* VSX Vector Blend Variable Doubleword, xxblendvd */
6808 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn_suffix
));
6823 /* Record the prefixed instructions with primary op code 34. The arguments
6824 are the first 32-bits of the instruction(insn_prefix) and the following
6825 32-bits of the instruction (insn_suffix). Return 0 on success. */
6828 ppc_process_record_prefix_op34 (struct gdbarch
*gdbarch
,
6829 struct regcache
*regcache
,
6830 uint32_t insn_prefix
, uint32_t insn_suffix
)
6832 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6833 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6834 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6835 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6840 switch (PPC_FIELD (insn_suffix
, 26, 2))
6842 case 0: /* VSX Vector Permute Extended 8RR, xxpermx */
6843 case 1: /* VSX Vector Evaluate 8RR, xxeval */
6844 ppc_record_vsr (regcache
, tdep
, P_PPC_XT (insn_suffix
));
6855 if (ST1
== 0) /* Prefixed Load Word and Zero, plbz */
6856 record_full_arch_list_add_reg (regcache
,
6857 tdep
->ppc_gp0_regnum
6858 + PPC_RT (insn_suffix
));
6869 /* Record the prefixed VSX store, form DS, instructions. The arguments are the
6870 instruction address (addr), the first 32-bits of the instruction
6871 (insn_prefix) followed by the 32-bit instruction suffix (insn_suffix).
6872 Return 0 on success. */
6875 ppc_process_record_prefix_store_vsx_ds_form (struct gdbarch
*gdbarch
,
6876 struct regcache
*regcache
,
6878 uint32_t insn_prefix
,
6879 uint32_t insn_suffix
)
6881 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6884 int R
= PPC_BIT (insn_prefix
, 11);
6885 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6886 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6888 if ((type
== 0) && (ST1
== 0))
6892 if (PPC_RA (insn_suffix
) != 0)
6893 regcache_raw_read_unsigned (regcache
,
6894 tdep
->ppc_gp0_regnum
6895 + PPC_RA (insn_suffix
),
6900 ea
= addr
; /* PC relative */
6903 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6904 switch (PPC_FIELD (insn_suffix
, 0, 6))
6906 case 46: /* Prefixed Store VSX Scalar Doubleword, pstxsd */
6909 case 47: /* Prefixed,Store VSX Scalar Single-Precision, pstxssp */
6915 record_full_arch_list_add_mem (ea
, size
);
6922 /* Record the prefixed VSX, form D, instructions. The arguments are the
6923 instruction address for PC-relative addresss (addr), the first 32-bits of
6924 the instruction (insn_prefix) and the following 32-bits of the instruction
6925 (insn_suffix). Return 0 on success. */
6928 ppc_process_record_prefix_vsx_d_form (struct gdbarch
*gdbarch
,
6929 struct regcache
*regcache
,
6931 uint32_t insn_prefix
,
6932 uint32_t insn_suffix
)
6934 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6937 int R
= PPC_BIT (insn_prefix
, 11);
6938 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6939 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6941 if ((type
== 0) && (ST1
== 0))
6943 switch (PPC_FIELD (insn_suffix
, 0, 5))
6945 case 25: /* Prefixed Load VSX Vector, plxv */
6946 ppc_record_vsr (regcache
, tdep
, P_PPC_XT5 (insn_prefix
));
6948 case 27: /* Prefixed Store VSX Vector 8LS, pstxv */
6953 if (PPC_RA (insn_suffix
) != 0)
6954 regcache_raw_read_unsigned (regcache
,
6955 tdep
->ppc_gp0_regnum
6956 + PPC_RA (insn_suffix
),
6961 ea
= addr
; /* PC relative */
6964 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6965 record_full_arch_list_add_mem (ea
, size
);
6975 /* Parse the current instruction and record the values of the registers and
6976 memory that will be changed in current instruction to "record_arch_list".
6977 Return -1 if something wrong. */
6979 /* This handles the recording of the various prefix instructions. It takes
6980 the instruction address, the first 32-bits of the instruction (insn_prefix)
6981 and the following 32-bits of the instruction (insn_suffix). Return 0 on
6985 ppc_process_prefix_instruction (int insn_prefix
, int insn_suffix
,
6986 CORE_ADDR addr
, struct gdbarch
*gdbarch
,
6987 struct regcache
*regcache
)
6989 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6990 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6991 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6994 /* D-form has uses a 5-bit opcode in the instruction suffix */
6995 if (ppc_process_record_prefix_vsx_d_form ( gdbarch
, regcache
, addr
,
6996 insn_prefix
, insn_suffix
) == 0)
6999 op6
= PPC_OP6 (insn_suffix
); /* 6-bit opcode in the instruction suffix */
7003 case 14: /* Prefixed Add Immediate, paddi */
7004 if ((type
== 2) && (ST1
== 0))
7005 record_full_arch_list_add_reg (regcache
,
7006 tdep
->ppc_gp0_regnum
7007 + PPC_RT (insn_suffix
));
7009 goto UNKNOWN_PREFIX_OP
;
7013 if (ppc_process_record_prefix_op32 (gdbarch
, regcache
,
7014 insn_prefix
, insn_suffix
) != 0)
7015 goto UNKNOWN_PREFIX_OP
;
7019 if (ppc_process_record_prefix_op33 (gdbarch
, regcache
,
7020 insn_prefix
, insn_suffix
) != 0)
7021 goto UNKNOWN_PREFIX_OP
;
7024 case 34: /* Prefixed Load Byte and Zero, plbz */
7025 if (ppc_process_record_prefix_op34 (gdbarch
, regcache
,
7026 insn_prefix
, insn_suffix
) != 0)
7027 goto UNKNOWN_PREFIX_OP
;
7029 case 40: /* Prefixed Load Halfword and Zero, plhz */
7030 if ((type
== 2) && (ST1
== 0))
7031 record_full_arch_list_add_reg (regcache
,
7032 tdep
->ppc_gp0_regnum
7033 + PPC_RT (insn_suffix
));
7035 goto UNKNOWN_PREFIX_OP
;
7040 case 36: /* Prefixed Store Word, pstw */
7041 case 38: /* Prefixed Store Byte, pstb */
7042 case 44: /* Prefixed Store Halfword, psth */
7043 case 52: /* Prefixed Store Floating-Point Single, pstfs */
7044 case 54: /* Prefixed Store Floating-Point Double, pstfd */
7045 case 60: /* Prefixed Store Quadword, pstq */
7046 case 61: /* Prefixed Store Doubleword, pstd */
7047 if (ppc_process_record_prefix_store (gdbarch
, regcache
, addr
,
7048 insn_prefix
, insn_suffix
) != 0)
7049 goto UNKNOWN_PREFIX_OP
;
7053 if (ppc_process_record_prefix_op42 (gdbarch
, regcache
,
7054 insn_prefix
, insn_suffix
) != 0)
7055 goto UNKNOWN_PREFIX_OP
;
7058 case 43: /* Prefixed Load VSX Scalar Single-Precision, plxssp */
7059 if ((type
== 0) && (ST1
== 0))
7060 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
7062 goto UNKNOWN_PREFIX_OP
;
7067 if (ppc_process_record_prefix_store_vsx_ds_form (gdbarch
, regcache
, addr
,
7068 insn_prefix
, insn_suffix
) != 0)
7069 goto UNKNOWN_PREFIX_OP
;
7072 case 56: /* Prefixed Load Quadword, plq */
7074 if ((type
== 0) && (ST1
== 0))
7077 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn_suffix
) & ~1);
7078 record_full_arch_list_add_reg (regcache
, tmp
);
7079 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7082 goto UNKNOWN_PREFIX_OP
;
7086 case 41: /* Prefixed Load Word Algebraic, plwa */
7087 case 57: /* Prefixed Load Doubleword, pld */
7088 if ((type
== 0) && (ST1
== 0))
7089 record_full_arch_list_add_reg (regcache
,
7090 tdep
->ppc_gp0_regnum
7091 + PPC_RT (insn_suffix
));
7093 goto UNKNOWN_PREFIX_OP
;
7096 case 48: /* Prefixed Load Floating-Point Single, plfs */
7097 case 50: /* Prefixed Load Floating-Point Double, plfd */
7098 if ((type
== 2) && (ST1
== 0))
7099 record_full_arch_list_add_reg (regcache
,
7100 tdep
->ppc_fp0_regnum
7101 + PPC_FRT (insn_suffix
));
7103 goto UNKNOWN_PREFIX_OP
;
7106 case 58: /* Prefixed Load VSX Vector Paired, plxvp */
7107 if ((type
== 0) && (ST1
== 0))
7109 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
));
7110 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
) + 1);
7113 goto UNKNOWN_PREFIX_OP
;
7117 if (ppc_process_record_prefix_op59_XX3 (gdbarch
, regcache
, insn_prefix
,
7119 goto UNKNOWN_PREFIX_OP
;
7122 case 62: /* Prefixed Store VSX Vector Paired 8LS, pstxvp */
7123 if ((type
== 0) && (ST1
== 0))
7125 int R
= PPC_BIT (insn_prefix
, 11);
7130 if (PPC_RA (insn_suffix
) != 0)
7131 regcache_raw_read_unsigned (regcache
,
7132 tdep
->ppc_gp0_regnum
7133 + PPC_RA (insn_suffix
), &ea
);
7137 ea
= addr
; /* PC relative */
7140 ea
+= P_PPC_D (insn_prefix
, insn_suffix
) << 4;
7141 record_full_arch_list_add_mem (ea
, 32);
7144 goto UNKNOWN_PREFIX_OP
;
7149 gdb_printf (gdb_stdlog
,
7150 "Warning: Don't know how to record prefix instruction "
7151 "%08x %08x at %s, %d.\n",
7152 insn_prefix
, insn_suffix
, paddress (gdbarch
, addr
),
7158 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7161 if (record_full_arch_list_add_end ())
7167 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7170 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
7171 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7172 uint32_t insn
, insn_suffix
;
7175 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
7176 op6
= PPC_OP6 (insn
);
7180 case 1: /* prefixed instruction */
7182 /* Get the lower 32-bits of the prefixed instruction. */
7183 insn_suffix
= read_memory_unsigned_integer (addr
+4, 4, byte_order
);
7184 return ppc_process_prefix_instruction (insn
, insn_suffix
, addr
,
7187 case 2: /* Trap Doubleword Immediate */
7188 case 3: /* Trap Word Immediate */
7192 case 4: /* Vector Integer, Compare, Logical, Shift, etc. */
7193 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
7197 case 6: /* Vector Load and Store */
7198 if (ppc_process_record_op6 (gdbarch
, regcache
, addr
, insn
) != 0)
7202 case 17: /* System call */
7203 if (PPC_LEV (insn
) != 0)
7206 if (tdep
->ppc_syscall_record
!= NULL
)
7208 if (tdep
->ppc_syscall_record (regcache
) != 0)
7213 gdb_printf (gdb_stderr
, _("no syscall record support\n"));
7218 case 7: /* Multiply Low Immediate */
7219 record_full_arch_list_add_reg (regcache
,
7220 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7223 case 8: /* Subtract From Immediate Carrying */
7224 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7225 record_full_arch_list_add_reg (regcache
,
7226 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7229 case 10: /* Compare Logical Immediate */
7230 case 11: /* Compare Immediate */
7231 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7234 case 13: /* Add Immediate Carrying and Record */
7235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7237 case 12: /* Add Immediate Carrying */
7238 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7240 case 14: /* Add Immediate */
7241 case 15: /* Add Immediate Shifted */
7242 record_full_arch_list_add_reg (regcache
,
7243 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7246 case 16: /* Branch Conditional */
7247 if ((PPC_BO (insn
) & 0x4) == 0)
7248 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
7250 case 18: /* Branch */
7252 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
7256 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
7260 case 20: /* Rotate Left Word Immediate then Mask Insert */
7261 case 21: /* Rotate Left Word Immediate then AND with Mask */
7262 case 23: /* Rotate Left Word then AND with Mask */
7263 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
7264 /* Rotate Left Doubleword Immediate then Clear Right */
7265 /* Rotate Left Doubleword Immediate then Clear */
7266 /* Rotate Left Doubleword then Clear Left */
7267 /* Rotate Left Doubleword then Clear Right */
7268 /* Rotate Left Doubleword Immediate then Mask Insert */
7270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7271 record_full_arch_list_add_reg (regcache
,
7272 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7275 case 28: /* AND Immediate */
7276 case 29: /* AND Immediate Shifted */
7277 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7279 case 24: /* OR Immediate */
7280 case 25: /* OR Immediate Shifted */
7281 case 26: /* XOR Immediate */
7282 case 27: /* XOR Immediate Shifted */
7283 record_full_arch_list_add_reg (regcache
,
7284 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7288 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
7292 case 33: /* Load Word and Zero with Update */
7293 case 35: /* Load Byte and Zero with Update */
7294 case 41: /* Load Halfword and Zero with Update */
7295 case 43: /* Load Halfword Algebraic with Update */
7296 record_full_arch_list_add_reg (regcache
,
7297 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7299 case 32: /* Load Word and Zero */
7300 case 34: /* Load Byte and Zero */
7301 case 40: /* Load Halfword and Zero */
7302 case 42: /* Load Halfword Algebraic */
7303 record_full_arch_list_add_reg (regcache
,
7304 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7307 case 46: /* Load Multiple Word */
7308 for (i
= PPC_RT (insn
); i
< 32; i
++)
7309 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
7312 case 56: /* Load Quadword */
7313 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
7314 record_full_arch_list_add_reg (regcache
, tmp
);
7315 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7318 case 49: /* Load Floating-Point Single with Update */
7319 case 51: /* Load Floating-Point Double with Update */
7320 record_full_arch_list_add_reg (regcache
,
7321 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7323 case 48: /* Load Floating-Point Single */
7324 case 50: /* Load Floating-Point Double */
7325 record_full_arch_list_add_reg (regcache
,
7326 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
7329 case 47: /* Store Multiple Word */
7333 if (PPC_RA (insn
) != 0)
7334 regcache_raw_read_unsigned (regcache
,
7335 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7338 iaddr
+= PPC_D (insn
);
7339 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
7343 case 37: /* Store Word with Update */
7344 case 39: /* Store Byte with Update */
7345 case 45: /* Store Halfword with Update */
7346 case 53: /* Store Floating-Point Single with Update */
7347 case 55: /* Store Floating-Point Double with Update */
7348 record_full_arch_list_add_reg (regcache
,
7349 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7351 case 36: /* Store Word */
7352 case 38: /* Store Byte */
7353 case 44: /* Store Halfword */
7354 case 52: /* Store Floating-Point Single */
7355 case 54: /* Store Floating-Point Double */
7360 if (PPC_RA (insn
) != 0)
7361 regcache_raw_read_unsigned (regcache
,
7362 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7364 iaddr
+= PPC_D (insn
);
7366 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
7368 else if (op6
== 54 || op6
== 55)
7370 else if (op6
== 44 || op6
== 45)
7372 else if (op6
== 38 || op6
== 39)
7377 record_full_arch_list_add_mem (iaddr
, size
);
7384 case 0: /* Load Floating-Point Double Pair */
7385 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
7386 record_full_arch_list_add_reg (regcache
, tmp
);
7387 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7389 case 2: /* Load VSX Scalar Doubleword */
7390 case 3: /* Load VSX Scalar Single */
7391 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
7398 case 58: /* Load Doubleword */
7399 /* Load Doubleword with Update */
7400 /* Load Word Algebraic */
7401 if (PPC_FIELD (insn
, 30, 2) > 2)
7404 record_full_arch_list_add_reg (regcache
,
7405 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7406 if (PPC_BIT (insn
, 31))
7407 record_full_arch_list_add_reg (regcache
,
7408 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7412 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
7417 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
7422 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
7426 case 62: /* Store Doubleword */
7427 /* Store Doubleword with Update */
7428 /* Store Quadword with Update */
7432 int sub2
= PPC_FIELD (insn
, 30, 2);
7437 if (PPC_RA (insn
) != 0)
7438 regcache_raw_read_unsigned (regcache
,
7439 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7442 size
= (sub2
== 2) ? 16 : 8;
7444 iaddr
+= PPC_DS (insn
) << 2;
7445 record_full_arch_list_add_mem (iaddr
, size
);
7447 if (op6
== 62 && sub2
== 1)
7448 record_full_arch_list_add_reg (regcache
,
7449 tdep
->ppc_gp0_regnum
+
7456 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
7462 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
7463 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
7467 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7469 if (record_full_arch_list_add_end ())
7474 /* Used for matching tw, twi, td and tdi instructions for POWER. */
7476 static constexpr uint32_t TX_INSN_MASK
= 0xFC0007FF;
7477 static constexpr uint32_t TW_INSN
= 0x7C000008;
7478 static constexpr uint32_t TD_INSN
= 0x7C000088;
7480 static constexpr uint32_t TXI_INSN_MASK
= 0xFC000000;
7481 static constexpr uint32_t TWI_INSN
= 0x0C000000;
7482 static constexpr uint32_t TDI_INSN
= 0x08000000;
7485 is_tw_insn (uint32_t insn
)
7487 return (insn
& TX_INSN_MASK
) == TW_INSN
;
7491 is_twi_insn (uint32_t insn
)
7493 return (insn
& TXI_INSN_MASK
) == TWI_INSN
;
7497 is_td_insn (uint32_t insn
)
7499 return (insn
& TX_INSN_MASK
) == TD_INSN
;
7503 is_tdi_insn (uint32_t insn
)
7505 return (insn
& TXI_INSN_MASK
) == TDI_INSN
;
7508 /* Implementation of gdbarch_program_breakpoint_here_p for POWER. */
7511 rs6000_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
7513 gdb_byte target_mem
[PPC_INSN_SIZE
];
7515 /* Enable the automatic memory restoration from breakpoints while
7516 we read the memory. Otherwise we may find temporary breakpoints, ones
7517 inserted by GDB, and flag them as permanent breakpoints. */
7518 scoped_restore restore_memory
7519 = make_scoped_restore_show_memory_breakpoints (0);
7521 if (target_read_memory (address
, target_mem
, PPC_INSN_SIZE
) == 0)
7523 uint32_t insn
= (uint32_t) extract_unsigned_integer
7524 (target_mem
, PPC_INSN_SIZE
, gdbarch_byte_order_for_code (gdbarch
));
7526 /* Check if INSN is a TW, TWI, TD or TDI instruction. There
7527 are multiple choices of such instructions with different registers
7528 and / or immediate values but they all cause a break. */
7529 if (is_tw_insn (insn
) || is_twi_insn (insn
) || is_td_insn (insn
)
7530 || is_tdi_insn (insn
))
7537 /* Implement the update_call_site_pc arch hook. */
7540 ppc64_update_call_site_pc (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
7542 /* Some versions of GCC emit:
7548 but emit DWARF where the DW_AT_call_return_pc points to
7549 instruction after the 'nop'. Note that while the compiler emits
7550 a 'nop', the linker might put some other instruction there -- so
7551 we just unconditionally check the next instruction. */
7555 /* Initialize the current architecture based on INFO. If possible, re-use an
7556 architecture from ARCHES, which is a list of architectures already created
7557 during this debugging session.
7559 Called e.g. at program startup, when reading a core file, and when reading
7562 static struct gdbarch
*
7563 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7565 int wordsize
, from_xcoff_exec
, from_elf_exec
;
7566 enum bfd_architecture arch
;
7569 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
7571 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
7572 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
7573 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
7574 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
7575 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
7576 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
7577 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
7578 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
7579 int have_htm_tar
= 0;
7580 int tdesc_wordsize
= -1;
7581 const struct target_desc
*tdesc
= info
.target_desc
;
7582 tdesc_arch_data_up tdesc_data
;
7583 int num_pseudoregs
= 0;
7586 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7587 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
7589 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7590 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
7592 /* Check word size. If INFO is from a binary file, infer it from
7593 that, else choose a likely default. */
7594 if (from_xcoff_exec
)
7596 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
7601 else if (from_elf_exec
)
7603 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
7608 else if (tdesc_has_registers (tdesc
))
7612 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
7613 wordsize
= (info
.bfd_arch_info
->bits_per_word
7614 / info
.bfd_arch_info
->bits_per_byte
);
7619 /* Get the architecture and machine from the BFD. */
7620 arch
= info
.bfd_arch_info
->arch
;
7621 mach
= info
.bfd_arch_info
->mach
;
7623 /* For e500 executables, the apuinfo section is of help here. Such
7624 section contains the identifier and revision number of each
7625 Application-specific Processing Unit that is present on the
7626 chip. The content of the section is determined by the assembler
7627 which looks at each instruction and determines which unit (and
7628 which version of it) can execute it. Grovel through the section
7629 looking for relevant e500 APUs. */
7631 if (bfd_uses_spe_extensions (info
.abfd
))
7633 arch
= info
.bfd_arch_info
->arch
;
7634 mach
= bfd_mach_ppc_e500
;
7635 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
7636 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
7639 /* Find a default target description which describes our register
7640 layout, if we do not already have one. */
7641 if (! tdesc_has_registers (tdesc
))
7643 const struct ppc_variant
*v
;
7645 /* Choose variant. */
7646 v
= find_variant_by_arch (arch
, mach
);
7653 gdb_assert (tdesc_has_registers (tdesc
));
7655 /* Check any target description for validity. */
7656 if (tdesc_has_registers (tdesc
))
7658 static const char *const gprs
[] = {
7659 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7660 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7661 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7662 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7664 const struct tdesc_feature
*feature
;
7666 static const char *const msr_names
[] = { "msr", "ps" };
7667 static const char *const cr_names
[] = { "cr", "cnd" };
7668 static const char *const ctr_names
[] = { "ctr", "cnt" };
7670 feature
= tdesc_find_feature (tdesc
,
7671 "org.gnu.gdb.power.core");
7672 if (feature
== NULL
)
7675 tdesc_data
= tdesc_data_alloc ();
7678 for (i
= 0; i
< ppc_num_gprs
; i
++)
7679 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7681 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7682 PPC_PC_REGNUM
, "pc");
7683 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7684 PPC_LR_REGNUM
, "lr");
7685 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7686 PPC_XER_REGNUM
, "xer");
7688 /* Allow alternate names for these registers, to accommodate GDB's
7690 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7691 PPC_MSR_REGNUM
, msr_names
);
7692 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7693 PPC_CR_REGNUM
, cr_names
);
7694 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7695 PPC_CTR_REGNUM
, ctr_names
);
7700 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7701 PPC_MQ_REGNUM
, "mq");
7703 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
7705 wordsize
= tdesc_wordsize
;
7707 feature
= tdesc_find_feature (tdesc
,
7708 "org.gnu.gdb.power.fpu");
7709 if (feature
!= NULL
)
7711 static const char *const fprs
[] = {
7712 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7713 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7714 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7715 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
7718 for (i
= 0; i
< ppc_num_fprs
; i
++)
7719 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7720 PPC_F0_REGNUM
+ i
, fprs
[i
]);
7721 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7722 PPC_FPSCR_REGNUM
, "fpscr");
7728 /* The fpscr register was expanded in isa 2.05 to 64 bits
7729 along with the addition of the decimal floating point
7731 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
7737 feature
= tdesc_find_feature (tdesc
,
7738 "org.gnu.gdb.power.altivec");
7739 if (feature
!= NULL
)
7741 static const char *const vector_regs
[] = {
7742 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
7743 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
7744 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
7745 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
7749 for (i
= 0; i
< ppc_num_gprs
; i
++)
7750 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7753 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7754 PPC_VSCR_REGNUM
, "vscr");
7755 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7756 PPC_VRSAVE_REGNUM
, "vrsave");
7758 if (have_spe
|| !valid_p
)
7765 /* Check for POWER7 VSX registers support. */
7766 feature
= tdesc_find_feature (tdesc
,
7767 "org.gnu.gdb.power.vsx");
7769 if (feature
!= NULL
)
7771 static const char *const vsx_regs
[] = {
7772 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
7773 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
7774 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
7775 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
7776 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
7782 for (i
= 0; i
< ppc_num_vshrs
; i
++)
7783 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7784 PPC_VSR0_UPPER_REGNUM
+ i
,
7787 if (!valid_p
|| !have_fpu
|| !have_altivec
)
7795 /* On machines supporting the SPE APU, the general-purpose registers
7796 are 64 bits long. There are SIMD vector instructions to treat them
7797 as pairs of floats, but the rest of the instruction set treats them
7798 as 32-bit registers, and only operates on their lower halves.
7800 In the GDB regcache, we treat their high and low halves as separate
7801 registers. The low halves we present as the general-purpose
7802 registers, and then we have pseudo-registers that stitch together
7803 the upper and lower halves and present them as pseudo-registers.
7805 Thus, the target description is expected to supply the upper
7806 halves separately. */
7808 feature
= tdesc_find_feature (tdesc
,
7809 "org.gnu.gdb.power.spe");
7810 if (feature
!= NULL
)
7812 static const char *const upper_spe
[] = {
7813 "ev0h", "ev1h", "ev2h", "ev3h",
7814 "ev4h", "ev5h", "ev6h", "ev7h",
7815 "ev8h", "ev9h", "ev10h", "ev11h",
7816 "ev12h", "ev13h", "ev14h", "ev15h",
7817 "ev16h", "ev17h", "ev18h", "ev19h",
7818 "ev20h", "ev21h", "ev22h", "ev23h",
7819 "ev24h", "ev25h", "ev26h", "ev27h",
7820 "ev28h", "ev29h", "ev30h", "ev31h"
7824 for (i
= 0; i
< ppc_num_gprs
; i
++)
7825 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7826 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
7828 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7829 PPC_SPE_ACC_REGNUM
, "acc");
7830 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7831 PPC_SPE_FSCR_REGNUM
, "spefscr");
7833 if (have_mq
|| have_fpu
|| !valid_p
)
7840 /* Program Priority Register. */
7841 feature
= tdesc_find_feature (tdesc
,
7842 "org.gnu.gdb.power.ppr");
7843 if (feature
!= NULL
)
7846 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7847 PPC_PPR_REGNUM
, "ppr");
7856 /* Data Stream Control Register. */
7857 feature
= tdesc_find_feature (tdesc
,
7858 "org.gnu.gdb.power.dscr");
7859 if (feature
!= NULL
)
7862 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7863 PPC_DSCR_REGNUM
, "dscr");
7872 /* Target Address Register. */
7873 feature
= tdesc_find_feature (tdesc
,
7874 "org.gnu.gdb.power.tar");
7875 if (feature
!= NULL
)
7878 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7879 PPC_TAR_REGNUM
, "tar");
7888 /* Event-based Branching Registers. */
7889 feature
= tdesc_find_feature (tdesc
,
7890 "org.gnu.gdb.power.ebb");
7891 if (feature
!= NULL
)
7893 static const char *const ebb_regs
[] = {
7894 "bescr", "ebbhr", "ebbrr"
7898 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
7899 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7900 PPC_BESCR_REGNUM
+ i
,
7909 /* Subset of the ISA 2.07 Performance Monitor Registers provided
7911 feature
= tdesc_find_feature (tdesc
,
7912 "org.gnu.gdb.power.linux.pmu");
7913 if (feature
!= NULL
)
7917 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7920 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7923 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7926 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7929 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7940 /* Hardware Transactional Memory Registers. */
7941 feature
= tdesc_find_feature (tdesc
,
7942 "org.gnu.gdb.power.htm.spr");
7943 if (feature
!= NULL
)
7945 static const char *const tm_spr_regs
[] = {
7946 "tfhar", "texasr", "tfiar"
7950 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
7951 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7952 PPC_TFHAR_REGNUM
+ i
,
7962 feature
= tdesc_find_feature (tdesc
,
7963 "org.gnu.gdb.power.htm.core");
7964 if (feature
!= NULL
)
7966 static const char *const cgprs
[] = {
7967 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
7968 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
7969 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
7970 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
7971 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
7976 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
7977 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7988 feature
= tdesc_find_feature (tdesc
,
7989 "org.gnu.gdb.power.htm.fpu");
7990 if (feature
!= NULL
)
7994 static const char *const cfprs
[] = {
7995 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
7996 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
7997 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
7998 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
7999 "cf30", "cf31", "cfpscr"
8002 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
8003 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8014 feature
= tdesc_find_feature (tdesc
,
8015 "org.gnu.gdb.power.htm.altivec");
8016 if (feature
!= NULL
)
8020 static const char *const cvmx
[] = {
8021 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
8022 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
8023 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
8024 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
8025 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
8029 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
8030 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8031 PPC_CVR0_REGNUM
+ i
,
8036 have_htm_altivec
= 1;
8039 have_htm_altivec
= 0;
8041 feature
= tdesc_find_feature (tdesc
,
8042 "org.gnu.gdb.power.htm.vsx");
8043 if (feature
!= NULL
)
8047 static const char *const cvsx
[] = {
8048 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
8049 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
8050 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
8051 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
8052 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
8056 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
8057 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8058 (PPC_CVSR0_UPPER_REGNUM
8062 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
8069 feature
= tdesc_find_feature (tdesc
,
8070 "org.gnu.gdb.power.htm.ppr");
8071 if (feature
!= NULL
)
8073 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
8074 PPC_CPPR_REGNUM
, "cppr");
8083 feature
= tdesc_find_feature (tdesc
,
8084 "org.gnu.gdb.power.htm.dscr");
8085 if (feature
!= NULL
)
8087 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
8088 PPC_CDSCR_REGNUM
, "cdscr");
8097 feature
= tdesc_find_feature (tdesc
,
8098 "org.gnu.gdb.power.htm.tar");
8099 if (feature
!= NULL
)
8101 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
8102 PPC_CTAR_REGNUM
, "ctar");
8112 /* If we have a 64-bit binary on a 32-bit target, complain. Also
8113 complain for a 32-bit binary on a 64-bit target; we do not yet
8114 support that. For instance, the 32-bit ABI routines expect
8117 As long as there isn't an explicit target description, we'll
8118 choose one based on the BFD architecture and get a word size
8119 matching the binary (probably powerpc:common or
8120 powerpc:common64). So there is only trouble if a 64-bit target
8121 supplies a 64-bit description while debugging a 32-bit
8123 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
8129 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
8132 elf_abi
= POWERPC_ELF_V1
;
8135 elf_abi
= POWERPC_ELF_V2
;
8142 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
8144 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8145 Tag_GNU_Power_ABI_FP
) & 3)
8148 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
8151 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
8158 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
8160 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8161 Tag_GNU_Power_ABI_FP
) >> 2)
8164 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
8167 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
8174 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
8176 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8177 Tag_GNU_Power_ABI_Vector
))
8180 vector_abi
= POWERPC_VEC_GENERIC
;
8183 vector_abi
= POWERPC_VEC_ALTIVEC
;
8186 vector_abi
= POWERPC_VEC_SPE
;
8194 /* At this point, the only supported ELF-based 64-bit little-endian
8195 operating system is GNU/Linux, and this uses the ELFv2 ABI by
8196 default. All other supported ELF-based operating systems use the
8197 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
8198 e.g. because we run a legacy binary, or have attached to a process
8199 and have not found any associated binary file, set the default
8200 according to this heuristic. */
8201 if (elf_abi
== POWERPC_ELF_AUTO
)
8203 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
8204 elf_abi
= POWERPC_ELF_V2
;
8206 elf_abi
= POWERPC_ELF_V1
;
8209 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
8211 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
8214 soft_float
= !have_fpu
;
8216 /* If we have a hard float binary or setting but no floating point
8217 registers, downgrade to soft float anyway. We're still somewhat
8218 useful in this scenario. */
8219 if (!soft_float
&& !have_fpu
)
8222 /* Similarly for vector registers. */
8223 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
8224 vector_abi
= POWERPC_VEC_GENERIC
;
8226 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
8227 vector_abi
= POWERPC_VEC_GENERIC
;
8229 if (vector_abi
== POWERPC_VEC_AUTO
)
8232 vector_abi
= POWERPC_VEC_ALTIVEC
;
8234 vector_abi
= POWERPC_VEC_SPE
;
8236 vector_abi
= POWERPC_VEC_GENERIC
;
8239 /* Do not limit the vector ABI based on available hardware, since we
8240 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
8242 /* Find a candidate among extant architectures. */
8243 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8245 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8247 /* Word size in the various PowerPC bfd_arch_info structs isn't
8248 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
8249 separate word size check. */
8250 ppc_gdbarch_tdep
*tdep
8251 = gdbarch_tdep
<ppc_gdbarch_tdep
> (arches
->gdbarch
);
8252 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
8254 if (tdep
&& tdep
->soft_float
!= soft_float
)
8256 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
8258 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
8260 if (tdep
&& tdep
->wordsize
== wordsize
)
8261 return arches
->gdbarch
;
8264 /* None found, create a new architecture from INFO, whose bfd_arch_info
8265 validity depends on the source:
8266 - executable useless
8267 - rs6000_host_arch() good
8269 - "set arch" trust blindly
8270 - GDB startup useless but harmless */
8273 = gdbarch_alloc (&info
, gdbarch_tdep_up (new ppc_gdbarch_tdep
));
8274 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
8276 tdep
->wordsize
= wordsize
;
8277 tdep
->elf_abi
= elf_abi
;
8278 tdep
->soft_float
= soft_float
;
8279 tdep
->long_double_abi
= long_double_abi
;
8280 tdep
->vector_abi
= vector_abi
;
8282 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
8283 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
8284 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
8285 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
8286 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
8287 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
8288 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
8289 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
8291 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
8292 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
8293 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
8294 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
8295 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
8296 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
8297 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
8298 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
8299 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
8300 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
8301 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
8302 tdep
->have_ebb
= have_ebb
;
8304 /* If additional pmu registers are added, care must be taken when
8305 setting new fields in the tdep below, to maintain compatibility
8306 with features that only provide some of the registers. Currently
8307 gdb access to the pmu registers is only supported in linux, and
8308 linux only provides a subset of the pmu registers defined in the
8311 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
8312 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
8313 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
8314 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
8315 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
8317 tdep
->have_htm_spr
= have_htm_spr
;
8318 tdep
->have_htm_core
= have_htm_core
;
8319 tdep
->have_htm_fpu
= have_htm_fpu
;
8320 tdep
->have_htm_altivec
= have_htm_altivec
;
8321 tdep
->have_htm_vsx
= have_htm_vsx
;
8322 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
8323 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
8324 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
8326 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
8327 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
8328 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
8329 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
8331 /* The XML specification for PowerPC sensibly calls the MSR "msr".
8332 GDB traditionally called it "ps", though, so let GDB add an
8334 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
8338 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
8339 set_gdbarch_update_call_site_pc (gdbarch
, ppc64_update_call_site_pc
);
8342 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
8343 set_gdbarch_get_return_buf_addr (gdbarch
, ppc_sysv_get_return_buf_addr
);
8345 /* Set lr_frame_offset. */
8347 tdep
->lr_frame_offset
= 16;
8349 tdep
->lr_frame_offset
= 4;
8351 if (have_spe
|| have_dfp
|| have_altivec
8352 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
8354 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
8355 set_gdbarch_pseudo_register_write (gdbarch
,
8356 rs6000_pseudo_register_write
);
8357 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8358 rs6000_ax_pseudo_register_collect
);
8361 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
8363 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8365 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
8368 num_pseudoregs
+= 32;
8370 num_pseudoregs
+= 16;
8372 num_pseudoregs
+= 32;
8374 /* Include both VSX and Extended FP registers. */
8375 num_pseudoregs
+= 96;
8377 num_pseudoregs
+= 16;
8378 /* Include both checkpointed VSX and EFP registers. */
8380 num_pseudoregs
+= 64 + 32;
8382 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
8384 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8385 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
8386 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8387 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8388 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8389 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8390 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8391 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
8392 set_gdbarch_char_signed (gdbarch
, 0);
8394 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
8397 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
8399 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
8400 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
8401 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
8402 set_gdbarch_value_from_register (gdbarch
, rs6000_value_from_register
);
8404 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
8405 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
8408 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
8409 else if (wordsize
== 8)
8410 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
8412 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
8413 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
8414 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
8416 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8418 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
8419 rs6000_breakpoint::kind_from_pc
);
8420 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
8421 rs6000_breakpoint::bp_from_kind
);
8422 set_gdbarch_program_breakpoint_here_p (gdbarch
,
8423 rs6000_program_breakpoint_here_p
);
8425 /* The value of symbols of type N_SO and N_FUN maybe null when
8427 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
8429 /* Handles single stepping of atomic sequences. */
8430 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
8432 /* Not sure on this. FIXMEmgo */
8433 set_gdbarch_frame_args_skip (gdbarch
, 8);
8435 /* Helpers for function argument information. */
8436 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
8439 set_gdbarch_in_solib_return_trampoline
8440 (gdbarch
, rs6000_in_solib_return_trampoline
);
8441 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
8443 /* Hook in the DWARF CFI frame unwinder. */
8444 dwarf2_append_unwinders (gdbarch
);
8445 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
8447 /* Frame handling. */
8448 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
8450 /* Setup displaced stepping. */
8451 set_gdbarch_displaced_step_copy_insn (gdbarch
,
8452 ppc_displaced_step_copy_insn
);
8453 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
8454 ppc_displaced_step_hw_singlestep
);
8455 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
8456 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
8457 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
8458 set_gdbarch_displaced_step_restore_all_in_ptid
8459 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
8460 set_gdbarch_displaced_step_buffer_length (gdbarch
, 2 * PPC_INSN_SIZE
);
8462 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
8464 /* Hook in ABI-specific overrides, if they have been registered. */
8465 info
.target_desc
= tdesc
;
8466 info
.tdesc_data
= tdesc_data
.get ();
8467 gdbarch_init_osabi (info
, gdbarch
);
8471 case GDB_OSABI_LINUX
:
8472 case GDB_OSABI_NETBSD
:
8473 case GDB_OSABI_UNKNOWN
:
8474 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8475 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8476 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8479 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
8481 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8482 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8483 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8486 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
8487 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
8488 rs6000_pseudo_register_reggroup_p
);
8489 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8491 /* Override the normal target description method to make the SPE upper
8492 halves anonymous. */
8493 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
8495 /* Choose register numbers for all supported pseudo-registers. */
8496 tdep
->ppc_ev0_regnum
= -1;
8497 tdep
->ppc_dl0_regnum
= -1;
8498 tdep
->ppc_v0_alias_regnum
= -1;
8499 tdep
->ppc_vsr0_regnum
= -1;
8500 tdep
->ppc_efpr0_regnum
= -1;
8501 tdep
->ppc_cdl0_regnum
= -1;
8502 tdep
->ppc_cvsr0_regnum
= -1;
8503 tdep
->ppc_cefpr0_regnum
= -1;
8505 cur_reg
= gdbarch_num_regs (gdbarch
);
8509 tdep
->ppc_ev0_regnum
= cur_reg
;
8514 tdep
->ppc_dl0_regnum
= cur_reg
;
8519 tdep
->ppc_v0_alias_regnum
= cur_reg
;
8524 tdep
->ppc_vsr0_regnum
= cur_reg
;
8526 tdep
->ppc_efpr0_regnum
= cur_reg
;
8531 tdep
->ppc_cdl0_regnum
= cur_reg
;
8536 tdep
->ppc_cvsr0_regnum
= cur_reg
;
8538 tdep
->ppc_cefpr0_regnum
= cur_reg
;
8542 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
8544 /* Register the ravenscar_arch_ops. */
8545 if (mach
== bfd_mach_ppc_e500
)
8546 register_e500_ravenscar_ops (gdbarch
);
8548 register_ppc_ravenscar_ops (gdbarch
);
8550 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
8551 set_gdbarch_valid_disassembler_options (gdbarch
,
8552 disassembler_options_powerpc ());
8558 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8560 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
8565 /* FIXME: Dump gdbarch_tdep. */
8569 powerpc_set_soft_float (const char *args
, int from_tty
,
8570 struct cmd_list_element
*c
)
8572 struct gdbarch_info info
;
8574 /* Update the architecture. */
8575 if (!gdbarch_update_p (info
))
8576 internal_error (_("could not update architecture"));
8580 powerpc_set_vector_abi (const char *args
, int from_tty
,
8581 struct cmd_list_element
*c
)
8585 for (vector_abi
= POWERPC_VEC_AUTO
;
8586 vector_abi
!= POWERPC_VEC_LAST
;
8588 if (strcmp (powerpc_vector_abi_string
,
8589 powerpc_vector_strings
[vector_abi
]) == 0)
8591 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
8595 if (vector_abi
== POWERPC_VEC_LAST
)
8596 internal_error (_("Invalid vector ABI accepted: %s."),
8597 powerpc_vector_abi_string
);
8599 /* Update the architecture. */
8601 if (!gdbarch_update_p (info
))
8602 internal_error (_("could not update architecture"));
8605 /* Show the current setting of the exact watchpoints flag. */
8608 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
8609 struct cmd_list_element
*c
,
8612 gdb_printf (file
, _("Use of exact watchpoints is %s.\n"), value
);
8615 /* Read a PPC instruction from memory. */
8618 read_insn (frame_info_ptr frame
, CORE_ADDR pc
)
8620 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8621 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8623 return read_memory_unsigned_integer (pc
, 4, byte_order
);
8626 /* Return non-zero if the instructions at PC match the series
8627 described in PATTERN, or zero otherwise. PATTERN is an array of
8628 'struct ppc_insn_pattern' objects, terminated by an entry whose
8631 When the match is successful, fill INSNS[i] with what PATTERN[i]
8632 matched. If PATTERN[i] is optional, and the instruction wasn't
8633 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
8634 INSNS should have as many elements as PATTERN, minus the terminator.
8635 Note that, if PATTERN contains optional instructions which aren't
8636 present in memory, then INSNS will have holes, so INSNS[i] isn't
8637 necessarily the i'th instruction in memory. */
8640 ppc_insns_match_pattern (frame_info_ptr frame
, CORE_ADDR pc
,
8641 const struct ppc_insn_pattern
*pattern
,
8642 unsigned int *insns
)
8647 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
8650 insn
= read_insn (frame
, pc
);
8652 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
8658 else if (!pattern
[i
].optional
)
8665 /* Return the 'd' field of the d-form instruction INSN, properly
8669 ppc_insn_d_field (unsigned int insn
)
8671 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
8674 /* Return the 'ds' field of the ds-form instruction INSN, with the two
8675 zero bits concatenated at the right, and properly
8679 ppc_insn_ds_field (unsigned int insn
)
8681 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
8685 ppc_insn_prefix_dform (unsigned int insn1
, unsigned int insn2
)
8687 /* result is 34-bits */
8688 return (CORE_ADDR
) ((((insn1
& 0x3ffff) ^ 0x20000) - 0x20000) << 16)
8689 | (CORE_ADDR
)(insn2
& 0xffff);
8692 /* Initialization code. */
8694 void _initialize_rs6000_tdep ();
8696 _initialize_rs6000_tdep ()
8698 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8699 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8701 /* Initialize the standard target descriptions. */
8702 initialize_tdesc_powerpc_32 ();
8703 initialize_tdesc_powerpc_altivec32 ();
8704 initialize_tdesc_powerpc_vsx32 ();
8705 initialize_tdesc_powerpc_403 ();
8706 initialize_tdesc_powerpc_403gc ();
8707 initialize_tdesc_powerpc_405 ();
8708 initialize_tdesc_powerpc_505 ();
8709 initialize_tdesc_powerpc_601 ();
8710 initialize_tdesc_powerpc_602 ();
8711 initialize_tdesc_powerpc_603 ();
8712 initialize_tdesc_powerpc_604 ();
8713 initialize_tdesc_powerpc_64 ();
8714 initialize_tdesc_powerpc_altivec64 ();
8715 initialize_tdesc_powerpc_vsx64 ();
8716 initialize_tdesc_powerpc_7400 ();
8717 initialize_tdesc_powerpc_750 ();
8718 initialize_tdesc_powerpc_860 ();
8719 initialize_tdesc_powerpc_e500 ();
8720 initialize_tdesc_rs6000 ();
8722 /* Add root prefix command for all "set powerpc"/"show powerpc"
8724 add_setshow_prefix_cmd ("powerpc", no_class
,
8725 _("Various PowerPC-specific commands."),
8726 _("Various PowerPC-specific commands."),
8727 &setpowerpccmdlist
, &showpowerpccmdlist
,
8728 &setlist
, &showlist
);
8730 /* Add a command to allow the user to force the ABI. */
8731 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
8732 &powerpc_soft_float_global
,
8733 _("Set whether to use a soft-float ABI."),
8734 _("Show whether to use a soft-float ABI."),
8736 powerpc_set_soft_float
, NULL
,
8737 &setpowerpccmdlist
, &showpowerpccmdlist
);
8739 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
8740 &powerpc_vector_abi_string
,
8741 _("Set the vector ABI."),
8742 _("Show the vector ABI."),
8743 NULL
, powerpc_set_vector_abi
, NULL
,
8744 &setpowerpccmdlist
, &showpowerpccmdlist
);
8746 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
8747 &target_exact_watchpoints
,
8749 Set whether to use just one debug register for watchpoints on scalars."),
8751 Show whether to use just one debug register for watchpoints on scalars."),
8753 If true, GDB will use only one debug register when watching a variable of\n\
8754 scalar type, thus assuming that the variable is accessed through the address\n\
8755 of its first byte."),
8756 NULL
, show_powerpc_exact_watchpoints
,
8757 &setpowerpccmdlist
, &showpowerpccmdlist
);