gpr_hazard.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity gpr_hazard is
   9     generic (
  10         PIPELINE_DEPTH : natural := 1
  11         );
  12     port(
  13         clk                : in std_ulogic;
  14         busy_in            : in std_ulogic;
  15         deferred           : in std_ulogic;
  16         complete_in        : in std_ulogic;
  17         flush_in           : in std_ulogic;
  18         issuing            : in std_ulogic;
  19         repeated           : in std_ulogic;
  20
  21         gpr_write_valid_in : in std_ulogic;
  22         gpr_write_in       : in gspr_index_t;
  23         bypass_avail       : in std_ulogic;
  24         gpr_read_valid_in  : in std_ulogic;
  25         gpr_read_in        : in gspr_index_t;
  26
  27         ugpr_write_valid   : in std_ulogic;
  28         ugpr_write_reg     : in gspr_index_t;
  29
  30         stall_out          : out std_ulogic;
  31         use_bypass         : out std_ulogic
  32         );
  33 end entity gpr_hazard;
  34 architecture behaviour of gpr_hazard is
  35     type pipeline_entry_type is record
  36         valid  : std_ulogic;
  37         bypass : std_ulogic;
  38         gpr    : gspr_index_t;
  39         ugpr_valid : std_ulogic;
  40         ugpr   : gspr_index_t;
  41     end record;
  42     constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0', gpr => (others => '0'),
  43                                                            ugpr_valid => '0', ugpr => (others => '0'));
  44
  45     type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
  46     constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
  47
  48     signal r, rin : pipeline_t := pipeline_t_init;
  49 begin
  50     gpr_hazard0: process(clk)
  51     begin
  52         if rising_edge(clk) then
  53             r <= rin;
  54         end if;
  55     end process;
  56
  57     gpr_hazard1: process(all)
  58         variable v     : pipeline_t;
  59     begin
  60         v := r;
  61
  62         if complete_in = '1' then
  63             v(PIPELINE_DEPTH).valid := '0';
  64             v(PIPELINE_DEPTH).ugpr_valid := '0';
  65         end if;
  66
  67         stall_out <= '0';
  68         use_bypass <= '0';
  69         if repeated = '0' and gpr_read_valid_in = '1' then
  70             loop_0: for i in 0 to PIPELINE_DEPTH loop
  71                 -- The second half of a split instruction never has GPR
  72                 -- dependencies on the first half's output GPR,
  73                 -- so ignore matches when i = 0 for the second half.
  74                 if v(i).valid = '1' and r(i).gpr = gpr_read_in and
  75                     not (i = 0 and repeated = '1') then
  76                     if r(i).bypass = '1' then
  77                         use_bypass <= '1';
  78                     else
  79                         stall_out <= '1';
  80                     end if;
  81                 end if;
  82                 if v(i).ugpr_valid = '1' and r(i).ugpr = gpr_read_in then
  83                     stall_out <= '1';
  84                 end if;
  85             end loop;
  86         end if;
  87
  88         -- XXX assumes PIPELINE_DEPTH = 1
  89         if busy_in = '0' then
  90             v(1) := v(0);
  91             v(0).valid := '0';
  92             v(0).ugpr_valid := '0';
  93         end if;
  94         if deferred = '0' and issuing = '1' then
  95             v(0).valid  := gpr_write_valid_in;
  96             v(0).bypass := bypass_avail;
  97             v(0).gpr    := gpr_write_in;
  98             v(0).ugpr_valid := ugpr_write_valid;
  99             v(0).ugpr   := ugpr_write_reg;
 100         end if;
 101         if flush_in = '1' then
 102             v(0).valid := '0';
 103             v(0).ugpr_valid := '0';
 104             v(1).valid := '0';
 105             v(1).ugpr_valid := '0';
 106         end if;
 107
 108         -- update registers
 109         rin <= v;
 110
 111     end process;
 112 end;