gpr_hazard.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity gpr_hazard is
   9     generic (
  10         PIPELINE_DEPTH : natural := 1
  11         );
  12     port(
  13         clk                : in std_ulogic;
  14         busy_in            : in std_ulogic;
  15         deferred           : in std_ulogic;
  16         complete_in        : in std_ulogic;
  17         flush_in           : in std_ulogic;
  18         issuing            : in std_ulogic;
  19
  20         gpr_write_valid_in : in std_ulogic;
  21         gpr_write_in       : in gspr_index_t;
  22         bypass_avail       : in std_ulogic;
  23         gpr_read_valid_in  : in std_ulogic;
  24         gpr_read_in        : in gspr_index_t;
  25
  26         ugpr_write_valid   : in std_ulogic;
  27         ugpr_write_reg     : in gspr_index_t;
  28
  29         stall_out          : out std_ulogic;
  30         use_bypass         : out std_ulogic
  31         );
  32 end entity gpr_hazard;
  33 architecture behaviour of gpr_hazard is
  34     type pipeline_entry_type is record
  35         valid  : std_ulogic;
  36         bypass : std_ulogic;
  37         gpr    : gspr_index_t;
  38         ugpr_valid : std_ulogic;
  39         ugpr   : gspr_index_t;
  40     end record;
  41     constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0', gpr => (others => '0'),
  42                                                            ugpr_valid => '0', ugpr => (others => '0'));
  43
  44     type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
  45     constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
  46
  47     signal r, rin : pipeline_t := pipeline_t_init;
  48 begin
  49     gpr_hazard0: process(clk)
  50     begin
  51         if rising_edge(clk) then
  52             r <= rin;
  53         end if;
  54     end process;
  55
  56     gpr_hazard1: process(all)
  57         variable v     : pipeline_t;
  58     begin
  59         v := r;
  60
  61         if complete_in = '1' then
  62             v(PIPELINE_DEPTH).valid := '0';
  63             v(PIPELINE_DEPTH).ugpr_valid := '0';
  64         end if;
  65
  66         stall_out <= '0';
  67         use_bypass <= '0';
  68         if gpr_read_valid_in = '1' then
  69             loop_0: for i in 0 to PIPELINE_DEPTH loop
  70                 if v(i).valid = '1' and r(i).gpr = gpr_read_in then
  71                     if r(i).bypass = '1' then
  72                         use_bypass <= '1';
  73                     else
  74                         stall_out <= '1';
  75                     end if;
  76                 end if;
  77                 if v(i).ugpr_valid = '1' and r(i).ugpr = gpr_read_in then
  78                     stall_out <= '1';
  79                 end if;
  80             end loop;
  81         end if;
  82
  83         -- XXX assumes PIPELINE_DEPTH = 1
  84         if busy_in = '0' then
  85             v(1) := v(0);
  86             v(0).valid := '0';
  87             v(0).ugpr_valid := '0';
  88         end if;
  89         if deferred = '0' and issuing = '1' then
  90             v(0).valid  := gpr_write_valid_in;
  91             v(0).bypass := bypass_avail;
  92             v(0).gpr    := gpr_write_in;
  93             v(0).ugpr_valid := ugpr_write_valid;
  94             v(0).ugpr   := ugpr_write_reg;
  95         end if;
  96         if flush_in = '1' then
  97             v(0).valid := '0';
  98             v(0).ugpr_valid := '0';
  99             v(1).valid := '0';
 100             v(1).ugpr_valid := '0';
 101         end if;
 102
 103         -- update registers
 104         rin <= v;
 105
 106     end process;
 107 end;