371f674e972342d4a04c86afbeb58c4c9e7fa9d1
3 from lambdasoc
.periph
import Peripheral
5 from gram
.dfii
import DFIInjector
6 from gram
.compat
import CSRPrefixProxy
7 from gram
.core
.controller
import ControllerSettings
, gramController
8 from gram
.core
.crossbar
import gramCrossbar
10 __ALL__
= ["gramCore"]
12 class gramCore(Peripheral
, Elaboratable
):
13 def __init__(self
, phy
, geom_settings
, timing_settings
, clk_freq
, **kwargs
):
14 super().__init
__("core")
16 bank
= self
.csr_bank()
19 self
._geom
_settings
= geom_settings
20 self
._timing
_settings
= timing_settings
21 self
._clk
_freq
= clk_freq
24 self
.dfii
= DFIInjector(
25 csr_bank
=CSRPrefixProxy(bank
, "dfii"),
26 addressbits
=self
._geom
_settings
.addressbits
,
27 bankbits
=self
._geom
_settings
.bankbits
,
28 nranks
=self
._phy
.settings
.nranks
,
29 databits
=self
._phy
.settings
.dfi_databits
,
30 nphases
=self
._phy
.settings
.nphases
)
32 self
.controller
= gramController(
33 phy_settings
=self
._phy
.settings
,
34 geom_settings
=self
._geom
_settings
,
35 timing_settings
=self
._timing
_settings
,
36 clk_freq
=self
._clk
_freq
,
40 self
.size
= 2**geom_settings
.bankbits
* 2**geom_settings
.rowbits
* 2**geom_settings
.colbits
42 self
.crossbar
= gramCrossbar(self
.controller
.interface
)
44 self
._bridge
= self
.bridge(data_width
=32, granularity
=8, alignment
=2)
45 self
.bus
= self
._bridge
.bus
47 def elaborate(self
, platform
):
50 m
.submodules
.bridge
= self
._bridge
52 m
.submodules
.dfii
= self
.dfii
53 m
.d
.comb
+= self
.dfii
.master
.connect(self
._phy
.dfi
)
55 m
.submodules
.controller
= self
.controller
56 m
.d
.comb
+= self
.controller
.dfi
.connect(self
.dfii
.slave
)
58 m
.submodules
.crossbar
= self
.crossbar