gram/phy/ecp5ddrphy.py

   1 # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
   2 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
   7 # DDR3: 800 MT/s
   8
   9 import math
  10
  11 from nmigen import *
  12 from nmigen.hdl.ast import Rose
  13 from nmigen.lib.cdc import FFSynchronizer
  14 from nmigen.utils import log2_int
  15
  16 from lambdasoc.periph import Peripheral
  17
  18 from gram.common import *
  19 from gram.phy.dfi import Interface
  20 from gram.compat import Timeline
  21
  22 __all__ = ["ECP5DDRPHY"]
  23
  24
  25 class ECP5DDRPHYInit(Elaboratable):
  26     def __init__(self):
  27         self.pause = Signal()
  28         self.stop = Signal()
  29         self.delay = Signal()
  30         self.reset = Signal()
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34
  35         update = Signal()
  36         freeze = Signal()
  37
  38         # DDRDLLA instance -------------------------------------------------------------------------
  39         _lock = Signal()
  40         lock = Signal()
  41         lock_d = Signal()
  42         m.submodules += Instance("DDRDLLA",
  43             i_CLK=ClockSignal("sync2x"),
  44             i_RST=ResetSignal("init"),
  45             i_UDDCNTLN=~update,
  46             i_FREEZE=freeze,
  47             o_DDRDEL=self.delay,
  48             o_LOCK=_lock)
  49         m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
  50         m.d.init += lock_d.eq(lock)
  51
  52         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
  53         t = 8  # in cycles
  54         tl = Timeline([
  55             (1*t,  [    freeze.eq(1)]),  # Freeze DDRDLLA
  56             (2*t,  [ self.stop.eq(1)]),   # Stop ECLK domain
  57             (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
  58             (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
  59             (5*t,  [ self.stop.eq(0)]),   # Release ECLK domain stop
  60             (6*t,  [    freeze.eq(0)]),  # Release DDRDLLA freeze
  61             (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
  62             (8*t,  [    update.eq(1)]),  # Update DDRDLLA
  63             (9*t,  [    update.eq(0)]),  # Release DDRDMMA update
  64             (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
  65         ])
  66         m.d.comb += tl.trigger.eq(lock & ~lock_d) # Trigger timeline on lock rising edge
  67         m.submodules += DomainRenamer("init")(tl)
  68
  69         return m
  70
  71
  72 class _DQSBUFMSettingManager(Elaboratable):
  73     """DQSBUFM setting manager.
  74
  75     The DQSBUFM primitive requires a very basic sequence when updating
  76     read delay or other parameters. This elaboratable generates this
  77     sequence from CSR events.
  78
  79     Parameters
  80     ----------
  81     rdly_slr : CSR
  82         CSR storing the rdly value.
  83
  84     Attributes
  85     ----------
  86     pause : Signal(), out
  87         Pause signal for DQSBUFM.
  88     readclksel : Signal(3), out
  89         Readclksel signal for DQSBUFM.
  90     """
  91     def __init__(self, rdly_csr):
  92         self.rdly_csr = rdly_csr
  93
  94         self.pause = Signal()
  95         self.readclksel = Signal(3)
  96
  97     def elaborate(self, platform):
  98         m = Module()
  99
 100         with m.FSM():
 101             with m.State("Idle"):
 102                 with m.If(self.rdly_csr.w_stb):
 103                     m.d.sync += self.pause.eq(1)
 104                     m.next = "RdlyUpdateRequestedDelay1"
 105
 106             with m.State("RdlyUpdateRequestedDelay1"):
 107                 m.next = "RdlyUpdateRequestedDelay2"
 108
 109             with m.State("RdlyUpdateRequestedDelay2"):
 110                 m.next = "RdlyUpdateRequestedDelay3"
 111
 112             with m.State("RdlyUpdateRequestedDelay3"):
 113                 m.next = "RdlyUpdateRequested"
 114
 115             with m.State("RdlyUpdateRequested"):
 116                 m.d.sync += self.readclksel.eq(self.rdly_csr.w_data)
 117                 m.next = "ResetPauseDelay1"
 118
 119             with m.State("ResetPauseDelay1"):
 120                 m.next = "ResetPauseDelay2"
 121
 122             with m.State("ResetPauseDelay2"):
 123                 m.next = "ResetPauseDelay3"
 124
 125             with m.State("ResetPauseDelay3"):
 126                 m.next = "ResetPause"
 127
 128             with m.State("ResetPause"):
 129                 m.d.sync += self.pause.eq(0)
 130                 m.next = "Idle"
 131
 132         return m
 133
 134
 135 class ECP5DDRPHY(Peripheral, Elaboratable):
 136     def __init__(self, pads, sys_clk_freq=100e6):
 137         super().__init__(name="phy")
 138
 139         self.pads = pads
 140         self._sys_clk_freq = sys_clk_freq
 141         self.init = ECP5DDRPHYInit()
 142
 143         databits = len(self.pads.dq.io)
 144         if databits % 8 != 0:
 145             raise ValueError("DQ pads should come in a multiple of 8")
 146
 147         # CSR
 148         bank = self.csr_bank()
 149
 150         self.burstdet = bank.csr(databits//8, "rw")
 151
 152         self.rdly = []
 153         self.rdly += [bank.csr(3, "rw", name="rdly_p0")]
 154         self.rdly += [bank.csr(3, "rw", name="rdly_p1")]
 155         self.bitslip = bank.csr(3, "rw") # phase-delay on read
 156
 157         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
 158         self.bus = self._bridge.bus
 159
 160         addressbits = len(self.pads.a.o0)
 161         bankbits = len(self.pads.ba.o0)
 162         nranks = 1
 163         if hasattr(self.pads, "cs_n") and hasattr(self.pads.cs_n, "o0"):
 164             nranks = len(self.pads.cs_n.o0)
 165         databits = len(self.pads.dq.io)
 166         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4,
 167                              name="ecp5phy")
 168
 169         # PHY settings -----------------------------------------------------------------------------
 170         tck = 1/(2*self._sys_clk_freq)
 171         nphases = 2
 172         databits = len(self.pads.dq.io)
 173         cl, cwl = get_cl_cw("DDR3", tck)
 174         cl_sys_latency = get_sys_latency(nphases, cl)
 175         cwl_sys_latency = get_sys_latency(nphases, cwl)
 176         rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
 177         wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
 178         self.settings = PhySettings(
 179             phytype="ECP5DDRPHY",
 180             memtype="DDR3",
 181             databits=databits,
 182             dfi_databits=4*databits,
 183             nranks=nranks,
 184             nphases=nphases,
 185             rdphase=rdphase,
 186             wrphase=wrphase,
 187             rdcmdphase    = (rdphase - 1)%nphases,
 188             wrcmdphase    = (wrphase - 1)%nphases,
 189             cl=cl,
 190             cwl=cwl,
 191             read_latency  = cl_sys_latency + 10,
 192             write_latency=cwl_sys_latency
 193         )
 194
 195     def elaborate(self, platform):
 196         m = Module()
 197
 198         m.submodules.bridge = self._bridge
 199
 200         tck = 1/(2*self._sys_clk_freq)
 201         nphases = 2
 202         databits = len(self.pads.dq.io)
 203
 204         burstdet_reg = Signal(databits//8, reset_less=True)
 205         m.d.comb += self.burstdet.r_data.eq(burstdet_reg)
 206
 207         # Burstdet clear
 208         with m.If(self.burstdet.w_stb):
 209             m.d.sync += burstdet_reg.eq(0)
 210
 211         # Init -------------------------------------------------------------------------------------
 212         m.submodules.init = init = self.init
 213
 214         # Parameters -------------------------------------------------------------------------------
 215         cl, cwl = get_cl_cw("DDR3", tck)
 216         cl_sys_latency = get_sys_latency(nphases, cl)
 217         cwl_sys_latency = get_sys_latency(nphases, cwl)
 218
 219         # DFI Interface ----------------------------------------------------------------------------
 220         dfi = self.dfi
 221
 222         bl8_chunk = Signal()
 223
 224         # Clock --------------------------------------------------------------------------------
 225         m.d.comb += [
 226             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
 227             self.pads.clk.o_fclk.eq(ClockSignal("sync2x")),
 228         ]
 229         for i in range(len(self.pads.clk.o0)):
 230             m.d.comb += [
 231                 self.pads.clk.o0[i].eq(0),
 232                 self.pads.clk.o1[i].eq(1),
 233                 self.pads.clk.o2[i].eq(0),
 234                 self.pads.clk.o3[i].eq(1),
 235             ]
 236
 237         # Addresses and Commands ---------------------------------------------------------------
 238         m.d.comb += [
 239             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
 240             self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
 241             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
 242             self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
 243         ]
 244         for i in range(len(self.pads.a.o0)):
 245             m.d.comb += [
 246                 self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
 247                 self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
 248                 self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
 249                 self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
 250             ]
 251         for i in range(len(self.pads.ba.o0)):
 252             m.d.comb += [
 253                 self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
 254                 self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
 255                 self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
 256                 self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
 257             ]
 258
 259         # Control pins: all of thees have to be declared "xdr 4" when
 260         # requesting the resource:
 261         # ddr_pins = platform.request("ddr3", 0, xdr={"clk":4, "odt":4, ... })
 262         controls = ["ras", "cas", "we", "clk_en", "odt"]
 263         if hasattr(self.pads, "rst"): # this gets renamed later to match dfi
 264             controls.append("rst")
 265         if hasattr(self.pads, "cs"):
 266             controls.append("cs")
 267         for name in controls:
 268             print ("clock", name, getattr(self.pads, name))
 269             pad = getattr(self.pads, name)
 270             # sigh, convention in nmigen_boards is "rst" but in
 271             # dfi.Interface it is "reset"
 272             dfi2pads = {'rst': 'reset', 'cs': 'cs_n'}
 273             name = dfi2pads.get(name, name) # remap if exists
 274             if name == "reset":
 275                 m.d.comb += [
 276                     pad.o_clk.eq(ClockSignal("sync")),
 277                 ]
 278             else:
 279                 m.d.comb += [
 280                     pad.o_clk.eq(ClockSignal("dramsync")),
 281                     pad.o_fclk.eq(ClockSignal("sync2x")),
 282                 ]
 283             if name == "reset":
 284                 for i in range(len(pad.o)):
 285                     m.d.comb += [
 286                         pad.o[i].eq(getattr(dfi.phases[0], name)[i]),
 287                     ]
 288             elif name == "cs_n":
 289                 # cs_n can't be directly connected to cs without being inverted first...
 290                 for i in range(len(pad.o0)):
 291                     m.d.comb += [
 292                         pad.o0[i].eq(~getattr(dfi.phases[0], name)[i]),
 293                         pad.o1[i].eq(~getattr(dfi.phases[0], name)[i]),
 294                         pad.o2[i].eq(~getattr(dfi.phases[1], name)[i]),
 295                         pad.o3[i].eq(~getattr(dfi.phases[1], name)[i]),
 296                     ]
 297             else:
 298                 for i in range(len(pad.o0)):
 299                     m.d.comb += [
 300                         pad.o0[i].eq(getattr(dfi.phases[0], name)[i]),
 301                         pad.o1[i].eq(getattr(dfi.phases[0], name)[i]),
 302                         pad.o2[i].eq(getattr(dfi.phases[1], name)[i]),
 303                         pad.o3[i].eq(getattr(dfi.phases[1], name)[i]),
 304                     ]
 305
 306         # DQ ---------------------------------------------------------------------------------------
 307         dq_oe = Signal()
 308         dqs_re = Signal()
 309         dqs_oe = Signal()
 310         dqs_postamble = Signal()
 311         dqs_preamble = Signal()
 312         for i in range(databits//8):
 313             # DQSBUFM
 314             dqs_i = Signal()
 315             dqsr90 = Signal()
 316             dqsw270 = Signal()
 317             dqsw = Signal()
 318             rdpntr = Signal(3)
 319             wrpntr = Signal(3)
 320             burstdet = Signal()
 321             datavalid = Signal()
 322             datavalid_prev = Signal()
 323             m.d.sync += datavalid_prev.eq(datavalid)
 324
 325             dqsbufm_manager = _DQSBUFMSettingManager(self.rdly[i])
 326             setattr(m.submodules, f"dqsbufm_manager{i}", dqsbufm_manager)
 327
 328             m.submodules += Instance("DQSBUFM",
 329                 p_DQS_LI_DEL_ADJ="MINUS",
 330                 p_DQS_LI_DEL_VAL=1,
 331                 p_DQS_LO_DEL_ADJ="MINUS",
 332                 p_DQS_LO_DEL_VAL=4,
 333
 334                 # Delay
 335                 i_DYNDELAY0=0,
 336                 i_DYNDELAY1=0,
 337                 i_DYNDELAY2=0,
 338                 i_DYNDELAY3=0,
 339                 i_DYNDELAY4=0,
 340                 i_DYNDELAY5=0,
 341                 i_DYNDELAY6=0,
 342                 i_DYNDELAY7=0,
 343
 344                 # Clocks / Reset
 345                 i_SCLK=ClockSignal("sync"),
 346                 i_ECLK=ClockSignal("sync2x"),
 347                 i_RST=ResetSignal("dramsync"),
 348                 i_DDRDEL=init.delay,
 349                 i_PAUSE=init.pause | dqsbufm_manager.pause,
 350
 351                 # Control
 352                 # Assert LOADNs to use DDRDEL control
 353                 i_RDLOADN=0,
 354                 i_RDMOVE=0,
 355                 i_RDDIRECTION=1,
 356                 i_WRLOADN=0,
 357                 i_WRMOVE=0,
 358                 i_WRDIRECTION=1,
 359
 360                 # Reads (generate shifted DQS clock for reads)
 361                 i_READ0=dqs_re,
 362                 i_READ1=dqs_re,
 363                 i_READCLKSEL0=dqsbufm_manager.readclksel[0],
 364                 i_READCLKSEL1=dqsbufm_manager.readclksel[1],
 365                 i_READCLKSEL2=dqsbufm_manager.readclksel[2],
 366                 i_DQSI=dqs_i,
 367                 o_DQSR90=dqsr90,
 368                 o_RDPNTR0=rdpntr[0],
 369                 o_RDPNTR1=rdpntr[1],
 370                 o_RDPNTR2=rdpntr[2],
 371                 o_WRPNTR0=wrpntr[0],
 372                 o_WRPNTR1=wrpntr[1],
 373                 o_WRPNTR2=wrpntr[2],
 374                 o_BURSTDET=burstdet,
 375                 o_DATAVALID=datavalid,
 376
 377                 # Writes (generate shifted ECLK clock for writes)
 378                 o_DQSW270=dqsw270,
 379                 o_DQSW=dqsw)
 380
 381             with m.If(Rose(burstdet)):
 382                 m.d.sync += burstdet_reg[i].eq(1)
 383
 384             # DQS and DM ---------------------------------------------------------------------------
 385             dm_o_data = Signal(8)
 386             dm_o_data_d = Signal(8, reset_less=True)
 387             dm_o_data_muxed = Signal(4, reset_less=True)
 388             m.d.comb += dm_o_data.eq(Cat(
 389                 dfi.phases[0].wrdata_mask[0*databits//8+i],
 390                 dfi.phases[0].wrdata_mask[1*databits//8+i],
 391                 dfi.phases[0].wrdata_mask[2*databits//8+i],
 392                 dfi.phases[0].wrdata_mask[3*databits//8+i],
 393
 394                 dfi.phases[1].wrdata_mask[0*databits//8+i],
 395                 dfi.phases[1].wrdata_mask[1*databits//8+i],
 396                 dfi.phases[1].wrdata_mask[2*databits//8+i],
 397                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
 398             )
 399             m.d.sync += dm_o_data_d.eq(dm_o_data)
 400
 401             with m.If(bl8_chunk):
 402                 m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
 403             with m.Else():
 404                 m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
 405
 406             m.submodules += Instance("ODDRX2DQA",
 407                 i_RST=ResetSignal("dramsync"),
 408                 i_ECLK=ClockSignal("sync2x"),
 409                 i_SCLK=ClockSignal("dramsync"),
 410                 i_DQSW270=dqsw270,
 411                 i_D0=dm_o_data_muxed[0],
 412                 i_D1=dm_o_data_muxed[1],
 413                 i_D2=dm_o_data_muxed[2],
 414                 i_D3=dm_o_data_muxed[3],
 415                 o_Q=self.pads.dm.o[i])
 416
 417             dqs = Signal()
 418             dqs_oe_n = Signal()
 419             m.submodules += [
 420                 Instance("ODDRX2DQSB",
 421                     i_RST=ResetSignal("dramsync"),
 422                     i_ECLK=ClockSignal("sync2x"),
 423                     i_SCLK=ClockSignal(),
 424                     i_DQSW=dqsw,
 425                     i_D0=0,
 426                     i_D1=1,
 427                     i_D2=0,
 428                     i_D3=1,
 429                     o_Q=dqs),
 430                 Instance("TSHX2DQSA",
 431                     i_RST=ResetSignal("dramsync"),
 432                     i_ECLK=ClockSignal("sync2x"),
 433                     i_SCLK=ClockSignal(),
 434                     i_DQSW=dqsw,
 435                     i_T0=~(dqs_oe | dqs_postamble),
 436                     i_T1=~(dqs_oe | dqs_preamble),
 437                     o_Q=dqs_oe_n),
 438                 Instance("BB",
 439                     i_I=dqs,
 440                     i_T=dqs_oe_n,
 441                     o_O=dqs_i,
 442                     io_B=self.pads.dqs.p[i]),
 443             ]
 444
 445             for j in range(8*i, 8*(i+1)):
 446                 dq_o = Signal()
 447                 dq_i = Signal()
 448                 dq_oe_n = Signal()
 449                 dq_i_delayed = Signal()
 450                 dq_i_data = Signal(4)
 451                 dq_o_data = Signal(8)
 452                 dq_o_data_d = Signal(8, reset_less=True)
 453                 dq_o_data_muxed = Signal(4, reset_less=True)
 454                 m.d.comb += dq_o_data.eq(Cat(
 455                     dfi.phases[0].wrdata[0*databits+j],
 456                     dfi.phases[0].wrdata[1*databits+j],
 457                     dfi.phases[0].wrdata[2*databits+j],
 458                     dfi.phases[0].wrdata[3*databits+j],
 459                     dfi.phases[1].wrdata[0*databits+j],
 460                     dfi.phases[1].wrdata[1*databits+j],
 461                     dfi.phases[1].wrdata[2*databits+j],
 462                     dfi.phases[1].wrdata[3*databits+j])
 463                 )
 464
 465                 m.d.sync += dq_o_data_d.eq(dq_o_data)
 466                 with m.If(bl8_chunk):
 467                     m.d.sync += dq_o_data_muxed.eq(dq_o_data_d[4:])
 468                 with m.Else():
 469                     m.d.sync += dq_o_data_muxed.eq(dq_o_data[:4])
 470
 471                 m.submodules += [
 472                     Instance("ODDRX2DQA",
 473                         i_RST=ResetSignal("dramsync"),
 474                         i_ECLK=ClockSignal("sync2x"),
 475                         i_SCLK=ClockSignal(),
 476                         i_DQSW270=dqsw270,
 477                         i_D0=dq_o_data_muxed[0],
 478                         i_D1=dq_o_data_muxed[1],
 479                         i_D2=dq_o_data_muxed[2],
 480                         i_D3=dq_o_data_muxed[3],
 481                         o_Q=dq_o),
 482                     Instance("DELAYG",
 483                         p_DEL_MODE = "DQS_ALIGNED_X2",
 484                         i_A        = dq_i,
 485                         o_Z        = dq_i_delayed),
 486                     Instance("IDDRX2DQA",
 487                         i_RST=ResetSignal("dramsync"),
 488                         i_ECLK=ClockSignal("sync2x"),
 489                         i_SCLK=ClockSignal(),
 490                         i_DQSR90=dqsr90,
 491                         i_RDPNTR0=rdpntr[0],
 492                         i_RDPNTR1=rdpntr[1],
 493                         i_RDPNTR2=rdpntr[2],
 494                         i_WRPNTR0=wrpntr[0],
 495                         i_WRPNTR1=wrpntr[1],
 496                         i_WRPNTR2=wrpntr[2],
 497                         i_D=dq_i_delayed,
 498                         o_Q0=dq_i_data[0],
 499                         o_Q1=dq_i_data[1],
 500                         o_Q2=dq_i_data[2],
 501                         o_Q3=dq_i_data[3]),
 502                     Instance("TSHX2DQA",
 503                         i_RST=ResetSignal("dramsync"),
 504                         i_ECLK=ClockSignal("sync2x"),
 505                         i_SCLK=ClockSignal(),
 506                         i_DQSW270=dqsw270,
 507                         i_T0=~dq_oe,
 508                         i_T1=~dq_oe,
 509                         o_Q=dq_oe_n),
 510                     Instance("BB",
 511                         i_I=dq_o,
 512                         i_T=dq_oe_n,
 513                         o_O=dq_i,
 514                         io_B=self.pads.dq.io[j])
 515                 ]
 516                 with m.If(~datavalid_prev & datavalid):
 517                     m.d.sync += [
 518                         dfi.phases[0].rddata[0*databits+j].eq(dq_i_data[0]),
 519                         dfi.phases[0].rddata[1*databits+j].eq(dq_i_data[1]),
 520                         dfi.phases[0].rddata[2*databits+j].eq(dq_i_data[2]),
 521                         dfi.phases[0].rddata[3*databits+j].eq(dq_i_data[3]),
 522                     ]
 523                 with m.Elif(datavalid):
 524                     m.d.sync += [
 525                         dfi.phases[1].rddata[0*databits+j].eq(dq_i_data[0]),
 526                         dfi.phases[1].rddata[1*databits+j].eq(dq_i_data[1]),
 527                         dfi.phases[1].rddata[2*databits+j].eq(dq_i_data[2]),
 528                         dfi.phases[1].rddata[3*databits+j].eq(dq_i_data[3]),
 529                     ]
 530
 531         # Read Control Path ------------------------------------------------------------------------
 532         # Creates a shift register of read commands coming from the DFI interface. This shift register
 533         # is used to control DQS read (internal read pulse of the DQSBUF) and to indicate to the
 534         # DFI interface that the read data is valid.
 535         #
 536         # The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
 537         # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
 538         #
 539         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
 540         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
 541         rddata_en = Signal(self.settings.read_latency)
 542         rddata_en_last = Signal.like(rddata_en)
 543         m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
 544         m.d.sync += rddata_en_last.eq(rddata_en)
 545         m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2])
 546
 547         rddata_valid = Signal()
 548         m.d.sync += rddata_valid.eq(datavalid_prev & ~datavalid)
 549         for phase in dfi.phases:
 550             m.d.comb += phase.rddata_valid.eq(rddata_valid)
 551
 552         # Write Control Path -----------------------------------------------------------------------
 553         # Creates a shift register of write commands coming from the DFI interface. This shift register
 554         # is used to control DQ/DQS tristates and to select write data of the DRAM burst from the DFI
 555         # interface: The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles:
 556         # 2x for DDR, 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency.
 557         # Writes are then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
 558         # FIXME: understand +2
 559         wrdata_en = Signal(cwl_sys_latency + 4)
 560         wrdata_en_last = Signal.like(wrdata_en)
 561         m.d.comb += wrdata_en.eq(Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
 562         m.d.sync += wrdata_en_last.eq(wrdata_en)
 563         m.d.comb += dq_oe.eq(wrdata_en[cwl_sys_latency + 1] | wrdata_en[cwl_sys_latency + 2])
 564         m.d.comb += bl8_chunk.eq(wrdata_en[cwl_sys_latency + 1])
 565         m.d.comb += dqs_oe.eq(dq_oe)
 566
 567         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
 568         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
 569         # write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
 570         # 1 for Preamble, 2 for the Write and 1 for the Postamble.
 571         m.d.comb += dqs_preamble.eq(wrdata_en[cwl_sys_latency + 0] & ~wrdata_en[cwl_sys_latency + 1])
 572         m.d.comb += dqs_postamble.eq(wrdata_en[cwl_sys_latency + 3] & ~wrdata_en[cwl_sys_latency + 2])
 573
 574         return m