gram/simulation/simsoctb.v

   1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 `timescale 1 ns / 1 ns
   4
   5 module simsoctb;
   6   // GSR & PUR init requires for Lattice models
   7   GSR GSR_INST (
   8     .GSR(1'b1)
   9   );
  10   PUR PUR_INST (
  11     .PUR (1'b1)
  12   );
  13
  14   reg clkin;
  15   wire sync;
  16   wire sync2x;
  17   wire dramsync;
  18   wire init;
  19
  20   // Generate 100 Mhz clock
  21   always
  22     begin
  23       clkin = 1;
  24       #5;
  25       clkin = 0;
  26       #5;
  27     end
  28
  29   // DDR3 init
  30   wire dram_ck;
  31   wire dram_cke;
  32   wire dram_we_n;
  33   wire dram_cs_n;
  34   wire dram_ras_n;
  35   wire dram_cas_n;
  36   wire [15:0] dram_dq;
  37   inout wire [1:0] dram_dqs;
  38   inout wire [1:0] dram_dqs_n;
  39   wire [13:0] dram_a;
  40   wire [2:0] dram_ba;
  41   wire [1:0] dram_dm;
  42   wire dram_odt;
  43   wire [1:0] dram_tdqs_n;
  44   wire dram_rst;
  45
  46   ddr3 #(
  47     .check_strict_timing(0)
  48   ) ram_chip (
  49     .rst_n(dram_rst),
  50     .ck(dram_ck),
  51     .ck_n(~dram_ck),
  52     .cke(dram_cke),
  53     .cs_n(~dram_cs_n),
  54     .ras_n(dram_ras_n),
  55     .cas_n(dram_cas_n),
  56     .we_n(dram_we_n),
  57     .dm_tdqs(dram_dm),
  58     .ba(dram_ba),
  59     .addr(dram_a),
  60     .dq(dram_dq),
  61     .dqs(dram_dqs),
  62     .dqs_n(dram_dqs_n),
  63     .tdqs_n(dram_tdqs_n),
  64     .odt(dram_odt)
  65   );
  66
  67   assign dram_dqs_n = (dram_dqs != 2'hz) ? ~dram_dqs : 2'hz;
  68
  69   // Wishbone
  70   reg [31:0] wishbone_adr = 0;
  71   reg [31:0] wishbone_dat_w = 0;
  72   wire [31:0] wishbone_dat_r;
  73   reg [3:0] wishbone_sel = 0;
  74   reg wishbone_cyc = 0;
  75   reg wishbone_stb = 0;
  76   reg wishbone_we = 0;
  77   wire wishbone_ack;
  78
  79   //defparam ram_chip.
  80
  81   top simsoctop (
  82     .ddr3_0__rst__io(dram_rst),
  83     .ddr3_0__dq__io(dram_dq),
  84     .ddr3_0__dqs__p(dram_dqs),
  85     .ddr3_0__clk__io(dram_ck),
  86     .ddr3_0__clk_en__io(dram_cke),
  87     .ddr3_0__we__io(dram_we_n),
  88     .ddr3_0__cs__io(dram_cs_n),
  89     .ddr3_0__ras__io(dram_ras_n),
  90     .ddr3_0__cas__io(dram_cas_n),
  91     .ddr3_0__a__io(dram_a),
  92     .ddr3_0__ba__io(dram_ba),
  93     .ddr3_0__dm__io(dram_dm),
  94     .ddr3_0__odt__io(dram_odt),
  95     .wishbone_0__adr__io(wishbone_adr),
  96     .wishbone_0__dat_r__io(wishbone_dat_r),
  97     .wishbone_0__dat_w__io(wishbone_dat_w),
  98     .wishbone_0__cyc__io(wishbone_cyc),
  99     .wishbone_0__stb__io(wishbone_stb),
 100     .wishbone_0__sel__io(wishbone_sel),
 101     .wishbone_0__ack__io(wishbone_ack),
 102     .wishbone_0__we__io(wishbone_we),
 103     .clk100_0__io(clkin),
 104     .rst_0__io(1'b0)
 105   );
 106
 107   initial
 108     begin
 109       $dumpfile("simsoc.fst");
 110       $dumpvars(0, clkin);
 111       $dumpvars(0, dram_rst);
 112       $dumpvars(0, dram_dq);
 113       $dumpvars(0, dram_dqs);
 114       $dumpvars(0, dram_ck);
 115       $dumpvars(0, dram_cke);
 116       $dumpvars(0, dram_cs_n);
 117       $dumpvars(0, dram_we_n);
 118       $dumpvars(0, dram_ras_n);
 119       $dumpvars(0, dram_cas_n);
 120       $dumpvars(0, dram_a);
 121       $dumpvars(0, dram_ba);
 122       $dumpvars(0, dram_dm);
 123       $dumpvars(0, dram_odt);
 124       $dumpvars(0, wishbone_adr);
 125       $dumpvars(0, wishbone_dat_w);
 126       $dumpvars(0, wishbone_dat_r);
 127       $dumpvars(0, wishbone_ack);
 128       $dumpvars(0, wishbone_stb);
 129       $dumpvars(0, wishbone_cyc);
 130       $dumpvars(0, wishbone_sel);
 131       $dumpvars(0, wishbone_we);
 132       $dumpvars(0, simsoctop);
 133       $dumpvars(0, ram_chip);
 134     end
 135
 136   // UART
 137   reg [31:0] tmp;
 138   initial
 139     begin
 140       #350; // Wait for RESET and POR
 141
 142       $display("Release RESET_N");
 143       wishbone_write(32'h0000900c >> 2, 32'h0); // p0 address
 144       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
 145       wishbone_write(32'h00009000 >> 2, 8'h0C); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N
 146
 147       $display("Enable CKE");
 148       wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
 149       if (dram_cke != 1)
 150         begin
 151           $display("CKE activation failure");
 152           $finish;
 153         end
 154
 155       // Set MR2
 156       $display("Set MR2");
 157       wishbone_write(32'h0000900c >> 2, 32'h200); // p0 address
 158       wishbone_write(32'h00009010 >> 2, 32'h2); // p0 baddress
 159       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
 160       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 161
 162       // Set MR3
 163       $display("Set MR3");
 164       wishbone_write(32'h0000900c >> 2, 32'h0); // p0 address
 165       wishbone_write(32'h00009010 >> 2, 32'h3); // p0 baddress
 166       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
 167       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 168
 169       // Set MR1
 170       $display("Set MR1");
 171       wishbone_write(32'h0000900c >> 2, 32'h6); // p0 address
 172       wishbone_write(32'h00009010 >> 2, 32'h1); // p0 baddress
 173       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
 174       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 175
 176       // Set MR0
 177       $display("Set MR0");
 178       wishbone_write(32'h0000900c >> 2, 32'h320); // p0 address
 179       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
 180       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
 181       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 182       wishbone_write(32'h0000900c >> 2, 32'h220); // p0 address
 183       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
 184       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
 185       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 186       #6000; // tDLLK
 187
 188       // ZQ calibration
 189       $display("Start ZQ calibration");
 190       wishbone_write(32'h0000900c >> 2, 32'h400); // p0 address (A10=1)
 191       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
 192       wishbone_write(32'h00009004 >> 2, 8'h03); // WE|CS
 193       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
 194       #6000; // tZQinit
 195
 196       // Hardware control
 197       wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL
 198       #2000;
 199
 200       // reset burst detect
 201       //wishbone_write(32'h00008000 >> 2, 0); // burst detect reset
 202
 203       // read on burst detect
 204       //wishbone_read(32'h00008000 >> 2, tmp); // burst detect
 205
 206       // Read test on provisioned data, row 0, col 0-7
 207       wishbone_read(32'h10000000 >> 2, tmp);
 208       assert_equal_32(tmp, 32'hFACECA8C);
 209       wishbone_read(32'h10000004 >> 2, tmp);
 210       assert_equal_32(tmp, 32'h0A0A0A0A);
 211       wishbone_read(32'h10000008 >> 2, tmp);
 212       assert_equal_32(tmp, 32'hFAAFFEEF);
 213       wishbone_read(32'h1000000C >> 2, tmp);
 214       assert_equal_32(tmp, 32'h12345678);
 215
 216       // Read test on provisioned data, row 0, col 8-15
 217       wishbone_read(32'h10000010 >> 2, tmp);
 218       assert_equal_32(tmp, 32'h33333333);
 219       wishbone_read(32'h10000014 >> 2, tmp);
 220       assert_equal_32(tmp, 32'h22222222);
 221       wishbone_read(32'h10000018 >> 2, tmp);
 222       assert_equal_32(tmp, 32'h11111111);
 223       wishbone_read(32'h1000001C >> 2, tmp);
 224       assert_equal_32(tmp, 32'h00000000);
 225
 226       // Read test on provisioned data, row 0, col 16-23
 227       wishbone_read(32'h10000020 >> 2, tmp);
 228       assert_equal_32(tmp, 32'hA0A0A0A0);
 229       wishbone_read(32'h10000024 >> 2, tmp);
 230       assert_equal_32(tmp, 32'h55556666);
 231       wishbone_read(32'h10000028 >> 2, tmp);
 232       assert_equal_32(tmp, 32'h01020304);
 233       wishbone_read(32'h1000002C >> 2, tmp);
 234       assert_equal_32(tmp, 32'hF00DF00D);
 235
 236       // Read test on provisioned data, row 0, col 24-31
 237       wishbone_read(32'h10000030 >> 2, tmp);
 238       assert_equal_32(tmp, 32'hAAAAAAAA);
 239       wishbone_read(32'h10000034 >> 2, tmp);
 240       assert_equal_32(tmp, 32'h000C0C0A);
 241       wishbone_read(32'h10000038 >> 2, tmp);
 242       assert_equal_32(tmp, 32'h000CACA0);
 243       wishbone_read(32'h1000003C >> 2, tmp);
 244       assert_equal_32(tmp, 32'hC0CAC0CA);
 245
 246       // Write
 247       wishbone_write(32'h1000000C >> 2, 32'h00BA0BAB);
 248       wishbone_write(32'h10000008 >> 2, 32'h13374242);
 249       wishbone_write(32'h10000004 >> 2, 32'hC0DEC0DE);
 250       wishbone_write(32'h10000000 >> 2, 32'h01020304);
 251
 252       wishbone_read(32'h10000000 >> 2, tmp);
 253       assert_equal_32(tmp, 32'h01020304);
 254       wishbone_read(32'h10000004 >> 2, tmp);
 255       assert_equal_32(tmp, 32'hC0DEC0DE);
 256       wishbone_read(32'h10000008 >> 2, tmp);
 257       assert_equal_32(tmp, 32'h13374242);
 258       wishbone_read(32'h1000000C >> 2, tmp);
 259       assert_equal_32(tmp, 32'h00BA0BAB);
 260
 261       $finish;
 262     end
 263
 264   task wishbone_write;
 265     input [31:0] address;
 266     input [31:0] value;
 267
 268     begin
 269       wishbone_adr = address;
 270       wishbone_dat_w = value;
 271       wishbone_cyc = 1;
 272       wishbone_stb = 1;
 273       wishbone_sel = 4'hF;
 274       wishbone_we = 1;
 275
 276       while (wishbone_ack == 0)
 277         begin
 278           #10;
 279         end
 280
 281       wishbone_cyc = 0;
 282       wishbone_stb = 0;
 283
 284       #10;
 285     end
 286   endtask
 287
 288   task wishbone_read;
 289     input [31:0] address;
 290     output [31:0] value;
 291
 292     begin
 293       wishbone_adr = address;
 294       wishbone_we = 0;
 295       wishbone_cyc = 1;
 296       wishbone_stb = 1;
 297       wishbone_sel = 4'hF;
 298
 299       while (wishbone_ack == 0)
 300         begin
 301           #10;
 302         end
 303
 304       value = wishbone_dat_r;
 305       wishbone_cyc = 0;
 306       wishbone_stb = 0;
 307
 308       #10;
 309     end
 310   endtask
 311
 312   task assert_equal_32;
 313     input [31:0] inA;
 314     input [31:0] inB;
 315
 316     begin
 317       if (inA != inB)
 318         begin
 319           $display("%m at %t: Assertion failed (32-bit) equality: %08x != %08x", $time, inA, inB);
 320           $finish;
 321         end
 322     end
 323   endtask
 324
 325   integer i;
 326   integer tstart;
 327   integer tend;
 328
 329   task speedtest_read;
 330     begin
 331       tstart = $time;
 332       for (i = 0; i < 10; i = i+1) begin
 333         wishbone_read(32'h10000000 >> 2, tmp);
 334         wishbone_read(32'h10000004 >> 2, tmp);
 335         wishbone_read(32'h10000008 >> 2, tmp);
 336         wishbone_read(32'h1000000C >> 2, tmp);
 337         wishbone_read(32'h10000010 >> 2, tmp);
 338         wishbone_read(32'h10000014 >> 2, tmp);
 339         wishbone_read(32'h10000018 >> 2, tmp);
 340         wishbone_read(32'h1000001C >> 2, tmp);
 341         wishbone_read(32'h10000020 >> 2, tmp);
 342         wishbone_read(32'h10000024 >> 2, tmp);
 343         wishbone_read(32'h10000028 >> 2, tmp);
 344         wishbone_read(32'h1000002C >> 2, tmp);
 345         wishbone_read(32'h10000030 >> 2, tmp);
 346         wishbone_read(32'h10000034 >> 2, tmp);
 347         wishbone_read(32'h10000038 >> 2, tmp);
 348         wishbone_read(32'h1000003C >> 2, tmp);
 349       end
 350       tend = $time;
 351
 352       //$display("Read speedtest: %d B/s", (10*16*4)*1000000000/(1024*1024)/(tend-tstart));
 353       $display("Read speedtest: %d MB/s", 610352/(tend-tstart));
 354     end
 355   endtask
 356
 357     task speedtest_write;
 358     begin
 359       tstart = $time;
 360       for (i = 0; i < 10; i = i+1) begin
 361         wishbone_write(32'h1000000C >> 2, 32'h00BA0BAB);
 362         wishbone_write(32'h10000008 >> 2, 32'h13374242);
 363         wishbone_write(32'h10000004 >> 2, 32'hC0DEC0DE);
 364         wishbone_write(32'h10000000 >> 2, 32'h01020304);
 365         wishbone_write(32'h1000001C >> 2, 32'h00BA0BAB);
 366         wishbone_write(32'h10000018 >> 2, 32'h13374242);
 367         wishbone_write(32'h10000014 >> 2, 32'hC0DEC0DE);
 368         wishbone_write(32'h10000010 >> 2, 32'h01020304);
 369         wishbone_write(32'h1000002C >> 2, 32'h00BA0BAB);
 370         wishbone_write(32'h10000028 >> 2, 32'h13374242);
 371         wishbone_write(32'h10000024 >> 2, 32'hC0DEC0DE);
 372         wishbone_write(32'h10000020 >> 2, 32'h01020304);
 373         wishbone_write(32'h1000003C >> 2, 32'h00BA0BAB);
 374         wishbone_write(32'h10000038 >> 2, 32'h13374242);
 375         wishbone_write(32'h10000034 >> 2, 32'hC0DEC0DE);
 376         wishbone_write(32'h10000030 >> 2, 32'h01020304);
 377       end
 378       tend = $time;
 379
 380       //$display("Write speedtest: %d B/s", (10*16*4)*1000000000/(1024*1024)/(tend-tstart));
 381       $display("Write speedtest: %d MB/s", 610352/(tend-tstart));
 382     end
 383   endtask
 384 endmodule