hwacha/decode_hwacha.h

   1 #ifndef _DECODE_HWACHA_H
   2 #define _DECODE_HWACHA_H
   3
   4 #include "hwacha.h"
   5 #include "hwacha_xcpt.h"
   6
   7 #define XS1 (xs1)
   8 #define XS2 (xs2)
   9 #define WRITE_XRD(value) (xd = value)
  10
  11 #define NXPR (h->get_ct_state()->nxpr)
  12 #define NFPR (h->get_ct_state()->nfpr)
  13 #define MAXVL (h->get_ct_state()->maxvl)
  14 #define VL (h->get_ct_state()->vl)
  15 #define VF_PC (h->get_ct_state()->vf_pc)
  16 #define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
  17 #define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
  18 #define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
  19 #define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
  20 #define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
  21
  22 #define INSN_RS1 (insn.rs1())
  23 #define INSN_RS2 (insn.rs2())
  24 #define INSN_RS3 (insn.rs3())
  25 #define INSN_RD (insn.rd())
  26 #define INSN_SEG ((insn.i_imm() >> 9)+1)
  27
  28 static inline reg_t read_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
  29 {
  30   if (src >= h->get_ct_state()->nxpr)
  31     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  32   return (h->get_ut_state(idx)->XPR[src]);
  33 }
  34
  35 static inline void write_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
  36 {
  37   if (dst >= h->get_ct_state()->nxpr)
  38     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  39   h->get_ut_state(idx)->XPR.write(dst, value);
  40 }
  41
  42 #define UT_READ_XPR(idx, src) read_xpr(h, insn, idx, src)
  43 #define UT_WRITE_XPR(idx, dst, value) write_xpr(h, insn, idx, dst, value)
  44 #define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
  45 #define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
  46 #define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
  47
  48 static inline reg_t read_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
  49 {
  50   if (src >= h->get_ct_state()->nfpr)
  51     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  52   return (h->get_ut_state(idx)->FPR[src]);
  53 }
  54
  55 static inline void write_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
  56 {
  57   if (dst >= h->get_ct_state()->nfpr)
  58     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  59   h->get_ut_state(idx)->FPR.write(dst, value);
  60 }
  61
  62 #define UT_READ_FPR(idx, src) read_fpr(h, insn, idx, src)
  63 #define UT_WRITE_FPR(idx, dst, value) write_fpr(h, insn, idx, dst, value)
  64 #define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
  65 #define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
  66 #define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
  67 #define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
  68
  69 #define VEC_SEG_LOAD(dst, func, inc) \
  70   VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
  71
  72 #define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
  73   reg_t seg_addr = XS1; \
  74   for (uint32_t i=0; i<VL; i++) { \
  75     reg_t addr = seg_addr; \
  76     seg_addr += stride; \
  77     for (uint32_t j=0; j<INSN_SEG; j++) { \
  78       UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
  79       addr += inc; \
  80     } \
  81   }
  82
  83 #define VEC_SEG_STORE(src, func, inc) \
  84   VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
  85
  86 #define VEC_SEG_ST_STORE(src, func, stride, inc) \
  87   reg_t seg_addr = XS1; \
  88   for (uint32_t i=0; i<VL; i++) { \
  89     reg_t addr = seg_addr; \
  90     seg_addr += stride; \
  91     for (uint32_t j=0; j<INSN_SEG; j++) { \
  92       p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
  93       addr += inc; \
  94     } \
  95   }
  96
  97 #define require_supervisor_hwacha \
  98   if (unlikely(!(p->get_state()->sr & SR_S))) \
  99     h->take_exception(HWACHA_CAUSE_PRIVILEGED_INSTRUCTION, insn.bits());
 100
 101 #endif