hwacha/disasm.cc

   1 hwacha_disassembler::hwacha_disassembler()
   2 {
   3   #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg)
   4   #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg)
   5   #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg)
   6   #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg)
   7   #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg)
   8   #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg)
   9
  10   DEFINE_RS1(vxcptsave);
  11   DEFINE_RS1(vxcptrestore);
  12   DEFINE_NOARG(vxcptkill);
  13
  14   DEFINE_RS1(vxcptevac);
  15   DEFINE_NOARG(vxcpthold);
  16   DEFINE_RS1_RS2(venqcmd);
  17   DEFINE_RS1_RS2(venqimm1);
  18   DEFINE_RS1_RS2(venqimm2);
  19   DEFINE_RS1_RS2(venqcnt);
  20
  21   DEFINE_VEC_XMEM(vld);
  22   DEFINE_VEC_XMEM(vlw);
  23   DEFINE_VEC_XMEM(vlwu);
  24   DEFINE_VEC_XMEM(vlh);
  25   DEFINE_VEC_XMEM(vlhu);
  26   DEFINE_VEC_XMEM(vlb);
  27   DEFINE_VEC_XMEM(vlbu);
  28   DEFINE_VEC_FMEM(vfld);
  29   DEFINE_VEC_FMEM(vflw);
  30   DEFINE_VEC_XMEMST(vlstd);
  31   DEFINE_VEC_XMEMST(vlstw);
  32   DEFINE_VEC_XMEMST(vlstwu);
  33   DEFINE_VEC_XMEMST(vlsth);
  34   DEFINE_VEC_XMEMST(vlsthu);
  35   DEFINE_VEC_XMEMST(vlstb);
  36   DEFINE_VEC_XMEMST(vlstbu);
  37   DEFINE_VEC_FMEMST(vflstd);
  38   DEFINE_VEC_FMEMST(vflstw);
  39
  40   DEFINE_VEC_XMEM(vsd);
  41   DEFINE_VEC_XMEM(vsw);
  42   DEFINE_VEC_XMEM(vsh);
  43   DEFINE_VEC_XMEM(vsb);
  44   DEFINE_VEC_FMEM(vfsd);
  45   DEFINE_VEC_FMEM(vfsw);
  46   DEFINE_VEC_XMEMST(vsstd);
  47   DEFINE_VEC_XMEMST(vsstw);
  48   DEFINE_VEC_XMEMST(vssth);
  49   DEFINE_VEC_XMEMST(vsstb);
  50   DEFINE_VEC_FMEMST(vfsstd);
  51   DEFINE_VEC_FMEMST(vfsstw);
  52
  53   DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg);
  54   DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg);
  55   DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg);
  56   DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg);
  57   DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg);
  58   DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg);
  59   DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg);
  60   DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg);
  61
  62   DEFINE_RS1_RS2(vvcfg);
  63   DEFINE_RS1_RS2(vtcfg);
  64
  65   DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
  66   DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
  67   DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg);
  68   DISASM_INSN("vf", vf, 0, xrs1_reg, imm);
  69
  70   DEFINE_NOARG(fence_v_l);
  71   DEFINE_NOARG(fence_v_g);
  72 }