projects
/
riscv-isa-sim.git
/ blob
commit
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re
402d6d34cb441d9968fe93baefc1805d10719ec4
[riscv-isa-sim.git]
/
hwacha
/
insns
/
movn.h
1
require_vector
;
2
if
(
RS1
&
0x1
)
RD
=
RS2
;
projects / riscv-isa-sim.git / blob