hyperram_model/hbc_tb.v

   1 // Copyright 2017 Gnarly Grey LLC
   2
   3 // Permission is hereby granted, free of charge, to any person obtaining a
   4 // copy of this software and associated documentation files (the
   5 // "Software"), to deal in the Software without restriction, including
   6 // without limitation the rights to use, copy, modify, merge, publish,
   7 // distribute, sublicense, and/or sell copies of the Software, and to
   8 // permit persons to whom the Software is furnished to do so, subject to
   9 // the following conditions:
  10
  11 // The above copyright notice and this permission notice shall be included
  12 // in all copies or substantial portions of the Software.
  13
  14 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 // OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  16 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  17 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  18 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  19 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  20 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22 `timescale 1ns/1ps
  23
  24 module hbc_tb;
  25
  26 // Inputs
  27         reg i_clk;
  28         reg i_rstn;
  29         reg i_cfg_access;
  30         reg i_mem_valid;
  31         reg [3:0] i_mem_wstrb;
  32         reg [31:0] i_mem_addr;
  33         reg [31:0] i_mem_wdata;
  34
  35         // Outputs
  36         wire o_mem_ready;
  37         wire [31:0] o_mem_rdata;
  38         wire o_csn0;
  39         wire o_csn1;
  40         wire o_clk;
  41         wire o_clkn;
  42         wire o_resetn;
  43
  44         // Bidirs
  45         wire [7:0] io_dq;
  46         wire io_rwds;
  47
  48         reg   [31:0] test_data [0:31];
  49         integer i, k;
  50         integer uint8_addr = 0;
  51         integer uint16_addr = 128;
  52         integer uint32_addr = 256;
  53
  54 hbc_wrapper hbc (
  55     .i_clk(i_clk),
  56     .i_rstn(i_rstn),
  57     .i_cfg_access(i_cfg_access),
  58     .i_mem_valid(i_mem_valid),
  59     .o_mem_ready(o_mem_ready),
  60     .i_mem_wstrb(i_mem_wstrb),
  61     .i_mem_addr(i_mem_addr),
  62     .i_mem_wdata(i_mem_wdata),
  63     .o_mem_rdata(o_mem_rdata),
  64     .o_csn0(o_csn0),
  65     .o_csn1(o_csn1),
  66     .o_clk(o_clk),
  67     .o_clkn(o_clkn),
  68     .io_dq(io_dq),
  69     .io_rwds(io_rwds),
  70     .o_resetn(o_resetn)
  71     );
  72
  73 s27kl0641
  74         #(
  75         .TimingModel("S27KL0641DABHI000"))
  76         hyperram (
  77     .DQ7(io_dq[7]),
  78     .DQ6(io_dq[6]),
  79     .DQ5(io_dq[5]),
  80     .DQ4(io_dq[4]),
  81     .DQ3(io_dq[3]),
  82     .DQ2(io_dq[2]),
  83     .DQ1(io_dq[1]),
  84     .DQ0(io_dq[0]),
  85     .RWDS(io_rwds),
  86     .CSNeg(o_csn0),
  87     .CK(o_clk),
  88     .RESETNeg(o_resetn)
  89     );
  90
  91
  92         initial begin
  93                 // Initialize Inputs
  94                 i_clk = 0;
  95                 i_rstn = 0;
  96                 i_cfg_access = 0;
  97                 i_mem_valid = 0;
  98                 i_mem_wstrb = 0;
  99                 i_mem_addr = 0;
 100                 i_mem_wdata = 0;
 101
 102
 103                 #100;
 104       i_rstn = 1;
 105
 106                 $display("Waiting for device power-up...");
 107                 #160e6;
 108                 $display("Reading the ID/CFG registers");
 109
 110                 i_cfg_access = 1;
 111                 i_mem_valid  = 1;
 112                 i_mem_wstrb  = 0;
 113                 i_mem_addr   = 0;
 114                 #10;
 115                 i_mem_valid  = 0;
 116                 wait(o_mem_ready == 1);
 117                 $display("ID0: 0x%H", o_mem_rdata[15:0]);
 118                 #20;
 119                 i_mem_valid  = 1;
 120                 i_mem_wstrb  = 0;
 121                 i_mem_addr   = 2;
 122                 #10;
 123                 i_mem_valid  = 0;
 124                 wait(o_mem_ready == 1);
 125                 $display("ID1: 0x%H", o_mem_rdata[15:0]);
 126                 #20;
 127                 i_mem_valid  = 1;
 128                 i_mem_wstrb  = 0;
 129                 i_mem_addr   = 2048;
 130                 #10;
 131                 i_mem_valid  = 0;
 132                 wait(o_mem_ready == 1);
 133                 $display("CFG0: 0x%H", o_mem_rdata[15:0]);
 134                 #20;
 135                 i_mem_valid  = 1;
 136                 i_mem_wstrb  = 0;
 137                 i_mem_addr   = 2049;
 138                 #10;
 139                 i_mem_valid  = 0;
 140                 wait(o_mem_ready == 1);
 141                 $display("CFG1: 0x%H", o_mem_rdata[15:0]);
 142                 #20;
 143                 i_cfg_access = 0;
 144                 test_data[0] = 32'hDEADBEEF;
 145                 for(i = 1; i < 32; i = i + 1) begin
 146                         test_data[i] = {test_data[i - 1][27:0], test_data[i - 1][31:28]};
 147                 end
 148                 #20;
 149                 $display("UINT8_t test");
 150                 for(i = 0; i < 32; i = i + 1) begin
 151                         i_mem_wdata = test_data[i];
 152                         i_mem_addr  = uint8_addr + (i << 2);
 153                         for(k = 0; k < 4; k = k + 1) begin
 154                                 i_mem_valid = 1;
 155                                 i_mem_wstrb = (1 << k);
 156                                 #10;
 157                                 i_mem_valid = 0;
 158                                 wait(o_mem_ready == 1);
 159                                 #20;
 160                         end
 161                 end
 162                 #20;
 163                 $display("expected\tread\t\tstatus");
 164                 i_mem_wstrb = 0;
 165                 for(i = 0; i < 32; i = i + 1) begin
 166                         i_mem_addr  = uint8_addr + (i << 2);
 167                         for(k = 0; k < 4; k = k + 1) begin
 168                                 i_mem_valid = 1;
 169                                 #10;
 170                                 i_mem_valid = 0;
 171                                 wait(o_mem_ready == 1);
 172                                 if((o_mem_rdata & (255 << k*8)) == (test_data[i] & (255 << k*8))) begin
 173                                         $display("0x%H\t0x%H\tOK", (test_data[i] & (255 << k*8)), (o_mem_rdata & (255 << k*8)));
 174                                 end else begin
 175                                         $display("0x%H\t0x%H\tFAIL", (test_data[i] & (255 << k*8)), (o_mem_rdata & (255 << k*8)));
 176                                 end
 177                                 #20;
 178                         end
 179                 end
 180                 #20;
 181                 $display("UINT16_t test");
 182                 for(i = 0; i < 32; i = i + 1) begin
 183                         i_mem_wdata = test_data[i];
 184                         i_mem_addr  = uint16_addr + (i << 2);
 185                         for(k = 0; k < 2; k = k + 1) begin
 186                                 i_mem_valid = 1;
 187                                 i_mem_wstrb = (3 << (k*2));
 188                                 #10;
 189                                 i_mem_valid = 0;
 190                                 wait(o_mem_ready == 1);
 191                                 #20;
 192                         end
 193                 end
 194                 #20;
 195                 $display("expected\tread\t\tstatus");
 196                 i_mem_wstrb = 0;
 197                 for(i = 0; i < 32; i = i + 1) begin
 198                         i_mem_addr  = uint8_addr + (i << 2);
 199                         for(k = 0; k < 2; k = k + 1) begin
 200                                 i_mem_valid = 1;
 201                                 #10;
 202                                 i_mem_valid = 0;
 203                                 wait(o_mem_ready == 1);
 204                                 if((o_mem_rdata & (16'hFFFF << k*16)) == (test_data[i] & (16'hFFFF << k*16))) begin
 205                                         $display("0x%H\t0x%H\tOK", (test_data[i] & (16'hFFFF << k*16)), (o_mem_rdata & (16'hFFFF << k*16)));
 206                                 end else begin
 207                                         $display("0x%H\t0x%H\tFAIL", (test_data[i] & (16'hFFFF << k*16)), (o_mem_rdata & (16'hFFFF << k*16)));
 208                                 end
 209                                 #20;
 210                         end
 211                 end
 212                 #20;
 213                 $display("UINT32_t test");
 214                 for(i = 0; i < 32; i = i + 1) begin
 215                         i_mem_wdata = test_data[i];
 216                         i_mem_addr  = uint32_addr + (i << 2);
 217                         i_mem_valid = 1;
 218                         i_mem_wstrb = 15;
 219                         #10;
 220                         i_mem_valid = 0;
 221                         wait(o_mem_ready == 1);
 222                         #20;
 223                 end
 224                 #20;
 225                 $display("expected\tread\t\tstatus");
 226                 i_mem_wstrb = 0;
 227                 for(i = 0; i < 32; i = i + 1) begin
 228                         i_mem_addr  = uint8_addr + (i << 2);
 229                         i_mem_valid = 1;
 230                         #10;
 231                         i_mem_valid = 0;
 232                         wait(o_mem_ready == 1);
 233                         if(o_mem_rdata == test_data[i]) begin
 234                                 $display("0x%H\t0x%H\tOK", (test_data[i]), (o_mem_rdata));
 235                         end else begin
 236                                 $display("0x%H\t0x%H\tFAIL", (test_data[i]), (o_mem_rdata));
 237                         end
 238                         #20;
 239                 end
 240                 #20;
 241                 $stop;
 242         end
 243
 244         always @(*) begin
 245                 i_clk <= #5 ~i_clk;
 246         end
 247
 248   initial
 249     begin
 250       $dumpfile("hypersim.fst");
 251       $dumpvars(0, i_clk);
 252       $dumpvars(0, i_rstn);
 253       $dumpvars(0, o_clk);
 254       $dumpvars(0, o_resetn);
 255       $dumpvars(0, o_csn0);
 256       $dumpvars(0, o_csn1);
 257       $dumpvars(0, io_rwds);
 258       $dumpvars(0, io_dq);
 259       $dumpvars(0, i_cfg_access);
 260       $dumpvars(0, i_mem_valid);
 261       $dumpvars(0, o_mem_ready);
 262       $dumpvars(0, i_mem_wstrb);
 263       $dumpvars(0, i_mem_addr);
 264       $dumpvars(0, i_mem_wdata);
 265       $dumpvars(0, o_mem_rdata);
 266     end
 267
 268 endmodule