hyperram_model/hbc_wrapper.v

   1 // Copyright 2017 Gnarly Grey LLC
   2
   3 // Permission is hereby granted, free of charge, to any person obtaining a
   4 // copy of this software and associated documentation files (the
   5 // "Software"), to deal in the Software without restriction, including
   6 // without limitation the rights to use, copy, modify, merge, publish,
   7 // distribute, sublicense, and/or sell copies of the Software, and to
   8 // permit persons to whom the Software is furnished to do so, subject to
   9 // the following conditions:
  10
  11 // The above copyright notice and this permission notice shall be included
  12 // in all copies or substantial portions of the Software.
  13
  14 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 // OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  16 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  17 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  18 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  19 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  20 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22
  23 module hbc_wrapper
  24         (
  25                 input                   i_clk,
  26                 input                   i_rstn,
  27
  28                 input                   i_cfg_access,
  29                 input           i_mem_valid,
  30                 output          o_mem_ready,
  31                 input  [3:0]    i_mem_wstrb,
  32                 input  [31:0]   i_mem_addr,
  33                 input  [31:0]   i_mem_wdata,
  34                 output [31:0]   o_mem_rdata,
  35
  36                 output          o_csn0,
  37                 output                  o_csn1,
  38                 output          o_clk,
  39                 output          o_clkn,
  40                 inout  [7:0]    io_dq,
  41                 inout           io_rwds,
  42                 output          o_resetn
  43         );
  44
  45
  46 wire    [7:0]   dq_i;
  47 wire    [7:0]   dq_o;
  48 wire                    dq_de;
  49 wire                    rwds_i;
  50 wire                    rwds_de;
  51 wire                    rwds_o;
  52
  53 hbc u_hbc
  54         (
  55                 .i_clk(i_clk),
  56                 .i_rstn(i_rstn),
  57
  58                 .i_cfg_access(i_cfg_access),
  59                 .i_mem_valid(i_mem_valid),
  60                 .o_mem_ready(o_mem_ready),
  61                 .i_mem_wstrb(i_mem_wstrb),
  62                 .i_mem_addr(i_mem_addr),
  63                 .i_mem_wdata(i_mem_wdata),
  64                 .o_mem_rdata(o_mem_rdata),
  65
  66                 .o_csn0(o_csn0),
  67                 .o_csn1(o_csn1),
  68                 .o_clk(o_clk),
  69                 .o_clkn(o_clkn),
  70                 .o_dq(dq_o),
  71                 .i_dq(dq_i),
  72                 .o_dq_de(dq_de),
  73                 .o_rwds(rwds_o),
  74                 .i_rwds(rwds_i),
  75                 .o_rwds_de(rwds_de),
  76                 .o_resetn(o_resetn)
  77         );
  78
  79 hbc_io u_hbc_io
  80         (
  81                 .RWDS_i(rwds_i),
  82         .RWDS_de(rwds_de),
  83         .RWDS_o(rwds_o),
  84         .DQ_de(dq_de),
  85         .DQ_i(dq_i),
  86                         .DQ_o(dq_o),
  87                         .RWDS(io_rwds),
  88         .DQ(io_dq)
  89         );
  90
  91 endmodule