icache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity icache_tb is
   9 end icache_tb;
  10
  11 architecture behave of icache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal i_out        : Fetch1ToIcacheType;
  16     signal i_in         : IcacheToDecode1Type;
  17
  18     signal m_out        : MmuToIcacheType;
  19
  20     signal wb_bram_in   : wishbone_master_out;
  21     signal wb_bram_out  : wishbone_slave_out;
  22
  23     constant clk_period : time := 10 ns;
  24 begin
  25     icache0: entity work.icache
  26         generic map(
  27             LINE_SIZE => 64,
  28             NUM_LINES => 4
  29             )
  30         port map(
  31             clk => clk,
  32             rst => rst,
  33             i_in => i_out,
  34             i_out => i_in,
  35             m_in => m_out,
  36             stall_in => '0',
  37             flush_in => '0',
  38             inval_in => '0',
  39             wishbone_out => wb_bram_in,
  40             wishbone_in => wb_bram_out
  41             );
  42
  43     -- BRAM Memory slave
  44     bram0: entity work.wishbone_bram_wrapper
  45         generic map(
  46             MEMORY_SIZE   => 1024,
  47             RAM_INIT_FILE => "icache_test.bin"
  48             )
  49         port map(
  50             clk => clk,
  51             rst => rst,
  52             wishbone_in => wb_bram_in,
  53             wishbone_out => wb_bram_out
  54             );
  55
  56     clk_process: process
  57     begin
  58         clk <= '0';
  59         wait for clk_period/2;
  60         clk <= '1';
  61         wait for clk_period/2;
  62     end process;
  63
  64     rst_process: process
  65     begin
  66         rst <= '1';
  67         wait for 2*clk_period;
  68         rst <= '0';
  69         wait;
  70     end process;
  71
  72     stim: process
  73     begin
  74         i_out.req <= '0';
  75         i_out.nia <= (others => '0');
  76         i_out.stop_mark <= '0';
  77         i_out.priv_mode <= '1';
  78         i_out.virt_mode <= '0';
  79         i_out.big_endian <= '0';
  80
  81         m_out.tlbld <= '0';
  82         m_out.tlbie <= '0';
  83         m_out.addr <= (others => '0');
  84         m_out.pte <= (others => '0');
  85
  86         wait until rising_edge(clk);
  87         wait until rising_edge(clk);
  88         wait until rising_edge(clk);
  89         wait until rising_edge(clk);
  90
  91         i_out.req <= '1';
  92         i_out.nia <= x"0000000000000004";
  93
  94         wait for 30*clk_period;
  95         wait until rising_edge(clk);
  96
  97         assert i_in.valid = '1' severity failure;
  98         assert i_in.insn = x"00000001"
  99             report "insn @" & to_hstring(i_out.nia) &
 100             "=" & to_hstring(i_in.insn) &
 101             " expected 00000001"
 102             severity failure;
 103
 104         i_out.req <= '0';
 105
 106         wait until rising_edge(clk);
 107
 108         -- hit
 109         i_out.req <= '1';
 110         i_out.nia <= x"0000000000000008";
 111         wait until rising_edge(clk);
 112         wait until rising_edge(clk);
 113         assert i_in.valid = '1' severity failure;
 114         assert i_in.insn = x"00000002"
 115             report "insn @" & to_hstring(i_out.nia) &
 116             "=" & to_hstring(i_in.insn) &
 117             " expected 00000002"
 118             severity failure;
 119         wait until rising_edge(clk);
 120
 121         -- another miss
 122         i_out.req <= '1';
 123         i_out.nia <= x"0000000000000040";
 124
 125         wait for 30*clk_period;
 126         wait until rising_edge(clk);
 127
 128         assert i_in.valid = '1' severity failure;
 129         assert i_in.insn = x"00000010"
 130             report "insn @" & to_hstring(i_out.nia) &
 131             "=" & to_hstring(i_in.insn) &
 132             " expected 00000010"
 133             severity failure;
 134
 135         -- test something that aliases
 136         i_out.req <= '1';
 137         i_out.nia <= x"0000000000000100";
 138         wait until rising_edge(clk);
 139         wait until rising_edge(clk);
 140         assert i_in.valid = '0' severity failure;
 141         wait until rising_edge(clk);
 142
 143         wait for 30*clk_period;
 144         wait until rising_edge(clk);
 145
 146         assert i_in.valid = '1' severity failure;
 147         assert i_in.insn = x"00000040"
 148             report "insn @" & to_hstring(i_out.nia) &
 149             "=" & to_hstring(i_in.insn) &
 150             " expected 00000040"
 151             severity failure;
 152
 153         i_out.req <= '0';
 154
 155         std.env.finish;
 156     end process;
 157 end;