isa/macros/vector/test_macros.h

   1 #ifndef __TEST_MACROS_VECTOR_H
   2 #define __TEST_MACROS_VECTOR_H
   3
   4
   5 #-----------------------------------------------------------------------
   6 # Helper macros
   7 #-----------------------------------------------------------------------
   8
   9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  10   TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
  11
  12 # We use j fail, because for some cases branches are not enough to jump to fail
  13
  14 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
  15 test_ ## testnum: \
  16   vsetcfg nxreg,nfreg; \
  17   li a3,2048; \
  18   vsetvl a3,a3; \
  19   lui a0,%hi(vtcode ## testnum ); \
  20   vf %lo(vtcode ## testnum )(a0); \
  21   la a4,dst; \
  22   vsd v ## testreg, a4; \
  23   fence; \
  24   li a1,correctval; \
  25   li a2,0; \
  26   li x28, testnum; \
  27 test_loop ## testnum: \
  28   ld a0,0(a4); \
  29   beq a0,a1,skip ## testnum; \
  30   j fail; \
  31 skip ## testnum : \
  32   addi a4,a4,8; \
  33   addi a2,a2,1; \
  34   bne a2,a3,test_loop ## testnum; \
  35   j next ## testnum; \
  36 vtcode ## testnum : \
  37   code; \
  38   stop; \
  39 next ## testnum :
  40
  41 # We use a macro hack to simpify code generation for various numbers
  42 # of bubble cycles.
  43
  44 #define TEST_INSERT_NOPS_0
  45 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  46 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  47 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  48 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  49 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  50 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  51 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  52 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  53 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  54 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  55
  56
  57 #-----------------------------------------------------------------------
  58 # RV64UI MACROS
  59 #-----------------------------------------------------------------------
  60
  61 #-----------------------------------------------------------------------
  62 # Tests for instructions with immediate operand
  63 #-----------------------------------------------------------------------
  64
  65 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  66     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  67       li  x1, val1; \
  68       inst x3, x1, imm; \
  69     )
  70
  71 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  72     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  73       li  x1, val1; \
  74       inst x1, x1, imm; \
  75     )
  76
  77 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  78     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
  79       li  x1, val1; \
  80       inst x3, x1, imm; \
  81       TEST_INSERT_NOPS_ ## nop_cycles \
  82       addi  x4, x3, 0; \
  83     )
  84
  85 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  86     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  87       li  x1, val1; \
  88       TEST_INSERT_NOPS_ ## nop_cycles \
  89       inst x3, x1, imm; \
  90     )
  91
  92 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  93     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  94       inst x1, x0, imm; \
  95     )
  96
  97 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
  98     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
  99       li  x1, val1; \
 100       inst x0, x1, imm; \
 101     )
 102
 103 #-----------------------------------------------------------------------
 104 # Tests for an instruction with register operands
 105 #-----------------------------------------------------------------------
 106
 107 #define TEST_R_OP( testnum, inst, result, val1 ) \
 108     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 109       li  x1, val1; \
 110       inst x3, x1; \
 111     )
 112
 113 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 114     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 115       li  x1, val1; \
 116       inst x1, x1; \
 117     )
 118
 119 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 120     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 121       li  x1, val1; \
 122       inst x3, x1; \
 123       TEST_INSERT_NOPS_ ## nop_cycles \
 124       addi  x4, x3, 0; \
 125     )
 126
 127 #-----------------------------------------------------------------------
 128 # Tests for an instruction with register-register operands
 129 #-----------------------------------------------------------------------
 130
 131 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 132     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 133       li  x1, val1; \
 134       li  x2, val2; \
 135       inst x3, x1, x2; \
 136     )
 137
 138 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 139     TEST_CASE_NREG( testnum, 3, 0, x1, result, \
 140       li  x1, val1; \
 141       li  x2, val2; \
 142       inst x1, x1, x2; \
 143     )
 144
 145 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 146     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 147       li  x1, val1; \
 148       li  x2, val2; \
 149       inst x2, x1, x2; \
 150     )
 151
 152 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 153     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 154       li  x1, val1; \
 155       inst x1, x1, x1; \
 156     )
 157
 158 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 159     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 160       li  x1, val1; \
 161       li  x2, val2; \
 162       inst x3, x1, x2; \
 163       TEST_INSERT_NOPS_ ## nop_cycles \
 164       addi  x4, x3, 0; \
 165     )
 166
 167 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 168     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 169       li  x1, val1; \
 170       TEST_INSERT_NOPS_ ## src1_nops \
 171       li  x2, val2; \
 172       TEST_INSERT_NOPS_ ## src2_nops \
 173       inst x3, x1, x2; \
 174     )
 175
 176 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 177     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 178       li  x2, val2; \
 179       TEST_INSERT_NOPS_ ## src1_nops \
 180       li  x1, val1; \
 181       TEST_INSERT_NOPS_ ## src2_nops \
 182       inst x3, x1, x2; \
 183     )
 184
 185 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 186     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 187       li x1, val; \
 188       inst x2, x0, x1; \
 189     )
 190
 191 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 192     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 193       li x1, val; \
 194       inst x2, x1, x0; \
 195     )
 196
 197 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 198     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 199       inst x1, x0, x0; \
 200     )
 201
 202 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 203     TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
 204       li x1, val1; \
 205       li x2, val2; \
 206       inst x0, x1, x2; \
 207     )
 208
 209
 210 #-----------------------------------------------------------------------
 211 # RV64UF MACROS
 212 #-----------------------------------------------------------------------
 213
 214 #-----------------------------------------------------------------------
 215 # Tests floating-point instructions
 216 #-----------------------------------------------------------------------
 217
 218 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 219 test_ ## testnum: \
 220   vsetcfg nxreg,nfreg; \
 221   li a3,2048; \
 222   vsetvl a3,a3; \
 223   la  a5, test_ ## testnum ## _data ;\
 224   vflstw vf0, a5, x0; \
 225   addi a5,a5,4; \
 226   vflstw vf1, a5, x0; \
 227   addi a5,a5,4; \
 228   vflstw vf2, a5, x0; \
 229   addi a5,a5,4; \
 230   lui a0,%hi(vtcode ## testnum ); \
 231   vf %lo(vtcode ## testnum )(a0); \
 232   la a4,dst; \
 233   vsw vx1, a4; \
 234   fence; \
 235   lw  a1, 0(a5); \
 236   li a2, 0; \
 237   li x28, testnum; \
 238 test_loop ## testnum: \
 239   lw a0,0(a4); \
 240   beq a0,a1,skip ## testnum; \
 241   j fail; \
 242 skip ## testnum : \
 243   addi a4,a4,4; \
 244   addi a2,a2,1; \
 245   bne a2,a3,test_loop ## testnum; \
 246   b 1f; \
 247 vtcode ## testnum : \
 248   code; \
 249   stop; \
 250   .align 2; \
 251   test_ ## testnum ## _data: \
 252   .float val1; \
 253   .float val2; \
 254   .float val3; \
 255   .result; \
 256 1:
 257
 258 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 259 test_ ## testnum: \
 260   vsetcfg nxreg,nfreg; \
 261   li a3,2048; \
 262   vsetvl a3,a3; \
 263   la  a5, test_ ## testnum ## _data ;\
 264   vflstd vf0, a5, x0; \
 265   addi a5,a5,8; \
 266   vflstd vf1, a5, x0; \
 267   addi a5,a5,8; \
 268   vflstd vf2, a5, x0; \
 269   addi a5,a5,8; \
 270   lui a0,%hi(vtcode ## testnum ); \
 271   vf %lo(vtcode ## testnum )(a0); \
 272   la a4,dst; \
 273   vsd vx1, a4; \
 274   fence; \
 275   ld  a1, 0(a5); \
 276   li a2, 0; \
 277   li x28, testnum; \
 278 test_loop ## testnum: \
 279   ld a0,0(a4); \
 280   beq a0,a1,skip ## testnum; \
 281   j fail; \
 282 skip ## testnum : \
 283   addi a4,a4,8; \
 284   addi a2,a2,1; \
 285   bne a2,a3,test_loop ## testnum; \
 286   b 1f; \
 287 vtcode ## testnum : \
 288   code; \
 289   stop; \
 290   .align 3; \
 291   test_ ## testnum ## _data: \
 292   .double val1; \
 293   .double val2; \
 294   .double val3; \
 295   .result; \
 296 1:
 297
 298 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 299   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
 300                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d x1, f3)
 301
 302 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 303   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
 304                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
 305
 306 #define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
 307   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
 308                     inst f3, f0, f1; fmv.x.s x1, f3)
 309
 310 #define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
 311   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
 312                     inst f3, f0, f1; fmv.x.d x1, f3)
 313
 314 #define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
 315   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
 316                     inst f3, f0, f1, f2; fmv.x.s x1, f3)
 317
 318 #define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
 319   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
 320                     inst f3, f0, f1, f2; fmv.x.d x1, f3)
 321
 322 #define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
 323   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
 324                     inst x1, f0, rm)
 325
 326 #define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
 327   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
 328                     inst x1, f0, rm)
 329
 330 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 331   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
 332                     inst x1, f0, f1)
 333
 334 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 335   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
 336                     inst x1, f0, f1)
 337
 338 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 339 test_ ## testnum: \
 340   vsetcfg 2,1; \
 341   li a3,2048; \
 342   vsetvl a3,a3; \
 343   lui a0,%hi(vtcode ## testnum ); \
 344   vf %lo(vtcode ## testnum )(a0); \
 345   la a4,dst; \
 346   vsw vx1, a4; \
 347   fence; \
 348   la  a5, test_ ## testnum ## _data ;\
 349   lw  a1, 0(a5); \
 350   li a2, 0; \
 351   li x28, testnum; \
 352 test_loop ## testnum: \
 353   lw a0,0(a4); \
 354   beq a0,a1,skip ## testnum; \
 355   j fail; \
 356 skip ## testnum : \
 357   addi a4,a4,4; \
 358   addi a2,a2,1; \
 359   bne a2,a3,test_loop ## testnum; \
 360   b 1f; \
 361 vtcode ## testnum : \
 362   li x1, val1; \
 363   inst f0, x1; \
 364   fmv.x.s x1, f0; \
 365   stop; \
 366   .align 2; \
 367   test_ ## testnum ## _data: \
 368   .float result; \
 369 1:
 370
 371 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 372 test_ ## testnum: \
 373   vsetcfg 2,1; \
 374   li a3,2048; \
 375   vsetvl a3,a3; \
 376   lui a0,%hi(vtcode ## testnum ); \
 377   vf %lo(vtcode ## testnum )(a0); \
 378   la a4,dst; \
 379   vsd vx1, a4; \
 380   fence; \
 381   la  a5, test_ ## testnum ## _data ;\
 382   ld  a1, 0(a5); \
 383   li a2, 0; \
 384   li x28, testnum; \
 385 test_loop ## testnum: \
 386   ld a0,0(a4); \
 387   beq a0,a1,skip ## testnum; \
 388   j fail; \
 389 skip ## testnum : \
 390   addi a4,a4,8; \
 391   addi a2,a2,1; \
 392   bne a2,a3,test_loop ## testnum; \
 393   b 1f; \
 394 vtcode ## testnum : \
 395   li x1, val1; \
 396   inst f0, x1; \
 397   fmv.x.d x1, f0; \
 398   stop; \
 399   .align 3; \
 400   test_ ## testnum ## _data: \
 401   .double result; \
 402 1:
 403
 404
 405 #-----------------------------------------------------------------------
 406 # RV64UV MACROS
 407 #-----------------------------------------------------------------------
 408
 409 #-----------------------------------------------------------------------
 410 # Test branch instructions
 411 #-----------------------------------------------------------------------
 412
 413 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
 414     TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 415       li x1, val1; \
 416       li x2, val2; \
 417       add x3, x0, x0; \
 418       inst x1, x2, 2f; \
 419       addi x3, x3, 1; \
 420 1:    j 3f; \
 421       addi x3, x3, 4; \
 422 2:    inst x1, x2, 1b; \
 423       addi x3, x3, 2; \
 424 3: \
 425     )
 426
 427 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 428   TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 429     li  x1, val1; \
 430     li  x2, val2; \
 431     add x3, x0, x0; \
 432     inst x1, x2, 1f; \
 433     j 2f; \
 434 1:  addi x3, x3, 1; \
 435     j 3f; \
 436 2:  inst x1, x2, 1b; \
 437 3: \
 438                   )
 439
 440 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 441   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 442     add x3, x0, x0; \
 443     li  x4, 0; \
 444 1:  li  x1, val1; \
 445     TEST_INSERT_NOPS_ ## src1_nops \
 446     li  x2, val2; \
 447     TEST_INSERT_NOPS_ ## src2_nops \
 448     inst x1, x2, 2f; \
 449     addi  x4, x4, 1; \
 450     li  x5, 2; \
 451     bne x4, x5, 1b; \
 452     j 3f; \
 453 2:  add x3, x3, 1; \
 454 3:  \
 455   )
 456
 457 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 458   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 459     add x3, x0, x0; \
 460     li  x4, 0; \
 461 1:  li  x2, val2; \
 462     TEST_INSERT_NOPS_ ## src1_nops \
 463     li  x1, val1; \
 464     TEST_INSERT_NOPS_ ## src2_nops \
 465     inst x1, x2, 2f; \
 466     addi  x4, x4, 1; \
 467     li  x5, 2; \
 468     bne x4, x4, 1b; \
 469     j 3f; \
 470 2:  add x3, x3, 1; \
 471 3: \
 472                   )
 473
 474 #define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...)   \
 475   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 476     utidx x1; \
 477     andi x2, x1, 1;\
 478     add x3, x0, x0; \
 479     li x4, n; \
 480 1: \
 481     beq x0, x2, 2f; \
 482     code; \
 483     j 3f; \
 484 2: \
 485     code; \
 486 3: \
 487     addi x4, x4, -1; \
 488     bne x4, x0, 1b; \
 489                   )
 490
 491 #define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... )    \
 492   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 493     utidx x1; \
 494     sltiu x2, x1, 1; \
 495     add x3, x0, x0; \
 496     li x4, n; \
 497 1: \
 498     inst x2, x4, 2f; \
 499     addi x1, x1, -1; \
 500     sltiu x2, x1, 1; \
 501     j 1b; \
 502 2: \
 503     code; \
 504                  )
 505
 506 #define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... )    \
 507   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 508     utidx x1; \
 509     sltiu x2, x1, 1; \
 510     add x3, x0, x0; \
 511     li x4, n; \
 512 1: \
 513     inst x4, x2, 2f; \
 514     addi x1, x1, -1; \
 515     sltiu x2, x1, 1; \
 516     j 1b; \
 517 2: \
 518     code; \
 519                  )
 520
 521 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
 522 test_ ## testnum: \
 523   vsetcfg nxreg,nfreg; \
 524   li a3,2048; \
 525   vsetvl a3,a3; \
 526   lui a0,%hi(vtcode ## testnum ); \
 527   vf %lo(vtcode ## testnum )(a0); \
 528   la a4,dst; \
 529   fence; \
 530   li a1,correctval; \
 531   li a2,0; \
 532   li x28, testnum; \
 533 test_loop ## testnum: \
 534   ld a0,0(a4); \
 535   beq a0,a1,skip ## testnum; \
 536   j fail; \
 537 skip ## testnum : \
 538   addi a4,a4,8; \
 539   addi a2,a2,1; \
 540   bne a2,a3,test_loop ## testnum; \
 541   j next ## testnum; \
 542 vtcode ## testnum : \
 543   code; \
 544   stop; \
 545 next ## testnum :
 546
 547 #define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
 548   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 549     utidx x5; \
 550     slli x5, x5, 3; \
 551     la x6, dst; \
 552     add x5, x5, x6; \
 553     sd x0, 0(x5); \
 554     utidx x1; \
 555     sltiu x2, x1, 1; \
 556     li x4, n; \
 557 1: \
 558     inst x2, x4, 2f; \
 559     addi x1, x1, -1; \
 560     sltiu x2, x1, 1; \
 561     j 1b; \
 562 2: \
 563     ld x3, 0(x5); \
 564     addi x3, x3, 1; \
 565     sd x3, 0(x5); \
 566                  )
 567
 568 #define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
 569   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 570     utidx x5; \
 571     slli x5, x5, 3; \
 572     la x6, dst; \
 573     add x5, x5, x6; \
 574     sd x0, 0(x5); \
 575     utidx x1; \
 576     sltiu x2, x1, 1; \
 577     li x4, n; \
 578 1: \
 579     inst x4, x2, 2f; \
 580     addi x1, x1, -1; \
 581     sltiu x2, x1, 1; \
 582     j 1b; \
 583 2: \
 584     ld x3, 0(x5); \
 585     addi x3, x3, 1; \
 586     sd x3, 0(x5); \
 587                  )
 588
 589 #-----------------------------------------------------------------------
 590 # Pass and fail code (assumes test num is in x28)
 591 #-----------------------------------------------------------------------
 592
 593 #define TEST_PASSFAIL \
 594         bne x0, x28, pass; \
 595 fail: \
 596         RVTEST_FAIL \
 597 pass: \
 598         RVTEST_PASS \
 599
 600
 601 #-----------------------------------------------------------------------
 602 # Test data section
 603 #-----------------------------------------------------------------------
 604
 605 #define TEST_DATA \
 606         .data; \
 607         .align 3; \
 608 dst: \
 609         .skip 16384; \
 610
 611 #endif