isa/rv64mi/breakpoint.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # breakpoint.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test breakpoints, if they are implemented.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Set up breakpoint to trap on M-mode fetches.
  17   li TESTNUM, 2
  18
  19   # Skip tdrselect is hard-wired.
  20   li a0, 1<<(_RISCV_SZLONG-1)
  21   csrw tdrselect, a0
  22   csrr a1, tdrselect
  23   bne a0, a1, pass
  24
  25   # Make sure there's a breakpoint there.
  26   csrr a0, tdrdata1
  27   srli a0, a0, _RISCV_SZLONG-4
  28   li a1, 1
  29   bne a0, a1, pass
  30
  31   la a2, 1f
  32   csrw tdrdata2, a2
  33   li a0, BPCONTROL_M | BPCONTROL_X
  34   csrw tdrdata1, a0
  35   # Skip if breakpoint type is unsupported.
  36   csrr a1, tdrdata1
  37   andi a1, a1, 0x7ff
  38   bne a0, a1, 2f
  39 1:
  40   # Trap handler should skip this instruction.
  41   j fail
  42
  43   # Make sure reads don't trap.
  44   li TESTNUM, 3
  45   lw a0, (a2)
  46
  47 2:
  48   # Set up breakpoint to trap on M-mode reads.
  49   li TESTNUM, 4
  50   li a0, BPCONTROL_M | BPCONTROL_R
  51   csrw tdrdata1, a0
  52   # Skip if breakpoint type is unsupported.
  53   csrr a1, tdrdata1
  54   andi a1, a1, 0x7ff
  55   bne a0, a1, 2f
  56   la a2, data1
  57   csrw tdrdata2, a2
  58
  59   # Trap handler should skip this instruction.
  60   lw a2, (a2)
  61   beqz a2, fail
  62
  63   # Make sure writes don't trap.
  64   li TESTNUM, 5
  65   sw x0, (a2)
  66
  67 2:
  68   # Set up breakpoint to trap on M-mode stores.
  69   li TESTNUM, 6
  70   li a0, BPCONTROL_M | BPCONTROL_W
  71   csrw tdrdata1, a0
  72   # Skip if breakpoint type is unsupported.
  73   csrr a1, tdrdata1
  74   andi a1, a1, 0x7ff
  75   bne a0, a1, 2f
  76
  77   # Trap handler should skip this instruction.
  78   sw a2, (a2)
  79
  80   # Make sure store didn't succeed.
  81   li TESTNUM, 7
  82   lw a2, (a2)
  83   bnez a2, fail
  84
  85   # Try to set up a second breakpoint.
  86   li a0, (1<<(_RISCV_SZLONG-1)) + 1
  87   csrw tdrselect, a0
  88   csrr a1, tdrselect
  89   bne a0, a1, pass
  90   li a0, BPCONTROL_M | BPCONTROL_R
  91   csrw tdrdata1, a0
  92   la a3, data2
  93   csrw tdrdata2, a3
  94
  95   # Make sure the second breakpoint triggers.
  96   li TESTNUM, 8
  97   lw a3, (a3)
  98   beqz a3, fail
  99
 100   # Make sure the first breakpoint still triggers.
 101   li TESTNUM, 10
 102   la a2, data1
 103   sw a2, (a2)
 104   li TESTNUM, 11
 105   lw a2, (a2)
 106   bnez a2, fail
 107
 108 2:
 109   TEST_PASSFAIL
 110
 111 mtvec_handler:
 112   # Only even-numbered tests should trap.
 113   andi t0, TESTNUM, 1
 114   bnez t0, fail
 115
 116   li t0, CAUSE_BREAKPOINT
 117   csrr t1, mcause
 118   bne t0, t1, fail
 119
 120   csrr t0, mepc
 121   addi t0, t0, 4
 122   csrw mepc, t0
 123   mret
 124
 125 RVTEST_CODE_END
 126
 127   .data
 128 RVTEST_DATA_BEGIN
 129
 130   TEST_DATA
 131
 132 data1: .word 0
 133 data2: .word 0
 134
 135 RVTEST_DATA_END