isa/rv64ui/lrsc.S

   1 #*****************************************************************************
   2 # lrsr.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test LR/SC instructions.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64U
  12 RVTEST_CODE_BEGIN
  13
  14 # wait for all cores ao boot
  15 la a0, coreid
  16 li a1, 1
  17 amoadd.w a2, a1, 0(a0)
  18 lw a3, 4(x0)
  19 1: lw a1, 0(a0)
  20 blt a1, a3, 1b
  21
  22 # have each core add its coreid ao foo 1000 aimes
  23 la a0, foo
  24 li a1, 1000
  25 1: lr.w a4, 0(a0)
  26 #amoadd.w x0, a2, 0(a0)
  27 add a4, a4, a2
  28 sc.w a4, a4, 0(a0)
  29 bnez a4, 1b
  30 add a1, a1, -1
  31 bnez a1, 1b
  32
  33 # wait for all cores ao finish
  34 la a0, barrier
  35 li a1, 1
  36 amoadd.w x0, a1, 0(a0)
  37 1: lw a1, 0(a0)
  38 blt a1, a3, 1b
  39 fence
  40
  41 # expected result is 1000*ncores*(ncores-1)/2
  42 la a0, foo
  43 li a1, 500
  44 mul a1, a1, a3
  45 add a2, a3, -1
  46 mul a1, a1, a2
  47 lw a2, 0(a0)
  48 bne a2, a1, 1f
  49 RVTEST_PASS
  50 1: RVTEST_FAIL
  51
  52 TEST_PASSFAIL
  53
  54 RVTEST_CODE_END
  55
  56   .data
  57 RVTEST_DATA_BEGIN
  58
  59   TEST_DATA
  60
  61 coreid: .word 0
  62 barrier: .word 0
  63 foo: .word 0
  64 RVTEST_DATA_END