Benchmarks now run in user-mode.
[riscv-tests.git] / isa / rv64uv / fsw.S
1 #*****************************************************************************
2 # fsw.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test fsw instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a4,2048
15 vvcfgivl a4,a4,4,1
16
17 la a5,src
18 vflw vf0,a5
19 la a6,dest
20 vmsv vx2,a6
21 lui a0,%hi(vtcode)
22 vf %lo(vtcode)(a0)
23 fence.v.l
24
25 li a2,0
26 loop:
27 lw a0,0(a6)
28 addi x28,a2,2
29 lw a1,0(a5)
30 bne a0,a1,fail
31 addi a6,a6,4
32 addi a5,a5,4
33 addi a2,a2,1
34 bne a2,a4,loop
35 j pass
36
37 vtcode:
38 utidx x3
39 slli x3,x3,2
40 add x2,x2,x3
41 fsw f0,0(x2)
42 stop
43
44 TEST_PASSFAIL
45
46 RVTEST_CODE_END
47
48 .data
49 RVTEST_DATA_BEGIN
50
51 TEST_DATA
52
53 src:
54 #include "data_fw.h"
55
56 dest:
57 .skip 16384
58
59 RVTEST_DATA_END