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[riscv-tests.git] / isa / rv64uv / imul.S
1 #*****************************************************************************
2 # imul.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test imul instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a3,2048
15 vvcfgivl a3,a3,3,0
16
17 li a4,20
18 li s0,2
19 vmsv vx1,a4
20 lui a0,%hi(vtcode)
21 vf %lo(vtcode)(a0)
22
23 nop
24 nop
25 nop
26 nop
27 nop
28 nop
29 nop
30 nop
31 nop
32 nop
33 nop
34 nop
35 nop
36 nop
37 nop
38 nop
39 nop
40 nop
41 nop
42 nop
43 mul s1,a4,s0
44
45 la a5,dest
46 vsd vx1,a5
47 fence.v.l
48
49 li s2,40
50 li x28,2
51 bne s1,s2,fail
52
53 li a1,0
54 li a2,0
55 loop:
56 ld a0,0(a5)
57 addi x28,a2,3
58 bne a0,a1,fail
59 addi a5,a5,8
60 addi a1,a1,20
61 addi a2,a2,1
62 bne a2,a3,loop
63 j pass
64
65 vtcode:
66 utidx x2
67 mul x1,x2,x1
68 stop
69
70 TEST_PASSFAIL
71
72 RVTEST_CODE_END
73
74 .data
75 RVTEST_DATA_BEGIN
76
77 TEST_DATA
78
79 dest:
80 .skip 16384
81
82 RVTEST_DATA_END