initial commit
[riscv-tests.git] / isa / rv64uv / utidx.S
1 #*****************************************************************************
2 # utidx.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test utidx instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a2,2048
15 vvcfgivl a2,a2,2,0
16
17 lui a0,%hi(vtcode)
18 vf %lo(vtcode)(a0)
19 la a4,dest
20 vsd vx1,a4
21 fence.v.l
22
23 li a1,1
24 loop:
25 ld a0,0(a4)
26 addi x28,a1,2
27 bne a0,a1,fail
28 addi a4,a4,8
29 addi a1,a1,1
30 bne a1,a2,loop
31 j pass
32
33 vtcode:
34 utidx x1
35 addi x1,x1,1
36 stop
37
38 TEST_PASSFAIL
39
40 RVTEST_CODE_END
41
42 .data
43 RVTEST_DATA_BEGIN
44
45 TEST_DATA
46
47 dest:
48 .skip 16384
49
50 RVTEST_DATA_END