jtag_tap.c

   1 /**
   2  * Code adapted from Arduino-JTAG;
   3  *    portions copyright (c) 2015 Marcelo Roberto Jimenez <marcelo.jimenez (at) gmail (dot) com>.
   4  *    portions copyright (c) 2019 Katherine J. Temkin <kate@ktemkin.com>
   5  *    portions copyright (c) 2019 Great Scott Gadgets <ktemkin@greatscottgadgets.com>
   6  */
   7
   8 #include <ftdi.h>
   9 #include <stdio.h>
  10 #include <stdint.h>
  11 #include <stdbool.h>
  12 #include <stdlib.h>
  13 #include <unistd.h>
  14
  15 #include "mpsse.h"
  16 #include "jtag.h"
  17
  18 void jtag_state_ack(bool tms);
  19
  20 /*
  21  * Low nibble : TMS == 0
  22  * High nibble: TMS == 1
  23  */
  24
  25 #define TMS_T(TMS_HIGH_STATE, TMS_LOW_STATE) (((TMS_HIGH_STATE) << 4) | (TMS_LOW_STATE))
  26
  27 static const uint8_t tms_transitions[] = {
  28         /* STATE_TEST_LOGIC_RESET */ TMS_T(STATE_TEST_LOGIC_RESET, STATE_RUN_TEST_IDLE),
  29         /* STATE_RUN_TEST_IDLE    */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  30         /* STATE_SELECT_DR_SCAN   */ TMS_T(STATE_SELECT_IR_SCAN,   STATE_CAPTURE_DR),
  31         /* STATE_CAPTURE_DR       */ TMS_T(STATE_EXIT1_DR,         STATE_SHIFT_DR),
  32         /* STATE_SHIFT_DR         */ TMS_T(STATE_EXIT1_DR,         STATE_SHIFT_DR),
  33         /* STATE_EXIT1_DR         */ TMS_T(STATE_UPDATE_DR,        STATE_PAUSE_DR),
  34         /* STATE_PAUSE_DR         */ TMS_T(STATE_EXIT2_DR,         STATE_PAUSE_DR),
  35         /* STATE_EXIT2_DR         */ TMS_T(STATE_UPDATE_DR,        STATE_SHIFT_DR),
  36         /* STATE_UPDATE_DR        */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  37         /* STATE_SELECT_IR_SCAN   */ TMS_T(STATE_TEST_LOGIC_RESET, STATE_CAPTURE_IR),
  38         /* STATE_CAPTURE_IR       */ TMS_T(STATE_EXIT1_IR,         STATE_SHIFT_IR),
  39         /* STATE_SHIFT_IR         */ TMS_T(STATE_EXIT1_IR,         STATE_SHIFT_IR),
  40         /* STATE_EXIT1_IR         */ TMS_T(STATE_UPDATE_IR,        STATE_PAUSE_IR),
  41         /* STATE_PAUSE_IR         */ TMS_T(STATE_EXIT2_IR,         STATE_PAUSE_IR),
  42         /* STATE_EXIT2_IR         */ TMS_T(STATE_UPDATE_IR,        STATE_SHIFT_IR),
  43         /* STATE_UPDATE_IR        */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  44 };
  45
  46 #define BITSTR(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P) ( \
  47         ((uint16_t)(A) << 15) | \
  48         ((uint16_t)(B) << 14) | \
  49         ((uint16_t)(C) << 13) | \
  50         ((uint16_t)(D) << 12) | \
  51         ((uint16_t)(E) << 11) | \
  52         ((uint16_t)(F) << 10) | \
  53         ((uint16_t)(G) <<  9) | \
  54         ((uint16_t)(H) <<  8) | \
  55         ((uint16_t)(I) <<  7) | \
  56         ((uint16_t)(J) <<  6) | \
  57         ((uint16_t)(K) <<  5) | \
  58         ((uint16_t)(L) <<  4) | \
  59         ((uint16_t)(M) <<  3) | \
  60         ((uint16_t)(N) <<  2) | \
  61         ((uint16_t)(O) <<  1) | \
  62         ((uint16_t)(P) <<  0) )
  63
  64 /*
  65  * The index of this vector is the current state. The i-th bit tells you the
  66  * value TMS must assume in order to go to state "i".
  67
  68 ------------------------------------------------------------------------------------------------------------
  69 |                        |   || F | E | D | C || B | A | 9 | 8 || 7 | 6 | 5 | 4 || 3 | 2 | 1 | 0 ||   HEX  |
  70 ------------------------------------------------------------------------------------------------------------
  71 | STATE_TEST_LOGIC_RESET | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 1 || 0x0001 |
  72 | STATE_RUN_TEST_IDLE    | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0xFFFD |
  73 | STATE_SELECT_DR_SCAN   | 2 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || 0 | 0 | 0 | 0 || 0 | x | 1 | 1 || 0xFE03 |
  74 | STATE_CAPTURE_DR       | 3 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || x | 1 | 1 | 1 || 0xFFE7 |
  75 | STATE_SHIFT_DR         | 4 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 || 0xFFEF |
  76 | STATE_EXIT1_DR         | 5 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0 | 0 | x | 0 || 1 | 1 | 1 | 1 || 0xFF0F |
  77 | STATE_PAUSE_DR         | 6 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 0 | 1 | 1 || 1 | 1 | 1 | 1 || 0xFFBF |
  78 | STATE_EXIT2_DR         | 7 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || x | 0 | 0 | 0 || 1 | 1 | 1 | 1 || 0xFF0F |
  79 | STATE_UPDATE_DR        | 8 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | x || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0xFEFD |
  80 | STATE_SELECT_IR_SCAN   | 9 || 0 | 0 | 0 | 0 || 0 | 0 | x | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x01FF |
  81 | STATE_CAPTURE_IR       | A || 1 | 1 | 1 | 1 || 0 | x | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xF3FF |
  82 | STATE_SHIFT_IR         | B || 1 | 1 | 1 | 1 || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xF7FF |
  83 | STATE_EXIT1_IR         | C || 1 | 0 | 0 | x || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x87FF |
  84 | STATE_PAUSE_IR         | D || 1 | 1 | 0 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xDFFF |
  85 | STATE_EXIT2_IR         | E || 1 | x | 0 | 0 || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x87FF |
  86 | STATE_UPDATE_IR        | F || x | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0x7FFD |
  87 ------------------------------------------------------------------------------------------------------------
  88
  89 */
  90 static const uint16_t tms_map[] = {
  91 /* STATE_TEST_LOGIC_RESET */ BITSTR(  0, 0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 1  ),
  92 /* STATE_RUN_TEST_IDLE    */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 0, 1  ),
  93 /* STATE_SELECT_DR_SCAN   */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 0,   0, 0, 0, 0,   0, 0, 1, 1  ),
  94 /* STATE_CAPTURE_DR       */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 0,   0, 1, 1, 1  ),
  95 /* STATE_SHIFT_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 0,   1, 1, 1, 1  ),
  96 /* STATE_EXIT1_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   0, 0, 0, 0,   1, 1, 1, 1  ),
  97 /* STATE_PAUSE_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 0, 1, 1,   1, 1, 1, 1  ),
  98 /* STATE_EXIT2_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   0, 0, 0, 0,   1, 1, 1, 1  ),
  99 /* STATE_UPDATE_DR        */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 0,   1, 1, 1, 1,   1, 1, 0, 1  ),
 100 /* STATE_SELECT_IR_SCAN   */ BITSTR(  0, 0, 0, 0,   0, 0, 0, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 101 /* STATE_CAPTURE_IR       */ BITSTR(  1, 1, 1, 1,   0, 0, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 102 /* STATE_SHIFT_IR         */ BITSTR(  1, 1, 1, 1,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 103 /* STATE_EXIT1_IR         */ BITSTR(  1, 0, 0, 0,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 104 /* STATE_PAUSE_IR         */ BITSTR(  1, 1, 0, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 105 /* STATE_EXIT2_IR         */ BITSTR(  1, 0, 0, 0,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 106 /* STATE_UPDATE_IR        */ BITSTR(  0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 0, 1  ),
 107 };
 108
 109 static uint8_t current_state;
 110
 111 uint8_t jtag_current_state(void)
 112 {
 113         return current_state;
 114 }
 115
 116 void jtag_set_current_state(uint8_t state)
 117 {
 118         current_state = state;
 119 }
 120
 121 void jtag_error(int status){
 122         mpsse_error(status);
 123 }
 124
 125 void jtag_deinit(){
 126         mpsse_close();
 127 }
 128
 129 /**
 130  * Performs any start-of-day tasks necessary to talk JTAG to our FPGA.
 131  */
 132 void jtag_init(int ifnum, const char *devstr, bool slow_clock)
 133 {
 134         mpsse_init(ifnum, devstr, slow_clock);
 135
 136         jtag_set_current_state(STATE_TEST_LOGIC_RESET);
 137     jtag_go_to_state(STATE_TEST_LOGIC_RESET);
 138 }
 139
 140 uint8_t data[32*1024];
 141 uint8_t* ptr;
 142 uint16_t rx_cnt;
 143
 144 extern struct ftdi_context mpsse_ftdic;
 145
 146 static inline void jtag_pulse_clock_and_read_tdo(bool tms, bool tdi)
 147 {
 148     *ptr++ = MC_DATA_TMS | MC_DATA_IN | MC_DATA_LSB | MC_DATA_BITS;
 149         *ptr++ =  0;
 150     *ptr++ = (tdi ? 0x80 : 0) | (tms ? 0x01 : 0);
 151         rx_cnt++;
 152 }
 153
 154 static void _jtag_tap_shift(
 155         uint8_t *input_data,
 156         uint8_t *output_data,
 157         uint32_t data_bits,
 158         bool must_end)
 159 {
 160
 161         //printf("_jtag_tap_shift(0x%08x,0x%08x,%u,%s);\n",input_data, output_data, data_bits, must_end ? "true" : "false");
 162         uint32_t bit_count = data_bits;
 163         uint32_t byte_count = (data_bits + 7) / 8;
 164         rx_cnt = 0;
 165         ptr = data;
 166
 167         for (uint32_t i = 0; i < byte_count; ++i) {
 168                 uint8_t byte_out = input_data[i];
 169                 for (int j = 0; j < 8 && bit_count-- > 0; ++j) {
 170             bool tms = false;
 171                         if (bit_count == 0 && must_end) {
 172                 tms = true;
 173                                 jtag_state_ack(1);
 174                         }
 175                         jtag_pulse_clock_and_read_tdo(tms, byte_out & 1);
 176                         byte_out >>= 1;
 177                 }
 178         }
 179
 180         mpsse_xfer(data, ptr-data, rx_cnt);
 181
 182         /* Data out from the FTDI is actually from an internal shift register
 183          * Instead of reconstructing the bitpattern, we can just take every 8th byte.*/
 184         for(int i = 0; i < rx_cnt/8; i++)
 185                 output_data[i] = data[7+i*8];
 186 }
 187
 188 #define MIN(a,b) (a < b) ? a : b
 189
 190 void jtag_tap_shift(
 191         uint8_t *input_data,
 192         uint8_t *output_data,
 193         uint32_t data_bits,
 194         bool must_end)
 195 {
 196         uint32_t data_bits_sent = 0;
 197         while(data_bits_sent != data_bits){
 198
 199                 uint32_t _data_bits = MIN(256, data_bits);
 200                 bool last = (data_bits_sent + _data_bits) == data_bits;
 201
 202                 _jtag_tap_shift(
 203                         input_data + data_bits_sent/8,
 204                         output_data + data_bits_sent/8,
 205                         _data_bits,
 206                         last & must_end
 207                 );
 208                 data_bits_sent += _data_bits;
 209         }
 210 }
 211
 212 void jtag_state_ack(bool tms)
 213 {
 214         if (tms) {
 215                 jtag_set_current_state((tms_transitions[jtag_current_state()] >> 4) & 0xf);
 216         } else {
 217                 jtag_set_current_state(tms_transitions[jtag_current_state()] & 0xf);
 218         }
 219 }
 220
 221 void jtag_go_to_state(unsigned state)
 222 {
 223
 224         if (state == STATE_TEST_LOGIC_RESET) {
 225                 for (int i = 0; i < 5; ++i) {
 226                         jtag_state_ack(true);
 227                 }
 228
 229                 uint8_t data[3] = {
 230                         MC_DATA_TMS | MC_DATA_LSB | MC_DATA_BITS,
 231                         5 - 1,
 232                         0b11111
 233                 };
 234                 mpsse_xfer(data, 3, 0);
 235
 236         } else {
 237                 while (jtag_current_state() != state) {
 238                         uint8_t data[3] = {
 239                                 MC_DATA_TMS | MC_DATA_LSB | MC_DATA_ICN | MC_DATA_BITS,
 240                                 0,
 241                                 (tms_map[jtag_current_state()] >> state) & 1
 242                         };
 243
 244                         jtag_state_ack((tms_map[jtag_current_state()] >> state) & 1);
 245                         mpsse_xfer(data, 3, 0);
 246                 }
 247         }
 248 }
 249
 250 void jtag_wait_time(uint32_t microseconds)
 251 {
 252         uint16_t bytes = microseconds / 8;
 253         uint8_t remain = microseconds % 8;
 254
 255         uint8_t data[3] = {
 256                 MC_CLK_N8,
 257                 bytes & 0xFF,
 258                 (bytes >> 8) & 0xFF
 259         };
 260         mpsse_xfer(data, 3, 0);
 261
 262         if(remain){
 263                 data[0] = MC_CLK_N;
 264                 data[1] = remain;
 265                 mpsse_xfer(data, 2, 0);
 266         }
 267 }
 268