jtag_tap.c

   1 /**
   2  * Code adapted from Arduino-JTAG;
   3  *    portions copyright (c) 2015 Marcelo Roberto Jimenez <marcelo.jimenez (at) gmail (dot) com>.
   4  *    portions copyright (c) 2019 Katherine J. Temkin <kate@ktemkin.com>
   5  *    portions copyright (c) 2019 Great Scott Gadgets <ktemkin@greatscottgadgets.com>
   6  */
   7
   8 #include <ftdi.h>
   9 #include <stdio.h>
  10 #include <stdint.h>
  11 #include <stdbool.h>
  12 #include <stdlib.h>
  13 #include <unistd.h>
  14
  15 #include "mpsse.h"
  16 #include "jtag.h"
  17
  18 void jtag_state_ack(bool tms);
  19
  20 /*
  21  * Low nibble : TMS == 0
  22  * High nibble: TMS == 1
  23  */
  24
  25 #define TMS_T(TMS_HIGH_STATE, TMS_LOW_STATE) (((TMS_HIGH_STATE) << 4) | (TMS_LOW_STATE))
  26
  27 static const uint8_t tms_transitions[] = {
  28         /* STATE_TEST_LOGIC_RESET */ TMS_T(STATE_TEST_LOGIC_RESET, STATE_RUN_TEST_IDLE),
  29         /* STATE_RUN_TEST_IDLE    */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  30         /* STATE_SELECT_DR_SCAN   */ TMS_T(STATE_SELECT_IR_SCAN,   STATE_CAPTURE_DR),
  31         /* STATE_CAPTURE_DR       */ TMS_T(STATE_EXIT1_DR,         STATE_SHIFT_DR),
  32         /* STATE_SHIFT_DR         */ TMS_T(STATE_EXIT1_DR,         STATE_SHIFT_DR),
  33         /* STATE_EXIT1_DR         */ TMS_T(STATE_UPDATE_DR,        STATE_PAUSE_DR),
  34         /* STATE_PAUSE_DR         */ TMS_T(STATE_EXIT2_DR,         STATE_PAUSE_DR),
  35         /* STATE_EXIT2_DR         */ TMS_T(STATE_UPDATE_DR,        STATE_SHIFT_DR),
  36         /* STATE_UPDATE_DR        */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  37         /* STATE_SELECT_IR_SCAN   */ TMS_T(STATE_TEST_LOGIC_RESET, STATE_CAPTURE_IR),
  38         /* STATE_CAPTURE_IR       */ TMS_T(STATE_EXIT1_IR,         STATE_SHIFT_IR),
  39         /* STATE_SHIFT_IR         */ TMS_T(STATE_EXIT1_IR,         STATE_SHIFT_IR),
  40         /* STATE_EXIT1_IR         */ TMS_T(STATE_UPDATE_IR,        STATE_PAUSE_IR),
  41         /* STATE_PAUSE_IR         */ TMS_T(STATE_EXIT2_IR,         STATE_PAUSE_IR),
  42         /* STATE_EXIT2_IR         */ TMS_T(STATE_UPDATE_IR,        STATE_SHIFT_IR),
  43         /* STATE_UPDATE_IR        */ TMS_T(STATE_SELECT_DR_SCAN,   STATE_RUN_TEST_IDLE),
  44 };
  45
  46 #define BITSTR(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P) ( \
  47         ((uint16_t)(A) << 15) | \
  48         ((uint16_t)(B) << 14) | \
  49         ((uint16_t)(C) << 13) | \
  50         ((uint16_t)(D) << 12) | \
  51         ((uint16_t)(E) << 11) | \
  52         ((uint16_t)(F) << 10) | \
  53         ((uint16_t)(G) <<  9) | \
  54         ((uint16_t)(H) <<  8) | \
  55         ((uint16_t)(I) <<  7) | \
  56         ((uint16_t)(J) <<  6) | \
  57         ((uint16_t)(K) <<  5) | \
  58         ((uint16_t)(L) <<  4) | \
  59         ((uint16_t)(M) <<  3) | \
  60         ((uint16_t)(N) <<  2) | \
  61         ((uint16_t)(O) <<  1) | \
  62         ((uint16_t)(P) <<  0) )
  63
  64 /*
  65  * The index of this vector is the current state. The i-th bit tells you the
  66  * value TMS must assume in order to go to state "i".
  67
  68 ------------------------------------------------------------------------------------------------------------
  69 |                        |   || F | E | D | C || B | A | 9 | 8 || 7 | 6 | 5 | 4 || 3 | 2 | 1 | 0 ||   HEX  |
  70 ------------------------------------------------------------------------------------------------------------
  71 | STATE_TEST_LOGIC_RESET | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 || 0 | 0 | 0 | 1 || 0x0001 |
  72 | STATE_RUN_TEST_IDLE    | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0xFFFD |
  73 | STATE_SELECT_DR_SCAN   | 2 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || 0 | 0 | 0 | 0 || 0 | x | 1 | 1 || 0xFE03 |
  74 | STATE_CAPTURE_DR       | 3 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || x | 1 | 1 | 1 || 0xFFE7 |
  75 | STATE_SHIFT_DR         | 4 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 || 0xFFEF |
  76 | STATE_EXIT1_DR         | 5 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0 | 0 | x | 0 || 1 | 1 | 1 | 1 || 0xFF0F |
  77 | STATE_PAUSE_DR         | 6 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 0 | 1 | 1 || 1 | 1 | 1 | 1 || 0xFFBF |
  78 | STATE_EXIT2_DR         | 7 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || x | 0 | 0 | 0 || 1 | 1 | 1 | 1 || 0xFF0F |
  79 | STATE_UPDATE_DR        | 8 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | x || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0xFEFD |
  80 | STATE_SELECT_IR_SCAN   | 9 || 0 | 0 | 0 | 0 || 0 | 0 | x | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x01FF |
  81 | STATE_CAPTURE_IR       | A || 1 | 1 | 1 | 1 || 0 | x | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xF3FF |
  82 | STATE_SHIFT_IR         | B || 1 | 1 | 1 | 1 || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xF7FF |
  83 | STATE_EXIT1_IR         | C || 1 | 0 | 0 | x || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x87FF |
  84 | STATE_PAUSE_IR         | D || 1 | 1 | 0 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0xDFFF |
  85 | STATE_EXIT2_IR         | E || 1 | x | 0 | 0 || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 0x87FF |
  86 | STATE_UPDATE_IR        | F || x | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 || 1 | 1 | 0 | 1 || 0x7FFD |
  87 ------------------------------------------------------------------------------------------------------------
  88
  89 */
  90 static const uint16_t tms_map[] = {
  91 /* STATE_TEST_LOGIC_RESET */ BITSTR(  0, 0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 1  ),
  92 /* STATE_RUN_TEST_IDLE    */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 0, 1  ),
  93 /* STATE_SELECT_DR_SCAN   */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 0,   0, 0, 0, 0,   0, 0, 1, 1  ),
  94 /* STATE_CAPTURE_DR       */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 0,   0, 1, 1, 1  ),
  95 /* STATE_SHIFT_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 0,   1, 1, 1, 1  ),
  96 /* STATE_EXIT1_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   0, 0, 0, 0,   1, 1, 1, 1  ),
  97 /* STATE_PAUSE_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   1, 0, 1, 1,   1, 1, 1, 1  ),
  98 /* STATE_EXIT2_DR         */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 1,   0, 0, 0, 0,   1, 1, 1, 1  ),
  99 /* STATE_UPDATE_DR        */ BITSTR(  1, 1, 1, 1,   1, 1, 1, 0,   1, 1, 1, 1,   1, 1, 0, 1  ),
 100 /* STATE_SELECT_IR_SCAN   */ BITSTR(  0, 0, 0, 0,   0, 0, 0, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 101 /* STATE_CAPTURE_IR       */ BITSTR(  1, 1, 1, 1,   0, 0, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 102 /* STATE_SHIFT_IR         */ BITSTR(  1, 1, 1, 1,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 103 /* STATE_EXIT1_IR         */ BITSTR(  1, 0, 0, 0,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 104 /* STATE_PAUSE_IR         */ BITSTR(  1, 1, 0, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 105 /* STATE_EXIT2_IR         */ BITSTR(  1, 0, 0, 0,   0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1  ),
 106 /* STATE_UPDATE_IR        */ BITSTR(  0, 1, 1, 1,   1, 1, 1, 1,   1, 1, 1, 1,   1, 1, 0, 1  ),
 107 };
 108
 109 static uint8_t current_state;
 110
 111 uint8_t jtag_current_state(void)
 112 {
 113         return current_state;
 114 }
 115
 116 void jtag_set_current_state(uint8_t state)
 117 {
 118         current_state = state;
 119 }
 120
 121
 122 /**
 123  * Hook for any per-platform initialization that needs to occur.
 124  */
 125 __attribute__((weak)) void jtag_platform_init(void)
 126 {
 127
 128 }
 129
 130
 131 /**
 132  * Performs any start-of-day tasks necessary to talk JTAG to our FPGA.
 133  */
 134 void jtag_init(void)
 135 {
 136         jtag_platform_init();
 137         jtag_set_current_state(STATE_TEST_LOGIC_RESET);
 138     jtag_go_to_state(STATE_TEST_LOGIC_RESET);
 139 }
 140
 141
 142 static inline void jtag_pulse_clock(void)
 143 {
 144         //mpsse_send_byte(MC_CLK_N);
 145         //mpsse_send_byte(0x00);
 146     mpsse_send_byte(MC_DATA_TMS | MC_DATA_IN | MC_DATA_LSB | MC_DATA_BITS);
 147         mpsse_send_byte(0);
 148     mpsse_send_byte(0);
 149 }
 150
 151 static inline uint8_t jtag_pulse_clock_and_read_tdo(bool tms, bool tdi)
 152 {
 153         uint8_t ret;
 154
 155     mpsse_send_byte(MC_DATA_TMS | MC_DATA_IN  | MC_DATA_LSB |  MC_DATA_BITS);
 156         mpsse_send_byte(0);
 157
 158     uint8_t data = 0;
 159     if(tdi)
 160         data |= 0x80;
 161     if(tms)
 162         data |= 0x01;
 163
 164     mpsse_send_byte(data);
 165         ret = mpsse_recv_byte();
 166
 167         return (ret >> 7) & 1;
 168 }
 169
 170
 171 void jtag_tap_shift(
 172         uint8_t *input_data,
 173         uint8_t *output_data,
 174         uint32_t data_bits,
 175         bool must_end)
 176 {
 177
 178         uint32_t bit_count = data_bits;
 179         uint32_t byte_count = (data_bits + 7) / 8;
 180
 181         for (uint32_t i = 0; i < byte_count; ++i) {
 182                 uint8_t byte_out = input_data[i];
 183                 uint8_t tdo_byte = 0;
 184                 for (int j = 0; j < 8 && bit_count-- > 0; ++j) {
 185             bool tms = false;
 186             bool tdi = false;
 187                         if (bit_count == 0 && must_end) {
 188                 tms = true;
 189                                 jtag_state_ack(1);
 190                         }
 191                         if (byte_out & 1) {
 192                                 tdi = true;
 193                         } else {
 194                                 tdi = false;
 195                         }
 196                         byte_out >>= 1;
 197                         bool tdo = jtag_pulse_clock_and_read_tdo(tms, tdi);
 198                         tdo_byte |= tdo << j;
 199                 }
 200                 output_data[i] = tdo_byte;
 201         }
 202 }
 203
 204 void jtag_state_ack(bool tms)
 205 {
 206         if (tms) {
 207                 jtag_set_current_state((tms_transitions[jtag_current_state()] >> 4) & 0xf);
 208         } else {
 209                 jtag_set_current_state(tms_transitions[jtag_current_state()] & 0xf);
 210         }
 211 }
 212
 213 void jtag_state_step(bool tms)
 214 {
 215
 216     //mpsse_send_byte(MC_DATA_TMS | MC_DATA_LSB | MC_DATA_BITS);
 217         //mpsse_send_byte(0);
 218         if (tms) {
 219     //  mpsse_send_byte(1);
 220         } else {
 221     //    mpsse_send_byte(0);
 222         }
 223
 224         jtag_state_ack(tms);
 225 }
 226
 227
 228 uint8_t bit_reverse(uint8_t);
 229
 230 void jtag_go_to_state(unsigned state)
 231 {
 232         mpsse_purge();
 233
 234         if (state == STATE_TEST_LOGIC_RESET) {
 235                 for (int i = 0; i < 5; ++i) {
 236                         jtag_state_step(true);
 237                 }
 238                 mpsse_send_byte(MC_DATA_TMS | MC_DATA_LSB | MC_DATA_BITS);
 239                 mpsse_send_byte(5 - 1);
 240                 mpsse_send_byte(0b11111);
 241
 242         } else {
 243                 uint8_t d = 0;
 244                 uint8_t count = 0;
 245                 while (jtag_current_state() != state) {
 246                         d = (d >> 1) & ~0x80;
 247                         if((tms_map[jtag_current_state()] >> state) & 1){
 248                                 d |= 0x80;
 249                         }
 250                         count++;
 251
 252                         jtag_state_step((tms_map[jtag_current_state()] >> state) & 1);
 253                 }
 254                 mpsse_send_byte(MC_DATA_TMS | MC_DATA_LSB | MC_DATA_BITS);
 255                 mpsse_send_byte(count - 1);
 256                 mpsse_send_byte(d >> (8-count));
 257
 258         }
 259 }
 260
 261 void jtag_wait_time(uint32_t microseconds)
 262 {
 263         while (microseconds--) {
 264                 jtag_pulse_clock();
 265         }
 266 }
 267