lambdasoc/test/test_hyperbus.py

   1 # Test of HyperRAM class
   2 #
   3 # Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   5 #
   6 # Based on code from Kermarrec, Licensed BSD-2-Clause
   7 #
   8 # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
   9 # under EU Grants 871528 and 957073, under the LGPLv3+ License
  10
  11 import unittest
  12
  13 from nmigen import (Record, Module, Signal, Elaboratable)
  14 from nmigen.compat.sim import run_simulation
  15
  16 from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, TestHyperRAMPHY
  17
  18 def c2bool(c):
  19     return {"-": 1, "_": 0}[c]
  20
  21
  22 def wb_write(bus, addr, data, sel):
  23     yield bus.adr.eq(addr)
  24     yield bus.dat_w.eq(data)
  25     yield bus.sel.eq(sel)
  26     yield bus.we.eq(1)
  27     yield bus.cyc.eq(1)
  28     yield bus.stb.eq(1)
  29     yield
  30     while not (yield bus.ack):
  31         yield
  32     yield bus.cyc.eq(0)
  33     yield bus.stb.eq(0)
  34
  35
  36 def wb_read(bus, addr, sel):
  37     yield bus.adr.eq(addr)
  38     yield bus.sel.eq(sel)
  39     yield bus.cyc.eq(1)
  40     yield bus.stb.eq(1)
  41     yield
  42     while not (yield bus.ack):
  43         yield
  44     yield bus.cyc.eq(0)
  45     yield bus.stb.eq(0)
  46
  47     return (yield bus.dat_r)
  48
  49
  50 class TestHyperBusWrite(unittest.TestCase):
  51
  52     def test_hyperram_write(self):
  53         def fpga_gen(dut):
  54             yield from wb_write(dut.bus, 0x1234, 0xdeadbeef, sel=0b1001)
  55             yield
  56
  57         def hyperram_gen(dut):
  58             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
  59             cs_n    = "--________________________________________________________________------"
  60             dq_oe   = "__------------____________________________________________--------______"
  61             dq_o    = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
  62             rwds_oe = "__________________________________________________________--------______"
  63             rwds_o  = "____________________________________________________________----________"
  64
  65             #clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
  66             #cs_n    = "--________________________________________________________________------"
  67             #dq_oe   = "__------------____________________________________________--------______"
  68             #dq_o    = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
  69             #rwds_oe = "__________________________________________________________--------______"
  70             #rwds_o  = "________________________________________________________________________"
  71             for i in range(3):
  72                 yield
  73             if False: # useful for printing out expected vs results
  74               for i in range(len(clk)):
  75                 print ("i", i)
  76                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
  77                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
  78                 print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
  79                 print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
  80                                     hex((yield dut.phy.pads.dq.o)))
  81                 print ("rwds_oe", c2bool(rwds_oe[i]),
  82                                     (yield dut.phy.pads.rwds.oe))
  83                 print ("rwds_o", c2bool(rwds_o[i]),
  84                                     (yield dut.phy.pads.rwds.o))
  85                 yield
  86             for i in range(len(clk)):
  87                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
  88                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
  89                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
  90                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
  91                                     (yield dut.phy.pads.dq.o))
  92                 self.assertEqual(c2bool(rwds_oe[i]),
  93                                     (yield dut.phy.pads.rwds.oe))
  94                 self.assertEqual(c2bool(rwds_o[i]),
  95                                     (yield dut.phy.pads.rwds.o))
  96                 yield
  97
  98         dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
  99         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
 100                             vcd_name="sim.vcd")
 101
 102     def test_hyperram_read(self):
 103         def fpga_gen(dut):
 104             dat = yield from wb_read(dut.bus, 0x1234, 0b1111)
 105             self.assertEqual(dat, 0xdeadbeef)
 106             dat = yield from wb_read(dut.bus, 0x1235, 0b1111)
 107             self.assertEqual(dat, 0xcafefade)
 108
 109         def hyperram_gen(dut):
 110             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
 111             cs_n    = "--________________________________________________________________________________"
 112             dq_oe   = "__------------____________________________________________________________________"
 113             dq_o    = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
 114             dq_i    = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
 115             rwds_oe = "__________________________________________________________________________________"
 116
 117             for i in range(3):
 118                 print ("prep", i)
 119                 yield
 120             for i in range(len(clk)):
 121                 print ("i", i)
 122                 yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
 123                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
 124                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 125                 yield
 126                 continue
 127                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
 128                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 129                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 130                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
 131                             (yield dut.phy.pads.dq.o))
 132                 self.assertEqual(c2bool(rwds_oe[i]),
 133                             (yield dut.phy.pads.rwds.oe))
 134                 yield
 135
 136         dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
 137         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
 138                             vcd_name="rd_sim.vcd")
 139
 140 class TestHyperBusRead(unittest.TestCase):
 141     def test_hyperram_read(self):
 142         def fpga_gen(dut):
 143             dat = yield from wb_read(dut.bus, 0x1234, 0b1111)
 144             self.assertEqual(dat, 0xdeadbeef)
 145             dat = yield from wb_read(dut.bus, 0x1235, 0b1111)
 146             self.assertEqual(dat, 0xcafefade)
 147             yield
 148             yield
 149             yield
 150             yield
 151             yield
 152
 153         def hyperram_gen(dut):
 154             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
 155             cs_n    = "--________________________________________________________________________________"
 156             dq_oe   = "__------------____________________________________________________________________"
 157             dq_o    = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
 158             dq_i    = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
 159             rwds_oe = "__________________________________________________________________________________"
 160
 161             for i in range(3):
 162                 print ("prep", i)
 163                 yield
 164             for i in range(len(clk)):
 165                 print ("i", i)
 166                 yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
 167                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
 168                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 169                 print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 170                 print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
 171                                     hex((yield dut.phy.pads.dq.o)))
 172                 print ("rwds_oe", c2bool(rwds_oe[i]),
 173                                     (yield dut.phy.pads.rwds.oe))
 174                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
 175                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 176                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 177                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
 178                             (yield dut.phy.pads.dq.o))
 179                 self.assertEqual(c2bool(rwds_oe[i]),
 180                             (yield dut.phy.pads.rwds.oe))
 181                 yield
 182
 183         dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
 184         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
 185                             vcd_name="rd_sim.vcd")
 186
 187 if __name__ == '__main__':
 188     unittest.main()
 189     #t = TestHyperBusRead()
 190     #t.test_hyperram_read()
 191     #t = TestHyperBusWrite()
 192     #t.test_hyperram_write()