lambdasoc/test/test_hyperbus.py

   1 # Test of HyperRAM class
   2 #
   3 # Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   5 #
   6 # Based on code from Kermarrec, Licensed BSD-2-Clause
   7 #
   8 # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
   9 # under EU Grants 871528 and 957073, under the LGPLv3+ License
  10
  11 import unittest
  12
  13 from nmigen import (Record, Module, Signal, Elaboratable)
  14 from nmigen.compat.sim import run_simulation
  15
  16 from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, HyperRAMPHY
  17
  18 def c2bool(c):
  19     return {"-": 1, "_": 0}[c]
  20
  21
  22 def wb_write(bus, addr, data, sel):
  23     yield bus.adr.eq(addr)
  24     yield bus.dat_w.eq(data)
  25     yield bus.sel.eq(sel)
  26     yield bus.we.eq(1)
  27     yield bus.cyc.eq(1)
  28     yield bus.stb.eq(1)
  29     yield
  30     while not (yield bus.ack):
  31         yield
  32     yield bus.cyc.eq(0)
  33     yield bus.stb.eq(0)
  34
  35
  36 def wb_read(bus, addr, sel):
  37     yield bus.adr.eq(addr)
  38     yield bus.sel.eq(sel)
  39     yield bus.cyc.eq(1)
  40     yield bus.stb.eq(1)
  41     yield
  42     while not (yield bus.ack):
  43         yield
  44     yield bus.cyc.eq(0)
  45     yield bus.stb.eq(0)
  46
  47     return (yield bus.dat_r)
  48
  49
  50 class TestHyperBusWrite(unittest.TestCase):
  51
  52     def test_hyperram_write(self):
  53         def fpga_gen(dut):
  54             yield from wb_write(dut.bus, 0x1234, 0xdeadbeef, sel=0b1001)
  55             yield
  56
  57         def hyperram_gen(dut):
  58             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
  59             cs_n    = "--________________________________________________________________------"
  60             dq_oe   = "__------------____________________________________________--------______"
  61             dq_o    = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
  62             rwds_oe = "__________________________________________________________--------______"
  63             rwds_o  = "____________________________________________________________----________"
  64
  65             for i in range(3):
  66                 yield
  67             if False: # useful for printing out expected vs results
  68               for i in range(len(clk)):
  69                 print ("i", i)
  70                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
  71                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
  72                 print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
  73                 print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
  74                                     hex((yield dut.phy.pads.dq.o)))
  75                 print ("rwds_oe", c2bool(rwds_oe[i]),
  76                                     (yield dut.phy.pads.rwds.oe))
  77                 print ("rwds_o", c2bool(rwds_o[i]),
  78                                     (yield dut.phy.pads.rwds.o))
  79                 yield
  80             for i in range(len(clk)):
  81                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
  82                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
  83                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
  84                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
  85                                     (yield dut.phy.pads.dq.o))
  86                 self.assertEqual(c2bool(rwds_oe[i]),
  87                                     (yield dut.phy.pads.rwds.oe))
  88                 self.assertEqual(c2bool(rwds_o[i]),
  89                                     (yield dut.phy.pads.rwds.o))
  90                 yield
  91
  92         dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
  93         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
  94                             vcd_name="sim.vcd")
  95
  96     def test_hyperram_read(self):
  97         def fpga_gen(dut):
  98             dat = yield from wb_read(dut.bus, 0x1234, 0b1111)
  99             self.assertEqual(dat, 0xdeadbeef)
 100             dat = yield from wb_read(dut.bus, 0x1235, 0b1111)
 101             self.assertEqual(dat, 0xcafefade)
 102
 103         def hyperram_gen(dut):
 104             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
 105             cs_n    = "--________________________________________________________________________________"
 106             dq_oe   = "__------------____________________________________________________________________"
 107             dq_o    = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
 108             dq_i    = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
 109             rwds_oe = "__________________________________________________________________________________"
 110
 111             for i in range(3):
 112                 print ("prep", i)
 113                 yield
 114             for i in range(len(clk)):
 115                 print ("i", i)
 116                 yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
 117                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
 118                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 119                 yield
 120                 continue
 121                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
 122                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 123                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 124                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
 125                             (yield dut.phy.pads.dq.o))
 126                 self.assertEqual(c2bool(rwds_oe[i]),
 127                             (yield dut.phy.pads.rwds.oe))
 128                 yield
 129
 130         dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
 131         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
 132                             vcd_name="rd_sim.vcd")
 133
 134
 135 class TestHyperBusRead(unittest.TestCase):
 136     def test_hyperram_read(self):
 137         def fpga_gen(dut):
 138             dat = yield from wb_read(dut.bus, 0x1234, 0b1111)
 139             self.assertEqual(dat, 0xdeadbeef)
 140             dat = yield from wb_read(dut.bus, 0x1235, 0b1111)
 141             self.assertEqual(dat, 0xcafefade)
 142             yield
 143             yield
 144             yield
 145             yield
 146             yield
 147
 148         def hyperram_gen(dut):
 149             clk     = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
 150             cs_n    = "--________________________________________________________________________________"
 151             dq_oe   = "__------------____________________________________________________________________"
 152             dq_o    = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
 153             dq_i    = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
 154             rwds_oe = "__________________________________________________________________________________"
 155
 156             for i in range(3):
 157                 print ("prep", i)
 158                 yield
 159             for i in range(len(clk)):
 160                 print ("i", i)
 161                 yield dut.phy.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
 162                 print ("clk", c2bool(clk[i]), (yield dut.phy.pads.clk))
 163                 print ("cs_n", c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 164                 print ("dq_oe", c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 165                 print ("dq_o", hex(int(dq_o[2*(i//2):2*(i//2)+2], 16)),
 166                                     hex((yield dut.phy.pads.dq.o)))
 167                 print ("rwds_oe", c2bool(rwds_oe[i]),
 168                                     (yield dut.phy.pads.rwds.oe))
 169                 self.assertEqual(c2bool(clk[i]), (yield dut.phy.pads.clk))
 170                 self.assertEqual(c2bool(cs_n[i]), (yield dut.phy.pads.cs_n))
 171                 self.assertEqual(c2bool(dq_oe[i]), (yield dut.phy.pads.dq.oe))
 172                 self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16),
 173                             (yield dut.phy.pads.dq.o))
 174                 self.assertEqual(c2bool(rwds_oe[i]),
 175                             (yield dut.phy.pads.rwds.oe))
 176                 yield
 177
 178         dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
 179         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
 180                             vcd_name="rd_sim.vcd")
 181
 182 if __name__ == '__main__':
 183     unittest.main()
 184     #t = TestHyperBusRead()
 185     #t.test_hyperram_read()
 186     #t = TestHyperBusWrite()
 187     #t.test_hyperram_write()