lambdasoc/test/test_periph_event.py

   1 # nmigen: UnusedElaboratable=no
   2
   3 import unittest
   4 from nmigen import *
   5 from nmigen.back.pysim import *
   6
   7 from ..periph.event import *
   8
   9
  10 def simulation_test(dut, process):
  11     with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
  12         sim.add_clock(1e-6)
  13         sim.add_sync_process(process)
  14         sim.run()
  15
  16
  17 class EventSourceTestCase(unittest.TestCase):
  18     def test_simple(self):
  19         ev = EventSource()
  20         self.assertEqual(ev.name, "ev")
  21         self.assertEqual(ev.mode, "level")
  22
  23     def test_name_wrong(self):
  24         with self.assertRaisesRegex(TypeError,
  25                 r"Name must be a string, not 2"):
  26             EventSource(name=2)
  27
  28     def test_mode_wrong(self):
  29         with self.assertRaisesRegex(ValueError,
  30                 r"Invalid trigger mode 'foo'; must be one of level, rise, fall"):
  31             ev = EventSource(mode="foo")
  32
  33
  34 class InterruptSourceTestCase(unittest.TestCase):
  35     def test_simple(self):
  36         ev_0 = EventSource()
  37         ev_1 = EventSource()
  38         dut = InterruptSource((ev_0, ev_1))
  39         self.assertEqual(dut.name, "dut")
  40         self.assertEqual(dut.status.width, 2)
  41         self.assertEqual(dut.pending.width, 2)
  42         self.assertEqual(dut.enable.width, 2)
  43
  44     def test_name_wrong(self):
  45         with self.assertRaisesRegex(TypeError,
  46                 r"Name must be a string, not 2"):
  47             InterruptSource((), name=2)
  48
  49     def test_event_wrong(self):
  50         with self.assertRaisesRegex(TypeError,
  51                 r"Event source must be an instance of EventSource, not 'foo'"):
  52             dut = InterruptSource(("foo",))
  53
  54     def test_events(self):
  55         ev_0 = EventSource(mode="level")
  56         ev_1 = EventSource(mode="rise")
  57         ev_2 = EventSource(mode="fall")
  58         dut  = InterruptSource((ev_0, ev_1, ev_2))
  59
  60         def process():
  61             yield ev_0.stb.eq(1)
  62             yield ev_1.stb.eq(0)
  63             yield ev_2.stb.eq(1)
  64             yield
  65             self.assertEqual((yield dut.irq), 0)
  66
  67             yield dut.status.r_stb.eq(1)
  68             yield
  69             yield dut.status.r_stb.eq(0)
  70             yield
  71             self.assertEqual((yield dut.status.r_data), 0b101)
  72             yield
  73
  74             yield dut.enable.w_stb.eq(1)
  75             yield dut.enable.w_data.eq(0b111)
  76             yield
  77             yield dut.enable.w_stb.eq(0)
  78             yield
  79             yield
  80             self.assertEqual((yield dut.irq), 1)
  81
  82             yield dut.pending.w_stb.eq(1)
  83             yield dut.pending.w_data.eq(0b001)
  84             yield
  85             yield dut.pending.w_stb.eq(0)
  86             yield
  87
  88             yield dut.pending.r_stb.eq(1)
  89             yield
  90             yield dut.pending.r_stb.eq(0)
  91             yield
  92             self.assertEqual((yield dut.pending.r_data), 0b001)
  93             self.assertEqual((yield dut.irq), 1)
  94             yield
  95
  96             yield ev_0.stb.eq(0)
  97             yield dut.pending.w_stb.eq(1)
  98             yield dut.pending.w_data.eq(0b001)
  99             yield
 100             yield dut.pending.w_stb.eq(0)
 101             yield
 102             yield
 103             self.assertEqual((yield dut.irq), 0)
 104
 105             yield ev_1.stb.eq(1)
 106             yield dut.pending.r_stb.eq(1)
 107             yield
 108             yield dut.pending.r_stb.eq(0)
 109             yield
 110             self.assertEqual((yield dut.pending.r_data), 0b010)
 111             self.assertEqual((yield dut.irq), 1)
 112
 113             yield dut.pending.w_stb.eq(1)
 114             yield dut.pending.w_data.eq(0b010)
 115             yield
 116             yield dut.pending.w_stb.eq(0)
 117             yield
 118             yield
 119             self.assertEqual((yield dut.irq), 0)
 120
 121             yield ev_2.stb.eq(0)
 122             yield
 123             yield dut.pending.r_stb.eq(1)
 124             yield
 125             yield dut.pending.r_stb.eq(0)
 126             yield
 127             self.assertEqual((yield dut.pending.r_data), 0b100)
 128             self.assertEqual((yield dut.irq), 1)
 129
 130             yield dut.pending.w_stb.eq(1)
 131             yield dut.pending.w_data.eq(0b100)
 132             yield
 133             yield dut.pending.w_stb.eq(0)
 134             yield
 135             yield
 136             self.assertEqual((yield dut.irq), 0)
 137
 138         simulation_test(dut, process)