lambdasoc/test/test_periph_serial.py

   1 import unittest
   2
   3 from nmigen import *
   4 from nmigen.lib.io import pin_layout
   5 from nmigen.back.pysim import *
   6
   7 from ._wishbone import *
   8 from ..periph.serial import AsyncSerialPeripheral
   9
  10
  11 divisor_addr    = 0x00 >> 2
  12 rx_data_addr    = 0x04 >> 2
  13 rx_rdy_addr     = 0x08 >> 2
  14 rx_err_addr     = 0x0c >> 2
  15 tx_data_addr    = 0x10 >> 2
  16 tx_rdy_addr     = 0x14 >> 2
  17 ev_status_addr  = 0x20 >> 2
  18 ev_pending_addr = 0x24 >> 2
  19 ev_enable_addr  = 0x28 >> 2
  20
  21
  22 class AsyncSerialPeripheralTestCase(unittest.TestCase):
  23     def test_loopback(self):
  24         pins = Record([("rx", pin_layout(1, dir="i")),
  25                        ("tx", pin_layout(1, dir="o"))])
  26         dut = AsyncSerialPeripheral(divisor=5, pins=pins)
  27         m = Module()
  28         m.submodules.serial = dut
  29         m.d.comb += pins.rx.i.eq(pins.tx.o)
  30
  31         def process():
  32             # enable rx_rdy event
  33             yield from wb_write(dut.bus, addr=ev_enable_addr, data=0b001, sel=0xf)
  34             yield
  35
  36             tx_rdy = yield from wb_read(dut.bus, addr=tx_rdy_addr, sel=0xf)
  37             self.assertEqual(tx_rdy, 1)
  38             yield
  39
  40             yield from wb_write(dut.bus, addr=tx_data_addr, data=0xab, sel=0xf)
  41             yield
  42
  43             for i in range(10):
  44                 yield
  45             self.assertTrue((yield dut.irq))
  46
  47             rx_rdy = yield from wb_read(dut.bus, addr=rx_rdy_addr, sel=0xf)
  48             self.assertEqual(rx_rdy, 1)
  49             yield
  50             rx_data = yield from wb_read(dut.bus, addr=rx_data_addr, sel=0xf)
  51             self.assertEqual(rx_data, 0xab)
  52             yield
  53
  54         with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
  55             sim.add_clock(1e-6)
  56             sim.add_sync_process(process)
  57             sim.run()