lambdasoc/test/test_periph_serial.py

   1 import unittest
   2
   3 from nmigen import *
   4 from nmigen.lib.io import pin_layout
   5 from nmigen.back.pysim import *
   6
   7 from nmigen_stdio.serial import AsyncSerial
   8
   9 from .utils.wishbone import *
  10 from ..periph.serial import AsyncSerialPeripheral
  11
  12
  13 divisor_addr    = 0x00 >> 2
  14 rx_data_addr    = 0x04 >> 2
  15 rx_rdy_addr     = 0x08 >> 2
  16 rx_err_addr     = 0x0c >> 2
  17 tx_data_addr    = 0x10 >> 2
  18 tx_rdy_addr     = 0x14 >> 2
  19 ev_status_addr  = 0x20 >> 2
  20 ev_pending_addr = 0x24 >> 2
  21 ev_enable_addr  = 0x28 >> 2
  22
  23
  24 class AsyncSerialPeripheralTestCase(unittest.TestCase):
  25     def test_loopback(self):
  26         pins = Record([("rx", pin_layout(1, dir="i")),
  27                        ("tx", pin_layout(1, dir="o"))])
  28
  29         core = AsyncSerial(divisor=5, pins=pins)
  30         dut = AsyncSerialPeripheral(core=core)
  31         m = Module()
  32         m.submodules.serial = dut
  33         m.d.comb += pins.rx.i.eq(pins.tx.o)
  34
  35         def process():
  36             # enable rx_rdy event
  37             yield from wb_write(dut.bus, addr=ev_enable_addr, data=0b001, sel=0xf)
  38             yield
  39
  40             tx_rdy = yield from wb_read(dut.bus, addr=tx_rdy_addr, sel=0xf)
  41             self.assertEqual(tx_rdy, 1)
  42             yield
  43
  44             yield from wb_write(dut.bus, addr=tx_data_addr, data=0xab, sel=0xf)
  45             yield
  46
  47             for i in range(61):
  48                 yield
  49             self.assertTrue((yield dut.irq))
  50
  51             rx_rdy = yield from wb_read(dut.bus, addr=rx_rdy_addr, sel=0xf)
  52             self.assertEqual(rx_rdy, 1)
  53             yield
  54             rx_data = yield from wb_read(dut.bus, addr=rx_data_addr, sel=0xf)
  55             self.assertEqual(rx_data, 0xab)
  56             yield
  57
  58         sim = Simulator(m)
  59         sim.add_clock(1e-6)
  60         sim.add_sync_process(process)
  61         with sim.write_vcd("test.vcd"):
  62             sim.run()