libgram/src/dfii.c

   1 #include <stdint.h>
   2
   3 #include "hw_regs.h"
   4 #include <gram.h>
   5 #include "dfii.h"
   6 #include "helpers.h"
   7 #include "io.h"
   8
   9 static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) {
  10 #ifdef GRAM_RW_FUNC
  11         gram_write(ctx, (void*)&(ctx->core->control), val);
  12 #else
  13         writel(val, (unsigned long)&(ctx->core->control));
  14 #endif
  15 }
  16
  17 void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
  18         if (software_control) {
  19                 dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET|DFII_COMMAND_CS);
  20         } else {
  21                 dfii_setcontrol(ctx, DFII_CONTROL_SEL|DFII_CONTROL_RESET);
  22         }
  23 }
  24
  25 void dfii_set_p0_address(const struct gramCtx *ctx, uint32_t val) {
  26 #ifdef GRAM_RW_FUNC
  27         gram_write(ctx, (void*)&(ctx->core->phases[0].address), val);
  28 #else
  29         writel(val, (unsigned long)&(ctx->core->phases[0].address));
  30 #endif
  31 }
  32
  33 void dfii_set_p0_baddress(const struct gramCtx *ctx, uint32_t val) {
  34 #ifdef GRAM_RW_FUNC
  35         gram_write(ctx, (void*)&(ctx->core->phases[0].baddress), val);
  36 #else
  37         writel(val, (unsigned long)&(ctx->core->phases[0].baddress));
  38 #endif
  39 }
  40
  41 void dfii_p0_command(const struct gramCtx *ctx, uint32_t cmd) {
  42 #ifdef GRAM_RW_FUNC
  43         gram_write(ctx, (void*)&(ctx->core->phases[0].command), cmd);
  44         gram_write(ctx, (void*)&(ctx->core->phases[0].command_issue), 1);
  45 #else
  46         writel(cmd, (unsigned long)&(ctx->core->phases[0].command));
  47         writel(1, (unsigned long)&(ctx->core->phases[0].command_issue));
  48 #endif
  49 }
  50
  51 /* Set MRx register */
  52 static void dfii_set_mr(const struct gramCtx *ctx, uint8_t mr, uint16_t val) {
  53         dfii_set_p0_address(ctx, val);
  54         dfii_set_p0_baddress(ctx, mr);
  55         dfii_p0_command(ctx, DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
  56 }
  57
  58 //comment these in to speed up icarus verilog simulations dramatically
  59 //#define LONG_TIMER_MULT 1
  60 //#define SHORT_TIMER_MULT 1
  61
  62 #define MR0_DLL_RESET (1 << 8)
  63 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile) {
  64         /* Release reset */
  65         dfii_set_p0_address(ctx, 0x0);
  66         dfii_set_p0_baddress(ctx, 0);
  67         dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
  68         //cdelay(5*LONG_TIMER_MULT);
  69
  70         /* Bring CKE high */
  71         //dfii_set_p0_address(ctx, 0x0);
  72         //dfii_set_p0_baddress(ctx, 0);
  73         dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
  74         cdelay(1*LONG_TIMER_MULT);
  75
  76         /* Load Mode Register 2, CWL=5 */
  77         dfii_set_mr(ctx, 2, profile->mode_registers[2]);
  78
  79         /* Load Mode Register 3 */
  80         dfii_set_mr(ctx, 3, profile->mode_registers[3]);
  81
  82         /* Load Mode Register 1 */
  83         dfii_set_mr(ctx, 1, profile->mode_registers[1]);
  84
  85         /* Load Mode Register 0, CL=6, BL=8 */
  86         dfii_set_mr(ctx, 0, profile->mode_registers[0]);
  87     if (profile->mode_registers[0] & MR0_DLL_RESET) {
  88            cdelay(1*SHORT_TIMER_MULT);
  89            dfii_set_mr(ctx, 0, profile->mode_registers[0] & ~MR0_DLL_RESET);
  90     }
  91         cdelay(6*SHORT_TIMER_MULT);
  92
  93         /* ZQ Calibration */
  94         dfii_set_p0_address(ctx, 0x400);
  95         dfii_set_p0_baddress(ctx, 0);
  96         dfii_p0_command(ctx, DFII_COMMAND_WE|DFII_COMMAND_CS);
  97         cdelay(6*SHORT_TIMER_MULT);
  98 }