3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 from litex
.build
.generic_platform
import ConstraintManager
11 CPU_VARIANTS
= ["standard", "standard32", "standardjtag",
12 "standardjtagtestgpio", "ls180", "ls180sram4k",
17 def make_wb_bus(prefix
, obj
, simple
=False):
19 outpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
21 outpins
+= ['cti', 'bte']
23 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
24 for i
in ['ack', 'err', 'dat_r']:
25 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
28 def make_wb_slave(prefix
, obj
, simple
=False):
30 inpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
32 inpins
+= ['cti', 'bte']
34 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
35 for o
in ['ack', 'err', 'dat_r']:
36 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
39 def make_pad(res
, dirn
, name
, suffix
, cpup
, iop
):
40 cpud
, iod
= ('i', 'o') if dirn
else ('o', 'i')
41 cname
= '%s_%s__core__%s' % (cpud
, name
, suffix
)
42 pname
= '%s_%s__pad__%s' % (iod
, name
, suffix
)
43 print ("make pad", name
, dirn
, cpud
, iod
, cname
, pname
, suffix
, cpup
, iop
)
44 res
[cname
], res
[pname
] = cpup
, iop
46 def get_field(rec
, name
):
49 print ("get_field", f
, name
)
53 return getattr(rec
, f
)
56 def make_jtag_ioconn(res
, pin
, cpupads
, iopads
):
57 # XXX normally this is NOT done, however to avoid import problems
58 # in litex, move the import into where it is optionally called
59 from c4m
.nmigen
.jtag
.tap
import IOType
61 (fn
, pin
, iotype
, pin_name
, scan_idx
) = pin
62 #serial_tx__core__o, serial_rx__pad__i,
63 # special-case sdram_clock
64 #if pin == 'clock' and fn == 'sdr':
65 # cpu = cpupads['sdram_clock']
66 # io = iopads['sdram_clock']
72 print ("make_jtag_ioconn", scan_idx
)
73 print ("cpupads", cpupads
)
74 print ("iopads", iopads
)
75 print ("pin", fn
, pin
, iotype
, pin_name
)
78 name
= "%s_%s" % (fn
, pin
)
82 if iotype
in (IOType
.In
, IOType
.Out
):
84 #if pin == 'clock' and fn == 'sdr':
87 if len(ps
) == 2 and ps
[-1].isdigit():
90 print ("ps split", pin
, idx
)
91 cpup
= getattr(cpu
, pin
)[idx
]
92 iop
= getattr(io
, pin
)[idx
]
93 elif pin
.isdigit() and fn
!= 'eint':
100 cpup
= getattr(cpu
, pin
)
101 iop
= getattr(io
, pin
)
103 if iotype
== IOType
.Out
:
104 # output from the pad is routed through C4M JTAG and so
105 # is an *INPUT* into core. ls180soc connects this to "real" peripheral
106 make_pad(res
, True, name
, "o", cpup
, iop
)
108 elif iotype
== IOType
.In
:
109 # input to the pad is routed through C4M JTAG and so
110 # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
111 make_pad(res
, False, name
, "i", cpup
, iop
)
113 elif iotype
== IOType
.InTriOut
:
114 if fn
== 'gpio': # sigh decode GPIO special-case
118 elif fn
.startswith('sd') and pin
.startswith('data'):
123 idx
= int(pin
.split('_')[-1])
125 pfx
= pin
.split('_')[0]+"_"
130 print ("gpio tri", fn
, pin
, iotype
, pin_name
, scan_idx
, idx
)
132 cpup
, iop
= get_field(cpu
, pfx
+"i")[idx
], \
133 get_field(io
, pfx
+"i")[idx
]
134 make_pad(res
, False, name
, "i", cpup
, iop
)
136 cpup
, iop
= get_field(cpu
, pfx
+"o")[idx
], \
137 get_field(io
, pfx
+"o")[idx
]
138 make_pad(res
, True, name
, "o", cpup
, iop
)
140 cpup
, iop
= get_field(cpu
, pfx
+"oe")[oe_idx
], \
141 get_field(io
, pfx
+"oe")[oe_idx
]
142 make_pad(res
, True, name
, "oe", cpup
, iop
)
144 if iotype
in (IOType
.In
, IOType
.InTriOut
):
145 sigs
.append(("i", 1))
146 if iotype
in (IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
):
147 sigs
.append(("o", 1))
148 if iotype
in (IOType
.TriOut
, IOType
.InTriOut
):
149 sigs
.append(("oe", 1))
154 human_name
= "Libre-SoC"
155 variants
= CPU_VARIANTS
156 endianness
= "little"
157 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
158 linker_output_format
= "elf64-powerpcle"
160 io_regions
= {0xc0000000: 0x10000000} # origin, length
164 return {"csr": 0xc0000000}
169 flags
+= "-mabi=elfv2 "
170 flags
+= "-msoft-float "
171 flags
+= "-mno-string "
172 flags
+= "-mno-multiple "
174 flags
+= "-mno-altivec "
175 flags
+= "-mlittle-endian "
176 flags
+= "-mstrict-align "
177 flags
+= "-fno-stack-protector "
178 flags
+= "-mcmodel=small "
179 flags
+= "-D__microwatt__ "
182 def __init__(self
, platform
, variant
="standard"):
183 self
.platform
= platform
184 self
.variant
= variant
185 self
.reset
= Signal()
187 irq_en
= "noirq" not in variant
190 self
.interrupt
= Signal(16)
192 if variant
== "standard32":
194 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
196 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
198 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
200 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
201 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
203 jtag_en
= ('jtag' in variant
) or ('ls180' in variant
)
205 if "testgpio" in variant
:
206 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
208 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=32, adr_width
=30)
210 self
.srams
= srams
= []
211 if "sram4k" in variant
:
213 srams
.append(wb
.Interface(data_width
=64, adr_width
=29))
215 self
.periph_buses
= [ibus
, dbus
]
216 self
.memory_buses
= []
219 self
.periph_buses
.append(jtag_wb
)
220 self
.jtag_tck
= Signal(1)
221 self
.jtag_tms
= Signal(1)
222 self
.jtag_tdi
= Signal(1)
223 self
.jtag_tdo
= Signal(1)
225 self
.dmi_addr
= Signal(4)
226 self
.dmi_din
= Signal(64)
227 self
.dmi_dout
= Signal(64)
228 self
.dmi_wr
= Signal(1)
229 self
.dmi_ack
= Signal(1)
230 self
.dmi_req
= Signal(1)
234 self
.cpu_params
= dict(
236 i_clk
= ClockSignal(),
237 i_rst
= ResetSignal() | self
.reset
,
239 # Monitoring / Debugging
242 i_core_bigendian_i
= 0, # Signal(),
243 o_busy_o
= Signal(), # not connected
244 o_memerr_o
= Signal(), # not connected
245 o_pc_o
= Signal(64), # not connected
250 self
.cpu_params
['i_int_level_i'] = self
.interrupt
253 self
.cpu_params
.update(dict(
255 o_TAP_bus__tdo
= self
.jtag_tdo
,
256 i_TAP_bus__tdi
= self
.jtag_tdi
,
257 i_TAP_bus__tms
= self
.jtag_tms
,
258 i_TAP_bus__tck
= self
.jtag_tck
,
261 self
.cpu_params
.update(dict(
263 i_dmi_addr_i
= self
.dmi_addr
,
264 i_dmi_din
= self
.dmi_din
,
265 o_dmi_dout
= self
.dmi_dout
,
266 i_dmi_req_i
= self
.dmi_req
,
267 i_dmi_we_i
= self
.dmi_wr
,
268 o_dmi_ack_o
= self
.dmi_ack
,
271 # add clock select, pll output
272 if "ls180" in variant
and "pll" not in variant
:
273 self
.pll_18_o
= Signal()
274 self
.clk_sel
= Signal(2)
275 self
.pll_ana_o
= Signal()
276 self
.cpu_params
['i_clk_sel_i'] = self
.clk_sel
277 self
.cpu_params
['o_pll_18_o'] = self
.pll_18_o
278 self
.cpu_params
['o_vco_test_ana'] = self
.pll_ana_o
280 # add wishbone buses to cpu params
281 self
.cpu_params
.update(make_wb_bus("ibus", ibus
, True))
282 self
.cpu_params
.update(make_wb_bus("dbus", dbus
, True))
283 self
.cpu_params
.update(make_wb_slave("ics_wb", ics
, True))
284 self
.cpu_params
.update(make_wb_slave("icp_wb", icp
, True))
285 if "testgpio" in variant
:
286 self
.cpu_params
.update(make_wb_slave("gpio_wb", gpio
))
288 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
, simple
=True))
289 if "sram4k" in variant
:
290 for i
, sram
in enumerate(srams
):
291 self
.cpu_params
.update(make_wb_slave("sram4k_%d_wb" % i
,
294 # and set ibus advanced tags to zero (disable)
295 self
.cpu_params
['i_ibus__cti'] = 0
296 self
.cpu_params
['i_ibus__bte'] = 0
297 self
.cpu_params
['i_dbus__cti'] = 0
298 self
.cpu_params
['i_dbus__bte'] = 0
300 if "ls180" in variant
:
301 # XXX normally this is NOT done, however to avoid import problems
302 # in litex, move the import into where it is optionally called
303 # then, for non-ls180 platforms, huge numbers of dependencies
304 # behind these simple-looking imports are not needed
305 from soc
.config
.pinouts
import get_pinspecs
306 from soc
.debug
.jtag
import Pins
307 from libresoc
.ls180
import io
309 # urr yuk. have to expose iopads / pins from core to litex
310 # then back again. cut _some_ of that out by connecting up
311 # padresources. this mirrors what is done inside litex
312 self
.padresources
= io()
313 self
.pad_cm
= ConstraintManager(self
.padresources
, [])
317 subset
= {'uart', 'mtwi', 'eint', 'mspi0',
323 for periph
in subset
:
326 if periph
[-1].isdigit():
327 periph
, num
= periph
[:-1], int(periph
[-1])
328 print ("periph request", periph
, num
)
331 periph
, num
= 'spimaster', None
333 periph
, num
= 'spisdcard', None
334 elif periph
== 'sdr':
336 elif periph
== 'mtwi':
339 periph
, num
= 'sdcard', None
340 litexmap
[origperiph
] = (periph
, num
)
341 self
.cpupads
[origperiph
] = self
.pad_cm
.request(periph
, num
)
342 iopads
[origperiph
] = platform
.request(periph
, num
)
343 #if periph == 'sdram':
344 # # special-case sdram clock
345 # ck = self.pad_cm.request("sdram_clock")
346 # self.cpupads['sdram_clock'] = ck
347 # ck = platform.request("sdram_clock")
348 # iopads['sdram_clock'] = ck
350 # for the 180nm ASIC, obtain the pinspecs so that JTAG can be
351 # routed in and back out again. litex is such hell (migen)
352 # that trying to create an auto-generated boundary scan in
353 # migen is just not sane.
354 pinset
= get_pinspecs(subset
=subset
)
357 make_jtag_ioconn(self
.cpu_params
, pin
, self
.cpupads
, iopads
)
359 # add verilog sources
360 self
.add_sources(platform
)
362 def set_reset_address(self
, reset_address
):
363 assert not hasattr(self
, "reset_address")
364 self
.reset_address
= reset_address
365 assert reset_address
== 0x00000000
368 def add_sources(platform
):
369 cdir
= os
.path
.dirname(__file__
)
370 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
371 platform
.add_source(os
.path
.join(cdir
, "SPBlock_512W64B8W.v"))
373 def do_finalize(self
):
374 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)