3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 from soc
.config
.pinouts
import get_pinspecs
9 from soc
.debug
.jtag
import Pins
10 from c4m
.nmigen
.jtag
.tap
import IOType
12 from libresoc
.ls180
import io
13 from litex
.build
.generic_platform
import ConstraintManager
16 CPU_VARIANTS
= ["standard", "standard32", "standardjtag",
17 "standardjtagtestgpio", "ls180", "ls180sram4k",
21 def make_wb_bus(prefix
, obj
, simple
=False):
23 outpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
25 outpins
+= ['cti', 'bte']
27 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
28 for i
in ['ack', 'err', 'dat_r']:
29 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
32 def make_wb_slave(prefix
, obj
, simple
=False):
34 inpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
36 inpins
+= ['cti', 'bte']
38 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
39 for o
in ['ack', 'err', 'dat_r']:
40 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
43 def make_pad(res
, dirn
, name
, suffix
, cpup
, iop
):
44 cpud
, iod
= ('i', 'o') if dirn
else ('o', 'i')
45 cname
= '%s_%s__core__%s' % (cpud
, name
, suffix
)
46 pname
= '%s_%s__pad__%s' % (iod
, name
, suffix
)
47 print ("make pad", name
, dirn
, cpud
, iod
, cname
, pname
, suffix
, cpup
, iop
)
48 res
[cname
], res
[pname
] = cpup
, iop
50 def get_field(rec
, name
):
53 print ("get_field", f
, name
)
57 return getattr(rec
, f
)
60 def make_jtag_ioconn(res
, pin
, cpupads
, iopads
):
61 (fn
, pin
, iotype
, pin_name
, scan_idx
) = pin
62 #serial_tx__core__o, serial_rx__pad__i,
63 # special-case sdram_clock
64 if pin
== 'clock' and fn
== 'sdr':
65 cpu
= cpupads
['sdram_clock']
66 io
= iopads
['sdram_clock']
70 print ("make_jtag_ioconn", scan_idx
)
71 print ("cpupads", cpupads
)
72 print ("iopads", iopads
)
73 print ("pin", fn
, pin
, iotype
, pin_name
)
76 name
= "%s_%s" % (fn
, pin
)
80 if iotype
in (IOType
.In
, IOType
.Out
):
82 if pin
== 'clock' and fn
== 'sdr':
85 elif len(ps
) == 2 and ps
[-1].isdigit():
88 print ("ps split", pin
, idx
)
89 cpup
= getattr(cpu
, pin
)[idx
]
90 iop
= getattr(io
, pin
)[idx
]
97 cpup
= getattr(cpu
, pin
)
98 iop
= getattr(io
, pin
)
100 if iotype
== IOType
.Out
:
101 # output from the pad is routed through C4M JTAG and so
102 # is an *INPUT* into core. ls180soc connects this to "real" peripheral
103 make_pad(res
, True, name
, "o", cpup
, iop
)
105 elif iotype
== IOType
.In
:
106 # input to the pad is routed through C4M JTAG and so
107 # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
108 make_pad(res
, False, name
, "i", cpup
, iop
)
110 elif iotype
== IOType
.InTriOut
:
111 if fn
== 'gpio': # sigh decode GPIO special-case
115 elif fn
.startswith('sd') and pin
.startswith('data'):
120 idx
= int(pin
.split('_')[-1])
122 pfx
= pin
.split('_')[0]+"_"
127 print ("gpio tri", fn
, pin
, iotype
, pin_name
, scan_idx
, idx
)
129 cpup
, iop
= get_field(cpu
, pfx
+"i")[idx
], \
130 get_field(io
, pfx
+"i")[idx
]
131 make_pad(res
, False, name
, "i", cpup
, iop
)
133 cpup
, iop
= get_field(cpu
, pfx
+"o")[idx
], \
134 get_field(io
, pfx
+"o")[idx
]
135 make_pad(res
, True, name
, "o", cpup
, iop
)
137 cpup
, iop
= get_field(cpu
, pfx
+"oe")[oe_idx
], \
138 get_field(io
, pfx
+"oe")[oe_idx
]
139 make_pad(res
, True, name
, "oe", cpup
, iop
)
141 if iotype
in (IOType
.In
, IOType
.InTriOut
):
142 sigs
.append(("i", 1))
143 if iotype
in (IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
):
144 sigs
.append(("o", 1))
145 if iotype
in (IOType
.TriOut
, IOType
.InTriOut
):
146 sigs
.append(("oe", 1))
151 human_name
= "Libre-SoC"
152 variants
= CPU_VARIANTS
153 endianness
= "little"
154 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
155 linker_output_format
= "elf64-powerpcle"
157 io_regions
= {0xc0000000: 0x10000000} # origin, length
161 return {"csr": 0xc0000000}
166 flags
+= "-mabi=elfv2 "
167 flags
+= "-msoft-float "
168 flags
+= "-mno-string "
169 flags
+= "-mno-multiple "
171 flags
+= "-mno-altivec "
172 flags
+= "-mlittle-endian "
173 flags
+= "-mstrict-align "
174 flags
+= "-fno-stack-protector "
175 flags
+= "-mcmodel=small "
176 flags
+= "-D__microwatt__ "
179 def __init__(self
, platform
, variant
="standard"):
180 self
.platform
= platform
181 self
.variant
= variant
182 self
.reset
= Signal()
184 irq_en
= "noirq" not in variant
187 self
.interrupt
= Signal(16)
189 if variant
== "standard32":
191 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
193 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
195 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
197 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
198 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
200 jtag_en
= ('jtag' in variant
) or ('ls180' in variant
)
202 if "testgpio" in variant
:
203 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
205 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=64, adr_width
=29)
207 self
.srams
= srams
= []
208 if "sram4k" in variant
:
210 srams
.append(wb
.Interface(data_width
=64, adr_width
=29))
212 self
.periph_buses
= [ibus
, dbus
]
213 self
.memory_buses
= []
216 self
.periph_buses
.append(jtag_wb
)
217 self
.jtag_tck
= Signal(1)
218 self
.jtag_tms
= Signal(1)
219 self
.jtag_tdi
= Signal(1)
220 self
.jtag_tdo
= Signal(1)
222 self
.dmi_addr
= Signal(4)
223 self
.dmi_din
= Signal(64)
224 self
.dmi_dout
= Signal(64)
225 self
.dmi_wr
= Signal(1)
226 self
.dmi_ack
= Signal(1)
227 self
.dmi_req
= Signal(1)
231 self
.cpu_params
= dict(
233 i_clk
= ClockSignal(),
234 i_rst
= ResetSignal() | self
.reset
,
236 # Monitoring / Debugging
239 i_core_bigendian_i
= 0, # Signal(),
240 o_busy_o
= Signal(), # not connected
241 o_memerr_o
= Signal(), # not connected
242 o_pc_o
= Signal(64), # not connected
247 self
.cpu_params
['i_int_level_i'] = self
.interrupt
250 self
.cpu_params
.update(dict(
252 o_TAP_bus__tdo
= self
.jtag_tdo
,
253 i_TAP_bus__tdi
= self
.jtag_tdi
,
254 i_TAP_bus__tms
= self
.jtag_tms
,
255 i_TAP_bus__tck
= self
.jtag_tck
,
258 self
.cpu_params
.update(dict(
260 i_dmi_addr_i
= self
.dmi_addr
,
261 i_dmi_din
= self
.dmi_din
,
262 o_dmi_dout
= self
.dmi_dout
,
263 i_dmi_req_i
= self
.dmi_req
,
264 i_dmi_we_i
= self
.dmi_wr
,
265 o_dmi_ack_o
= self
.dmi_ack
,
268 # add clock select, pll output
269 if "ls180" in variant
:
270 self
.pll_18_o
= Signal()
271 self
.clk_sel
= Signal(2)
272 self
.pll_lck_o
= Signal()
273 self
.cpu_params
['i_clk_sel_i'] = self
.clk_sel
274 self
.cpu_params
['o_pll_18_o'] = self
.pll_18_o
275 self
.cpu_params
['o_pll_lck_o'] = self
.pll_lck_o
277 # add wishbone buses to cpu params
278 self
.cpu_params
.update(make_wb_bus("ibus", ibus
, True))
279 self
.cpu_params
.update(make_wb_bus("dbus", dbus
, True))
280 self
.cpu_params
.update(make_wb_slave("ics_wb", ics
, True))
281 self
.cpu_params
.update(make_wb_slave("icp_wb", icp
, True))
282 if "testgpio" in variant
:
283 self
.cpu_params
.update(make_wb_slave("gpio_wb", gpio
))
285 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
, simple
=True))
286 if "sram4k" in variant
:
287 for i
, sram
in enumerate(srams
):
288 self
.cpu_params
.update(make_wb_slave("sram4k_%d_wb" % i
,
291 # and set ibus advanced tags to zero (disable)
292 self
.cpu_params
['i_ibus__cti'] = 0
293 self
.cpu_params
['i_ibus__bte'] = 0
294 self
.cpu_params
['i_dbus__cti'] = 0
295 self
.cpu_params
['i_dbus__bte'] = 0
297 if "ls180" in variant
:
298 # urr yuk. have to expose iopads / pins from core to litex
299 # then back again. cut _some_ of that out by connecting
300 self
.padresources
= io()
301 self
.pad_cm
= ConstraintManager(self
.padresources
, [])
305 subset
= {'uart', 'mtwi', 'eint', 'mspi0',
311 for periph
in subset
:
314 if periph
[-1].isdigit():
315 periph
, num
= periph
[:-1], int(periph
[-1])
316 print ("periph request", periph
, num
)
319 periph
, num
= 'spimaster', None
321 periph
, num
= 'spisdcard', None
322 elif periph
== 'sdr':
324 elif periph
== 'mtwi':
327 periph
, num
= 'sdcard', None
328 litexmap
[origperiph
] = (periph
, num
)
329 self
.cpupads
[origperiph
] = self
.pad_cm
.request(periph
, num
)
330 iopads
[origperiph
] = platform
.request(periph
, num
)
331 if periph
== 'sdram':
332 # special-case sdram clock
333 ck
= self
.pad_cm
.request("sdram_clock")
334 self
.cpupads
['sdram_clock'] = ck
335 ck
= platform
.request("sdram_clock")
336 iopads
['sdram_clock'] = ck
338 pinset
= get_pinspecs(subset
=subset
)
341 make_jtag_ioconn(self
.cpu_params
, pin
, self
.cpupads
, iopads
)
343 # add verilog sources
344 self
.add_sources(platform
)
346 def set_reset_address(self
, reset_address
):
347 assert not hasattr(self
, "reset_address")
348 self
.reset_address
= reset_address
349 assert reset_address
== 0x00000000
352 def add_sources(platform
):
353 cdir
= os
.path
.dirname(__file__
)
354 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
356 def do_finalize(self
):
357 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)