libresoc/ls180.py

   1 #
   2 # This file is part of LiteX.
   3 #
   4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # SPDX-License-Identifier: BSD-2-Clause
   6
   7 """ls180 ASIC platform
   8
   9 conceptually similar to the following:
  10
  11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
  12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
  13
  14 Total I/O pins: 84.
  15 Fits in a JEDEC QFP-100
  16
  17 """
  18
  19 from migen.fhdl.structure import _Fragment
  20 from litex.build.generic_platform import (GenericPlatform, Pins,
  21                                         Subsignal, IOStandard, Misc,
  22                                         )
  23 import os
  24
  25
  26 def make_uart(name, num):
  27     return (name, num,
  28         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  29         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  30     )
  31
  32 def make_eint(name, num):
  33     return (name, num,
  34         Subsignal("0", Pins("E0"), IOStandard("LVCMOS33")),
  35         Subsignal("1", Pins("E1"), IOStandard("LVCMOS33")),
  36         Subsignal("2", Pins("E2"), IOStandard("LVCMOS33")),
  37     )
  38
  39 def make_gpio(name, num, n_gpio):
  40     pins = []
  41     for i in range(n_gpio):
  42         pins.append("X%d" % i)
  43     pins = ' '.join(pins)
  44     return (name, 0,
  45              Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
  46              Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
  47              Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
  48             IOStandard("LVCMOS33"))
  49
  50
  51
  52 # IOs ---------------------------------------------------------------------
  53
  54 def io():
  55     _io = [
  56         # CLK/RST: 2 pins
  57         ("sys_pllclk", 0, Pins("G2"), IOStandard("LVCMOS33")),
  58         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
  59         ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
  60         ("sys_pll_testout_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
  61         ("sys_pll_vco_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
  62
  63         # JTAG0: 4 pins
  64         ("jtag", 0,
  65             Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
  66             Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
  67             Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
  68             Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
  69         ),
  70
  71         # I2C0: 2 pins
  72         ("i2c", 0,
  73             Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
  74             Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
  75             Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
  76             Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
  77         ),
  78
  79         # SPI0: 4 pins
  80         ("spimaster", 0,
  81             Subsignal("clk",  Pins("J1")),
  82             Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  83             Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  84             Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  85             Misc("SLEWRATE=FAST"),
  86             IOStandard("LVCMOS33"),
  87         ),
  88
  89         # SPICARD0: 4 pins
  90         ("spisdcard", 0,
  91             Subsignal("clk",  Pins("J1")),
  92             Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  93             Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  94             Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  95             Misc("SLEWRATE=FAST"),
  96             IOStandard("LVCMOS33"),
  97         ),
  98
  99         # SDCARD0: 6 pins
 100         ("sdcard", 0,
 101             Subsignal("clk",  Pins("J1")),
 102             Subsignal("cmd_i",  Pins("J3"), Misc("PULLMODE=UP")),
 103             Subsignal("cmd_o",  Pins("J3"), Misc("PULLMODE=UP")),
 104             Subsignal("cmd_oe",  Pins("J3"), Misc("PULLMODE=UP")),
 105             Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
 106             Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
 107             Subsignal("data_oe", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
 108             Misc("SLEWRATE=FAST"),
 109             IOStandard("LVCMOS33"),
 110         ),
 111
 112         # SDRAM: 39 pins
 113         #("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
 114         ("sdram", 0,
 115             Subsignal("a",     Pins(
 116                 "M20 M19 L20 L19 K20 K19 K18 J20",
 117                 "J19 H20 N19 G20 G19")),
 118             Subsignal("dq_i",    Pins(
 119                 "J16 L18 M18 N18 P18 T18 T17 U20",
 120                 "E19 D20 D19 C20 E18 F18 J18 J17")),
 121             Subsignal("dq_o",    Pins(
 122                 "J16 L18 M18 N18 P18 T18 T17 U20",
 123                 "E19 D20 D19 C20 E18 F18 J18 J17")),
 124             # ASIC pads all need an OE driver
 125             Subsignal("dq_oe",    Pins(
 126                 "J16 L18 M18 N18 P18 T18 T17 U20",
 127                 "E19 D20 D19 C20 E18 F18 J18 J17")),
 128             Subsignal("we_n",  Pins("T20")),
 129             Subsignal("ras_n", Pins("R20")),
 130             Subsignal("cas_n", Pins("T19")),
 131             Subsignal("cs_n",  Pins("P30")),
 132             Subsignal("cke",   Pins("F21")),
 133             Subsignal("ba",    Pins("P19 N20")),
 134             Subsignal("dm",    Pins("U19 E20")),
 135             Subsignal("clock",    Pins("F19")),
 136             IOStandard("LVCMOS33"),
 137             Misc("SLEWRATE=FAST"),
 138         ),
 139
 140         # PWM: 2 pins
 141         ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")),
 142     ]
 143
 144     n_gpio = 16
 145
 146     # 16 GPIOs
 147     _io.append( make_gpio("gpio", 0, n_gpio) )
 148
 149     # EINT: 3 pins
 150     _io.append(make_eint("eint", 0))
 151
 152     # UART0: 2 pins
 153     _io.append(make_uart("uart", 0))
 154     # UART1: 2 pins
 155     _io.append(make_uart("uart", 1))
 156
 157     # not connected - eurgh have to adjust this to match the total pincount.
 158     num_nc = 24
 159     num_nc - 16 # added 16 more power/gnd
 160     num_nc += 4 # mspi1 comments out, litex problems 25mar2021
 161     num_nc += 6 # sd0 comments out, litex problems 25mar2021
 162     num_nc += 2 # pwm comments out, litex problems 25mar2021
 163     #num_nc += 4 # PLL disabled for now
 164     nc = ' '.join("NC%d" % i for i in range(num_nc))
 165     _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 166
 167     return _io
 168
 169 # Platform ----------------------------------------------------------------
 170
 171 class LS180Platform(GenericPlatform):
 172     default_clk_name   = "sys_clk"
 173     default_clk_period = 1e9/50e6
 174
 175     def __init__(self, device="LS180", **kwargs):
 176         assert device in ["LS180"]
 177         GenericPlatform.__init__(self, device, io(), **kwargs)
 178
 179     def build(self, fragment,
 180                     build_dir      = "build",
 181                     build_name     = "top",
 182                     run            = True,
 183                     timingstrict   = True,
 184                     **kwargs):
 185
 186         platform = self
 187
 188         # Create build directory
 189         os.makedirs(build_dir, exist_ok=True)
 190         cwd = os.getcwd()
 191         os.chdir(build_dir)
 192
 193         # Finalize design
 194         if not isinstance(fragment, _Fragment):
 195             fragment = fragment.get_fragment()
 196         platform.finalize(fragment)
 197
 198         # Generate verilog
 199         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
 200         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 201         v_file = build_name + ".v"
 202         v_output.write(v_file)
 203         platform.add_source(v_file)
 204
 205         os.chdir(cwd)
 206
 207         return v_output.ns
 208
 209     def do_finalize(self, fragment):
 210         super().do_finalize(fragment)
 211         return
 212         self.add_period_constraint(self.lookup_request("clk", loose=True),
 213                                    1e9/50e6)