libresoc/ls180.py

   1 #
   2 # This file is part of LiteX.
   3 #
   4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # SPDX-License-Identifier: BSD-2-Clause
   6
   7 """ls180 ASIC platform
   8
   9 conceptually similar to the following:
  10
  11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
  12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
  13
  14 Total I/O pins: 84.
  15 Fits in a JEDEC QFP-100
  16
  17 """
  18
  19 from migen.fhdl.structure import _Fragment
  20 from litex.build.generic_platform import (GenericPlatform, Pins,
  21                                         Subsignal, IOStandard, Misc,
  22                                         )
  23 import os
  24
  25
  26 def make_uart(name, num):
  27     return (name, num,
  28         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  29         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  30     )
  31
  32 def make_gpio(name, num, n_gpio):
  33     pins = []
  34     for i in range(n_gpio):
  35         pins.append("X%d" % i)
  36     pins = ' '.join(pins)
  37     return (name, 0,
  38              Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
  39              Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
  40              Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
  41             IOStandard("LVCMOS33"))
  42
  43
  44
  45 # IOs ---------------------------------------------------------------------
  46
  47 def io():
  48     _io = [
  49         # CLK/RST: 2 pins
  50         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
  51         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
  52         ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
  53         ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
  54         ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
  55
  56         # JTAG0: 4 pins
  57         ("jtag", 0,
  58             Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
  59             Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
  60             Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
  61             Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
  62         ),
  63
  64         # I2C0: 2 pins
  65         ("i2c", 0,
  66             Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
  67             Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
  68             Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
  69             Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
  70         ),
  71
  72         # SPI0: 4 pins
  73         ("spimaster", 0,
  74             Subsignal("clk",  Pins("J1")),
  75             Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  76             Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  77             Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  78             Misc("SLEWRATE=FAST"),
  79             IOStandard("LVCMOS33"),
  80         ),
  81
  82         # SPICARD0: 4 pins
  83         ("spisdcard", 0,
  84             Subsignal("clk",  Pins("J1")),
  85             Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  86             Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  87             Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  88             Misc("SLEWRATE=FAST"),
  89             IOStandard("LVCMOS33"),
  90         ),
  91
  92         # SDCARD0: 6 pins
  93         ("sdcard", 0,
  94             Subsignal("clk",  Pins("J1")),
  95             Subsignal("cmd_i",  Pins("J3"), Misc("PULLMODE=UP")),
  96             Subsignal("cmd_o",  Pins("J3"), Misc("PULLMODE=UP")),
  97             Subsignal("cmd_oe",  Pins("J3"), Misc("PULLMODE=UP")),
  98             Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
  99             Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
 100             Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
 101             Misc("SLEWRATE=FAST"),
 102             IOStandard("LVCMOS33"),
 103         ),
 104
 105         # SDRAM: 39 pins
 106         ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
 107         ("sdram", 0,
 108             Subsignal("a",     Pins(
 109                 "M20 M19 L20 L19 K20 K19 K18 J20",
 110                 "J19 H20 N19 G20 G19")),
 111             Subsignal("dq_i",    Pins(
 112                 "J16 L18 M18 N18 P18 T18 T17 U20",
 113                 "E19 D20 D19 C20 E18 F18 J18 J17")),
 114             Subsignal("dq_o",    Pins(
 115                 "J16 L18 M18 N18 P18 T18 T17 U20",
 116                 "E19 D20 D19 C20 E18 F18 J18 J17")),
 117             Subsignal("dq_oe",    Pins("J17")),
 118             Subsignal("we_n",  Pins("T20")),
 119             Subsignal("ras_n", Pins("R20")),
 120             Subsignal("cas_n", Pins("T19")),
 121             Subsignal("cs_n",  Pins("P30")),
 122             Subsignal("cke",   Pins("F21")),
 123             Subsignal("ba",    Pins("P19 N20")),
 124             Subsignal("dm",    Pins("U19 E20")),
 125             IOStandard("LVCMOS33"),
 126             Misc("SLEWRATE=FAST"),
 127         ),
 128
 129         # PWM: 2 pins
 130         ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")),
 131     ]
 132
 133     n_gpio = 16
 134
 135     # 16 GPIOs
 136     _io.append( make_gpio("gpio", 0, n_gpio) )
 137
 138     # EINT: 3 pins
 139     _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
 140
 141     # UART0: 2 pins
 142     _io.append(make_uart("uart", 0))
 143     # UART1: 2 pins
 144     _io.append(make_uart("uart", 1))
 145
 146     # not connected - eurgh have to adjust this to match the total pincount.
 147     num_nc = 24
 148     num_nc += 4 # mspi1 comments out, litex problems 25mar2021
 149     #num_nc += 6 # sd0 comments out, litex problems 25mar2021
 150     num_nc += 2 # pwm comments out, litex problems 25mar2021
 151     nc = ' '.join("NC%d" % i for i in range(num_nc))
 152     _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 153
 154     return _io
 155
 156 # Platform ----------------------------------------------------------------
 157
 158 class LS180Platform(GenericPlatform):
 159     default_clk_name   = "sys_clk"
 160     default_clk_period = 1e9/50e6
 161
 162     def __init__(self, device="LS180", **kwargs):
 163         assert device in ["LS180"]
 164         GenericPlatform.__init__(self, device, io(), **kwargs)
 165
 166     def build(self, fragment,
 167                     build_dir      = "build",
 168                     build_name     = "top",
 169                     run            = True,
 170                     timingstrict   = True,
 171                     **kwargs):
 172
 173         platform = self
 174
 175         # Create build directory
 176         os.makedirs(build_dir, exist_ok=True)
 177         cwd = os.getcwd()
 178         os.chdir(build_dir)
 179
 180         # Finalize design
 181         if not isinstance(fragment, _Fragment):
 182             fragment = fragment.get_fragment()
 183         platform.finalize(fragment)
 184
 185         # Generate verilog
 186         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
 187         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 188         v_file = build_name + ".v"
 189         v_output.write(v_file)
 190         platform.add_source(v_file)
 191
 192         os.chdir(cwd)
 193
 194         return v_output.ns
 195
 196     def do_finalize(self, fragment):
 197         super().do_finalize(fragment)
 198         return
 199         self.add_period_constraint(self.lookup_request("clk", loose=True),
 200                                    1e9/50e6)