litedram/extras/sim_litedram.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 package sim_litedram is
   5     -- WB req format:
   6     -- 73 .. 71 : cti(2..0)
   7     -- 70 .. 69 : bte(1..0)
   8     -- 68 .. 65 : sel(3..0)
   9     -- 64       : we
  10     -- 63       : stb
  11     -- 62       : cyc
  12     -- 61 .. 32 : addr(29..0)
  13     -- 31 ..  0 : write_data(31..0)
  14     --
  15     procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0));
  16     attribute foreign of litedram_set_wb : procedure is "VHPIDIRECT litedram_set_wb";
  17
  18     -- WB rsp format:
  19     -- 35       : init_error;
  20     -- 34       : init_done;
  21     -- 33       : err
  22     -- 32       : ack
  23     -- 31 ..  0 : read_data(31..0)
  24     --
  25     procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0));
  26     attribute foreign of litedram_get_wb : procedure is "VHPIDIRECT litedram_get_wb";
  27
  28     -- User req format:
  29     -- 171        : cmd_valid
  30     -- 170        : cmd_we
  31     -- 169        : wdata_valid
  32     -- 168        : rdata_ready
  33     -- 167 .. 144 : cmd_addr(23..0)
  34     -- 143 .. 128 : wdata_we(15..0)
  35     -- 127 ..   0 : wdata_data(127..0)
  36     --
  37     procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0));
  38     attribute foreign of litedram_set_user : procedure is "VHPIDIRECT litedram_set_user";
  39
  40     -- User rsp format:
  41     -- 130        : cmd_ready
  42     -- 129        : wdata_ready
  43     -- 128        : rdata_valid
  44     -- 127 ..   0 : rdata_data(127..0)
  45
  46     procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0));
  47     attribute foreign of litedram_get_user : procedure is "VHPIDIRECT litedram_get_user";
  48
  49     procedure litedram_clock;
  50     attribute foreign of litedram_clock : procedure is "VHPIDIRECT litedram_clock";
  51
  52     procedure litedram_init(trace: integer);
  53     attribute foreign of litedram_init : procedure is "VHPIDIRECT litedram_init";
  54 end sim_litedram;
  55
  56 package body sim_litedram is
  57     procedure litedram_set_wb(req : in  std_ulogic_vector(73 downto 0)) is
  58     begin
  59         assert false report "VHPI" severity failure;
  60     end procedure;
  61     procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0)) is
  62     begin
  63         assert false report "VHPI" severity failure;
  64     end procedure;
  65     procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0)) is
  66     begin
  67         assert false report "VHPI" severity failure;
  68     end procedure;
  69     procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0)) is
  70     begin
  71         assert false report "VHPI" severity failure;
  72     end procedure;
  73     procedure litedram_clock is
  74     begin
  75         assert false report "VHPI" severity failure;
  76     end procedure;
  77     procedure litedram_init(trace: integer) is
  78     begin
  79         assert false report "VHPI" severity failure;
  80     end procedure;
  81 end sim_litedram;
  82
  83 library ieee;
  84 use ieee.std_logic_1164.all;
  85 use ieee.numeric_std.all;
  86
  87 library work;
  88 use work.sim_litedram.all;
  89
  90 entity litedram_core is
  91     port(
  92         clk                            : in std_ulogic;
  93         rst                            : in std_ulogic;
  94         pll_locked                     : out std_ulogic;
  95         ddram_a                        : out std_ulogic_vector(0 downto 0);
  96         ddram_ba                       : out std_ulogic_vector(2 downto 0);
  97         ddram_ras_n                    : out std_ulogic;
  98         ddram_cas_n                    : out std_ulogic;
  99         ddram_we_n                     : out std_ulogic;
 100         ddram_cs_n                     : out std_ulogic;
 101         ddram_dm                       : out std_ulogic_vector(1 downto 0);
 102         ddram_dq                       : inout std_ulogic_vector(15 downto 0);
 103         ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
 104         ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
 105         ddram_clk_p                    : out std_ulogic;
 106         ddram_clk_n                    : out std_ulogic;
 107         ddram_cke                      : out std_ulogic;
 108         ddram_odt                      : out std_ulogic;
 109         ddram_reset_n                  : out std_ulogic;
 110         init_done                      : out std_ulogic;
 111         init_error                     : out std_ulogic;
 112         user_clk                       : out std_ulogic;
 113         user_rst                       : out std_ulogic;
 114         wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
 115         wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
 116         wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
 117         wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
 118         wb_ctrl_cyc                    : in std_ulogic;
 119         wb_ctrl_stb                    : in std_ulogic;
 120         wb_ctrl_ack                    : out std_ulogic;
 121         wb_ctrl_we                     : in std_ulogic;
 122         wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
 123         wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
 124         wb_ctrl_err                    : out std_ulogic;
 125         user_port_native_0_cmd_valid   : in std_ulogic;
 126         user_port_native_0_cmd_ready   : out std_ulogic;
 127         user_port_native_0_cmd_we      : in std_ulogic;
 128         user_port_native_0_cmd_addr    : in std_ulogic_vector(23 downto 0);
 129         user_port_native_0_wdata_valid : in std_ulogic;
 130         user_port_native_0_wdata_ready : out std_ulogic;
 131         user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
 132         user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
 133         user_port_native_0_rdata_valid : out std_ulogic;
 134         user_port_native_0_rdata_ready : in std_ulogic;
 135         user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
 136         );
 137 end entity litedram_core;
 138
 139 architecture behaviour of litedram_core is
 140     signal idone      : std_ulogic := '0';
 141     signal ierr       : std_ulogic := '0';
 142     signal old_wb_cyc : std_ulogic := '1';
 143 begin
 144     user_rst <= rst;
 145     user_clk <= clk;
 146     pll_locked <= '1';
 147     init_done <= idone;
 148     init_error <= ierr;
 149
 150     poll: process(user_clk)
 151         procedure send_signals is
 152         begin
 153             litedram_set_wb(wb_ctrl_cti & wb_ctrl_bte &
 154                             wb_ctrl_sel & wb_ctrl_we &
 155                             wb_ctrl_stb & wb_ctrl_cyc &
 156                             wb_ctrl_adr & wb_ctrl_dat_w);
 157             litedram_set_user(user_port_native_0_cmd_valid &
 158                               user_port_native_0_cmd_we &
 159                               user_port_native_0_wdata_valid &
 160                               user_port_native_0_rdata_ready &
 161                               user_port_native_0_cmd_addr &
 162                               user_port_native_0_wdata_we &
 163                               user_port_native_0_wdata_data);
 164         end procedure;
 165
 166         procedure recv_signals is
 167             variable wb_response  : std_ulogic_vector(35 downto 0);
 168             variable ur_response  : std_ulogic_vector(130 downto 0);
 169         begin
 170             litedram_get_wb(wb_response);
 171             wb_ctrl_dat_r <= wb_response(31 downto 0);
 172             wb_ctrl_ack   <= wb_response(32);
 173             wb_ctrl_err   <= wb_response(33);
 174             idone         <= wb_response(34);
 175             ierr          <= wb_response(35);
 176             litedram_get_user(ur_response);
 177             user_port_native_0_cmd_ready   <= ur_response(130);
 178             user_port_native_0_wdata_ready <= ur_response(129);
 179             user_port_native_0_rdata_valid <= ur_response(128);
 180             user_port_native_0_rdata_data  <= ur_response(127 downto 0);
 181         end procedure;
 182
 183     begin
 184         if rising_edge(user_clk) then
 185
 186             send_signals;
 187             recv_signals;
 188             -- Then generate a clock cycle ( 0->1 then 1->0 )
 189             litedram_clock;
 190             recv_signals;
 191         end if;
 192
 193         if falling_edge(user_clk) then
 194             send_signals;
 195             recv_signals;
 196         end if;
 197     end process;
 198
 199 end architecture;
 200
 201 library work;
 202 use work.sim_litedram.all;
 203
 204 entity litedram_trace_stub is
 205 end entity;
 206
 207 architecture behaviour of litedram_trace_stub is
 208 begin
 209     process
 210     begin
 211         litedram_init(1);
 212         wait;
 213     end process;
 214 end architecture;