litedram/gen-src/rcs-arctic-tern-bmc-card.yml

   1 # (c) 2022 Raptor Engineering, LLC
   2 #
   3 # NOTE
   4 # Arctic Tern uses two separate clock lines, one for each DRAM device,
   5 # for signal integrity and design flexibility.
   6 #
   7 # Unfortunately, LiteDRAM has no idea how to handle that in standalone
   8 # generator mode.  The files can be generated by modifying (hacking up)
   9 # litedram/gen.py and manually overriding the clock line counts...
  10 #                Subsignal("clk_p",   Pins(2*core_config["sdram_rank_nb"])),
  11 #                Subsignal("clk_n",   Pins(2*core_config["sdram_rank_nb"])),
  12
  13 {
  14     "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
  15     "device": "LFE5U-85F-8CABGA381",
  16     "memtype":    "DDR3",      # DRAM type
  17
  18     "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
  19     "sdram_module_nb": 4,             # Number of byte groups
  20     "sdram_rank_nb":   1,             # Number of ranks
  21     "sdram_phy":       "ECP5DDRPHY",    # Type of FPGA PHY
  22
  23     # Electrical ---------------------------------------------------------------
  24     "rtt_nom": "disabled",  # Nominal termination. ("disabled" from LiteX)
  25     "rtt_wr":  "60ohm",  # Write termination. (Default)
  26     "ron":     "34ohm",  # Output driver impedance. (Default)
  27
  28     # Frequency ----------------------------------------------------------------
  29     "init_clk_freq":   24e6,
  30     "input_clk_freq":   125e6, # Input clock frequency
  31     "sys_clk_freq":     48e6,  # System clock frequency (DDR_clk = 4 x sys_clk)
  32
  33     # 0 if freq >64e6 else 100. https://github.com/enjoy-digital/litedram/issues/130
  34     "cmd_delay": 100,
  35
  36     # Core ---------------------------------------------------------------------
  37     "cmd_buffer_depth": 16,    # Depth of the command buffer
  38
  39     "dm_swap": true,
  40
  41     # User Ports ---------------------------------------------------------------
  42     "user_ports": {
  43         "native_0": {
  44             "type": "native",
  45             "block_until_ready": False,
  46         },
  47     },
  48 }