litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v

   1 // -----------------------------------------------------------------------------
   2 // Auto-Generated by:        __   _ __      _  __
   3 //                          / /  (_) /____ | |/_/
   4 //                         / /__/ / __/ -_)>  <
   5 //                        /____/_/\__/\__/_/|_|
   6 //                     Build your hardware, easily!
   7 //                   https://github.com/enjoy-digital/litex
   8 //
   9 // Filename   : litedram_core.v
  10 // Device     : LFE5U-85F-8CABGA381
  11 // LiteX sha1 : 1b62f142
  12 // Date       : 2022-02-21 23:17:57
  13 //------------------------------------------------------------------------------
  14
  15
  16 //------------------------------------------------------------------------------
  17 // Module
  18 //------------------------------------------------------------------------------
  19
  20 module litedram_core (
  21         input  wire clk,
  22         input  wire rst,
  23         output wire pll_locked,
  24         output wire [14:0] ddram_a,
  25         output wire [2:0] ddram_ba,
  26         output wire ddram_ras_n,
  27         output wire ddram_cas_n,
  28         output wire ddram_we_n,
  29         output wire ddram_cs_n,
  30         output wire [3:0] ddram_dm,
  31         input  wire [31:0] ddram_dq,
  32         input  wire [3:0] ddram_dqs_p,
  33         input  wire [3:0] ddram_dqs_n,
  34         output wire [1:0] ddram_clk_p,
  35         input  wire ddram_clk_n,
  36         output wire ddram_cke,
  37         output wire ddram_odt,
  38         output wire ddram_reset_n,
  39         output wire init_done,
  40         output wire init_error,
  41         input  wire [29:0] wb_ctrl_adr,
  42         input  wire [31:0] wb_ctrl_dat_w,
  43         output wire [31:0] wb_ctrl_dat_r,
  44         input  wire [3:0] wb_ctrl_sel,
  45         input  wire wb_ctrl_cyc,
  46         input  wire wb_ctrl_stb,
  47         output wire wb_ctrl_ack,
  48         input  wire wb_ctrl_we,
  49         input  wire [2:0] wb_ctrl_cti,
  50         input  wire [1:0] wb_ctrl_bte,
  51         output wire wb_ctrl_err,
  52         output wire user_clk,
  53         output wire user_rst,
  54         input  wire user_port_native_0_cmd_valid,
  55         output wire user_port_native_0_cmd_ready,
  56         input  wire user_port_native_0_cmd_we,
  57         input  wire [24:0] user_port_native_0_cmd_addr,
  58         input  wire user_port_native_0_wdata_valid,
  59         output wire user_port_native_0_wdata_ready,
  60         input  wire [31:0] user_port_native_0_wdata_we,
  61         input  wire [255:0] user_port_native_0_wdata_data,
  62         output wire user_port_native_0_rdata_valid,
  63         input  wire user_port_native_0_rdata_ready,
  64         output wire [255:0] user_port_native_0_rdata_data
  65 );
  66
  67
  68 //------------------------------------------------------------------------------
  69 // Signals
  70 //------------------------------------------------------------------------------
  71
  72 reg  crg_rst = 1'd0;
  73 wire init_clk;
  74 wire init_rst;
  75 wire por_clk;
  76 wire sys_clk;
  77 wire sys_rst;
  78 wire sys2x_clk;
  79 wire sys2x_rst;
  80 wire sys2x_i_clk;
  81 wire crg_stop;
  82 wire crg_reset0;
  83 reg  [15:0] crg_por_count = 16'd65535;
  84 wire crg_por_done;
  85 wire crg_sys2x_clk_ecsout;
  86 wire crg_reset1;
  87 wire crg_locked;
  88 reg  crg_stdby = 1'd0;
  89 wire crg_clkin;
  90 wire crg_clkout0;
  91 wire crg_clkout1;
  92 wire ddrphy_pause0;
  93 wire ddrphy_stop0;
  94 wire ddrphy_delay0;
  95 wire ddrphy_reset0;
  96 wire ddrphy_new_lock;
  97 reg  ddrphy_update = 1'd0;
  98 reg  ddrphy_stop1 = 1'd0;
  99 reg  ddrphy_freeze = 1'd0;
 100 reg  ddrphy_pause1 = 1'd0;
 101 reg  ddrphy_reset1 = 1'd0;
 102 wire ddrphy_lock0;
 103 wire ddrphy_delay1;
 104 wire ddrphy_lock1;
 105 reg  ddrphy_lock_d = 1'd0;
 106 reg  [6:0] ddrphy_counter = 7'd0;
 107 reg  [3:0] ddrphy_dly_sel_storage = 4'd0;
 108 reg  ddrphy_dly_sel_re = 1'd0;
 109 reg  ddrphy_rdly_dq_rst_re = 1'd0;
 110 wire ddrphy_rdly_dq_rst_r;
 111 reg  ddrphy_rdly_dq_rst_we = 1'd0;
 112 reg  ddrphy_rdly_dq_rst_w = 1'd0;
 113 reg  ddrphy_rdly_dq_inc_re = 1'd0;
 114 wire ddrphy_rdly_dq_inc_r;
 115 reg  ddrphy_rdly_dq_inc_we = 1'd0;
 116 reg  ddrphy_rdly_dq_inc_w = 1'd0;
 117 reg  ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
 118 wire ddrphy_rdly_dq_bitslip_rst_r;
 119 reg  ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
 120 reg  ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
 121 reg  ddrphy_rdly_dq_bitslip_re = 1'd0;
 122 wire ddrphy_rdly_dq_bitslip_r;
 123 reg  ddrphy_rdly_dq_bitslip_we = 1'd0;
 124 reg  ddrphy_rdly_dq_bitslip_w = 1'd0;
 125 reg  ddrphy_burstdet_clr_re = 1'd0;
 126 wire ddrphy_burstdet_clr_r;
 127 reg  ddrphy_burstdet_clr_we = 1'd0;
 128 reg  ddrphy_burstdet_clr_w = 1'd0;
 129 reg  [3:0] ddrphy_burstdet_seen_status = 4'd0;
 130 wire ddrphy_burstdet_seen_we;
 131 reg  ddrphy_burstdet_seen_re = 1'd0;
 132 wire [3:0] ddrphy_datavalid;
 133 wire [14:0] ddrphy_dfi_p0_address;
 134 wire [2:0] ddrphy_dfi_p0_bank;
 135 wire ddrphy_dfi_p0_cas_n;
 136 wire ddrphy_dfi_p0_cs_n;
 137 wire ddrphy_dfi_p0_ras_n;
 138 wire ddrphy_dfi_p0_we_n;
 139 wire ddrphy_dfi_p0_cke;
 140 wire ddrphy_dfi_p0_odt;
 141 wire ddrphy_dfi_p0_reset_n;
 142 wire ddrphy_dfi_p0_act_n;
 143 wire [127:0] ddrphy_dfi_p0_wrdata;
 144 wire ddrphy_dfi_p0_wrdata_en;
 145 wire [15:0] ddrphy_dfi_p0_wrdata_mask;
 146 wire ddrphy_dfi_p0_rddata_en;
 147 reg  [127:0] ddrphy_dfi_p0_rddata = 128'd0;
 148 wire ddrphy_dfi_p0_rddata_valid;
 149 wire [14:0] ddrphy_dfi_p1_address;
 150 wire [2:0] ddrphy_dfi_p1_bank;
 151 wire ddrphy_dfi_p1_cas_n;
 152 wire ddrphy_dfi_p1_cs_n;
 153 wire ddrphy_dfi_p1_ras_n;
 154 wire ddrphy_dfi_p1_we_n;
 155 wire ddrphy_dfi_p1_cke;
 156 wire ddrphy_dfi_p1_odt;
 157 wire ddrphy_dfi_p1_reset_n;
 158 wire ddrphy_dfi_p1_act_n;
 159 wire [127:0] ddrphy_dfi_p1_wrdata;
 160 wire ddrphy_dfi_p1_wrdata_en;
 161 wire [15:0] ddrphy_dfi_p1_wrdata_mask;
 162 wire ddrphy_dfi_p1_rddata_en;
 163 reg  [127:0] ddrphy_dfi_p1_rddata = 128'd0;
 164 wire ddrphy_dfi_p1_rddata_valid;
 165 wire ddrphy_bl8_chunk;
 166 wire ddrphy_pad_oddrx2f0;
 167 wire ddrphy_pad_oddrx2f1;
 168 wire ddrphy_pad_oddrx2f2;
 169 wire ddrphy_pad_oddrx2f3;
 170 wire ddrphy_pad_oddrx2f4;
 171 wire ddrphy_pad_oddrx2f5;
 172 wire ddrphy_pad_oddrx2f6;
 173 wire ddrphy_pad_oddrx2f7;
 174 wire ddrphy_pad_oddrx2f8;
 175 wire ddrphy_pad_oddrx2f9;
 176 wire ddrphy_pad_oddrx2f10;
 177 wire ddrphy_pad_oddrx2f11;
 178 wire ddrphy_pad_oddrx2f12;
 179 wire ddrphy_pad_oddrx2f13;
 180 wire ddrphy_pad_oddrx2f14;
 181 wire ddrphy_pad_oddrx2f15;
 182 wire ddrphy_pad_oddrx2f16;
 183 wire ddrphy_pad_oddrx2f17;
 184 wire ddrphy_pad_oddrx2f18;
 185 wire ddrphy_pad_oddrx2f19;
 186 wire ddrphy_pad_oddrx2f20;
 187 wire ddrphy_pad_oddrx2f21;
 188 wire ddrphy_pad_oddrx2f22;
 189 wire ddrphy_pad_oddrx2f23;
 190 wire ddrphy_pad_oddrx2f24;
 191 wire ddrphy_pad_oddrx2f25;
 192 wire ddrphy_pad_oddrx2f26;
 193 wire ddrphy_dq_oe;
 194 wire ddrphy_dqs_re;
 195 wire ddrphy_dqs_oe;
 196 wire ddrphy_dqs_postamble;
 197 wire ddrphy_dqs_preamble;
 198 wire ddrphy_dqs_i0;
 199 wire ddrphy_dqsr900;
 200 wire ddrphy_dqsw2700;
 201 wire ddrphy_dqsw0;
 202 wire [2:0] ddrphy_rdpntr0;
 203 wire [2:0] ddrphy_wrpntr0;
 204 reg  [6:0] ddrphy_rdly0 = 7'd0;
 205 wire ddrphy_burstdet0;
 206 reg  ddrphy_burstdet_d0 = 1'd0;
 207 wire ddrphy_dqs0;
 208 wire ddrphy_dqs_oe_n0;
 209 reg  [7:0] ddrphy_dm_o_data0 = 8'd0;
 210 reg  [7:0] ddrphy_dm_o_data_d0 = 8'd0;
 211 reg  [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
 212 wire ddrphy_dq_o0;
 213 wire ddrphy_dq_i0;
 214 wire ddrphy_dq_oe_n0;
 215 wire ddrphy_dq_i_delayed0;
 216 wire [7:0] ddrphy_dq_i_data0;
 217 reg  [7:0] ddrphy_dq_o_data0 = 8'd0;
 218 reg  [7:0] ddrphy_dq_o_data_d0 = 8'd0;
 219 reg  [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
 220 wire [3:0] ddrphy_bitslip0_i;
 221 reg  [3:0] ddrphy_bitslip0_o = 4'd0;
 222 reg  [1:0] ddrphy_bitslip0_value = 2'd0;
 223 reg  [7:0] ddrphy_bitslip0_r = 8'd0;
 224 reg  [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
 225 wire ddrphy_dq_o1;
 226 wire ddrphy_dq_i1;
 227 wire ddrphy_dq_oe_n1;
 228 wire ddrphy_dq_i_delayed1;
 229 wire [7:0] ddrphy_dq_i_data1;
 230 reg  [7:0] ddrphy_dq_o_data1 = 8'd0;
 231 reg  [7:0] ddrphy_dq_o_data_d1 = 8'd0;
 232 reg  [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
 233 wire [3:0] ddrphy_bitslip1_i;
 234 reg  [3:0] ddrphy_bitslip1_o = 4'd0;
 235 reg  [1:0] ddrphy_bitslip1_value = 2'd0;
 236 reg  [7:0] ddrphy_bitslip1_r = 8'd0;
 237 reg  [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
 238 wire ddrphy_dq_o2;
 239 wire ddrphy_dq_i2;
 240 wire ddrphy_dq_oe_n2;
 241 wire ddrphy_dq_i_delayed2;
 242 wire [7:0] ddrphy_dq_i_data2;
 243 reg  [7:0] ddrphy_dq_o_data2 = 8'd0;
 244 reg  [7:0] ddrphy_dq_o_data_d2 = 8'd0;
 245 reg  [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
 246 wire [3:0] ddrphy_bitslip2_i;
 247 reg  [3:0] ddrphy_bitslip2_o = 4'd0;
 248 reg  [1:0] ddrphy_bitslip2_value = 2'd0;
 249 reg  [7:0] ddrphy_bitslip2_r = 8'd0;
 250 reg  [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
 251 wire ddrphy_dq_o3;
 252 wire ddrphy_dq_i3;
 253 wire ddrphy_dq_oe_n3;
 254 wire ddrphy_dq_i_delayed3;
 255 wire [7:0] ddrphy_dq_i_data3;
 256 reg  [7:0] ddrphy_dq_o_data3 = 8'd0;
 257 reg  [7:0] ddrphy_dq_o_data_d3 = 8'd0;
 258 reg  [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
 259 wire [3:0] ddrphy_bitslip3_i;
 260 reg  [3:0] ddrphy_bitslip3_o = 4'd0;
 261 reg  [1:0] ddrphy_bitslip3_value = 2'd0;
 262 reg  [7:0] ddrphy_bitslip3_r = 8'd0;
 263 reg  [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
 264 wire ddrphy_dq_o4;
 265 wire ddrphy_dq_i4;
 266 wire ddrphy_dq_oe_n4;
 267 wire ddrphy_dq_i_delayed4;
 268 wire [7:0] ddrphy_dq_i_data4;
 269 reg  [7:0] ddrphy_dq_o_data4 = 8'd0;
 270 reg  [7:0] ddrphy_dq_o_data_d4 = 8'd0;
 271 reg  [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
 272 wire [3:0] ddrphy_bitslip4_i;
 273 reg  [3:0] ddrphy_bitslip4_o = 4'd0;
 274 reg  [1:0] ddrphy_bitslip4_value = 2'd0;
 275 reg  [7:0] ddrphy_bitslip4_r = 8'd0;
 276 reg  [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
 277 wire ddrphy_dq_o5;
 278 wire ddrphy_dq_i5;
 279 wire ddrphy_dq_oe_n5;
 280 wire ddrphy_dq_i_delayed5;
 281 wire [7:0] ddrphy_dq_i_data5;
 282 reg  [7:0] ddrphy_dq_o_data5 = 8'd0;
 283 reg  [7:0] ddrphy_dq_o_data_d5 = 8'd0;
 284 reg  [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
 285 wire [3:0] ddrphy_bitslip5_i;
 286 reg  [3:0] ddrphy_bitslip5_o = 4'd0;
 287 reg  [1:0] ddrphy_bitslip5_value = 2'd0;
 288 reg  [7:0] ddrphy_bitslip5_r = 8'd0;
 289 reg  [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
 290 wire ddrphy_dq_o6;
 291 wire ddrphy_dq_i6;
 292 wire ddrphy_dq_oe_n6;
 293 wire ddrphy_dq_i_delayed6;
 294 wire [7:0] ddrphy_dq_i_data6;
 295 reg  [7:0] ddrphy_dq_o_data6 = 8'd0;
 296 reg  [7:0] ddrphy_dq_o_data_d6 = 8'd0;
 297 reg  [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
 298 wire [3:0] ddrphy_bitslip6_i;
 299 reg  [3:0] ddrphy_bitslip6_o = 4'd0;
 300 reg  [1:0] ddrphy_bitslip6_value = 2'd0;
 301 reg  [7:0] ddrphy_bitslip6_r = 8'd0;
 302 reg  [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
 303 wire ddrphy_dq_o7;
 304 wire ddrphy_dq_i7;
 305 wire ddrphy_dq_oe_n7;
 306 wire ddrphy_dq_i_delayed7;
 307 wire [7:0] ddrphy_dq_i_data7;
 308 reg  [7:0] ddrphy_dq_o_data7 = 8'd0;
 309 reg  [7:0] ddrphy_dq_o_data_d7 = 8'd0;
 310 reg  [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
 311 wire [3:0] ddrphy_bitslip7_i;
 312 reg  [3:0] ddrphy_bitslip7_o = 4'd0;
 313 reg  [1:0] ddrphy_bitslip7_value = 2'd0;
 314 reg  [7:0] ddrphy_bitslip7_r = 8'd0;
 315 reg  [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
 316 wire ddrphy_dqs_i1;
 317 wire ddrphy_dqsr901;
 318 wire ddrphy_dqsw2701;
 319 wire ddrphy_dqsw1;
 320 wire [2:0] ddrphy_rdpntr1;
 321 wire [2:0] ddrphy_wrpntr1;
 322 reg  [6:0] ddrphy_rdly1 = 7'd0;
 323 wire ddrphy_burstdet1;
 324 reg  ddrphy_burstdet_d1 = 1'd0;
 325 wire ddrphy_dqs1;
 326 wire ddrphy_dqs_oe_n1;
 327 reg  [7:0] ddrphy_dm_o_data1 = 8'd0;
 328 reg  [7:0] ddrphy_dm_o_data_d1 = 8'd0;
 329 reg  [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
 330 wire ddrphy_dq_o8;
 331 wire ddrphy_dq_i8;
 332 wire ddrphy_dq_oe_n8;
 333 wire ddrphy_dq_i_delayed8;
 334 wire [7:0] ddrphy_dq_i_data8;
 335 reg  [7:0] ddrphy_dq_o_data8 = 8'd0;
 336 reg  [7:0] ddrphy_dq_o_data_d8 = 8'd0;
 337 reg  [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
 338 wire [3:0] ddrphy_bitslip8_i;
 339 reg  [3:0] ddrphy_bitslip8_o = 4'd0;
 340 reg  [1:0] ddrphy_bitslip8_value = 2'd0;
 341 reg  [7:0] ddrphy_bitslip8_r = 8'd0;
 342 reg  [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
 343 wire ddrphy_dq_o9;
 344 wire ddrphy_dq_i9;
 345 wire ddrphy_dq_oe_n9;
 346 wire ddrphy_dq_i_delayed9;
 347 wire [7:0] ddrphy_dq_i_data9;
 348 reg  [7:0] ddrphy_dq_o_data9 = 8'd0;
 349 reg  [7:0] ddrphy_dq_o_data_d9 = 8'd0;
 350 reg  [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
 351 wire [3:0] ddrphy_bitslip9_i;
 352 reg  [3:0] ddrphy_bitslip9_o = 4'd0;
 353 reg  [1:0] ddrphy_bitslip9_value = 2'd0;
 354 reg  [7:0] ddrphy_bitslip9_r = 8'd0;
 355 reg  [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
 356 wire ddrphy_dq_o10;
 357 wire ddrphy_dq_i10;
 358 wire ddrphy_dq_oe_n10;
 359 wire ddrphy_dq_i_delayed10;
 360 wire [7:0] ddrphy_dq_i_data10;
 361 reg  [7:0] ddrphy_dq_o_data10 = 8'd0;
 362 reg  [7:0] ddrphy_dq_o_data_d10 = 8'd0;
 363 reg  [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
 364 wire [3:0] ddrphy_bitslip10_i;
 365 reg  [3:0] ddrphy_bitslip10_o = 4'd0;
 366 reg  [1:0] ddrphy_bitslip10_value = 2'd0;
 367 reg  [7:0] ddrphy_bitslip10_r = 8'd0;
 368 reg  [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
 369 wire ddrphy_dq_o11;
 370 wire ddrphy_dq_i11;
 371 wire ddrphy_dq_oe_n11;
 372 wire ddrphy_dq_i_delayed11;
 373 wire [7:0] ddrphy_dq_i_data11;
 374 reg  [7:0] ddrphy_dq_o_data11 = 8'd0;
 375 reg  [7:0] ddrphy_dq_o_data_d11 = 8'd0;
 376 reg  [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
 377 wire [3:0] ddrphy_bitslip11_i;
 378 reg  [3:0] ddrphy_bitslip11_o = 4'd0;
 379 reg  [1:0] ddrphy_bitslip11_value = 2'd0;
 380 reg  [7:0] ddrphy_bitslip11_r = 8'd0;
 381 reg  [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
 382 wire ddrphy_dq_o12;
 383 wire ddrphy_dq_i12;
 384 wire ddrphy_dq_oe_n12;
 385 wire ddrphy_dq_i_delayed12;
 386 wire [7:0] ddrphy_dq_i_data12;
 387 reg  [7:0] ddrphy_dq_o_data12 = 8'd0;
 388 reg  [7:0] ddrphy_dq_o_data_d12 = 8'd0;
 389 reg  [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
 390 wire [3:0] ddrphy_bitslip12_i;
 391 reg  [3:0] ddrphy_bitslip12_o = 4'd0;
 392 reg  [1:0] ddrphy_bitslip12_value = 2'd0;
 393 reg  [7:0] ddrphy_bitslip12_r = 8'd0;
 394 reg  [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
 395 wire ddrphy_dq_o13;
 396 wire ddrphy_dq_i13;
 397 wire ddrphy_dq_oe_n13;
 398 wire ddrphy_dq_i_delayed13;
 399 wire [7:0] ddrphy_dq_i_data13;
 400 reg  [7:0] ddrphy_dq_o_data13 = 8'd0;
 401 reg  [7:0] ddrphy_dq_o_data_d13 = 8'd0;
 402 reg  [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
 403 wire [3:0] ddrphy_bitslip13_i;
 404 reg  [3:0] ddrphy_bitslip13_o = 4'd0;
 405 reg  [1:0] ddrphy_bitslip13_value = 2'd0;
 406 reg  [7:0] ddrphy_bitslip13_r = 8'd0;
 407 reg  [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
 408 wire ddrphy_dq_o14;
 409 wire ddrphy_dq_i14;
 410 wire ddrphy_dq_oe_n14;
 411 wire ddrphy_dq_i_delayed14;
 412 wire [7:0] ddrphy_dq_i_data14;
 413 reg  [7:0] ddrphy_dq_o_data14 = 8'd0;
 414 reg  [7:0] ddrphy_dq_o_data_d14 = 8'd0;
 415 reg  [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
 416 wire [3:0] ddrphy_bitslip14_i;
 417 reg  [3:0] ddrphy_bitslip14_o = 4'd0;
 418 reg  [1:0] ddrphy_bitslip14_value = 2'd0;
 419 reg  [7:0] ddrphy_bitslip14_r = 8'd0;
 420 reg  [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
 421 wire ddrphy_dq_o15;
 422 wire ddrphy_dq_i15;
 423 wire ddrphy_dq_oe_n15;
 424 wire ddrphy_dq_i_delayed15;
 425 wire [7:0] ddrphy_dq_i_data15;
 426 reg  [7:0] ddrphy_dq_o_data15 = 8'd0;
 427 reg  [7:0] ddrphy_dq_o_data_d15 = 8'd0;
 428 reg  [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
 429 wire [3:0] ddrphy_bitslip15_i;
 430 reg  [3:0] ddrphy_bitslip15_o = 4'd0;
 431 reg  [1:0] ddrphy_bitslip15_value = 2'd0;
 432 reg  [7:0] ddrphy_bitslip15_r = 8'd0;
 433 reg  [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
 434 wire ddrphy_dqs_i2;
 435 wire ddrphy_dqsr902;
 436 wire ddrphy_dqsw2702;
 437 wire ddrphy_dqsw2;
 438 wire [2:0] ddrphy_rdpntr2;
 439 wire [2:0] ddrphy_wrpntr2;
 440 reg  [6:0] ddrphy_rdly2 = 7'd0;
 441 wire ddrphy_burstdet2;
 442 reg  ddrphy_burstdet_d2 = 1'd0;
 443 wire ddrphy_dqs2;
 444 wire ddrphy_dqs_oe_n2;
 445 reg  [7:0] ddrphy_dm_o_data2 = 8'd0;
 446 reg  [7:0] ddrphy_dm_o_data_d2 = 8'd0;
 447 reg  [3:0] ddrphy_dm_o_data_muxed2 = 4'd0;
 448 wire ddrphy_dq_o16;
 449 wire ddrphy_dq_i16;
 450 wire ddrphy_dq_oe_n16;
 451 wire ddrphy_dq_i_delayed16;
 452 wire [7:0] ddrphy_dq_i_data16;
 453 reg  [7:0] ddrphy_dq_o_data16 = 8'd0;
 454 reg  [7:0] ddrphy_dq_o_data_d16 = 8'd0;
 455 reg  [3:0] ddrphy_dq_o_data_muxed16 = 4'd0;
 456 wire [3:0] ddrphy_bitslip16_i;
 457 reg  [3:0] ddrphy_bitslip16_o = 4'd0;
 458 reg  [1:0] ddrphy_bitslip16_value = 2'd0;
 459 reg  [7:0] ddrphy_bitslip16_r = 8'd0;
 460 reg  [3:0] ddrphy_dq_i_bitslip_o_d16 = 4'd0;
 461 wire ddrphy_dq_o17;
 462 wire ddrphy_dq_i17;
 463 wire ddrphy_dq_oe_n17;
 464 wire ddrphy_dq_i_delayed17;
 465 wire [7:0] ddrphy_dq_i_data17;
 466 reg  [7:0] ddrphy_dq_o_data17 = 8'd0;
 467 reg  [7:0] ddrphy_dq_o_data_d17 = 8'd0;
 468 reg  [3:0] ddrphy_dq_o_data_muxed17 = 4'd0;
 469 wire [3:0] ddrphy_bitslip17_i;
 470 reg  [3:0] ddrphy_bitslip17_o = 4'd0;
 471 reg  [1:0] ddrphy_bitslip17_value = 2'd0;
 472 reg  [7:0] ddrphy_bitslip17_r = 8'd0;
 473 reg  [3:0] ddrphy_dq_i_bitslip_o_d17 = 4'd0;
 474 wire ddrphy_dq_o18;
 475 wire ddrphy_dq_i18;
 476 wire ddrphy_dq_oe_n18;
 477 wire ddrphy_dq_i_delayed18;
 478 wire [7:0] ddrphy_dq_i_data18;
 479 reg  [7:0] ddrphy_dq_o_data18 = 8'd0;
 480 reg  [7:0] ddrphy_dq_o_data_d18 = 8'd0;
 481 reg  [3:0] ddrphy_dq_o_data_muxed18 = 4'd0;
 482 wire [3:0] ddrphy_bitslip18_i;
 483 reg  [3:0] ddrphy_bitslip18_o = 4'd0;
 484 reg  [1:0] ddrphy_bitslip18_value = 2'd0;
 485 reg  [7:0] ddrphy_bitslip18_r = 8'd0;
 486 reg  [3:0] ddrphy_dq_i_bitslip_o_d18 = 4'd0;
 487 wire ddrphy_dq_o19;
 488 wire ddrphy_dq_i19;
 489 wire ddrphy_dq_oe_n19;
 490 wire ddrphy_dq_i_delayed19;
 491 wire [7:0] ddrphy_dq_i_data19;
 492 reg  [7:0] ddrphy_dq_o_data19 = 8'd0;
 493 reg  [7:0] ddrphy_dq_o_data_d19 = 8'd0;
 494 reg  [3:0] ddrphy_dq_o_data_muxed19 = 4'd0;
 495 wire [3:0] ddrphy_bitslip19_i;
 496 reg  [3:0] ddrphy_bitslip19_o = 4'd0;
 497 reg  [1:0] ddrphy_bitslip19_value = 2'd0;
 498 reg  [7:0] ddrphy_bitslip19_r = 8'd0;
 499 reg  [3:0] ddrphy_dq_i_bitslip_o_d19 = 4'd0;
 500 wire ddrphy_dq_o20;
 501 wire ddrphy_dq_i20;
 502 wire ddrphy_dq_oe_n20;
 503 wire ddrphy_dq_i_delayed20;
 504 wire [7:0] ddrphy_dq_i_data20;
 505 reg  [7:0] ddrphy_dq_o_data20 = 8'd0;
 506 reg  [7:0] ddrphy_dq_o_data_d20 = 8'd0;
 507 reg  [3:0] ddrphy_dq_o_data_muxed20 = 4'd0;
 508 wire [3:0] ddrphy_bitslip20_i;
 509 reg  [3:0] ddrphy_bitslip20_o = 4'd0;
 510 reg  [1:0] ddrphy_bitslip20_value = 2'd0;
 511 reg  [7:0] ddrphy_bitslip20_r = 8'd0;
 512 reg  [3:0] ddrphy_dq_i_bitslip_o_d20 = 4'd0;
 513 wire ddrphy_dq_o21;
 514 wire ddrphy_dq_i21;
 515 wire ddrphy_dq_oe_n21;
 516 wire ddrphy_dq_i_delayed21;
 517 wire [7:0] ddrphy_dq_i_data21;
 518 reg  [7:0] ddrphy_dq_o_data21 = 8'd0;
 519 reg  [7:0] ddrphy_dq_o_data_d21 = 8'd0;
 520 reg  [3:0] ddrphy_dq_o_data_muxed21 = 4'd0;
 521 wire [3:0] ddrphy_bitslip21_i;
 522 reg  [3:0] ddrphy_bitslip21_o = 4'd0;
 523 reg  [1:0] ddrphy_bitslip21_value = 2'd0;
 524 reg  [7:0] ddrphy_bitslip21_r = 8'd0;
 525 reg  [3:0] ddrphy_dq_i_bitslip_o_d21 = 4'd0;
 526 wire ddrphy_dq_o22;
 527 wire ddrphy_dq_i22;
 528 wire ddrphy_dq_oe_n22;
 529 wire ddrphy_dq_i_delayed22;
 530 wire [7:0] ddrphy_dq_i_data22;
 531 reg  [7:0] ddrphy_dq_o_data22 = 8'd0;
 532 reg  [7:0] ddrphy_dq_o_data_d22 = 8'd0;
 533 reg  [3:0] ddrphy_dq_o_data_muxed22 = 4'd0;
 534 wire [3:0] ddrphy_bitslip22_i;
 535 reg  [3:0] ddrphy_bitslip22_o = 4'd0;
 536 reg  [1:0] ddrphy_bitslip22_value = 2'd0;
 537 reg  [7:0] ddrphy_bitslip22_r = 8'd0;
 538 reg  [3:0] ddrphy_dq_i_bitslip_o_d22 = 4'd0;
 539 wire ddrphy_dq_o23;
 540 wire ddrphy_dq_i23;
 541 wire ddrphy_dq_oe_n23;
 542 wire ddrphy_dq_i_delayed23;
 543 wire [7:0] ddrphy_dq_i_data23;
 544 reg  [7:0] ddrphy_dq_o_data23 = 8'd0;
 545 reg  [7:0] ddrphy_dq_o_data_d23 = 8'd0;
 546 reg  [3:0] ddrphy_dq_o_data_muxed23 = 4'd0;
 547 wire [3:0] ddrphy_bitslip23_i;
 548 reg  [3:0] ddrphy_bitslip23_o = 4'd0;
 549 reg  [1:0] ddrphy_bitslip23_value = 2'd0;
 550 reg  [7:0] ddrphy_bitslip23_r = 8'd0;
 551 reg  [3:0] ddrphy_dq_i_bitslip_o_d23 = 4'd0;
 552 wire ddrphy_dqs_i3;
 553 wire ddrphy_dqsr903;
 554 wire ddrphy_dqsw2703;
 555 wire ddrphy_dqsw3;
 556 wire [2:0] ddrphy_rdpntr3;
 557 wire [2:0] ddrphy_wrpntr3;
 558 reg  [6:0] ddrphy_rdly3 = 7'd0;
 559 wire ddrphy_burstdet3;
 560 reg  ddrphy_burstdet_d3 = 1'd0;
 561 wire ddrphy_dqs3;
 562 wire ddrphy_dqs_oe_n3;
 563 reg  [7:0] ddrphy_dm_o_data3 = 8'd0;
 564 reg  [7:0] ddrphy_dm_o_data_d3 = 8'd0;
 565 reg  [3:0] ddrphy_dm_o_data_muxed3 = 4'd0;
 566 wire ddrphy_dq_o24;
 567 wire ddrphy_dq_i24;
 568 wire ddrphy_dq_oe_n24;
 569 wire ddrphy_dq_i_delayed24;
 570 wire [7:0] ddrphy_dq_i_data24;
 571 reg  [7:0] ddrphy_dq_o_data24 = 8'd0;
 572 reg  [7:0] ddrphy_dq_o_data_d24 = 8'd0;
 573 reg  [3:0] ddrphy_dq_o_data_muxed24 = 4'd0;
 574 wire [3:0] ddrphy_bitslip24_i;
 575 reg  [3:0] ddrphy_bitslip24_o = 4'd0;
 576 reg  [1:0] ddrphy_bitslip24_value = 2'd0;
 577 reg  [7:0] ddrphy_bitslip24_r = 8'd0;
 578 reg  [3:0] ddrphy_dq_i_bitslip_o_d24 = 4'd0;
 579 wire ddrphy_dq_o25;
 580 wire ddrphy_dq_i25;
 581 wire ddrphy_dq_oe_n25;
 582 wire ddrphy_dq_i_delayed25;
 583 wire [7:0] ddrphy_dq_i_data25;
 584 reg  [7:0] ddrphy_dq_o_data25 = 8'd0;
 585 reg  [7:0] ddrphy_dq_o_data_d25 = 8'd0;
 586 reg  [3:0] ddrphy_dq_o_data_muxed25 = 4'd0;
 587 wire [3:0] ddrphy_bitslip25_i;
 588 reg  [3:0] ddrphy_bitslip25_o = 4'd0;
 589 reg  [1:0] ddrphy_bitslip25_value = 2'd0;
 590 reg  [7:0] ddrphy_bitslip25_r = 8'd0;
 591 reg  [3:0] ddrphy_dq_i_bitslip_o_d25 = 4'd0;
 592 wire ddrphy_dq_o26;
 593 wire ddrphy_dq_i26;
 594 wire ddrphy_dq_oe_n26;
 595 wire ddrphy_dq_i_delayed26;
 596 wire [7:0] ddrphy_dq_i_data26;
 597 reg  [7:0] ddrphy_dq_o_data26 = 8'd0;
 598 reg  [7:0] ddrphy_dq_o_data_d26 = 8'd0;
 599 reg  [3:0] ddrphy_dq_o_data_muxed26 = 4'd0;
 600 wire [3:0] ddrphy_bitslip26_i;
 601 reg  [3:0] ddrphy_bitslip26_o = 4'd0;
 602 reg  [1:0] ddrphy_bitslip26_value = 2'd0;
 603 reg  [7:0] ddrphy_bitslip26_r = 8'd0;
 604 reg  [3:0] ddrphy_dq_i_bitslip_o_d26 = 4'd0;
 605 wire ddrphy_dq_o27;
 606 wire ddrphy_dq_i27;
 607 wire ddrphy_dq_oe_n27;
 608 wire ddrphy_dq_i_delayed27;
 609 wire [7:0] ddrphy_dq_i_data27;
 610 reg  [7:0] ddrphy_dq_o_data27 = 8'd0;
 611 reg  [7:0] ddrphy_dq_o_data_d27 = 8'd0;
 612 reg  [3:0] ddrphy_dq_o_data_muxed27 = 4'd0;
 613 wire [3:0] ddrphy_bitslip27_i;
 614 reg  [3:0] ddrphy_bitslip27_o = 4'd0;
 615 reg  [1:0] ddrphy_bitslip27_value = 2'd0;
 616 reg  [7:0] ddrphy_bitslip27_r = 8'd0;
 617 reg  [3:0] ddrphy_dq_i_bitslip_o_d27 = 4'd0;
 618 wire ddrphy_dq_o28;
 619 wire ddrphy_dq_i28;
 620 wire ddrphy_dq_oe_n28;
 621 wire ddrphy_dq_i_delayed28;
 622 wire [7:0] ddrphy_dq_i_data28;
 623 reg  [7:0] ddrphy_dq_o_data28 = 8'd0;
 624 reg  [7:0] ddrphy_dq_o_data_d28 = 8'd0;
 625 reg  [3:0] ddrphy_dq_o_data_muxed28 = 4'd0;
 626 wire [3:0] ddrphy_bitslip28_i;
 627 reg  [3:0] ddrphy_bitslip28_o = 4'd0;
 628 reg  [1:0] ddrphy_bitslip28_value = 2'd0;
 629 reg  [7:0] ddrphy_bitslip28_r = 8'd0;
 630 reg  [3:0] ddrphy_dq_i_bitslip_o_d28 = 4'd0;
 631 wire ddrphy_dq_o29;
 632 wire ddrphy_dq_i29;
 633 wire ddrphy_dq_oe_n29;
 634 wire ddrphy_dq_i_delayed29;
 635 wire [7:0] ddrphy_dq_i_data29;
 636 reg  [7:0] ddrphy_dq_o_data29 = 8'd0;
 637 reg  [7:0] ddrphy_dq_o_data_d29 = 8'd0;
 638 reg  [3:0] ddrphy_dq_o_data_muxed29 = 4'd0;
 639 wire [3:0] ddrphy_bitslip29_i;
 640 reg  [3:0] ddrphy_bitslip29_o = 4'd0;
 641 reg  [1:0] ddrphy_bitslip29_value = 2'd0;
 642 reg  [7:0] ddrphy_bitslip29_r = 8'd0;
 643 reg  [3:0] ddrphy_dq_i_bitslip_o_d29 = 4'd0;
 644 wire ddrphy_dq_o30;
 645 wire ddrphy_dq_i30;
 646 wire ddrphy_dq_oe_n30;
 647 wire ddrphy_dq_i_delayed30;
 648 wire [7:0] ddrphy_dq_i_data30;
 649 reg  [7:0] ddrphy_dq_o_data30 = 8'd0;
 650 reg  [7:0] ddrphy_dq_o_data_d30 = 8'd0;
 651 reg  [3:0] ddrphy_dq_o_data_muxed30 = 4'd0;
 652 wire [3:0] ddrphy_bitslip30_i;
 653 reg  [3:0] ddrphy_bitslip30_o = 4'd0;
 654 reg  [1:0] ddrphy_bitslip30_value = 2'd0;
 655 reg  [7:0] ddrphy_bitslip30_r = 8'd0;
 656 reg  [3:0] ddrphy_dq_i_bitslip_o_d30 = 4'd0;
 657 wire ddrphy_dq_o31;
 658 wire ddrphy_dq_i31;
 659 wire ddrphy_dq_oe_n31;
 660 wire ddrphy_dq_i_delayed31;
 661 wire [7:0] ddrphy_dq_i_data31;
 662 reg  [7:0] ddrphy_dq_o_data31 = 8'd0;
 663 reg  [7:0] ddrphy_dq_o_data_d31 = 8'd0;
 664 reg  [3:0] ddrphy_dq_o_data_muxed31 = 4'd0;
 665 wire [3:0] ddrphy_bitslip31_i;
 666 reg  [3:0] ddrphy_bitslip31_o = 4'd0;
 667 reg  [1:0] ddrphy_bitslip31_value = 2'd0;
 668 reg  [7:0] ddrphy_bitslip31_r = 8'd0;
 669 reg  [3:0] ddrphy_dq_i_bitslip_o_d31 = 4'd0;
 670 reg  ddrphy_rddata_en_tappeddelayline0 = 1'd0;
 671 reg  ddrphy_rddata_en_tappeddelayline1 = 1'd0;
 672 reg  ddrphy_rddata_en_tappeddelayline2 = 1'd0;
 673 reg  ddrphy_rddata_en_tappeddelayline3 = 1'd0;
 674 reg  ddrphy_rddata_en_tappeddelayline4 = 1'd0;
 675 reg  ddrphy_rddata_en_tappeddelayline5 = 1'd0;
 676 reg  ddrphy_rddata_en_tappeddelayline6 = 1'd0;
 677 reg  ddrphy_rddata_en_tappeddelayline7 = 1'd0;
 678 reg  ddrphy_rddata_en_tappeddelayline8 = 1'd0;
 679 reg  ddrphy_rddata_en_tappeddelayline9 = 1'd0;
 680 reg  ddrphy_rddata_en_tappeddelayline10 = 1'd0;
 681 reg  ddrphy_rddata_en_tappeddelayline11 = 1'd0;
 682 reg  ddrphy_rddata_en_tappeddelayline12 = 1'd0;
 683 reg  ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
 684 reg  ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
 685 reg  ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
 686 reg  ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
 687 reg  ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
 688 reg  ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
 689 reg  ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
 690 wire [14:0] litedramcore_inti_p0_address;
 691 wire [2:0] litedramcore_inti_p0_bank;
 692 reg  litedramcore_inti_p0_cas_n = 1'd1;
 693 reg  litedramcore_inti_p0_cs_n = 1'd1;
 694 reg  litedramcore_inti_p0_ras_n = 1'd1;
 695 reg  litedramcore_inti_p0_we_n = 1'd1;
 696 wire litedramcore_inti_p0_cke;
 697 wire litedramcore_inti_p0_odt;
 698 wire litedramcore_inti_p0_reset_n;
 699 reg  litedramcore_inti_p0_act_n = 1'd1;
 700 wire [127:0] litedramcore_inti_p0_wrdata;
 701 wire litedramcore_inti_p0_wrdata_en;
 702 wire [15:0] litedramcore_inti_p0_wrdata_mask;
 703 wire litedramcore_inti_p0_rddata_en;
 704 reg  [127:0] litedramcore_inti_p0_rddata = 128'd0;
 705 reg  litedramcore_inti_p0_rddata_valid = 1'd0;
 706 wire [14:0] litedramcore_inti_p1_address;
 707 wire [2:0] litedramcore_inti_p1_bank;
 708 reg  litedramcore_inti_p1_cas_n = 1'd1;
 709 reg  litedramcore_inti_p1_cs_n = 1'd1;
 710 reg  litedramcore_inti_p1_ras_n = 1'd1;
 711 reg  litedramcore_inti_p1_we_n = 1'd1;
 712 wire litedramcore_inti_p1_cke;
 713 wire litedramcore_inti_p1_odt;
 714 wire litedramcore_inti_p1_reset_n;
 715 reg  litedramcore_inti_p1_act_n = 1'd1;
 716 wire [127:0] litedramcore_inti_p1_wrdata;
 717 wire litedramcore_inti_p1_wrdata_en;
 718 wire [15:0] litedramcore_inti_p1_wrdata_mask;
 719 wire litedramcore_inti_p1_rddata_en;
 720 reg  [127:0] litedramcore_inti_p1_rddata = 128'd0;
 721 reg  litedramcore_inti_p1_rddata_valid = 1'd0;
 722 wire [14:0] litedramcore_slave_p0_address;
 723 wire [2:0] litedramcore_slave_p0_bank;
 724 wire litedramcore_slave_p0_cas_n;
 725 wire litedramcore_slave_p0_cs_n;
 726 wire litedramcore_slave_p0_ras_n;
 727 wire litedramcore_slave_p0_we_n;
 728 wire litedramcore_slave_p0_cke;
 729 wire litedramcore_slave_p0_odt;
 730 wire litedramcore_slave_p0_reset_n;
 731 wire litedramcore_slave_p0_act_n;
 732 wire [127:0] litedramcore_slave_p0_wrdata;
 733 wire litedramcore_slave_p0_wrdata_en;
 734 wire [15:0] litedramcore_slave_p0_wrdata_mask;
 735 wire litedramcore_slave_p0_rddata_en;
 736 reg  [127:0] litedramcore_slave_p0_rddata = 128'd0;
 737 reg  litedramcore_slave_p0_rddata_valid = 1'd0;
 738 wire [14:0] litedramcore_slave_p1_address;
 739 wire [2:0] litedramcore_slave_p1_bank;
 740 wire litedramcore_slave_p1_cas_n;
 741 wire litedramcore_slave_p1_cs_n;
 742 wire litedramcore_slave_p1_ras_n;
 743 wire litedramcore_slave_p1_we_n;
 744 wire litedramcore_slave_p1_cke;
 745 wire litedramcore_slave_p1_odt;
 746 wire litedramcore_slave_p1_reset_n;
 747 wire litedramcore_slave_p1_act_n;
 748 wire [127:0] litedramcore_slave_p1_wrdata;
 749 wire litedramcore_slave_p1_wrdata_en;
 750 wire [15:0] litedramcore_slave_p1_wrdata_mask;
 751 wire litedramcore_slave_p1_rddata_en;
 752 reg  [127:0] litedramcore_slave_p1_rddata = 128'd0;
 753 reg  litedramcore_slave_p1_rddata_valid = 1'd0;
 754 reg  [14:0] litedramcore_master_p0_address = 15'd0;
 755 reg  [2:0] litedramcore_master_p0_bank = 3'd0;
 756 reg  litedramcore_master_p0_cas_n = 1'd1;
 757 reg  litedramcore_master_p0_cs_n = 1'd1;
 758 reg  litedramcore_master_p0_ras_n = 1'd1;
 759 reg  litedramcore_master_p0_we_n = 1'd1;
 760 reg  litedramcore_master_p0_cke = 1'd0;
 761 reg  litedramcore_master_p0_odt = 1'd0;
 762 reg  litedramcore_master_p0_reset_n = 1'd0;
 763 reg  litedramcore_master_p0_act_n = 1'd1;
 764 reg  [127:0] litedramcore_master_p0_wrdata = 128'd0;
 765 reg  litedramcore_master_p0_wrdata_en = 1'd0;
 766 reg  [15:0] litedramcore_master_p0_wrdata_mask = 16'd0;
 767 reg  litedramcore_master_p0_rddata_en = 1'd0;
 768 wire [127:0] litedramcore_master_p0_rddata;
 769 wire litedramcore_master_p0_rddata_valid;
 770 reg  [14:0] litedramcore_master_p1_address = 15'd0;
 771 reg  [2:0] litedramcore_master_p1_bank = 3'd0;
 772 reg  litedramcore_master_p1_cas_n = 1'd1;
 773 reg  litedramcore_master_p1_cs_n = 1'd1;
 774 reg  litedramcore_master_p1_ras_n = 1'd1;
 775 reg  litedramcore_master_p1_we_n = 1'd1;
 776 reg  litedramcore_master_p1_cke = 1'd0;
 777 reg  litedramcore_master_p1_odt = 1'd0;
 778 reg  litedramcore_master_p1_reset_n = 1'd0;
 779 reg  litedramcore_master_p1_act_n = 1'd1;
 780 reg  [127:0] litedramcore_master_p1_wrdata = 128'd0;
 781 reg  litedramcore_master_p1_wrdata_en = 1'd0;
 782 reg  [15:0] litedramcore_master_p1_wrdata_mask = 16'd0;
 783 reg  litedramcore_master_p1_rddata_en = 1'd0;
 784 wire [127:0] litedramcore_master_p1_rddata;
 785 wire litedramcore_master_p1_rddata_valid;
 786 wire litedramcore_sel;
 787 wire litedramcore_cke;
 788 wire litedramcore_odt;
 789 wire litedramcore_reset_n;
 790 reg  [3:0] litedramcore_storage = 4'd1;
 791 reg  litedramcore_re = 1'd0;
 792 reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
 793 reg  litedramcore_phaseinjector0_command_re = 1'd0;
 794 reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
 795 wire litedramcore_phaseinjector0_command_issue_r;
 796 reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
 797 reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
 798 reg  [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
 799 reg  litedramcore_phaseinjector0_address_re = 1'd0;
 800 reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
 801 reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
 802 reg  [127:0] litedramcore_phaseinjector0_wrdata_storage = 128'd0;
 803 reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
 804 reg  [127:0] litedramcore_phaseinjector0_rddata_status = 128'd0;
 805 wire litedramcore_phaseinjector0_rddata_we;
 806 reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
 807 reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
 808 reg  litedramcore_phaseinjector1_command_re = 1'd0;
 809 reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
 810 wire litedramcore_phaseinjector1_command_issue_r;
 811 reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
 812 reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
 813 reg  [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
 814 reg  litedramcore_phaseinjector1_address_re = 1'd0;
 815 reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
 816 reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
 817 reg  [127:0] litedramcore_phaseinjector1_wrdata_storage = 128'd0;
 818 reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
 819 reg  [127:0] litedramcore_phaseinjector1_rddata_status = 128'd0;
 820 wire litedramcore_phaseinjector1_rddata_we;
 821 reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
 822 wire litedramcore_interface_bank0_valid;
 823 wire litedramcore_interface_bank0_ready;
 824 wire litedramcore_interface_bank0_we;
 825 wire [21:0] litedramcore_interface_bank0_addr;
 826 wire litedramcore_interface_bank0_lock;
 827 wire litedramcore_interface_bank0_wdata_ready;
 828 wire litedramcore_interface_bank0_rdata_valid;
 829 wire litedramcore_interface_bank1_valid;
 830 wire litedramcore_interface_bank1_ready;
 831 wire litedramcore_interface_bank1_we;
 832 wire [21:0] litedramcore_interface_bank1_addr;
 833 wire litedramcore_interface_bank1_lock;
 834 wire litedramcore_interface_bank1_wdata_ready;
 835 wire litedramcore_interface_bank1_rdata_valid;
 836 wire litedramcore_interface_bank2_valid;
 837 wire litedramcore_interface_bank2_ready;
 838 wire litedramcore_interface_bank2_we;
 839 wire [21:0] litedramcore_interface_bank2_addr;
 840 wire litedramcore_interface_bank2_lock;
 841 wire litedramcore_interface_bank2_wdata_ready;
 842 wire litedramcore_interface_bank2_rdata_valid;
 843 wire litedramcore_interface_bank3_valid;
 844 wire litedramcore_interface_bank3_ready;
 845 wire litedramcore_interface_bank3_we;
 846 wire [21:0] litedramcore_interface_bank3_addr;
 847 wire litedramcore_interface_bank3_lock;
 848 wire litedramcore_interface_bank3_wdata_ready;
 849 wire litedramcore_interface_bank3_rdata_valid;
 850 wire litedramcore_interface_bank4_valid;
 851 wire litedramcore_interface_bank4_ready;
 852 wire litedramcore_interface_bank4_we;
 853 wire [21:0] litedramcore_interface_bank4_addr;
 854 wire litedramcore_interface_bank4_lock;
 855 wire litedramcore_interface_bank4_wdata_ready;
 856 wire litedramcore_interface_bank4_rdata_valid;
 857 wire litedramcore_interface_bank5_valid;
 858 wire litedramcore_interface_bank5_ready;
 859 wire litedramcore_interface_bank5_we;
 860 wire [21:0] litedramcore_interface_bank5_addr;
 861 wire litedramcore_interface_bank5_lock;
 862 wire litedramcore_interface_bank5_wdata_ready;
 863 wire litedramcore_interface_bank5_rdata_valid;
 864 wire litedramcore_interface_bank6_valid;
 865 wire litedramcore_interface_bank6_ready;
 866 wire litedramcore_interface_bank6_we;
 867 wire [21:0] litedramcore_interface_bank6_addr;
 868 wire litedramcore_interface_bank6_lock;
 869 wire litedramcore_interface_bank6_wdata_ready;
 870 wire litedramcore_interface_bank6_rdata_valid;
 871 wire litedramcore_interface_bank7_valid;
 872 wire litedramcore_interface_bank7_ready;
 873 wire litedramcore_interface_bank7_we;
 874 wire [21:0] litedramcore_interface_bank7_addr;
 875 wire litedramcore_interface_bank7_lock;
 876 wire litedramcore_interface_bank7_wdata_ready;
 877 wire litedramcore_interface_bank7_rdata_valid;
 878 reg  [255:0] litedramcore_interface_wdata = 256'd0;
 879 reg  [31:0] litedramcore_interface_wdata_we = 32'd0;
 880 wire [255:0] litedramcore_interface_rdata;
 881 reg  [14:0] litedramcore_dfi_p0_address = 15'd0;
 882 reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
 883 reg  litedramcore_dfi_p0_cas_n = 1'd1;
 884 reg  litedramcore_dfi_p0_cs_n = 1'd1;
 885 reg  litedramcore_dfi_p0_ras_n = 1'd1;
 886 reg  litedramcore_dfi_p0_we_n = 1'd1;
 887 wire litedramcore_dfi_p0_cke;
 888 wire litedramcore_dfi_p0_odt;
 889 wire litedramcore_dfi_p0_reset_n;
 890 reg  litedramcore_dfi_p0_act_n = 1'd1;
 891 wire [127:0] litedramcore_dfi_p0_wrdata;
 892 reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
 893 wire [15:0] litedramcore_dfi_p0_wrdata_mask;
 894 reg  litedramcore_dfi_p0_rddata_en = 1'd0;
 895 wire [127:0] litedramcore_dfi_p0_rddata;
 896 wire litedramcore_dfi_p0_rddata_valid;
 897 reg  [14:0] litedramcore_dfi_p1_address = 15'd0;
 898 reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
 899 reg  litedramcore_dfi_p1_cas_n = 1'd1;
 900 reg  litedramcore_dfi_p1_cs_n = 1'd1;
 901 reg  litedramcore_dfi_p1_ras_n = 1'd1;
 902 reg  litedramcore_dfi_p1_we_n = 1'd1;
 903 wire litedramcore_dfi_p1_cke;
 904 wire litedramcore_dfi_p1_odt;
 905 wire litedramcore_dfi_p1_reset_n;
 906 reg  litedramcore_dfi_p1_act_n = 1'd1;
 907 wire [127:0] litedramcore_dfi_p1_wrdata;
 908 reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
 909 wire [15:0] litedramcore_dfi_p1_wrdata_mask;
 910 reg  litedramcore_dfi_p1_rddata_en = 1'd0;
 911 wire [127:0] litedramcore_dfi_p1_rddata;
 912 wire litedramcore_dfi_p1_rddata_valid;
 913 reg  litedramcore_cmd_valid = 1'd0;
 914 reg  litedramcore_cmd_ready = 1'd0;
 915 reg  litedramcore_cmd_last = 1'd0;
 916 reg  [14:0] litedramcore_cmd_payload_a = 15'd0;
 917 reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
 918 reg  litedramcore_cmd_payload_cas = 1'd0;
 919 reg  litedramcore_cmd_payload_ras = 1'd0;
 920 reg  litedramcore_cmd_payload_we = 1'd0;
 921 reg  litedramcore_cmd_payload_is_read = 1'd0;
 922 reg  litedramcore_cmd_payload_is_write = 1'd0;
 923 wire litedramcore_wants_refresh;
 924 wire litedramcore_wants_zqcs;
 925 wire litedramcore_timer_wait;
 926 wire litedramcore_timer_done0;
 927 wire [8:0] litedramcore_timer_count0;
 928 wire litedramcore_timer_done1;
 929 reg  [8:0] litedramcore_timer_count1 = 9'd374;
 930 wire litedramcore_postponer_req_i;
 931 reg  litedramcore_postponer_req_o = 1'd0;
 932 reg  litedramcore_postponer_count = 1'd0;
 933 reg  litedramcore_sequencer_start0 = 1'd0;
 934 wire litedramcore_sequencer_done0;
 935 wire litedramcore_sequencer_start1;
 936 reg  litedramcore_sequencer_done1 = 1'd0;
 937 reg  [6:0] litedramcore_sequencer_counter = 7'd0;
 938 reg  litedramcore_sequencer_count = 1'd0;
 939 wire litedramcore_zqcs_timer_wait;
 940 wire litedramcore_zqcs_timer_done0;
 941 wire [25:0] litedramcore_zqcs_timer_count0;
 942 wire litedramcore_zqcs_timer_done1;
 943 reg  [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
 944 reg  litedramcore_zqcs_executer_start = 1'd0;
 945 reg  litedramcore_zqcs_executer_done = 1'd0;
 946 reg  [5:0] litedramcore_zqcs_executer_counter = 6'd0;
 947 wire litedramcore_bankmachine0_req_valid;
 948 wire litedramcore_bankmachine0_req_ready;
 949 wire litedramcore_bankmachine0_req_we;
 950 wire [21:0] litedramcore_bankmachine0_req_addr;
 951 wire litedramcore_bankmachine0_req_lock;
 952 reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
 953 reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
 954 wire litedramcore_bankmachine0_refresh_req;
 955 reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
 956 reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
 957 reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
 958 reg  [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
 959 wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
 960 reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
 961 reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
 962 reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
 963 reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
 964 reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
 965 reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
 966 reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
 967 wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
 968 wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
 969 reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
 970 reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 971 wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 972 wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 973 wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
 974 wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 975 wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
 976 wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
 977 wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
 978 wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
 979 wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
 980 wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
 981 wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 982 wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 983 wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 984 wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
 985 reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
 986 reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
 987 reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
 988 reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
 989 reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
 990 wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 991 wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
 992 wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
 993 wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
 994 wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
 995 wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
 996 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
 997 wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
 998 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
 999 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
1000 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
1001 wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
1002 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
1003 wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
1004 wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
1005 wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
1006 wire litedramcore_bankmachine0_cmd_buffer_sink_first;
1007 wire litedramcore_bankmachine0_cmd_buffer_sink_last;
1008 wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
1009 wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
1010 reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
1011 wire litedramcore_bankmachine0_cmd_buffer_source_ready;
1012 reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
1013 reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
1014 reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
1015 reg  [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
1016 reg  [14:0] litedramcore_bankmachine0_row = 15'd0;
1017 reg  litedramcore_bankmachine0_row_opened = 1'd0;
1018 wire litedramcore_bankmachine0_row_hit;
1019 reg  litedramcore_bankmachine0_row_open = 1'd0;
1020 reg  litedramcore_bankmachine0_row_close = 1'd0;
1021 reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
1022 wire litedramcore_bankmachine0_twtpcon_valid;
1023 reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
1024 reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
1025 wire litedramcore_bankmachine0_trccon_valid;
1026 reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
1027 reg  [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
1028 wire litedramcore_bankmachine0_trascon_valid;
1029 reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
1030 reg  [1:0] litedramcore_bankmachine0_trascon_count = 2'd0;
1031 wire litedramcore_bankmachine1_req_valid;
1032 wire litedramcore_bankmachine1_req_ready;
1033 wire litedramcore_bankmachine1_req_we;
1034 wire [21:0] litedramcore_bankmachine1_req_addr;
1035 wire litedramcore_bankmachine1_req_lock;
1036 reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
1037 reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
1038 wire litedramcore_bankmachine1_refresh_req;
1039 reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
1040 reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
1041 reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
1042 reg  [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
1043 wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
1044 reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
1045 reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
1046 reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
1047 reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
1048 reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
1049 reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
1050 reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
1051 wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
1052 wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
1053 reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
1054 reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
1055 wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
1056 wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
1057 wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
1058 wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
1059 wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
1060 wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
1061 wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
1062 wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
1063 wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
1064 wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
1065 wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
1066 wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
1067 wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
1068 wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
1069 reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
1070 reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
1071 reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
1072 reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
1073 reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
1074 wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
1075 wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
1076 wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
1077 wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
1078 wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
1079 wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
1080 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
1081 wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
1082 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
1083 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
1084 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
1085 wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
1086 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
1087 wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
1088 wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
1089 wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
1090 wire litedramcore_bankmachine1_cmd_buffer_sink_first;
1091 wire litedramcore_bankmachine1_cmd_buffer_sink_last;
1092 wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
1093 wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
1094 reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
1095 wire litedramcore_bankmachine1_cmd_buffer_source_ready;
1096 reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
1097 reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
1098 reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
1099 reg  [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
1100 reg  [14:0] litedramcore_bankmachine1_row = 15'd0;
1101 reg  litedramcore_bankmachine1_row_opened = 1'd0;
1102 wire litedramcore_bankmachine1_row_hit;
1103 reg  litedramcore_bankmachine1_row_open = 1'd0;
1104 reg  litedramcore_bankmachine1_row_close = 1'd0;
1105 reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
1106 wire litedramcore_bankmachine1_twtpcon_valid;
1107 reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
1108 reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
1109 wire litedramcore_bankmachine1_trccon_valid;
1110 reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
1111 reg  [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
1112 wire litedramcore_bankmachine1_trascon_valid;
1113 reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
1114 reg  [1:0] litedramcore_bankmachine1_trascon_count = 2'd0;
1115 wire litedramcore_bankmachine2_req_valid;
1116 wire litedramcore_bankmachine2_req_ready;
1117 wire litedramcore_bankmachine2_req_we;
1118 wire [21:0] litedramcore_bankmachine2_req_addr;
1119 wire litedramcore_bankmachine2_req_lock;
1120 reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
1121 reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
1122 wire litedramcore_bankmachine2_refresh_req;
1123 reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
1124 reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
1125 reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
1126 reg  [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
1127 wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
1128 reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
1129 reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
1130 reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
1131 reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
1132 reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
1133 reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
1134 reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
1135 wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
1136 wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
1137 reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
1138 reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
1139 wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
1140 wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
1141 wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
1142 wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
1143 wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
1144 wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
1145 wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
1146 wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
1147 wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
1148 wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
1149 wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
1150 wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
1151 wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
1152 wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
1153 reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
1154 reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
1155 reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
1156 reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
1157 reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
1158 wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
1159 wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
1160 wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
1161 wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
1162 wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
1163 wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
1164 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
1165 wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
1166 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
1167 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
1168 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
1169 wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
1170 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
1171 wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
1172 wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
1173 wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
1174 wire litedramcore_bankmachine2_cmd_buffer_sink_first;
1175 wire litedramcore_bankmachine2_cmd_buffer_sink_last;
1176 wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
1177 wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
1178 reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
1179 wire litedramcore_bankmachine2_cmd_buffer_source_ready;
1180 reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
1181 reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
1182 reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
1183 reg  [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
1184 reg  [14:0] litedramcore_bankmachine2_row = 15'd0;
1185 reg  litedramcore_bankmachine2_row_opened = 1'd0;
1186 wire litedramcore_bankmachine2_row_hit;
1187 reg  litedramcore_bankmachine2_row_open = 1'd0;
1188 reg  litedramcore_bankmachine2_row_close = 1'd0;
1189 reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
1190 wire litedramcore_bankmachine2_twtpcon_valid;
1191 reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
1192 reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
1193 wire litedramcore_bankmachine2_trccon_valid;
1194 reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
1195 reg  [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
1196 wire litedramcore_bankmachine2_trascon_valid;
1197 reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
1198 reg  [1:0] litedramcore_bankmachine2_trascon_count = 2'd0;
1199 wire litedramcore_bankmachine3_req_valid;
1200 wire litedramcore_bankmachine3_req_ready;
1201 wire litedramcore_bankmachine3_req_we;
1202 wire [21:0] litedramcore_bankmachine3_req_addr;
1203 wire litedramcore_bankmachine3_req_lock;
1204 reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
1205 reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
1206 wire litedramcore_bankmachine3_refresh_req;
1207 reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
1208 reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
1209 reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
1210 reg  [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
1211 wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
1212 reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
1213 reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
1214 reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
1215 reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
1216 reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
1217 reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
1218 reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
1219 wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
1220 wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
1221 reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
1222 reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
1223 wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
1224 wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
1225 wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
1226 wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
1227 wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
1228 wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
1229 wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
1230 wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
1231 wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
1232 wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
1233 wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
1234 wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
1235 wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
1236 wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
1237 reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
1238 reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
1239 reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
1240 reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
1241 reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
1242 wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
1243 wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
1244 wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
1245 wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
1246 wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
1247 wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
1248 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
1249 wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
1250 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
1251 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
1252 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
1253 wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
1254 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
1255 wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
1256 wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
1257 wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
1258 wire litedramcore_bankmachine3_cmd_buffer_sink_first;
1259 wire litedramcore_bankmachine3_cmd_buffer_sink_last;
1260 wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
1261 wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
1262 reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
1263 wire litedramcore_bankmachine3_cmd_buffer_source_ready;
1264 reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
1265 reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
1266 reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
1267 reg  [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
1268 reg  [14:0] litedramcore_bankmachine3_row = 15'd0;
1269 reg  litedramcore_bankmachine3_row_opened = 1'd0;
1270 wire litedramcore_bankmachine3_row_hit;
1271 reg  litedramcore_bankmachine3_row_open = 1'd0;
1272 reg  litedramcore_bankmachine3_row_close = 1'd0;
1273 reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
1274 wire litedramcore_bankmachine3_twtpcon_valid;
1275 reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
1276 reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
1277 wire litedramcore_bankmachine3_trccon_valid;
1278 reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
1279 reg  [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
1280 wire litedramcore_bankmachine3_trascon_valid;
1281 reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
1282 reg  [1:0] litedramcore_bankmachine3_trascon_count = 2'd0;
1283 wire litedramcore_bankmachine4_req_valid;
1284 wire litedramcore_bankmachine4_req_ready;
1285 wire litedramcore_bankmachine4_req_we;
1286 wire [21:0] litedramcore_bankmachine4_req_addr;
1287 wire litedramcore_bankmachine4_req_lock;
1288 reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
1289 reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
1290 wire litedramcore_bankmachine4_refresh_req;
1291 reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
1292 reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
1293 reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
1294 reg  [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
1295 wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
1296 reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
1297 reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
1298 reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
1299 reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
1300 reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
1301 reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
1302 reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
1303 wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
1304 wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
1305 reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
1306 reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
1307 wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
1308 wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
1309 wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
1310 wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
1311 wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
1312 wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
1313 wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
1314 wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
1315 wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
1316 wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
1317 wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
1318 wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
1319 wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
1320 wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
1321 reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
1322 reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
1323 reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
1324 reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
1325 reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
1326 wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
1327 wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
1328 wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
1329 wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
1330 wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
1331 wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
1332 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
1333 wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
1334 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
1335 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
1336 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
1337 wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
1338 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
1339 wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
1340 wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
1341 wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
1342 wire litedramcore_bankmachine4_cmd_buffer_sink_first;
1343 wire litedramcore_bankmachine4_cmd_buffer_sink_last;
1344 wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
1345 wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
1346 reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
1347 wire litedramcore_bankmachine4_cmd_buffer_source_ready;
1348 reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
1349 reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
1350 reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
1351 reg  [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
1352 reg  [14:0] litedramcore_bankmachine4_row = 15'd0;
1353 reg  litedramcore_bankmachine4_row_opened = 1'd0;
1354 wire litedramcore_bankmachine4_row_hit;
1355 reg  litedramcore_bankmachine4_row_open = 1'd0;
1356 reg  litedramcore_bankmachine4_row_close = 1'd0;
1357 reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
1358 wire litedramcore_bankmachine4_twtpcon_valid;
1359 reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
1360 reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
1361 wire litedramcore_bankmachine4_trccon_valid;
1362 reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
1363 reg  [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
1364 wire litedramcore_bankmachine4_trascon_valid;
1365 reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
1366 reg  [1:0] litedramcore_bankmachine4_trascon_count = 2'd0;
1367 wire litedramcore_bankmachine5_req_valid;
1368 wire litedramcore_bankmachine5_req_ready;
1369 wire litedramcore_bankmachine5_req_we;
1370 wire [21:0] litedramcore_bankmachine5_req_addr;
1371 wire litedramcore_bankmachine5_req_lock;
1372 reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
1373 reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
1374 wire litedramcore_bankmachine5_refresh_req;
1375 reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
1376 reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
1377 reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
1378 reg  [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
1379 wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
1380 reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
1381 reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
1382 reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
1383 reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
1384 reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
1385 reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
1386 reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
1387 wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
1388 wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
1389 reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
1390 reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
1391 wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
1392 wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
1393 wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
1394 wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
1395 wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
1396 wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
1397 wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
1398 wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
1399 wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
1400 wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
1401 wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
1402 wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
1403 wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
1404 wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
1405 reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
1406 reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
1407 reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
1408 reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
1409 reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
1410 wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
1411 wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
1412 wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
1413 wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
1414 wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
1415 wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
1416 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
1417 wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
1418 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
1419 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
1420 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
1421 wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
1422 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
1423 wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
1424 wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
1425 wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
1426 wire litedramcore_bankmachine5_cmd_buffer_sink_first;
1427 wire litedramcore_bankmachine5_cmd_buffer_sink_last;
1428 wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
1429 wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
1430 reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
1431 wire litedramcore_bankmachine5_cmd_buffer_source_ready;
1432 reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
1433 reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
1434 reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
1435 reg  [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
1436 reg  [14:0] litedramcore_bankmachine5_row = 15'd0;
1437 reg  litedramcore_bankmachine5_row_opened = 1'd0;
1438 wire litedramcore_bankmachine5_row_hit;
1439 reg  litedramcore_bankmachine5_row_open = 1'd0;
1440 reg  litedramcore_bankmachine5_row_close = 1'd0;
1441 reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
1442 wire litedramcore_bankmachine5_twtpcon_valid;
1443 reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
1444 reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
1445 wire litedramcore_bankmachine5_trccon_valid;
1446 reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
1447 reg  [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
1448 wire litedramcore_bankmachine5_trascon_valid;
1449 reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
1450 reg  [1:0] litedramcore_bankmachine5_trascon_count = 2'd0;
1451 wire litedramcore_bankmachine6_req_valid;
1452 wire litedramcore_bankmachine6_req_ready;
1453 wire litedramcore_bankmachine6_req_we;
1454 wire [21:0] litedramcore_bankmachine6_req_addr;
1455 wire litedramcore_bankmachine6_req_lock;
1456 reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
1457 reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
1458 wire litedramcore_bankmachine6_refresh_req;
1459 reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
1460 reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
1461 reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
1462 reg  [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
1463 wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
1464 reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
1465 reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
1466 reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
1467 reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
1468 reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
1469 reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
1470 reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
1471 wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
1472 wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
1473 reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
1474 reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
1475 wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
1476 wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
1477 wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
1478 wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
1479 wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
1480 wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
1481 wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
1482 wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
1483 wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
1484 wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
1485 wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
1486 wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
1487 wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
1488 wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
1489 reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
1490 reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
1491 reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
1492 reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
1493 reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
1494 wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
1495 wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
1496 wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
1497 wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
1498 wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
1499 wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
1500 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
1501 wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
1502 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
1503 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
1504 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
1505 wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
1506 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
1507 wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
1508 wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
1509 wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
1510 wire litedramcore_bankmachine6_cmd_buffer_sink_first;
1511 wire litedramcore_bankmachine6_cmd_buffer_sink_last;
1512 wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
1513 wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
1514 reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
1515 wire litedramcore_bankmachine6_cmd_buffer_source_ready;
1516 reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
1517 reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
1518 reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
1519 reg  [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
1520 reg  [14:0] litedramcore_bankmachine6_row = 15'd0;
1521 reg  litedramcore_bankmachine6_row_opened = 1'd0;
1522 wire litedramcore_bankmachine6_row_hit;
1523 reg  litedramcore_bankmachine6_row_open = 1'd0;
1524 reg  litedramcore_bankmachine6_row_close = 1'd0;
1525 reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
1526 wire litedramcore_bankmachine6_twtpcon_valid;
1527 reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
1528 reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
1529 wire litedramcore_bankmachine6_trccon_valid;
1530 reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
1531 reg  [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
1532 wire litedramcore_bankmachine6_trascon_valid;
1533 reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
1534 reg  [1:0] litedramcore_bankmachine6_trascon_count = 2'd0;
1535 wire litedramcore_bankmachine7_req_valid;
1536 wire litedramcore_bankmachine7_req_ready;
1537 wire litedramcore_bankmachine7_req_we;
1538 wire [21:0] litedramcore_bankmachine7_req_addr;
1539 wire litedramcore_bankmachine7_req_lock;
1540 reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
1541 reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
1542 wire litedramcore_bankmachine7_refresh_req;
1543 reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
1544 reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
1545 reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
1546 reg  [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
1547 wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
1548 reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
1549 reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
1550 reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
1551 reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
1552 reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
1553 reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
1554 reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
1555 wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
1556 wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
1557 reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
1558 reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
1559 wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
1560 wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
1561 wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
1562 wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
1563 wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
1564 wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
1565 wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
1566 wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
1567 wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
1568 wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
1569 wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
1570 wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
1571 wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
1572 wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
1573 reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
1574 reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
1575 reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
1576 reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
1577 reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
1578 wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
1579 wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
1580 wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
1581 wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
1582 wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
1583 wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
1584 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
1585 wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
1586 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
1587 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
1588 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
1589 wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
1590 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
1591 wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
1592 wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
1593 wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
1594 wire litedramcore_bankmachine7_cmd_buffer_sink_first;
1595 wire litedramcore_bankmachine7_cmd_buffer_sink_last;
1596 wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
1597 wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
1598 reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
1599 wire litedramcore_bankmachine7_cmd_buffer_source_ready;
1600 reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
1601 reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
1602 reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
1603 reg  [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
1604 reg  [14:0] litedramcore_bankmachine7_row = 15'd0;
1605 reg  litedramcore_bankmachine7_row_opened = 1'd0;
1606 wire litedramcore_bankmachine7_row_hit;
1607 reg  litedramcore_bankmachine7_row_open = 1'd0;
1608 reg  litedramcore_bankmachine7_row_close = 1'd0;
1609 reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
1610 wire litedramcore_bankmachine7_twtpcon_valid;
1611 reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
1612 reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
1613 wire litedramcore_bankmachine7_trccon_valid;
1614 reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
1615 reg  [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
1616 wire litedramcore_bankmachine7_trascon_valid;
1617 reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
1618 reg  [1:0] litedramcore_bankmachine7_trascon_count = 2'd0;
1619 wire litedramcore_ras_allowed;
1620 wire litedramcore_cas_allowed;
1621 reg  litedramcore_choose_cmd_want_reads = 1'd0;
1622 reg  litedramcore_choose_cmd_want_writes = 1'd0;
1623 reg  litedramcore_choose_cmd_want_cmds = 1'd0;
1624 reg  litedramcore_choose_cmd_want_activates = 1'd0;
1625 wire litedramcore_choose_cmd_cmd_valid;
1626 reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
1627 wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
1628 wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
1629 reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
1630 reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
1631 reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
1632 wire litedramcore_choose_cmd_cmd_payload_is_cmd;
1633 wire litedramcore_choose_cmd_cmd_payload_is_read;
1634 wire litedramcore_choose_cmd_cmd_payload_is_write;
1635 reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
1636 wire [7:0] litedramcore_choose_cmd_request;
1637 reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
1638 wire litedramcore_choose_cmd_ce;
1639 reg  litedramcore_choose_req_want_reads = 1'd0;
1640 reg  litedramcore_choose_req_want_writes = 1'd0;
1641 reg  litedramcore_choose_req_want_cmds = 1'd0;
1642 reg  litedramcore_choose_req_want_activates = 1'd0;
1643 wire litedramcore_choose_req_cmd_valid;
1644 reg  litedramcore_choose_req_cmd_ready = 1'd0;
1645 wire [14:0] litedramcore_choose_req_cmd_payload_a;
1646 wire [2:0] litedramcore_choose_req_cmd_payload_ba;
1647 reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
1648 reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
1649 reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
1650 wire litedramcore_choose_req_cmd_payload_is_cmd;
1651 wire litedramcore_choose_req_cmd_payload_is_read;
1652 wire litedramcore_choose_req_cmd_payload_is_write;
1653 reg  [7:0] litedramcore_choose_req_valids = 8'd0;
1654 wire [7:0] litedramcore_choose_req_request;
1655 reg  [2:0] litedramcore_choose_req_grant = 3'd0;
1656 wire litedramcore_choose_req_ce;
1657 reg  [14:0] litedramcore_nop_a = 15'd0;
1658 reg  [2:0] litedramcore_nop_ba = 3'd0;
1659 reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
1660 reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
1661 reg  litedramcore_steerer0 = 1'd1;
1662 reg  litedramcore_steerer1 = 1'd1;
1663 reg  litedramcore_steerer2 = 1'd1;
1664 reg  litedramcore_steerer3 = 1'd1;
1665 wire litedramcore_trrdcon_valid;
1666 reg  litedramcore_trrdcon_ready = 1'd0;
1667 reg  litedramcore_trrdcon_count = 1'd0;
1668 wire litedramcore_tfawcon_valid;
1669 reg  litedramcore_tfawcon_ready = 1'd1;
1670 wire [1:0] litedramcore_tfawcon_count;
1671 reg  [2:0] litedramcore_tfawcon_window = 3'd0;
1672 wire litedramcore_tccdcon_valid;
1673 reg  litedramcore_tccdcon_ready = 1'd0;
1674 reg  litedramcore_tccdcon_count = 1'd0;
1675 wire litedramcore_twtrcon_valid;
1676 reg  litedramcore_twtrcon_ready = 1'd0;
1677 reg  [2:0] litedramcore_twtrcon_count = 3'd0;
1678 wire litedramcore_read_available;
1679 wire litedramcore_write_available;
1680 reg  litedramcore_en0 = 1'd0;
1681 wire litedramcore_max_time0;
1682 reg  [4:0] litedramcore_time0 = 5'd0;
1683 reg  litedramcore_en1 = 1'd0;
1684 wire litedramcore_max_time1;
1685 reg  [3:0] litedramcore_time1 = 4'd0;
1686 wire litedramcore_go_to_refresh;
1687 reg  init_done_storage = 1'd0;
1688 reg  init_done_re = 1'd0;
1689 reg  init_error_storage = 1'd0;
1690 reg  init_error_re = 1'd0;
1691 wire [29:0] wb_bus_adr;
1692 wire [31:0] wb_bus_dat_w;
1693 wire [31:0] wb_bus_dat_r;
1694 wire [3:0] wb_bus_sel;
1695 wire wb_bus_cyc;
1696 wire wb_bus_stb;
1697 wire wb_bus_ack;
1698 wire wb_bus_we;
1699 wire [2:0] wb_bus_cti;
1700 wire [1:0] wb_bus_bte;
1701 wire wb_bus_err;
1702 wire user_enable;
1703 wire user_port_cmd_valid;
1704 wire user_port_cmd_ready;
1705 wire user_port_cmd_payload_we;
1706 wire [24:0] user_port_cmd_payload_addr;
1707 wire user_port_wdata_valid;
1708 wire user_port_wdata_ready;
1709 wire [255:0] user_port_wdata_payload_data;
1710 wire [31:0] user_port_wdata_payload_we;
1711 wire user_port_rdata_valid;
1712 wire user_port_rdata_ready;
1713 wire [255:0] user_port_rdata_payload_data;
1714 wire litedramecp5ddrphycrg_ecp5pll;
1715 wire litedramecp5ddrphycrg_locked;
1716 reg  [1:0] litedramcore_refresher_state = 2'd0;
1717 reg  [1:0] litedramcore_refresher_next_state = 2'd0;
1718 reg  [2:0] litedramcore_bankmachine0_state = 3'd0;
1719 reg  [2:0] litedramcore_bankmachine0_next_state = 3'd0;
1720 reg  [2:0] litedramcore_bankmachine1_state = 3'd0;
1721 reg  [2:0] litedramcore_bankmachine1_next_state = 3'd0;
1722 reg  [2:0] litedramcore_bankmachine2_state = 3'd0;
1723 reg  [2:0] litedramcore_bankmachine2_next_state = 3'd0;
1724 reg  [2:0] litedramcore_bankmachine3_state = 3'd0;
1725 reg  [2:0] litedramcore_bankmachine3_next_state = 3'd0;
1726 reg  [2:0] litedramcore_bankmachine4_state = 3'd0;
1727 reg  [2:0] litedramcore_bankmachine4_next_state = 3'd0;
1728 reg  [2:0] litedramcore_bankmachine5_state = 3'd0;
1729 reg  [2:0] litedramcore_bankmachine5_next_state = 3'd0;
1730 reg  [2:0] litedramcore_bankmachine6_state = 3'd0;
1731 reg  [2:0] litedramcore_bankmachine6_next_state = 3'd0;
1732 reg  [2:0] litedramcore_bankmachine7_state = 3'd0;
1733 reg  [2:0] litedramcore_bankmachine7_next_state = 3'd0;
1734 reg  [3:0] litedramcore_multiplexer_state = 4'd0;
1735 reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
1736 wire litedramcore_roundrobin0_request;
1737 wire litedramcore_roundrobin0_grant;
1738 wire litedramcore_roundrobin0_ce;
1739 wire litedramcore_roundrobin1_request;
1740 wire litedramcore_roundrobin1_grant;
1741 wire litedramcore_roundrobin1_ce;
1742 wire litedramcore_roundrobin2_request;
1743 wire litedramcore_roundrobin2_grant;
1744 wire litedramcore_roundrobin2_ce;
1745 wire litedramcore_roundrobin3_request;
1746 wire litedramcore_roundrobin3_grant;
1747 wire litedramcore_roundrobin3_ce;
1748 wire litedramcore_roundrobin4_request;
1749 wire litedramcore_roundrobin4_grant;
1750 wire litedramcore_roundrobin4_ce;
1751 wire litedramcore_roundrobin5_request;
1752 wire litedramcore_roundrobin5_grant;
1753 wire litedramcore_roundrobin5_ce;
1754 wire litedramcore_roundrobin6_request;
1755 wire litedramcore_roundrobin6_grant;
1756 wire litedramcore_roundrobin6_ce;
1757 wire litedramcore_roundrobin7_request;
1758 wire litedramcore_roundrobin7_grant;
1759 wire litedramcore_roundrobin7_ce;
1760 reg  litedramcore_locked0 = 1'd0;
1761 reg  litedramcore_locked1 = 1'd0;
1762 reg  litedramcore_locked2 = 1'd0;
1763 reg  litedramcore_locked3 = 1'd0;
1764 reg  litedramcore_locked4 = 1'd0;
1765 reg  litedramcore_locked5 = 1'd0;
1766 reg  litedramcore_locked6 = 1'd0;
1767 reg  litedramcore_locked7 = 1'd0;
1768 reg  litedramcore_new_master_wdata_ready0 = 1'd0;
1769 reg  litedramcore_new_master_wdata_ready1 = 1'd0;
1770 reg  litedramcore_new_master_wdata_ready2 = 1'd0;
1771 reg  litedramcore_new_master_wdata_ready3 = 1'd0;
1772 reg  litedramcore_new_master_rdata_valid0 = 1'd0;
1773 reg  litedramcore_new_master_rdata_valid1 = 1'd0;
1774 reg  litedramcore_new_master_rdata_valid2 = 1'd0;
1775 reg  litedramcore_new_master_rdata_valid3 = 1'd0;
1776 reg  litedramcore_new_master_rdata_valid4 = 1'd0;
1777 reg  litedramcore_new_master_rdata_valid5 = 1'd0;
1778 reg  litedramcore_new_master_rdata_valid6 = 1'd0;
1779 reg  litedramcore_new_master_rdata_valid7 = 1'd0;
1780 reg  litedramcore_new_master_rdata_valid8 = 1'd0;
1781 reg  litedramcore_new_master_rdata_valid9 = 1'd0;
1782 reg  litedramcore_new_master_rdata_valid10 = 1'd0;
1783 reg  litedramcore_new_master_rdata_valid11 = 1'd0;
1784 reg  litedramcore_new_master_rdata_valid12 = 1'd0;
1785 reg  litedramcore_new_master_rdata_valid13 = 1'd0;
1786 reg  [13:0] litedramcore_adr = 14'd0;
1787 reg  litedramcore_we = 1'd0;
1788 reg  [31:0] litedramcore_dat_w = 32'd0;
1789 wire [31:0] litedramcore_dat_r;
1790 wire [29:0] litedramcore_wishbone_adr;
1791 wire [31:0] litedramcore_wishbone_dat_w;
1792 reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
1793 wire [3:0] litedramcore_wishbone_sel;
1794 wire litedramcore_wishbone_cyc;
1795 wire litedramcore_wishbone_stb;
1796 reg  litedramcore_wishbone_ack = 1'd0;
1797 wire litedramcore_wishbone_we;
1798 wire [2:0] litedramcore_wishbone_cti;
1799 wire [1:0] litedramcore_wishbone_bte;
1800 reg  litedramcore_wishbone_err = 1'd0;
1801 wire [13:0] interface0_bank_bus_adr;
1802 wire interface0_bank_bus_we;
1803 wire [31:0] interface0_bank_bus_dat_w;
1804 reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
1805 reg  csrbank0_init_done0_re = 1'd0;
1806 wire csrbank0_init_done0_r;
1807 reg  csrbank0_init_done0_we = 1'd0;
1808 wire csrbank0_init_done0_w;
1809 reg  csrbank0_init_error0_re = 1'd0;
1810 wire csrbank0_init_error0_r;
1811 reg  csrbank0_init_error0_we = 1'd0;
1812 wire csrbank0_init_error0_w;
1813 wire csrbank0_sel;
1814 wire [13:0] interface1_bank_bus_adr;
1815 wire interface1_bank_bus_we;
1816 wire [31:0] interface1_bank_bus_dat_w;
1817 reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
1818 reg  csrbank1_dly_sel0_re = 1'd0;
1819 wire [3:0] csrbank1_dly_sel0_r;
1820 reg  csrbank1_dly_sel0_we = 1'd0;
1821 wire [3:0] csrbank1_dly_sel0_w;
1822 reg  csrbank1_burstdet_seen_re = 1'd0;
1823 wire [3:0] csrbank1_burstdet_seen_r;
1824 reg  csrbank1_burstdet_seen_we = 1'd0;
1825 wire [3:0] csrbank1_burstdet_seen_w;
1826 wire csrbank1_sel;
1827 wire [13:0] interface2_bank_bus_adr;
1828 wire interface2_bank_bus_we;
1829 wire [31:0] interface2_bank_bus_dat_w;
1830 reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
1831 reg  csrbank2_dfii_control0_re = 1'd0;
1832 wire [3:0] csrbank2_dfii_control0_r;
1833 reg  csrbank2_dfii_control0_we = 1'd0;
1834 wire [3:0] csrbank2_dfii_control0_w;
1835 reg  csrbank2_dfii_pi0_command0_re = 1'd0;
1836 wire [5:0] csrbank2_dfii_pi0_command0_r;
1837 reg  csrbank2_dfii_pi0_command0_we = 1'd0;
1838 wire [5:0] csrbank2_dfii_pi0_command0_w;
1839 reg  csrbank2_dfii_pi0_address0_re = 1'd0;
1840 wire [14:0] csrbank2_dfii_pi0_address0_r;
1841 reg  csrbank2_dfii_pi0_address0_we = 1'd0;
1842 wire [14:0] csrbank2_dfii_pi0_address0_w;
1843 reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
1844 wire [2:0] csrbank2_dfii_pi0_baddress0_r;
1845 reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
1846 wire [2:0] csrbank2_dfii_pi0_baddress0_w;
1847 reg  csrbank2_dfii_pi0_wrdata3_re = 1'd0;
1848 wire [31:0] csrbank2_dfii_pi0_wrdata3_r;
1849 reg  csrbank2_dfii_pi0_wrdata3_we = 1'd0;
1850 wire [31:0] csrbank2_dfii_pi0_wrdata3_w;
1851 reg  csrbank2_dfii_pi0_wrdata2_re = 1'd0;
1852 wire [31:0] csrbank2_dfii_pi0_wrdata2_r;
1853 reg  csrbank2_dfii_pi0_wrdata2_we = 1'd0;
1854 wire [31:0] csrbank2_dfii_pi0_wrdata2_w;
1855 reg  csrbank2_dfii_pi0_wrdata1_re = 1'd0;
1856 wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
1857 reg  csrbank2_dfii_pi0_wrdata1_we = 1'd0;
1858 wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
1859 reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
1860 wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
1861 reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
1862 wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
1863 reg  csrbank2_dfii_pi0_rddata3_re = 1'd0;
1864 wire [31:0] csrbank2_dfii_pi0_rddata3_r;
1865 reg  csrbank2_dfii_pi0_rddata3_we = 1'd0;
1866 wire [31:0] csrbank2_dfii_pi0_rddata3_w;
1867 reg  csrbank2_dfii_pi0_rddata2_re = 1'd0;
1868 wire [31:0] csrbank2_dfii_pi0_rddata2_r;
1869 reg  csrbank2_dfii_pi0_rddata2_we = 1'd0;
1870 wire [31:0] csrbank2_dfii_pi0_rddata2_w;
1871 reg  csrbank2_dfii_pi0_rddata1_re = 1'd0;
1872 wire [31:0] csrbank2_dfii_pi0_rddata1_r;
1873 reg  csrbank2_dfii_pi0_rddata1_we = 1'd0;
1874 wire [31:0] csrbank2_dfii_pi0_rddata1_w;
1875 reg  csrbank2_dfii_pi0_rddata0_re = 1'd0;
1876 wire [31:0] csrbank2_dfii_pi0_rddata0_r;
1877 reg  csrbank2_dfii_pi0_rddata0_we = 1'd0;
1878 wire [31:0] csrbank2_dfii_pi0_rddata0_w;
1879 reg  csrbank2_dfii_pi1_command0_re = 1'd0;
1880 wire [5:0] csrbank2_dfii_pi1_command0_r;
1881 reg  csrbank2_dfii_pi1_command0_we = 1'd0;
1882 wire [5:0] csrbank2_dfii_pi1_command0_w;
1883 reg  csrbank2_dfii_pi1_address0_re = 1'd0;
1884 wire [14:0] csrbank2_dfii_pi1_address0_r;
1885 reg  csrbank2_dfii_pi1_address0_we = 1'd0;
1886 wire [14:0] csrbank2_dfii_pi1_address0_w;
1887 reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
1888 wire [2:0] csrbank2_dfii_pi1_baddress0_r;
1889 reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
1890 wire [2:0] csrbank2_dfii_pi1_baddress0_w;
1891 reg  csrbank2_dfii_pi1_wrdata3_re = 1'd0;
1892 wire [31:0] csrbank2_dfii_pi1_wrdata3_r;
1893 reg  csrbank2_dfii_pi1_wrdata3_we = 1'd0;
1894 wire [31:0] csrbank2_dfii_pi1_wrdata3_w;
1895 reg  csrbank2_dfii_pi1_wrdata2_re = 1'd0;
1896 wire [31:0] csrbank2_dfii_pi1_wrdata2_r;
1897 reg  csrbank2_dfii_pi1_wrdata2_we = 1'd0;
1898 wire [31:0] csrbank2_dfii_pi1_wrdata2_w;
1899 reg  csrbank2_dfii_pi1_wrdata1_re = 1'd0;
1900 wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
1901 reg  csrbank2_dfii_pi1_wrdata1_we = 1'd0;
1902 wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
1903 reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
1904 wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
1905 reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
1906 wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
1907 reg  csrbank2_dfii_pi1_rddata3_re = 1'd0;
1908 wire [31:0] csrbank2_dfii_pi1_rddata3_r;
1909 reg  csrbank2_dfii_pi1_rddata3_we = 1'd0;
1910 wire [31:0] csrbank2_dfii_pi1_rddata3_w;
1911 reg  csrbank2_dfii_pi1_rddata2_re = 1'd0;
1912 wire [31:0] csrbank2_dfii_pi1_rddata2_r;
1913 reg  csrbank2_dfii_pi1_rddata2_we = 1'd0;
1914 wire [31:0] csrbank2_dfii_pi1_rddata2_w;
1915 reg  csrbank2_dfii_pi1_rddata1_re = 1'd0;
1916 wire [31:0] csrbank2_dfii_pi1_rddata1_r;
1917 reg  csrbank2_dfii_pi1_rddata1_we = 1'd0;
1918 wire [31:0] csrbank2_dfii_pi1_rddata1_w;
1919 reg  csrbank2_dfii_pi1_rddata0_re = 1'd0;
1920 wire [31:0] csrbank2_dfii_pi1_rddata0_r;
1921 reg  csrbank2_dfii_pi1_rddata0_we = 1'd0;
1922 wire [31:0] csrbank2_dfii_pi1_rddata0_w;
1923 wire csrbank2_sel;
1924 wire [13:0] csr_interconnect_adr;
1925 wire csr_interconnect_we;
1926 wire [31:0] csr_interconnect_dat_w;
1927 wire [31:0] csr_interconnect_dat_r;
1928 reg  [1:0] state = 2'd0;
1929 reg  [1:0] next_state = 2'd0;
1930 reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
1931 reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
1932 reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
1933 reg  litedramcore_adr_next_value_ce1 = 1'd0;
1934 reg  litedramcore_we_next_value2 = 1'd0;
1935 reg  litedramcore_we_next_value_ce2 = 1'd0;
1936 reg  rhs_array_muxed0 = 1'd0;
1937 reg  [14:0] rhs_array_muxed1 = 15'd0;
1938 reg  [2:0] rhs_array_muxed2 = 3'd0;
1939 reg  rhs_array_muxed3 = 1'd0;
1940 reg  rhs_array_muxed4 = 1'd0;
1941 reg  rhs_array_muxed5 = 1'd0;
1942 reg  t_array_muxed0 = 1'd0;
1943 reg  t_array_muxed1 = 1'd0;
1944 reg  t_array_muxed2 = 1'd0;
1945 reg  rhs_array_muxed6 = 1'd0;
1946 reg  [14:0] rhs_array_muxed7 = 15'd0;
1947 reg  [2:0] rhs_array_muxed8 = 3'd0;
1948 reg  rhs_array_muxed9 = 1'd0;
1949 reg  rhs_array_muxed10 = 1'd0;
1950 reg  rhs_array_muxed11 = 1'd0;
1951 reg  t_array_muxed3 = 1'd0;
1952 reg  t_array_muxed4 = 1'd0;
1953 reg  t_array_muxed5 = 1'd0;
1954 reg  [21:0] rhs_array_muxed12 = 22'd0;
1955 reg  rhs_array_muxed13 = 1'd0;
1956 reg  rhs_array_muxed14 = 1'd0;
1957 reg  [21:0] rhs_array_muxed15 = 22'd0;
1958 reg  rhs_array_muxed16 = 1'd0;
1959 reg  rhs_array_muxed17 = 1'd0;
1960 reg  [21:0] rhs_array_muxed18 = 22'd0;
1961 reg  rhs_array_muxed19 = 1'd0;
1962 reg  rhs_array_muxed20 = 1'd0;
1963 reg  [21:0] rhs_array_muxed21 = 22'd0;
1964 reg  rhs_array_muxed22 = 1'd0;
1965 reg  rhs_array_muxed23 = 1'd0;
1966 reg  [21:0] rhs_array_muxed24 = 22'd0;
1967 reg  rhs_array_muxed25 = 1'd0;
1968 reg  rhs_array_muxed26 = 1'd0;
1969 reg  [21:0] rhs_array_muxed27 = 22'd0;
1970 reg  rhs_array_muxed28 = 1'd0;
1971 reg  rhs_array_muxed29 = 1'd0;
1972 reg  [21:0] rhs_array_muxed30 = 22'd0;
1973 reg  rhs_array_muxed31 = 1'd0;
1974 reg  rhs_array_muxed32 = 1'd0;
1975 reg  [21:0] rhs_array_muxed33 = 22'd0;
1976 reg  rhs_array_muxed34 = 1'd0;
1977 reg  rhs_array_muxed35 = 1'd0;
1978 reg  [2:0] array_muxed0 = 3'd0;
1979 reg  [14:0] array_muxed1 = 15'd0;
1980 reg  array_muxed2 = 1'd0;
1981 reg  array_muxed3 = 1'd0;
1982 reg  array_muxed4 = 1'd0;
1983 reg  array_muxed5 = 1'd0;
1984 reg  array_muxed6 = 1'd0;
1985 reg  [2:0] array_muxed7 = 3'd0;
1986 reg  [14:0] array_muxed8 = 15'd0;
1987 reg  array_muxed9 = 1'd0;
1988 reg  array_muxed10 = 1'd0;
1989 reg  array_muxed11 = 1'd0;
1990 reg  array_muxed12 = 1'd0;
1991 reg  array_muxed13 = 1'd0;
1992 wire latticeecp5asyncresetsynchronizerimpl0_rst1;
1993 wire latticeecp5asyncresetsynchronizerimpl0_expr;
1994 wire latticeecp5asyncresetsynchronizerimpl1_rst1;
1995 wire latticeecp5asyncresetsynchronizerimpl2_rst1;
1996 wire latticeecp5asyncresetsynchronizerimpl3_rst1;
1997 reg  regs0 = 1'd0;
1998 reg  regs1 = 1'd0;
1999
2000 //------------------------------------------------------------------------------
2001 // Combinatorial Logic
2002 //------------------------------------------------------------------------------
2003
2004 assign crg_stop = ddrphy_stop0;
2005 assign crg_reset0 = ddrphy_reset0;
2006 assign init_done = init_done_storage;
2007 assign init_error = init_error_storage;
2008 assign wb_bus_adr = wb_ctrl_adr;
2009 assign wb_bus_dat_w = wb_ctrl_dat_w;
2010 assign wb_ctrl_dat_r = wb_bus_dat_r;
2011 assign wb_bus_sel = wb_ctrl_sel;
2012 assign wb_bus_cyc = wb_ctrl_cyc;
2013 assign wb_bus_stb = wb_ctrl_stb;
2014 assign wb_ctrl_ack = wb_bus_ack;
2015 assign wb_bus_we = wb_ctrl_we;
2016 assign wb_bus_cti = wb_ctrl_cti;
2017 assign wb_bus_bte = wb_ctrl_bte;
2018 assign wb_ctrl_err = wb_bus_err;
2019 assign user_clk = sys_clk;
2020 assign user_rst = sys_rst;
2021 assign user_enable = 1'd1;
2022 assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
2023 assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
2024 assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
2025 assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
2026 assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
2027 assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
2028 assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
2029 assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
2030 assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
2031 assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
2032 assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
2033 assign por_clk = clk;
2034 assign crg_por_done = (crg_por_count == 1'd0);
2035 assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst);
2036 assign pll_locked = crg_locked;
2037 assign crg_clkin = clk;
2038 assign sys2x_i_clk = crg_clkout0;
2039 assign init_clk = crg_clkout1;
2040 assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1));
2041 always @(*) begin
2042         ddrphy_dm_o_data0 <= 8'd0;
2043         ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
2044         ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[5];
2045         ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[9];
2046         ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[13];
2047         ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1];
2048         ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[5];
2049         ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[9];
2050         ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[13];
2051 end
2052 always @(*) begin
2053         ddrphy_dq_o_data0 <= 8'd0;
2054         ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0];
2055         ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[32];
2056         ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[64];
2057         ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[96];
2058         ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0];
2059         ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[32];
2060         ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[64];
2061         ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[96];
2062 end
2063 assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0};
2064 always @(*) begin
2065         ddrphy_dfi_p0_rddata <= 128'd0;
2066         ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0];
2067         ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[1];
2068         ddrphy_dfi_p0_rddata[64] <= ddrphy_dq_i_data0[2];
2069         ddrphy_dfi_p0_rddata[96] <= ddrphy_dq_i_data0[3];
2070         ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0];
2071         ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[1];
2072         ddrphy_dfi_p0_rddata[65] <= ddrphy_dq_i_data1[2];
2073         ddrphy_dfi_p0_rddata[97] <= ddrphy_dq_i_data1[3];
2074         ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0];
2075         ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[1];
2076         ddrphy_dfi_p0_rddata[66] <= ddrphy_dq_i_data2[2];
2077         ddrphy_dfi_p0_rddata[98] <= ddrphy_dq_i_data2[3];
2078         ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0];
2079         ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[1];
2080         ddrphy_dfi_p0_rddata[67] <= ddrphy_dq_i_data3[2];
2081         ddrphy_dfi_p0_rddata[99] <= ddrphy_dq_i_data3[3];
2082         ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0];
2083         ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[1];
2084         ddrphy_dfi_p0_rddata[68] <= ddrphy_dq_i_data4[2];
2085         ddrphy_dfi_p0_rddata[100] <= ddrphy_dq_i_data4[3];
2086         ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0];
2087         ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[1];
2088         ddrphy_dfi_p0_rddata[69] <= ddrphy_dq_i_data5[2];
2089         ddrphy_dfi_p0_rddata[101] <= ddrphy_dq_i_data5[3];
2090         ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0];
2091         ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[1];
2092         ddrphy_dfi_p0_rddata[70] <= ddrphy_dq_i_data6[2];
2093         ddrphy_dfi_p0_rddata[102] <= ddrphy_dq_i_data6[3];
2094         ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0];
2095         ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[1];
2096         ddrphy_dfi_p0_rddata[71] <= ddrphy_dq_i_data7[2];
2097         ddrphy_dfi_p0_rddata[103] <= ddrphy_dq_i_data7[3];
2098         ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0];
2099         ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[1];
2100         ddrphy_dfi_p0_rddata[72] <= ddrphy_dq_i_data8[2];
2101         ddrphy_dfi_p0_rddata[104] <= ddrphy_dq_i_data8[3];
2102         ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0];
2103         ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[1];
2104         ddrphy_dfi_p0_rddata[73] <= ddrphy_dq_i_data9[2];
2105         ddrphy_dfi_p0_rddata[105] <= ddrphy_dq_i_data9[3];
2106         ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0];
2107         ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[1];
2108         ddrphy_dfi_p0_rddata[74] <= ddrphy_dq_i_data10[2];
2109         ddrphy_dfi_p0_rddata[106] <= ddrphy_dq_i_data10[3];
2110         ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0];
2111         ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[1];
2112         ddrphy_dfi_p0_rddata[75] <= ddrphy_dq_i_data11[2];
2113         ddrphy_dfi_p0_rddata[107] <= ddrphy_dq_i_data11[3];
2114         ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0];
2115         ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[1];
2116         ddrphy_dfi_p0_rddata[76] <= ddrphy_dq_i_data12[2];
2117         ddrphy_dfi_p0_rddata[108] <= ddrphy_dq_i_data12[3];
2118         ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0];
2119         ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[1];
2120         ddrphy_dfi_p0_rddata[77] <= ddrphy_dq_i_data13[2];
2121         ddrphy_dfi_p0_rddata[109] <= ddrphy_dq_i_data13[3];
2122         ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0];
2123         ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[1];
2124         ddrphy_dfi_p0_rddata[78] <= ddrphy_dq_i_data14[2];
2125         ddrphy_dfi_p0_rddata[110] <= ddrphy_dq_i_data14[3];
2126         ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0];
2127         ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[1];
2128         ddrphy_dfi_p0_rddata[79] <= ddrphy_dq_i_data15[2];
2129         ddrphy_dfi_p0_rddata[111] <= ddrphy_dq_i_data15[3];
2130         ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data16[0];
2131         ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data16[1];
2132         ddrphy_dfi_p0_rddata[80] <= ddrphy_dq_i_data16[2];
2133         ddrphy_dfi_p0_rddata[112] <= ddrphy_dq_i_data16[3];
2134         ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data17[0];
2135         ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data17[1];
2136         ddrphy_dfi_p0_rddata[81] <= ddrphy_dq_i_data17[2];
2137         ddrphy_dfi_p0_rddata[113] <= ddrphy_dq_i_data17[3];
2138         ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data18[0];
2139         ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data18[1];
2140         ddrphy_dfi_p0_rddata[82] <= ddrphy_dq_i_data18[2];
2141         ddrphy_dfi_p0_rddata[114] <= ddrphy_dq_i_data18[3];
2142         ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data19[0];
2143         ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data19[1];
2144         ddrphy_dfi_p0_rddata[83] <= ddrphy_dq_i_data19[2];
2145         ddrphy_dfi_p0_rddata[115] <= ddrphy_dq_i_data19[3];
2146         ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data20[0];
2147         ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data20[1];
2148         ddrphy_dfi_p0_rddata[84] <= ddrphy_dq_i_data20[2];
2149         ddrphy_dfi_p0_rddata[116] <= ddrphy_dq_i_data20[3];
2150         ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data21[0];
2151         ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data21[1];
2152         ddrphy_dfi_p0_rddata[85] <= ddrphy_dq_i_data21[2];
2153         ddrphy_dfi_p0_rddata[117] <= ddrphy_dq_i_data21[3];
2154         ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data22[0];
2155         ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data22[1];
2156         ddrphy_dfi_p0_rddata[86] <= ddrphy_dq_i_data22[2];
2157         ddrphy_dfi_p0_rddata[118] <= ddrphy_dq_i_data22[3];
2158         ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data23[0];
2159         ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data23[1];
2160         ddrphy_dfi_p0_rddata[87] <= ddrphy_dq_i_data23[2];
2161         ddrphy_dfi_p0_rddata[119] <= ddrphy_dq_i_data23[3];
2162         ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data24[0];
2163         ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data24[1];
2164         ddrphy_dfi_p0_rddata[88] <= ddrphy_dq_i_data24[2];
2165         ddrphy_dfi_p0_rddata[120] <= ddrphy_dq_i_data24[3];
2166         ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data25[0];
2167         ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data25[1];
2168         ddrphy_dfi_p0_rddata[89] <= ddrphy_dq_i_data25[2];
2169         ddrphy_dfi_p0_rddata[121] <= ddrphy_dq_i_data25[3];
2170         ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data26[0];
2171         ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data26[1];
2172         ddrphy_dfi_p0_rddata[90] <= ddrphy_dq_i_data26[2];
2173         ddrphy_dfi_p0_rddata[122] <= ddrphy_dq_i_data26[3];
2174         ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data27[0];
2175         ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data27[1];
2176         ddrphy_dfi_p0_rddata[91] <= ddrphy_dq_i_data27[2];
2177         ddrphy_dfi_p0_rddata[123] <= ddrphy_dq_i_data27[3];
2178         ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data28[0];
2179         ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data28[1];
2180         ddrphy_dfi_p0_rddata[92] <= ddrphy_dq_i_data28[2];
2181         ddrphy_dfi_p0_rddata[124] <= ddrphy_dq_i_data28[3];
2182         ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data29[0];
2183         ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data29[1];
2184         ddrphy_dfi_p0_rddata[93] <= ddrphy_dq_i_data29[2];
2185         ddrphy_dfi_p0_rddata[125] <= ddrphy_dq_i_data29[3];
2186         ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data30[0];
2187         ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data30[1];
2188         ddrphy_dfi_p0_rddata[94] <= ddrphy_dq_i_data30[2];
2189         ddrphy_dfi_p0_rddata[126] <= ddrphy_dq_i_data30[3];
2190         ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data31[0];
2191         ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data31[1];
2192         ddrphy_dfi_p0_rddata[95] <= ddrphy_dq_i_data31[2];
2193         ddrphy_dfi_p0_rddata[127] <= ddrphy_dq_i_data31[3];
2194 end
2195 always @(*) begin
2196         ddrphy_dfi_p1_rddata <= 128'd0;
2197         ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4];
2198         ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[5];
2199         ddrphy_dfi_p1_rddata[64] <= ddrphy_dq_i_data0[6];
2200         ddrphy_dfi_p1_rddata[96] <= ddrphy_dq_i_data0[7];
2201         ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4];
2202         ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[5];
2203         ddrphy_dfi_p1_rddata[65] <= ddrphy_dq_i_data1[6];
2204         ddrphy_dfi_p1_rddata[97] <= ddrphy_dq_i_data1[7];
2205         ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4];
2206         ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[5];
2207         ddrphy_dfi_p1_rddata[66] <= ddrphy_dq_i_data2[6];
2208         ddrphy_dfi_p1_rddata[98] <= ddrphy_dq_i_data2[7];
2209         ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4];
2210         ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[5];
2211         ddrphy_dfi_p1_rddata[67] <= ddrphy_dq_i_data3[6];
2212         ddrphy_dfi_p1_rddata[99] <= ddrphy_dq_i_data3[7];
2213         ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4];
2214         ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[5];
2215         ddrphy_dfi_p1_rddata[68] <= ddrphy_dq_i_data4[6];
2216         ddrphy_dfi_p1_rddata[100] <= ddrphy_dq_i_data4[7];
2217         ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4];
2218         ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[5];
2219         ddrphy_dfi_p1_rddata[69] <= ddrphy_dq_i_data5[6];
2220         ddrphy_dfi_p1_rddata[101] <= ddrphy_dq_i_data5[7];
2221         ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4];
2222         ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[5];
2223         ddrphy_dfi_p1_rddata[70] <= ddrphy_dq_i_data6[6];
2224         ddrphy_dfi_p1_rddata[102] <= ddrphy_dq_i_data6[7];
2225         ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4];
2226         ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[5];
2227         ddrphy_dfi_p1_rddata[71] <= ddrphy_dq_i_data7[6];
2228         ddrphy_dfi_p1_rddata[103] <= ddrphy_dq_i_data7[7];
2229         ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4];
2230         ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[5];
2231         ddrphy_dfi_p1_rddata[72] <= ddrphy_dq_i_data8[6];
2232         ddrphy_dfi_p1_rddata[104] <= ddrphy_dq_i_data8[7];
2233         ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4];
2234         ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[5];
2235         ddrphy_dfi_p1_rddata[73] <= ddrphy_dq_i_data9[6];
2236         ddrphy_dfi_p1_rddata[105] <= ddrphy_dq_i_data9[7];
2237         ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4];
2238         ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[5];
2239         ddrphy_dfi_p1_rddata[74] <= ddrphy_dq_i_data10[6];
2240         ddrphy_dfi_p1_rddata[106] <= ddrphy_dq_i_data10[7];
2241         ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4];
2242         ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[5];
2243         ddrphy_dfi_p1_rddata[75] <= ddrphy_dq_i_data11[6];
2244         ddrphy_dfi_p1_rddata[107] <= ddrphy_dq_i_data11[7];
2245         ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4];
2246         ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[5];
2247         ddrphy_dfi_p1_rddata[76] <= ddrphy_dq_i_data12[6];
2248         ddrphy_dfi_p1_rddata[108] <= ddrphy_dq_i_data12[7];
2249         ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4];
2250         ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[5];
2251         ddrphy_dfi_p1_rddata[77] <= ddrphy_dq_i_data13[6];
2252         ddrphy_dfi_p1_rddata[109] <= ddrphy_dq_i_data13[7];
2253         ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4];
2254         ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[5];
2255         ddrphy_dfi_p1_rddata[78] <= ddrphy_dq_i_data14[6];
2256         ddrphy_dfi_p1_rddata[110] <= ddrphy_dq_i_data14[7];
2257         ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4];
2258         ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[5];
2259         ddrphy_dfi_p1_rddata[79] <= ddrphy_dq_i_data15[6];
2260         ddrphy_dfi_p1_rddata[111] <= ddrphy_dq_i_data15[7];
2261         ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data16[4];
2262         ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data16[5];
2263         ddrphy_dfi_p1_rddata[80] <= ddrphy_dq_i_data16[6];
2264         ddrphy_dfi_p1_rddata[112] <= ddrphy_dq_i_data16[7];
2265         ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data17[4];
2266         ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data17[5];
2267         ddrphy_dfi_p1_rddata[81] <= ddrphy_dq_i_data17[6];
2268         ddrphy_dfi_p1_rddata[113] <= ddrphy_dq_i_data17[7];
2269         ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data18[4];
2270         ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data18[5];
2271         ddrphy_dfi_p1_rddata[82] <= ddrphy_dq_i_data18[6];
2272         ddrphy_dfi_p1_rddata[114] <= ddrphy_dq_i_data18[7];
2273         ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data19[4];
2274         ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data19[5];
2275         ddrphy_dfi_p1_rddata[83] <= ddrphy_dq_i_data19[6];
2276         ddrphy_dfi_p1_rddata[115] <= ddrphy_dq_i_data19[7];
2277         ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data20[4];
2278         ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data20[5];
2279         ddrphy_dfi_p1_rddata[84] <= ddrphy_dq_i_data20[6];
2280         ddrphy_dfi_p1_rddata[116] <= ddrphy_dq_i_data20[7];
2281         ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data21[4];
2282         ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data21[5];
2283         ddrphy_dfi_p1_rddata[85] <= ddrphy_dq_i_data21[6];
2284         ddrphy_dfi_p1_rddata[117] <= ddrphy_dq_i_data21[7];
2285         ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data22[4];
2286         ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data22[5];
2287         ddrphy_dfi_p1_rddata[86] <= ddrphy_dq_i_data22[6];
2288         ddrphy_dfi_p1_rddata[118] <= ddrphy_dq_i_data22[7];
2289         ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data23[4];
2290         ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data23[5];
2291         ddrphy_dfi_p1_rddata[87] <= ddrphy_dq_i_data23[6];
2292         ddrphy_dfi_p1_rddata[119] <= ddrphy_dq_i_data23[7];
2293         ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data24[4];
2294         ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data24[5];
2295         ddrphy_dfi_p1_rddata[88] <= ddrphy_dq_i_data24[6];
2296         ddrphy_dfi_p1_rddata[120] <= ddrphy_dq_i_data24[7];
2297         ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data25[4];
2298         ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data25[5];
2299         ddrphy_dfi_p1_rddata[89] <= ddrphy_dq_i_data25[6];
2300         ddrphy_dfi_p1_rddata[121] <= ddrphy_dq_i_data25[7];
2301         ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data26[4];
2302         ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data26[5];
2303         ddrphy_dfi_p1_rddata[90] <= ddrphy_dq_i_data26[6];
2304         ddrphy_dfi_p1_rddata[122] <= ddrphy_dq_i_data26[7];
2305         ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data27[4];
2306         ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data27[5];
2307         ddrphy_dfi_p1_rddata[91] <= ddrphy_dq_i_data27[6];
2308         ddrphy_dfi_p1_rddata[123] <= ddrphy_dq_i_data27[7];
2309         ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data28[4];
2310         ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data28[5];
2311         ddrphy_dfi_p1_rddata[92] <= ddrphy_dq_i_data28[6];
2312         ddrphy_dfi_p1_rddata[124] <= ddrphy_dq_i_data28[7];
2313         ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data29[4];
2314         ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data29[5];
2315         ddrphy_dfi_p1_rddata[93] <= ddrphy_dq_i_data29[6];
2316         ddrphy_dfi_p1_rddata[125] <= ddrphy_dq_i_data29[7];
2317         ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data30[4];
2318         ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data30[5];
2319         ddrphy_dfi_p1_rddata[94] <= ddrphy_dq_i_data30[6];
2320         ddrphy_dfi_p1_rddata[126] <= ddrphy_dq_i_data30[7];
2321         ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data31[4];
2322         ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data31[5];
2323         ddrphy_dfi_p1_rddata[95] <= ddrphy_dq_i_data31[6];
2324         ddrphy_dfi_p1_rddata[127] <= ddrphy_dq_i_data31[7];
2325 end
2326 always @(*) begin
2327         ddrphy_dq_o_data1 <= 8'd0;
2328         ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1];
2329         ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[33];
2330         ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[65];
2331         ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[97];
2332         ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1];
2333         ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[33];
2334         ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[65];
2335         ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[97];
2336 end
2337 assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1};
2338 always @(*) begin
2339         ddrphy_dq_o_data2 <= 8'd0;
2340         ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2];
2341         ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[34];
2342         ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[66];
2343         ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[98];
2344         ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2];
2345         ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[34];
2346         ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[66];
2347         ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[98];
2348 end
2349 assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2};
2350 always @(*) begin
2351         ddrphy_dq_o_data3 <= 8'd0;
2352         ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3];
2353         ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[35];
2354         ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[67];
2355         ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[99];
2356         ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3];
2357         ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[35];
2358         ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[67];
2359         ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[99];
2360 end
2361 assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3};
2362 always @(*) begin
2363         ddrphy_dq_o_data4 <= 8'd0;
2364         ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4];
2365         ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[36];
2366         ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[68];
2367         ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[100];
2368         ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4];
2369         ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[36];
2370         ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[68];
2371         ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[100];
2372 end
2373 assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4};
2374 always @(*) begin
2375         ddrphy_dq_o_data5 <= 8'd0;
2376         ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5];
2377         ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[37];
2378         ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[69];
2379         ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[101];
2380         ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5];
2381         ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[37];
2382         ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[69];
2383         ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[101];
2384 end
2385 assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5};
2386 always @(*) begin
2387         ddrphy_dq_o_data6 <= 8'd0;
2388         ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6];
2389         ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[38];
2390         ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[70];
2391         ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[102];
2392         ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6];
2393         ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[38];
2394         ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[70];
2395         ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[102];
2396 end
2397 assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6};
2398 always @(*) begin
2399         ddrphy_dq_o_data7 <= 8'd0;
2400         ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7];
2401         ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[39];
2402         ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[71];
2403         ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[103];
2404         ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7];
2405         ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[39];
2406         ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[71];
2407         ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[103];
2408 end
2409 assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7};
2410 always @(*) begin
2411         ddrphy_dm_o_data1 <= 8'd0;
2412         ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0];
2413         ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[4];
2414         ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[8];
2415         ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[12];
2416         ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0];
2417         ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[4];
2418         ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[8];
2419         ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[12];
2420 end
2421 always @(*) begin
2422         ddrphy_dq_o_data8 <= 8'd0;
2423         ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8];
2424         ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[40];
2425         ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[72];
2426         ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[104];
2427         ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8];
2428         ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[40];
2429         ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[72];
2430         ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[104];
2431 end
2432 assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8};
2433 always @(*) begin
2434         ddrphy_dq_o_data9 <= 8'd0;
2435         ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9];
2436         ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[41];
2437         ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[73];
2438         ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[105];
2439         ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9];
2440         ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[41];
2441         ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[73];
2442         ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[105];
2443 end
2444 assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9};
2445 always @(*) begin
2446         ddrphy_dq_o_data10 <= 8'd0;
2447         ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10];
2448         ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[42];
2449         ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[74];
2450         ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[106];
2451         ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10];
2452         ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[42];
2453         ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[74];
2454         ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[106];
2455 end
2456 assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10};
2457 always @(*) begin
2458         ddrphy_dq_o_data11 <= 8'd0;
2459         ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11];
2460         ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[43];
2461         ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[75];
2462         ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[107];
2463         ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11];
2464         ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[43];
2465         ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[75];
2466         ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[107];
2467 end
2468 assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11};
2469 always @(*) begin
2470         ddrphy_dq_o_data12 <= 8'd0;
2471         ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12];
2472         ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[44];
2473         ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[76];
2474         ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[108];
2475         ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12];
2476         ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[44];
2477         ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[76];
2478         ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[108];
2479 end
2480 assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12};
2481 always @(*) begin
2482         ddrphy_dq_o_data13 <= 8'd0;
2483         ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13];
2484         ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[45];
2485         ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[77];
2486         ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[109];
2487         ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13];
2488         ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[45];
2489         ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[77];
2490         ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[109];
2491 end
2492 assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13};
2493 always @(*) begin
2494         ddrphy_dq_o_data14 <= 8'd0;
2495         ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14];
2496         ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[46];
2497         ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[78];
2498         ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[110];
2499         ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14];
2500         ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[46];
2501         ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[78];
2502         ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[110];
2503 end
2504 assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14};
2505 always @(*) begin
2506         ddrphy_dq_o_data15 <= 8'd0;
2507         ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15];
2508         ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[47];
2509         ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[79];
2510         ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[111];
2511         ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15];
2512         ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[47];
2513         ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[79];
2514         ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[111];
2515 end
2516 assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15};
2517 always @(*) begin
2518         ddrphy_dm_o_data2 <= 8'd0;
2519         ddrphy_dm_o_data2[0] <= ddrphy_dfi_p0_wrdata_mask[2];
2520         ddrphy_dm_o_data2[1] <= ddrphy_dfi_p0_wrdata_mask[6];
2521         ddrphy_dm_o_data2[2] <= ddrphy_dfi_p0_wrdata_mask[10];
2522         ddrphy_dm_o_data2[3] <= ddrphy_dfi_p0_wrdata_mask[14];
2523         ddrphy_dm_o_data2[4] <= ddrphy_dfi_p1_wrdata_mask[2];
2524         ddrphy_dm_o_data2[5] <= ddrphy_dfi_p1_wrdata_mask[6];
2525         ddrphy_dm_o_data2[6] <= ddrphy_dfi_p1_wrdata_mask[10];
2526         ddrphy_dm_o_data2[7] <= ddrphy_dfi_p1_wrdata_mask[14];
2527 end
2528 always @(*) begin
2529         ddrphy_dq_o_data16 <= 8'd0;
2530         ddrphy_dq_o_data16[0] <= ddrphy_dfi_p0_wrdata[16];
2531         ddrphy_dq_o_data16[1] <= ddrphy_dfi_p0_wrdata[48];
2532         ddrphy_dq_o_data16[2] <= ddrphy_dfi_p0_wrdata[80];
2533         ddrphy_dq_o_data16[3] <= ddrphy_dfi_p0_wrdata[112];
2534         ddrphy_dq_o_data16[4] <= ddrphy_dfi_p1_wrdata[16];
2535         ddrphy_dq_o_data16[5] <= ddrphy_dfi_p1_wrdata[48];
2536         ddrphy_dq_o_data16[6] <= ddrphy_dfi_p1_wrdata[80];
2537         ddrphy_dq_o_data16[7] <= ddrphy_dfi_p1_wrdata[112];
2538 end
2539 assign ddrphy_dq_i_data16 = {ddrphy_bitslip16_o, ddrphy_dq_i_bitslip_o_d16};
2540 always @(*) begin
2541         ddrphy_dq_o_data17 <= 8'd0;
2542         ddrphy_dq_o_data17[0] <= ddrphy_dfi_p0_wrdata[17];
2543         ddrphy_dq_o_data17[1] <= ddrphy_dfi_p0_wrdata[49];
2544         ddrphy_dq_o_data17[2] <= ddrphy_dfi_p0_wrdata[81];
2545         ddrphy_dq_o_data17[3] <= ddrphy_dfi_p0_wrdata[113];
2546         ddrphy_dq_o_data17[4] <= ddrphy_dfi_p1_wrdata[17];
2547         ddrphy_dq_o_data17[5] <= ddrphy_dfi_p1_wrdata[49];
2548         ddrphy_dq_o_data17[6] <= ddrphy_dfi_p1_wrdata[81];
2549         ddrphy_dq_o_data17[7] <= ddrphy_dfi_p1_wrdata[113];
2550 end
2551 assign ddrphy_dq_i_data17 = {ddrphy_bitslip17_o, ddrphy_dq_i_bitslip_o_d17};
2552 always @(*) begin
2553         ddrphy_dq_o_data18 <= 8'd0;
2554         ddrphy_dq_o_data18[0] <= ddrphy_dfi_p0_wrdata[18];
2555         ddrphy_dq_o_data18[1] <= ddrphy_dfi_p0_wrdata[50];
2556         ddrphy_dq_o_data18[2] <= ddrphy_dfi_p0_wrdata[82];
2557         ddrphy_dq_o_data18[3] <= ddrphy_dfi_p0_wrdata[114];
2558         ddrphy_dq_o_data18[4] <= ddrphy_dfi_p1_wrdata[18];
2559         ddrphy_dq_o_data18[5] <= ddrphy_dfi_p1_wrdata[50];
2560         ddrphy_dq_o_data18[6] <= ddrphy_dfi_p1_wrdata[82];
2561         ddrphy_dq_o_data18[7] <= ddrphy_dfi_p1_wrdata[114];
2562 end
2563 assign ddrphy_dq_i_data18 = {ddrphy_bitslip18_o, ddrphy_dq_i_bitslip_o_d18};
2564 always @(*) begin
2565         ddrphy_dq_o_data19 <= 8'd0;
2566         ddrphy_dq_o_data19[0] <= ddrphy_dfi_p0_wrdata[19];
2567         ddrphy_dq_o_data19[1] <= ddrphy_dfi_p0_wrdata[51];
2568         ddrphy_dq_o_data19[2] <= ddrphy_dfi_p0_wrdata[83];
2569         ddrphy_dq_o_data19[3] <= ddrphy_dfi_p0_wrdata[115];
2570         ddrphy_dq_o_data19[4] <= ddrphy_dfi_p1_wrdata[19];
2571         ddrphy_dq_o_data19[5] <= ddrphy_dfi_p1_wrdata[51];
2572         ddrphy_dq_o_data19[6] <= ddrphy_dfi_p1_wrdata[83];
2573         ddrphy_dq_o_data19[7] <= ddrphy_dfi_p1_wrdata[115];
2574 end
2575 assign ddrphy_dq_i_data19 = {ddrphy_bitslip19_o, ddrphy_dq_i_bitslip_o_d19};
2576 always @(*) begin
2577         ddrphy_dq_o_data20 <= 8'd0;
2578         ddrphy_dq_o_data20[0] <= ddrphy_dfi_p0_wrdata[20];
2579         ddrphy_dq_o_data20[1] <= ddrphy_dfi_p0_wrdata[52];
2580         ddrphy_dq_o_data20[2] <= ddrphy_dfi_p0_wrdata[84];
2581         ddrphy_dq_o_data20[3] <= ddrphy_dfi_p0_wrdata[116];
2582         ddrphy_dq_o_data20[4] <= ddrphy_dfi_p1_wrdata[20];
2583         ddrphy_dq_o_data20[5] <= ddrphy_dfi_p1_wrdata[52];
2584         ddrphy_dq_o_data20[6] <= ddrphy_dfi_p1_wrdata[84];
2585         ddrphy_dq_o_data20[7] <= ddrphy_dfi_p1_wrdata[116];
2586 end
2587 assign ddrphy_dq_i_data20 = {ddrphy_bitslip20_o, ddrphy_dq_i_bitslip_o_d20};
2588 always @(*) begin
2589         ddrphy_dq_o_data21 <= 8'd0;
2590         ddrphy_dq_o_data21[0] <= ddrphy_dfi_p0_wrdata[21];
2591         ddrphy_dq_o_data21[1] <= ddrphy_dfi_p0_wrdata[53];
2592         ddrphy_dq_o_data21[2] <= ddrphy_dfi_p0_wrdata[85];
2593         ddrphy_dq_o_data21[3] <= ddrphy_dfi_p0_wrdata[117];
2594         ddrphy_dq_o_data21[4] <= ddrphy_dfi_p1_wrdata[21];
2595         ddrphy_dq_o_data21[5] <= ddrphy_dfi_p1_wrdata[53];
2596         ddrphy_dq_o_data21[6] <= ddrphy_dfi_p1_wrdata[85];
2597         ddrphy_dq_o_data21[7] <= ddrphy_dfi_p1_wrdata[117];
2598 end
2599 assign ddrphy_dq_i_data21 = {ddrphy_bitslip21_o, ddrphy_dq_i_bitslip_o_d21};
2600 always @(*) begin
2601         ddrphy_dq_o_data22 <= 8'd0;
2602         ddrphy_dq_o_data22[0] <= ddrphy_dfi_p0_wrdata[22];
2603         ddrphy_dq_o_data22[1] <= ddrphy_dfi_p0_wrdata[54];
2604         ddrphy_dq_o_data22[2] <= ddrphy_dfi_p0_wrdata[86];
2605         ddrphy_dq_o_data22[3] <= ddrphy_dfi_p0_wrdata[118];
2606         ddrphy_dq_o_data22[4] <= ddrphy_dfi_p1_wrdata[22];
2607         ddrphy_dq_o_data22[5] <= ddrphy_dfi_p1_wrdata[54];
2608         ddrphy_dq_o_data22[6] <= ddrphy_dfi_p1_wrdata[86];
2609         ddrphy_dq_o_data22[7] <= ddrphy_dfi_p1_wrdata[118];
2610 end
2611 assign ddrphy_dq_i_data22 = {ddrphy_bitslip22_o, ddrphy_dq_i_bitslip_o_d22};
2612 always @(*) begin
2613         ddrphy_dq_o_data23 <= 8'd0;
2614         ddrphy_dq_o_data23[0] <= ddrphy_dfi_p0_wrdata[23];
2615         ddrphy_dq_o_data23[1] <= ddrphy_dfi_p0_wrdata[55];
2616         ddrphy_dq_o_data23[2] <= ddrphy_dfi_p0_wrdata[87];
2617         ddrphy_dq_o_data23[3] <= ddrphy_dfi_p0_wrdata[119];
2618         ddrphy_dq_o_data23[4] <= ddrphy_dfi_p1_wrdata[23];
2619         ddrphy_dq_o_data23[5] <= ddrphy_dfi_p1_wrdata[55];
2620         ddrphy_dq_o_data23[6] <= ddrphy_dfi_p1_wrdata[87];
2621         ddrphy_dq_o_data23[7] <= ddrphy_dfi_p1_wrdata[119];
2622 end
2623 assign ddrphy_dq_i_data23 = {ddrphy_bitslip23_o, ddrphy_dq_i_bitslip_o_d23};
2624 always @(*) begin
2625         ddrphy_dm_o_data3 <= 8'd0;
2626         ddrphy_dm_o_data3[0] <= ddrphy_dfi_p0_wrdata_mask[3];
2627         ddrphy_dm_o_data3[1] <= ddrphy_dfi_p0_wrdata_mask[7];
2628         ddrphy_dm_o_data3[2] <= ddrphy_dfi_p0_wrdata_mask[11];
2629         ddrphy_dm_o_data3[3] <= ddrphy_dfi_p0_wrdata_mask[15];
2630         ddrphy_dm_o_data3[4] <= ddrphy_dfi_p1_wrdata_mask[3];
2631         ddrphy_dm_o_data3[5] <= ddrphy_dfi_p1_wrdata_mask[7];
2632         ddrphy_dm_o_data3[6] <= ddrphy_dfi_p1_wrdata_mask[11];
2633         ddrphy_dm_o_data3[7] <= ddrphy_dfi_p1_wrdata_mask[15];
2634 end
2635 always @(*) begin
2636         ddrphy_dq_o_data24 <= 8'd0;
2637         ddrphy_dq_o_data24[0] <= ddrphy_dfi_p0_wrdata[24];
2638         ddrphy_dq_o_data24[1] <= ddrphy_dfi_p0_wrdata[56];
2639         ddrphy_dq_o_data24[2] <= ddrphy_dfi_p0_wrdata[88];
2640         ddrphy_dq_o_data24[3] <= ddrphy_dfi_p0_wrdata[120];
2641         ddrphy_dq_o_data24[4] <= ddrphy_dfi_p1_wrdata[24];
2642         ddrphy_dq_o_data24[5] <= ddrphy_dfi_p1_wrdata[56];
2643         ddrphy_dq_o_data24[6] <= ddrphy_dfi_p1_wrdata[88];
2644         ddrphy_dq_o_data24[7] <= ddrphy_dfi_p1_wrdata[120];
2645 end
2646 assign ddrphy_dq_i_data24 = {ddrphy_bitslip24_o, ddrphy_dq_i_bitslip_o_d24};
2647 always @(*) begin
2648         ddrphy_dq_o_data25 <= 8'd0;
2649         ddrphy_dq_o_data25[0] <= ddrphy_dfi_p0_wrdata[25];
2650         ddrphy_dq_o_data25[1] <= ddrphy_dfi_p0_wrdata[57];
2651         ddrphy_dq_o_data25[2] <= ddrphy_dfi_p0_wrdata[89];
2652         ddrphy_dq_o_data25[3] <= ddrphy_dfi_p0_wrdata[121];
2653         ddrphy_dq_o_data25[4] <= ddrphy_dfi_p1_wrdata[25];
2654         ddrphy_dq_o_data25[5] <= ddrphy_dfi_p1_wrdata[57];
2655         ddrphy_dq_o_data25[6] <= ddrphy_dfi_p1_wrdata[89];
2656         ddrphy_dq_o_data25[7] <= ddrphy_dfi_p1_wrdata[121];
2657 end
2658 assign ddrphy_dq_i_data25 = {ddrphy_bitslip25_o, ddrphy_dq_i_bitslip_o_d25};
2659 always @(*) begin
2660         ddrphy_dq_o_data26 <= 8'd0;
2661         ddrphy_dq_o_data26[0] <= ddrphy_dfi_p0_wrdata[26];
2662         ddrphy_dq_o_data26[1] <= ddrphy_dfi_p0_wrdata[58];
2663         ddrphy_dq_o_data26[2] <= ddrphy_dfi_p0_wrdata[90];
2664         ddrphy_dq_o_data26[3] <= ddrphy_dfi_p0_wrdata[122];
2665         ddrphy_dq_o_data26[4] <= ddrphy_dfi_p1_wrdata[26];
2666         ddrphy_dq_o_data26[5] <= ddrphy_dfi_p1_wrdata[58];
2667         ddrphy_dq_o_data26[6] <= ddrphy_dfi_p1_wrdata[90];
2668         ddrphy_dq_o_data26[7] <= ddrphy_dfi_p1_wrdata[122];
2669 end
2670 assign ddrphy_dq_i_data26 = {ddrphy_bitslip26_o, ddrphy_dq_i_bitslip_o_d26};
2671 always @(*) begin
2672         ddrphy_dq_o_data27 <= 8'd0;
2673         ddrphy_dq_o_data27[0] <= ddrphy_dfi_p0_wrdata[27];
2674         ddrphy_dq_o_data27[1] <= ddrphy_dfi_p0_wrdata[59];
2675         ddrphy_dq_o_data27[2] <= ddrphy_dfi_p0_wrdata[91];
2676         ddrphy_dq_o_data27[3] <= ddrphy_dfi_p0_wrdata[123];
2677         ddrphy_dq_o_data27[4] <= ddrphy_dfi_p1_wrdata[27];
2678         ddrphy_dq_o_data27[5] <= ddrphy_dfi_p1_wrdata[59];
2679         ddrphy_dq_o_data27[6] <= ddrphy_dfi_p1_wrdata[91];
2680         ddrphy_dq_o_data27[7] <= ddrphy_dfi_p1_wrdata[123];
2681 end
2682 assign ddrphy_dq_i_data27 = {ddrphy_bitslip27_o, ddrphy_dq_i_bitslip_o_d27};
2683 always @(*) begin
2684         ddrphy_dq_o_data28 <= 8'd0;
2685         ddrphy_dq_o_data28[0] <= ddrphy_dfi_p0_wrdata[28];
2686         ddrphy_dq_o_data28[1] <= ddrphy_dfi_p0_wrdata[60];
2687         ddrphy_dq_o_data28[2] <= ddrphy_dfi_p0_wrdata[92];
2688         ddrphy_dq_o_data28[3] <= ddrphy_dfi_p0_wrdata[124];
2689         ddrphy_dq_o_data28[4] <= ddrphy_dfi_p1_wrdata[28];
2690         ddrphy_dq_o_data28[5] <= ddrphy_dfi_p1_wrdata[60];
2691         ddrphy_dq_o_data28[6] <= ddrphy_dfi_p1_wrdata[92];
2692         ddrphy_dq_o_data28[7] <= ddrphy_dfi_p1_wrdata[124];
2693 end
2694 assign ddrphy_dq_i_data28 = {ddrphy_bitslip28_o, ddrphy_dq_i_bitslip_o_d28};
2695 always @(*) begin
2696         ddrphy_dq_o_data29 <= 8'd0;
2697         ddrphy_dq_o_data29[0] <= ddrphy_dfi_p0_wrdata[29];
2698         ddrphy_dq_o_data29[1] <= ddrphy_dfi_p0_wrdata[61];
2699         ddrphy_dq_o_data29[2] <= ddrphy_dfi_p0_wrdata[93];
2700         ddrphy_dq_o_data29[3] <= ddrphy_dfi_p0_wrdata[125];
2701         ddrphy_dq_o_data29[4] <= ddrphy_dfi_p1_wrdata[29];
2702         ddrphy_dq_o_data29[5] <= ddrphy_dfi_p1_wrdata[61];
2703         ddrphy_dq_o_data29[6] <= ddrphy_dfi_p1_wrdata[93];
2704         ddrphy_dq_o_data29[7] <= ddrphy_dfi_p1_wrdata[125];
2705 end
2706 assign ddrphy_dq_i_data29 = {ddrphy_bitslip29_o, ddrphy_dq_i_bitslip_o_d29};
2707 always @(*) begin
2708         ddrphy_dq_o_data30 <= 8'd0;
2709         ddrphy_dq_o_data30[0] <= ddrphy_dfi_p0_wrdata[30];
2710         ddrphy_dq_o_data30[1] <= ddrphy_dfi_p0_wrdata[62];
2711         ddrphy_dq_o_data30[2] <= ddrphy_dfi_p0_wrdata[94];
2712         ddrphy_dq_o_data30[3] <= ddrphy_dfi_p0_wrdata[126];
2713         ddrphy_dq_o_data30[4] <= ddrphy_dfi_p1_wrdata[30];
2714         ddrphy_dq_o_data30[5] <= ddrphy_dfi_p1_wrdata[62];
2715         ddrphy_dq_o_data30[6] <= ddrphy_dfi_p1_wrdata[94];
2716         ddrphy_dq_o_data30[7] <= ddrphy_dfi_p1_wrdata[126];
2717 end
2718 assign ddrphy_dq_i_data30 = {ddrphy_bitslip30_o, ddrphy_dq_i_bitslip_o_d30};
2719 always @(*) begin
2720         ddrphy_dq_o_data31 <= 8'd0;
2721         ddrphy_dq_o_data31[0] <= ddrphy_dfi_p0_wrdata[31];
2722         ddrphy_dq_o_data31[1] <= ddrphy_dfi_p0_wrdata[63];
2723         ddrphy_dq_o_data31[2] <= ddrphy_dfi_p0_wrdata[95];
2724         ddrphy_dq_o_data31[3] <= ddrphy_dfi_p0_wrdata[127];
2725         ddrphy_dq_o_data31[4] <= ddrphy_dfi_p1_wrdata[31];
2726         ddrphy_dq_o_data31[5] <= ddrphy_dfi_p1_wrdata[63];
2727         ddrphy_dq_o_data31[6] <= ddrphy_dfi_p1_wrdata[95];
2728         ddrphy_dq_o_data31[7] <= ddrphy_dfi_p1_wrdata[127];
2729 end
2730 assign ddrphy_dq_i_data31 = {ddrphy_bitslip31_o, ddrphy_dq_i_bitslip_o_d31};
2731 assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12;
2732 assign ddrphy_dfi_p1_rddata_valid = ddrphy_rddata_en_tappeddelayline12;
2733 assign ddrphy_dqs_re = (ddrphy_rddata_en_tappeddelayline3 | ddrphy_rddata_en_tappeddelayline4);
2734 assign ddrphy_dq_oe = (ddrphy_wrdata_en_tappeddelayline3 | ddrphy_wrdata_en_tappeddelayline4);
2735 assign ddrphy_bl8_chunk = ddrphy_wrdata_en_tappeddelayline3;
2736 assign ddrphy_dqs_oe = ddrphy_dq_oe;
2737 assign ddrphy_dqs_preamble = (ddrphy_wrdata_en_tappeddelayline2 & (~ddrphy_wrdata_en_tappeddelayline3));
2738 assign ddrphy_dqs_postamble = (ddrphy_wrdata_en_tappeddelayline5 & (~ddrphy_wrdata_en_tappeddelayline4));
2739 assign ddrphy_new_lock = (ddrphy_lock1 & (~ddrphy_lock_d));
2740 assign ddrphy_pause0 = ddrphy_pause1;
2741 assign ddrphy_stop0 = ddrphy_stop1;
2742 assign ddrphy_delay0 = ddrphy_delay1;
2743 assign ddrphy_reset0 = ddrphy_reset1;
2744 always @(*) begin
2745         ddrphy_bitslip0_o <= 4'd0;
2746         case (ddrphy_bitslip0_value)
2747                 1'd0: begin
2748                         ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0];
2749                 end
2750                 1'd1: begin
2751                         ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1];
2752                 end
2753                 2'd2: begin
2754                         ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2];
2755                 end
2756                 2'd3: begin
2757                         ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3];
2758                 end
2759         endcase
2760 end
2761 always @(*) begin
2762         ddrphy_bitslip1_o <= 4'd0;
2763         case (ddrphy_bitslip1_value)
2764                 1'd0: begin
2765                         ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0];
2766                 end
2767                 1'd1: begin
2768                         ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1];
2769                 end
2770                 2'd2: begin
2771                         ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2];
2772                 end
2773                 2'd3: begin
2774                         ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3];
2775                 end
2776         endcase
2777 end
2778 always @(*) begin
2779         ddrphy_bitslip2_o <= 4'd0;
2780         case (ddrphy_bitslip2_value)
2781                 1'd0: begin
2782                         ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0];
2783                 end
2784                 1'd1: begin
2785                         ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1];
2786                 end
2787                 2'd2: begin
2788                         ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2];
2789                 end
2790                 2'd3: begin
2791                         ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3];
2792                 end
2793         endcase
2794 end
2795 always @(*) begin
2796         ddrphy_bitslip3_o <= 4'd0;
2797         case (ddrphy_bitslip3_value)
2798                 1'd0: begin
2799                         ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0];
2800                 end
2801                 1'd1: begin
2802                         ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1];
2803                 end
2804                 2'd2: begin
2805                         ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2];
2806                 end
2807                 2'd3: begin
2808                         ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3];
2809                 end
2810         endcase
2811 end
2812 always @(*) begin
2813         ddrphy_bitslip4_o <= 4'd0;
2814         case (ddrphy_bitslip4_value)
2815                 1'd0: begin
2816                         ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0];
2817                 end
2818                 1'd1: begin
2819                         ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1];
2820                 end
2821                 2'd2: begin
2822                         ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2];
2823                 end
2824                 2'd3: begin
2825                         ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3];
2826                 end
2827         endcase
2828 end
2829 always @(*) begin
2830         ddrphy_bitslip5_o <= 4'd0;
2831         case (ddrphy_bitslip5_value)
2832                 1'd0: begin
2833                         ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0];
2834                 end
2835                 1'd1: begin
2836                         ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1];
2837                 end
2838                 2'd2: begin
2839                         ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2];
2840                 end
2841                 2'd3: begin
2842                         ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3];
2843                 end
2844         endcase
2845 end
2846 always @(*) begin
2847         ddrphy_bitslip6_o <= 4'd0;
2848         case (ddrphy_bitslip6_value)
2849                 1'd0: begin
2850                         ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0];
2851                 end
2852                 1'd1: begin
2853                         ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1];
2854                 end
2855                 2'd2: begin
2856                         ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2];
2857                 end
2858                 2'd3: begin
2859                         ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3];
2860                 end
2861         endcase
2862 end
2863 always @(*) begin
2864         ddrphy_bitslip7_o <= 4'd0;
2865         case (ddrphy_bitslip7_value)
2866                 1'd0: begin
2867                         ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0];
2868                 end
2869                 1'd1: begin
2870                         ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1];
2871                 end
2872                 2'd2: begin
2873                         ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2];
2874                 end
2875                 2'd3: begin
2876                         ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3];
2877                 end
2878         endcase
2879 end
2880 always @(*) begin
2881         ddrphy_bitslip8_o <= 4'd0;
2882         case (ddrphy_bitslip8_value)
2883                 1'd0: begin
2884                         ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0];
2885                 end
2886                 1'd1: begin
2887                         ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1];
2888                 end
2889                 2'd2: begin
2890                         ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2];
2891                 end
2892                 2'd3: begin
2893                         ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3];
2894                 end
2895         endcase
2896 end
2897 always @(*) begin
2898         ddrphy_bitslip9_o <= 4'd0;
2899         case (ddrphy_bitslip9_value)
2900                 1'd0: begin
2901                         ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0];
2902                 end
2903                 1'd1: begin
2904                         ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1];
2905                 end
2906                 2'd2: begin
2907                         ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2];
2908                 end
2909                 2'd3: begin
2910                         ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3];
2911                 end
2912         endcase
2913 end
2914 always @(*) begin
2915         ddrphy_bitslip10_o <= 4'd0;
2916         case (ddrphy_bitslip10_value)
2917                 1'd0: begin
2918                         ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0];
2919                 end
2920                 1'd1: begin
2921                         ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1];
2922                 end
2923                 2'd2: begin
2924                         ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2];
2925                 end
2926                 2'd3: begin
2927                         ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3];
2928                 end
2929         endcase
2930 end
2931 always @(*) begin
2932         ddrphy_bitslip11_o <= 4'd0;
2933         case (ddrphy_bitslip11_value)
2934                 1'd0: begin
2935                         ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0];
2936                 end
2937                 1'd1: begin
2938                         ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1];
2939                 end
2940                 2'd2: begin
2941                         ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2];
2942                 end
2943                 2'd3: begin
2944                         ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3];
2945                 end
2946         endcase
2947 end
2948 always @(*) begin
2949         ddrphy_bitslip12_o <= 4'd0;
2950         case (ddrphy_bitslip12_value)
2951                 1'd0: begin
2952                         ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0];
2953                 end
2954                 1'd1: begin
2955                         ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1];
2956                 end
2957                 2'd2: begin
2958                         ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2];
2959                 end
2960                 2'd3: begin
2961                         ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3];
2962                 end
2963         endcase
2964 end
2965 always @(*) begin
2966         ddrphy_bitslip13_o <= 4'd0;
2967         case (ddrphy_bitslip13_value)
2968                 1'd0: begin
2969                         ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0];
2970                 end
2971                 1'd1: begin
2972                         ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1];
2973                 end
2974                 2'd2: begin
2975                         ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2];
2976                 end
2977                 2'd3: begin
2978                         ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3];
2979                 end
2980         endcase
2981 end
2982 always @(*) begin
2983         ddrphy_bitslip14_o <= 4'd0;
2984         case (ddrphy_bitslip14_value)
2985                 1'd0: begin
2986                         ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0];
2987                 end
2988                 1'd1: begin
2989                         ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1];
2990                 end
2991                 2'd2: begin
2992                         ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2];
2993                 end
2994                 2'd3: begin
2995                         ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3];
2996                 end
2997         endcase
2998 end
2999 always @(*) begin
3000         ddrphy_bitslip15_o <= 4'd0;
3001         case (ddrphy_bitslip15_value)
3002                 1'd0: begin
3003                         ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0];
3004                 end
3005                 1'd1: begin
3006                         ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1];
3007                 end
3008                 2'd2: begin
3009                         ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2];
3010                 end
3011                 2'd3: begin
3012                         ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3];
3013                 end
3014         endcase
3015 end
3016 always @(*) begin
3017         ddrphy_bitslip16_o <= 4'd0;
3018         case (ddrphy_bitslip16_value)
3019                 1'd0: begin
3020                         ddrphy_bitslip16_o <= ddrphy_bitslip16_r[3:0];
3021                 end
3022                 1'd1: begin
3023                         ddrphy_bitslip16_o <= ddrphy_bitslip16_r[4:1];
3024                 end
3025                 2'd2: begin
3026                         ddrphy_bitslip16_o <= ddrphy_bitslip16_r[5:2];
3027                 end
3028                 2'd3: begin
3029                         ddrphy_bitslip16_o <= ddrphy_bitslip16_r[6:3];
3030                 end
3031         endcase
3032 end
3033 always @(*) begin
3034         ddrphy_bitslip17_o <= 4'd0;
3035         case (ddrphy_bitslip17_value)
3036                 1'd0: begin
3037                         ddrphy_bitslip17_o <= ddrphy_bitslip17_r[3:0];
3038                 end
3039                 1'd1: begin
3040                         ddrphy_bitslip17_o <= ddrphy_bitslip17_r[4:1];
3041                 end
3042                 2'd2: begin
3043                         ddrphy_bitslip17_o <= ddrphy_bitslip17_r[5:2];
3044                 end
3045                 2'd3: begin
3046                         ddrphy_bitslip17_o <= ddrphy_bitslip17_r[6:3];
3047                 end
3048         endcase
3049 end
3050 always @(*) begin
3051         ddrphy_bitslip18_o <= 4'd0;
3052         case (ddrphy_bitslip18_value)
3053                 1'd0: begin
3054                         ddrphy_bitslip18_o <= ddrphy_bitslip18_r[3:0];
3055                 end
3056                 1'd1: begin
3057                         ddrphy_bitslip18_o <= ddrphy_bitslip18_r[4:1];
3058                 end
3059                 2'd2: begin
3060                         ddrphy_bitslip18_o <= ddrphy_bitslip18_r[5:2];
3061                 end
3062                 2'd3: begin
3063                         ddrphy_bitslip18_o <= ddrphy_bitslip18_r[6:3];
3064                 end
3065         endcase
3066 end
3067 always @(*) begin
3068         ddrphy_bitslip19_o <= 4'd0;
3069         case (ddrphy_bitslip19_value)
3070                 1'd0: begin
3071                         ddrphy_bitslip19_o <= ddrphy_bitslip19_r[3:0];
3072                 end
3073                 1'd1: begin
3074                         ddrphy_bitslip19_o <= ddrphy_bitslip19_r[4:1];
3075                 end
3076                 2'd2: begin
3077                         ddrphy_bitslip19_o <= ddrphy_bitslip19_r[5:2];
3078                 end
3079                 2'd3: begin
3080                         ddrphy_bitslip19_o <= ddrphy_bitslip19_r[6:3];
3081                 end
3082         endcase
3083 end
3084 always @(*) begin
3085         ddrphy_bitslip20_o <= 4'd0;
3086         case (ddrphy_bitslip20_value)
3087                 1'd0: begin
3088                         ddrphy_bitslip20_o <= ddrphy_bitslip20_r[3:0];
3089                 end
3090                 1'd1: begin
3091                         ddrphy_bitslip20_o <= ddrphy_bitslip20_r[4:1];
3092                 end
3093                 2'd2: begin
3094                         ddrphy_bitslip20_o <= ddrphy_bitslip20_r[5:2];
3095                 end
3096                 2'd3: begin
3097                         ddrphy_bitslip20_o <= ddrphy_bitslip20_r[6:3];
3098                 end
3099         endcase
3100 end
3101 always @(*) begin
3102         ddrphy_bitslip21_o <= 4'd0;
3103         case (ddrphy_bitslip21_value)
3104                 1'd0: begin
3105                         ddrphy_bitslip21_o <= ddrphy_bitslip21_r[3:0];
3106                 end
3107                 1'd1: begin
3108                         ddrphy_bitslip21_o <= ddrphy_bitslip21_r[4:1];
3109                 end
3110                 2'd2: begin
3111                         ddrphy_bitslip21_o <= ddrphy_bitslip21_r[5:2];
3112                 end
3113                 2'd3: begin
3114                         ddrphy_bitslip21_o <= ddrphy_bitslip21_r[6:3];
3115                 end
3116         endcase
3117 end
3118 always @(*) begin
3119         ddrphy_bitslip22_o <= 4'd0;
3120         case (ddrphy_bitslip22_value)
3121                 1'd0: begin
3122                         ddrphy_bitslip22_o <= ddrphy_bitslip22_r[3:0];
3123                 end
3124                 1'd1: begin
3125                         ddrphy_bitslip22_o <= ddrphy_bitslip22_r[4:1];
3126                 end
3127                 2'd2: begin
3128                         ddrphy_bitslip22_o <= ddrphy_bitslip22_r[5:2];
3129                 end
3130                 2'd3: begin
3131                         ddrphy_bitslip22_o <= ddrphy_bitslip22_r[6:3];
3132                 end
3133         endcase
3134 end
3135 always @(*) begin
3136         ddrphy_bitslip23_o <= 4'd0;
3137         case (ddrphy_bitslip23_value)
3138                 1'd0: begin
3139                         ddrphy_bitslip23_o <= ddrphy_bitslip23_r[3:0];
3140                 end
3141                 1'd1: begin
3142                         ddrphy_bitslip23_o <= ddrphy_bitslip23_r[4:1];
3143                 end
3144                 2'd2: begin
3145                         ddrphy_bitslip23_o <= ddrphy_bitslip23_r[5:2];
3146                 end
3147                 2'd3: begin
3148                         ddrphy_bitslip23_o <= ddrphy_bitslip23_r[6:3];
3149                 end
3150         endcase
3151 end
3152 always @(*) begin
3153         ddrphy_bitslip24_o <= 4'd0;
3154         case (ddrphy_bitslip24_value)
3155                 1'd0: begin
3156                         ddrphy_bitslip24_o <= ddrphy_bitslip24_r[3:0];
3157                 end
3158                 1'd1: begin
3159                         ddrphy_bitslip24_o <= ddrphy_bitslip24_r[4:1];
3160                 end
3161                 2'd2: begin
3162                         ddrphy_bitslip24_o <= ddrphy_bitslip24_r[5:2];
3163                 end
3164                 2'd3: begin
3165                         ddrphy_bitslip24_o <= ddrphy_bitslip24_r[6:3];
3166                 end
3167         endcase
3168 end
3169 always @(*) begin
3170         ddrphy_bitslip25_o <= 4'd0;
3171         case (ddrphy_bitslip25_value)
3172                 1'd0: begin
3173                         ddrphy_bitslip25_o <= ddrphy_bitslip25_r[3:0];
3174                 end
3175                 1'd1: begin
3176                         ddrphy_bitslip25_o <= ddrphy_bitslip25_r[4:1];
3177                 end
3178                 2'd2: begin
3179                         ddrphy_bitslip25_o <= ddrphy_bitslip25_r[5:2];
3180                 end
3181                 2'd3: begin
3182                         ddrphy_bitslip25_o <= ddrphy_bitslip25_r[6:3];
3183                 end
3184         endcase
3185 end
3186 always @(*) begin
3187         ddrphy_bitslip26_o <= 4'd0;
3188         case (ddrphy_bitslip26_value)
3189                 1'd0: begin
3190                         ddrphy_bitslip26_o <= ddrphy_bitslip26_r[3:0];
3191                 end
3192                 1'd1: begin
3193                         ddrphy_bitslip26_o <= ddrphy_bitslip26_r[4:1];
3194                 end
3195                 2'd2: begin
3196                         ddrphy_bitslip26_o <= ddrphy_bitslip26_r[5:2];
3197                 end
3198                 2'd3: begin
3199                         ddrphy_bitslip26_o <= ddrphy_bitslip26_r[6:3];
3200                 end
3201         endcase
3202 end
3203 always @(*) begin
3204         ddrphy_bitslip27_o <= 4'd0;
3205         case (ddrphy_bitslip27_value)
3206                 1'd0: begin
3207                         ddrphy_bitslip27_o <= ddrphy_bitslip27_r[3:0];
3208                 end
3209                 1'd1: begin
3210                         ddrphy_bitslip27_o <= ddrphy_bitslip27_r[4:1];
3211                 end
3212                 2'd2: begin
3213                         ddrphy_bitslip27_o <= ddrphy_bitslip27_r[5:2];
3214                 end
3215                 2'd3: begin
3216                         ddrphy_bitslip27_o <= ddrphy_bitslip27_r[6:3];
3217                 end
3218         endcase
3219 end
3220 always @(*) begin
3221         ddrphy_bitslip28_o <= 4'd0;
3222         case (ddrphy_bitslip28_value)
3223                 1'd0: begin
3224                         ddrphy_bitslip28_o <= ddrphy_bitslip28_r[3:0];
3225                 end
3226                 1'd1: begin
3227                         ddrphy_bitslip28_o <= ddrphy_bitslip28_r[4:1];
3228                 end
3229                 2'd2: begin
3230                         ddrphy_bitslip28_o <= ddrphy_bitslip28_r[5:2];
3231                 end
3232                 2'd3: begin
3233                         ddrphy_bitslip28_o <= ddrphy_bitslip28_r[6:3];
3234                 end
3235         endcase
3236 end
3237 always @(*) begin
3238         ddrphy_bitslip29_o <= 4'd0;
3239         case (ddrphy_bitslip29_value)
3240                 1'd0: begin
3241                         ddrphy_bitslip29_o <= ddrphy_bitslip29_r[3:0];
3242                 end
3243                 1'd1: begin
3244                         ddrphy_bitslip29_o <= ddrphy_bitslip29_r[4:1];
3245                 end
3246                 2'd2: begin
3247                         ddrphy_bitslip29_o <= ddrphy_bitslip29_r[5:2];
3248                 end
3249                 2'd3: begin
3250                         ddrphy_bitslip29_o <= ddrphy_bitslip29_r[6:3];
3251                 end
3252         endcase
3253 end
3254 always @(*) begin
3255         ddrphy_bitslip30_o <= 4'd0;
3256         case (ddrphy_bitslip30_value)
3257                 1'd0: begin
3258                         ddrphy_bitslip30_o <= ddrphy_bitslip30_r[3:0];
3259                 end
3260                 1'd1: begin
3261                         ddrphy_bitslip30_o <= ddrphy_bitslip30_r[4:1];
3262                 end
3263                 2'd2: begin
3264                         ddrphy_bitslip30_o <= ddrphy_bitslip30_r[5:2];
3265                 end
3266                 2'd3: begin
3267                         ddrphy_bitslip30_o <= ddrphy_bitslip30_r[6:3];
3268                 end
3269         endcase
3270 end
3271 always @(*) begin
3272         ddrphy_bitslip31_o <= 4'd0;
3273         case (ddrphy_bitslip31_value)
3274                 1'd0: begin
3275                         ddrphy_bitslip31_o <= ddrphy_bitslip31_r[3:0];
3276                 end
3277                 1'd1: begin
3278                         ddrphy_bitslip31_o <= ddrphy_bitslip31_r[4:1];
3279                 end
3280                 2'd2: begin
3281                         ddrphy_bitslip31_o <= ddrphy_bitslip31_r[5:2];
3282                 end
3283                 2'd3: begin
3284                         ddrphy_bitslip31_o <= ddrphy_bitslip31_r[6:3];
3285                 end
3286         endcase
3287 end
3288 assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
3289 assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
3290 assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
3291 assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
3292 assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
3293 assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
3294 assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
3295 assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
3296 assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
3297 assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
3298 assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
3299 assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
3300 assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
3301 assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
3302 assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata;
3303 assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid;
3304 assign ddrphy_dfi_p1_address = litedramcore_master_p1_address;
3305 assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
3306 assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
3307 assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
3308 assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
3309 assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
3310 assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
3311 assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
3312 assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
3313 assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
3314 assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
3315 assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
3316 assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
3317 assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
3318 assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata;
3319 assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid;
3320 assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
3321 assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
3322 assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
3323 assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
3324 assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
3325 assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
3326 assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
3327 assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
3328 assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
3329 assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
3330 assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
3331 assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
3332 assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
3333 assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
3334 assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
3335 assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
3336 assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
3337 assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
3338 assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
3339 assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
3340 assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
3341 assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
3342 assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
3343 assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
3344 assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
3345 assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
3346 assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
3347 assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
3348 assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
3349 assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
3350 assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
3351 assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
3352 always @(*) begin
3353         litedramcore_master_p1_rddata_en <= 1'd0;
3354         if (litedramcore_sel) begin
3355                 litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
3356         end else begin
3357                 litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
3358         end
3359 end
3360 always @(*) begin
3361         litedramcore_slave_p0_rddata <= 128'd0;
3362         if (litedramcore_sel) begin
3363                 litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
3364         end else begin
3365         end
3366 end
3367 always @(*) begin
3368         litedramcore_slave_p0_rddata_valid <= 1'd0;
3369         if (litedramcore_sel) begin
3370                 litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
3371         end else begin
3372         end
3373 end
3374 always @(*) begin
3375         litedramcore_slave_p1_rddata <= 128'd0;
3376         if (litedramcore_sel) begin
3377                 litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
3378         end else begin
3379         end
3380 end
3381 always @(*) begin
3382         litedramcore_slave_p1_rddata_valid <= 1'd0;
3383         if (litedramcore_sel) begin
3384                 litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
3385         end else begin
3386         end
3387 end
3388 always @(*) begin
3389         litedramcore_master_p0_address <= 15'd0;
3390         if (litedramcore_sel) begin
3391                 litedramcore_master_p0_address <= litedramcore_slave_p0_address;
3392         end else begin
3393                 litedramcore_master_p0_address <= litedramcore_inti_p0_address;
3394         end
3395 end
3396 always @(*) begin
3397         litedramcore_master_p0_bank <= 3'd0;
3398         if (litedramcore_sel) begin
3399                 litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
3400         end else begin
3401                 litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
3402         end
3403 end
3404 always @(*) begin
3405         litedramcore_master_p0_cas_n <= 1'd1;
3406         if (litedramcore_sel) begin
3407                 litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
3408         end else begin
3409                 litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
3410         end
3411 end
3412 always @(*) begin
3413         litedramcore_master_p0_cs_n <= 1'd1;
3414         if (litedramcore_sel) begin
3415                 litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
3416         end else begin
3417                 litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
3418         end
3419 end
3420 always @(*) begin
3421         litedramcore_master_p0_ras_n <= 1'd1;
3422         if (litedramcore_sel) begin
3423                 litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
3424         end else begin
3425                 litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
3426         end
3427 end
3428 always @(*) begin
3429         litedramcore_inti_p0_rddata <= 128'd0;
3430         if (litedramcore_sel) begin
3431         end else begin
3432                 litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
3433         end
3434 end
3435 always @(*) begin
3436         litedramcore_master_p0_we_n <= 1'd1;
3437         if (litedramcore_sel) begin
3438                 litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
3439         end else begin
3440                 litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
3441         end
3442 end
3443 always @(*) begin
3444         litedramcore_inti_p0_rddata_valid <= 1'd0;
3445         if (litedramcore_sel) begin
3446         end else begin
3447                 litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
3448         end
3449 end
3450 always @(*) begin
3451         litedramcore_master_p0_cke <= 1'd0;
3452         if (litedramcore_sel) begin
3453                 litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
3454         end else begin
3455                 litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
3456         end
3457 end
3458 always @(*) begin
3459         litedramcore_master_p0_odt <= 1'd0;
3460         if (litedramcore_sel) begin
3461                 litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
3462         end else begin
3463                 litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
3464         end
3465 end
3466 always @(*) begin
3467         litedramcore_master_p0_reset_n <= 1'd0;
3468         if (litedramcore_sel) begin
3469                 litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
3470         end else begin
3471                 litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
3472         end
3473 end
3474 always @(*) begin
3475         litedramcore_master_p0_act_n <= 1'd1;
3476         if (litedramcore_sel) begin
3477                 litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
3478         end else begin
3479                 litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
3480         end
3481 end
3482 always @(*) begin
3483         litedramcore_master_p0_wrdata <= 128'd0;
3484         if (litedramcore_sel) begin
3485                 litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
3486         end else begin
3487                 litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
3488         end
3489 end
3490 always @(*) begin
3491         litedramcore_master_p0_wrdata_en <= 1'd0;
3492         if (litedramcore_sel) begin
3493                 litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
3494         end else begin
3495                 litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
3496         end
3497 end
3498 always @(*) begin
3499         litedramcore_master_p0_wrdata_mask <= 16'd0;
3500         if (litedramcore_sel) begin
3501                 litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
3502         end else begin
3503                 litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
3504         end
3505 end
3506 always @(*) begin
3507         litedramcore_master_p0_rddata_en <= 1'd0;
3508         if (litedramcore_sel) begin
3509                 litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
3510         end else begin
3511                 litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
3512         end
3513 end
3514 always @(*) begin
3515         litedramcore_master_p1_address <= 15'd0;
3516         if (litedramcore_sel) begin
3517                 litedramcore_master_p1_address <= litedramcore_slave_p1_address;
3518         end else begin
3519                 litedramcore_master_p1_address <= litedramcore_inti_p1_address;
3520         end
3521 end
3522 always @(*) begin
3523         litedramcore_master_p1_bank <= 3'd0;
3524         if (litedramcore_sel) begin
3525                 litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
3526         end else begin
3527                 litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
3528         end
3529 end
3530 always @(*) begin
3531         litedramcore_master_p1_cas_n <= 1'd1;
3532         if (litedramcore_sel) begin
3533                 litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
3534         end else begin
3535                 litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
3536         end
3537 end
3538 always @(*) begin
3539         litedramcore_master_p1_cs_n <= 1'd1;
3540         if (litedramcore_sel) begin
3541                 litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
3542         end else begin
3543                 litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
3544         end
3545 end
3546 always @(*) begin
3547         litedramcore_master_p1_ras_n <= 1'd1;
3548         if (litedramcore_sel) begin
3549                 litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
3550         end else begin
3551                 litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
3552         end
3553 end
3554 always @(*) begin
3555         litedramcore_inti_p1_rddata <= 128'd0;
3556         if (litedramcore_sel) begin
3557         end else begin
3558                 litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
3559         end
3560 end
3561 always @(*) begin
3562         litedramcore_master_p1_we_n <= 1'd1;
3563         if (litedramcore_sel) begin
3564                 litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
3565         end else begin
3566                 litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
3567         end
3568 end
3569 always @(*) begin
3570         litedramcore_inti_p1_rddata_valid <= 1'd0;
3571         if (litedramcore_sel) begin
3572         end else begin
3573                 litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
3574         end
3575 end
3576 always @(*) begin
3577         litedramcore_master_p1_cke <= 1'd0;
3578         if (litedramcore_sel) begin
3579                 litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
3580         end else begin
3581                 litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
3582         end
3583 end
3584 always @(*) begin
3585         litedramcore_master_p1_odt <= 1'd0;
3586         if (litedramcore_sel) begin
3587                 litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
3588         end else begin
3589                 litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
3590         end
3591 end
3592 always @(*) begin
3593         litedramcore_master_p1_reset_n <= 1'd0;
3594         if (litedramcore_sel) begin
3595                 litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
3596         end else begin
3597                 litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
3598         end
3599 end
3600 always @(*) begin
3601         litedramcore_master_p1_act_n <= 1'd1;
3602         if (litedramcore_sel) begin
3603                 litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
3604         end else begin
3605                 litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
3606         end
3607 end
3608 always @(*) begin
3609         litedramcore_master_p1_wrdata <= 128'd0;
3610         if (litedramcore_sel) begin
3611                 litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
3612         end else begin
3613                 litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
3614         end
3615 end
3616 always @(*) begin
3617         litedramcore_master_p1_wrdata_en <= 1'd0;
3618         if (litedramcore_sel) begin
3619                 litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
3620         end else begin
3621                 litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
3622         end
3623 end
3624 always @(*) begin
3625         litedramcore_master_p1_wrdata_mask <= 16'd0;
3626         if (litedramcore_sel) begin
3627                 litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
3628         end else begin
3629                 litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
3630         end
3631 end
3632 assign litedramcore_inti_p0_cke = litedramcore_cke;
3633 assign litedramcore_inti_p1_cke = litedramcore_cke;
3634 assign litedramcore_inti_p0_odt = litedramcore_odt;
3635 assign litedramcore_inti_p1_odt = litedramcore_odt;
3636 assign litedramcore_inti_p0_reset_n = litedramcore_reset_n;
3637 assign litedramcore_inti_p1_reset_n = litedramcore_reset_n;
3638 always @(*) begin
3639         litedramcore_inti_p0_cs_n <= 1'd1;
3640         if (litedramcore_phaseinjector0_command_issue_re) begin
3641                 litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
3642         end else begin
3643                 litedramcore_inti_p0_cs_n <= {1{1'd1}};
3644         end
3645 end
3646 always @(*) begin
3647         litedramcore_inti_p0_ras_n <= 1'd1;
3648         if (litedramcore_phaseinjector0_command_issue_re) begin
3649                 litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
3650         end else begin
3651                 litedramcore_inti_p0_ras_n <= 1'd1;
3652         end
3653 end
3654 always @(*) begin
3655         litedramcore_inti_p0_we_n <= 1'd1;
3656         if (litedramcore_phaseinjector0_command_issue_re) begin
3657                 litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
3658         end else begin
3659                 litedramcore_inti_p0_we_n <= 1'd1;
3660         end
3661 end
3662 always @(*) begin
3663         litedramcore_inti_p0_cas_n <= 1'd1;
3664         if (litedramcore_phaseinjector0_command_issue_re) begin
3665                 litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
3666         end else begin
3667                 litedramcore_inti_p0_cas_n <= 1'd1;
3668         end
3669 end
3670 assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
3671 assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
3672 assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
3673 assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
3674 assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
3675 assign litedramcore_inti_p0_wrdata_mask = 1'd0;
3676 always @(*) begin
3677         litedramcore_inti_p1_cs_n <= 1'd1;
3678         if (litedramcore_phaseinjector1_command_issue_re) begin
3679                 litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
3680         end else begin
3681                 litedramcore_inti_p1_cs_n <= {1{1'd1}};
3682         end
3683 end
3684 always @(*) begin
3685         litedramcore_inti_p1_ras_n <= 1'd1;
3686         if (litedramcore_phaseinjector1_command_issue_re) begin
3687                 litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
3688         end else begin
3689                 litedramcore_inti_p1_ras_n <= 1'd1;
3690         end
3691 end
3692 always @(*) begin
3693         litedramcore_inti_p1_we_n <= 1'd1;
3694         if (litedramcore_phaseinjector1_command_issue_re) begin
3695                 litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
3696         end else begin
3697                 litedramcore_inti_p1_we_n <= 1'd1;
3698         end
3699 end
3700 always @(*) begin
3701         litedramcore_inti_p1_cas_n <= 1'd1;
3702         if (litedramcore_phaseinjector1_command_issue_re) begin
3703                 litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
3704         end else begin
3705                 litedramcore_inti_p1_cas_n <= 1'd1;
3706         end
3707 end
3708 assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
3709 assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
3710 assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
3711 assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
3712 assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
3713 assign litedramcore_inti_p1_wrdata_mask = 1'd0;
3714 assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
3715 assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
3716 assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
3717 assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
3718 assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
3719 assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
3720 assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
3721 assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
3722 assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
3723 assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
3724 assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
3725 assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
3726 assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
3727 assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
3728 assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
3729 assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
3730 assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
3731 assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
3732 assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
3733 assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
3734 assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
3735 assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
3736 assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
3737 assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
3738 assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
3739 assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
3740 assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
3741 assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
3742 assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
3743 assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
3744 assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
3745 assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
3746 assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
3747 assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
3748 assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
3749 assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
3750 assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
3751 assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
3752 assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
3753 assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
3754 assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
3755 assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
3756 assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
3757 assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
3758 assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
3759 assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
3760 assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
3761 assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
3762 assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
3763 assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
3764 assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
3765 assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
3766 assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
3767 assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
3768 assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
3769 assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
3770 assign litedramcore_timer_wait = (~litedramcore_timer_done0);
3771 assign litedramcore_postponer_req_i = litedramcore_timer_done0;
3772 assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
3773 assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
3774 assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
3775 assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
3776 assign litedramcore_timer_done0 = litedramcore_timer_done1;
3777 assign litedramcore_timer_count0 = litedramcore_timer_count1;
3778 assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
3779 assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
3780 assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
3781 assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
3782 assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
3783 always @(*) begin
3784         litedramcore_refresher_next_state <= 2'd0;
3785         litedramcore_refresher_next_state <= litedramcore_refresher_state;
3786         case (litedramcore_refresher_state)
3787                 1'd1: begin
3788                         if (litedramcore_cmd_ready) begin
3789                                 litedramcore_refresher_next_state <= 2'd2;
3790                         end
3791                 end
3792                 2'd2: begin
3793                         if (litedramcore_sequencer_done0) begin
3794                                 if (litedramcore_wants_zqcs) begin
3795                                         litedramcore_refresher_next_state <= 2'd3;
3796                                 end else begin
3797                                         litedramcore_refresher_next_state <= 1'd0;
3798                                 end
3799                         end
3800                 end
3801                 2'd3: begin
3802                         if (litedramcore_zqcs_executer_done) begin
3803                                 litedramcore_refresher_next_state <= 1'd0;
3804                         end
3805                 end
3806                 default: begin
3807                         if (1'd1) begin
3808                                 if (litedramcore_wants_refresh) begin
3809                                         litedramcore_refresher_next_state <= 1'd1;
3810                                 end
3811                         end
3812                 end
3813         endcase
3814 end
3815 always @(*) begin
3816         litedramcore_sequencer_start0 <= 1'd0;
3817         case (litedramcore_refresher_state)
3818                 1'd1: begin
3819                         if (litedramcore_cmd_ready) begin
3820                                 litedramcore_sequencer_start0 <= 1'd1;
3821                         end
3822                 end
3823                 2'd2: begin
3824                 end
3825                 2'd3: begin
3826                 end
3827                 default: begin
3828                 end
3829         endcase
3830 end
3831 always @(*) begin
3832         litedramcore_cmd_valid <= 1'd0;
3833         case (litedramcore_refresher_state)
3834                 1'd1: begin
3835                         litedramcore_cmd_valid <= 1'd1;
3836                 end
3837                 2'd2: begin
3838                         litedramcore_cmd_valid <= 1'd1;
3839                         if (litedramcore_sequencer_done0) begin
3840                                 if (litedramcore_wants_zqcs) begin
3841                                 end else begin
3842                                         litedramcore_cmd_valid <= 1'd0;
3843                                 end
3844                         end
3845                 end
3846                 2'd3: begin
3847                         litedramcore_cmd_valid <= 1'd1;
3848                         if (litedramcore_zqcs_executer_done) begin
3849                                 litedramcore_cmd_valid <= 1'd0;
3850                         end
3851                 end
3852                 default: begin
3853                 end
3854         endcase
3855 end
3856 always @(*) begin
3857         litedramcore_zqcs_executer_start <= 1'd0;
3858         case (litedramcore_refresher_state)
3859                 1'd1: begin
3860                 end
3861                 2'd2: begin
3862                         if (litedramcore_sequencer_done0) begin
3863                                 if (litedramcore_wants_zqcs) begin
3864                                         litedramcore_zqcs_executer_start <= 1'd1;
3865                                 end else begin
3866                                 end
3867                         end
3868                 end
3869                 2'd3: begin
3870                 end
3871                 default: begin
3872                 end
3873         endcase
3874 end
3875 always @(*) begin
3876         litedramcore_cmd_last <= 1'd0;
3877         case (litedramcore_refresher_state)
3878                 1'd1: begin
3879                 end
3880                 2'd2: begin
3881                         if (litedramcore_sequencer_done0) begin
3882                                 if (litedramcore_wants_zqcs) begin
3883                                 end else begin
3884                                         litedramcore_cmd_last <= 1'd1;
3885                                 end
3886                         end
3887                 end
3888                 2'd3: begin
3889                         if (litedramcore_zqcs_executer_done) begin
3890                                 litedramcore_cmd_last <= 1'd1;
3891                         end
3892                 end
3893                 default: begin
3894                 end
3895         endcase
3896 end
3897 assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
3898 assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
3899 assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
3900 assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
3901 assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
3902 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
3903 assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
3904 assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
3905 assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
3906 assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
3907 assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
3908 assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
3909 assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
3910 assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
3911 always @(*) begin
3912         litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
3913         if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
3914                 litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
3915         end else begin
3916                 litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
3917         end
3918 end
3919 assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
3920 assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
3921 assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
3922 always @(*) begin
3923         litedramcore_bankmachine0_auto_precharge <= 1'd0;
3924         if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
3925                 if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
3926                         litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
3927                 end
3928         end
3929 end
3930 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
3931 assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
3932 assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
3933 assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
3934 assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
3935 assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
3936 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
3937 assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
3938 assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
3939 assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
3940 assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
3941 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
3942 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
3943 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
3944 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
3945 assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
3946 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
3947 always @(*) begin
3948         litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
3949         if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
3950                 litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
3951         end else begin
3952                 litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
3953         end
3954 end
3955 assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
3956 assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
3957 assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
3958 assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
3959 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
3960 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
3961 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
3962 assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
3963 always @(*) begin
3964         litedramcore_bankmachine0_next_state <= 3'd0;
3965         litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
3966         case (litedramcore_bankmachine0_state)
3967                 1'd1: begin
3968                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
3969                                 if (litedramcore_bankmachine0_cmd_ready) begin
3970                                         litedramcore_bankmachine0_next_state <= 3'd5;
3971                                 end
3972                         end
3973                 end
3974                 2'd2: begin
3975                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
3976                                 litedramcore_bankmachine0_next_state <= 3'd5;
3977                         end
3978                 end
3979                 2'd3: begin
3980                         if (litedramcore_bankmachine0_trccon_ready) begin
3981                                 if (litedramcore_bankmachine0_cmd_ready) begin
3982                                         litedramcore_bankmachine0_next_state <= 3'd6;
3983                                 end
3984                         end
3985                 end
3986                 3'd4: begin
3987                         if ((~litedramcore_bankmachine0_refresh_req)) begin
3988                                 litedramcore_bankmachine0_next_state <= 1'd0;
3989                         end
3990                 end
3991                 3'd5: begin
3992                         litedramcore_bankmachine0_next_state <= 2'd3;
3993                 end
3994                 3'd6: begin
3995                         litedramcore_bankmachine0_next_state <= 1'd0;
3996                 end
3997                 default: begin
3998                         if (litedramcore_bankmachine0_refresh_req) begin
3999                                 litedramcore_bankmachine0_next_state <= 3'd4;
4000                         end else begin
4001                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4002                                         if (litedramcore_bankmachine0_row_opened) begin
4003                                                 if (litedramcore_bankmachine0_row_hit) begin
4004                                                         if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
4005                                                                 litedramcore_bankmachine0_next_state <= 2'd2;
4006                                                         end
4007                                                 end else begin
4008                                                         litedramcore_bankmachine0_next_state <= 1'd1;
4009                                                 end
4010                                         end else begin
4011                                                 litedramcore_bankmachine0_next_state <= 2'd3;
4012                                         end
4013                                 end
4014                         end
4015                 end
4016         endcase
4017 end
4018 always @(*) begin
4019         litedramcore_bankmachine0_row_open <= 1'd0;
4020         case (litedramcore_bankmachine0_state)
4021                 1'd1: begin
4022                 end
4023                 2'd2: begin
4024                 end
4025                 2'd3: begin
4026                         if (litedramcore_bankmachine0_trccon_ready) begin
4027                                 litedramcore_bankmachine0_row_open <= 1'd1;
4028                         end
4029                 end
4030                 3'd4: begin
4031                 end
4032                 3'd5: begin
4033                 end
4034                 3'd6: begin
4035                 end
4036                 default: begin
4037                 end
4038         endcase
4039 end
4040 always @(*) begin
4041         litedramcore_bankmachine0_row_close <= 1'd0;
4042         case (litedramcore_bankmachine0_state)
4043                 1'd1: begin
4044                         litedramcore_bankmachine0_row_close <= 1'd1;
4045                 end
4046                 2'd2: begin
4047                         litedramcore_bankmachine0_row_close <= 1'd1;
4048                 end
4049                 2'd3: begin
4050                 end
4051                 3'd4: begin
4052                         litedramcore_bankmachine0_row_close <= 1'd1;
4053                 end
4054                 3'd5: begin
4055                 end
4056                 3'd6: begin
4057                 end
4058                 default: begin
4059                 end
4060         endcase
4061 end
4062 always @(*) begin
4063         litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
4064         case (litedramcore_bankmachine0_state)
4065                 1'd1: begin
4066                 end
4067                 2'd2: begin
4068                 end
4069                 2'd3: begin
4070                 end
4071                 3'd4: begin
4072                 end
4073                 3'd5: begin
4074                 end
4075                 3'd6: begin
4076                 end
4077                 default: begin
4078                         if (litedramcore_bankmachine0_refresh_req) begin
4079                         end else begin
4080                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4081                                         if (litedramcore_bankmachine0_row_opened) begin
4082                                                 if (litedramcore_bankmachine0_row_hit) begin
4083                                                         litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
4084                                                 end else begin
4085                                                 end
4086                                         end else begin
4087                                         end
4088                                 end
4089                         end
4090                 end
4091         endcase
4092 end
4093 always @(*) begin
4094         litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
4095         case (litedramcore_bankmachine0_state)
4096                 1'd1: begin
4097                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
4098                                 litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
4099                         end
4100                 end
4101                 2'd2: begin
4102                 end
4103                 2'd3: begin
4104                         if (litedramcore_bankmachine0_trccon_ready) begin
4105                                 litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
4106                         end
4107                 end
4108                 3'd4: begin
4109                 end
4110                 3'd5: begin
4111                 end
4112                 3'd6: begin
4113                 end
4114                 default: begin
4115                 end
4116         endcase
4117 end
4118 always @(*) begin
4119         litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
4120         case (litedramcore_bankmachine0_state)
4121                 1'd1: begin
4122                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
4123                                 litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
4124                         end
4125                 end
4126                 2'd2: begin
4127                 end
4128                 2'd3: begin
4129                 end
4130                 3'd4: begin
4131                 end
4132                 3'd5: begin
4133                 end
4134                 3'd6: begin
4135                 end
4136                 default: begin
4137                         if (litedramcore_bankmachine0_refresh_req) begin
4138                         end else begin
4139                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4140                                         if (litedramcore_bankmachine0_row_opened) begin
4141                                                 if (litedramcore_bankmachine0_row_hit) begin
4142                                                         if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
4143                                                                 litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
4144                                                         end else begin
4145                                                         end
4146                                                 end else begin
4147                                                 end
4148                                         end else begin
4149                                         end
4150                                 end
4151                         end
4152                 end
4153         endcase
4154 end
4155 always @(*) begin
4156         litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
4157         case (litedramcore_bankmachine0_state)
4158                 1'd1: begin
4159                 end
4160                 2'd2: begin
4161                 end
4162                 2'd3: begin
4163                         if (litedramcore_bankmachine0_trccon_ready) begin
4164                                 litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
4165                         end
4166                 end
4167                 3'd4: begin
4168                 end
4169                 3'd5: begin
4170                 end
4171                 3'd6: begin
4172                 end
4173                 default: begin
4174                 end
4175         endcase
4176 end
4177 always @(*) begin
4178         litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
4179         case (litedramcore_bankmachine0_state)
4180                 1'd1: begin
4181                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
4182                                 litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
4183                         end
4184                 end
4185                 2'd2: begin
4186                 end
4187                 2'd3: begin
4188                         if (litedramcore_bankmachine0_trccon_ready) begin
4189                                 litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
4190                         end
4191                 end
4192                 3'd4: begin
4193                         litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
4194                 end
4195                 3'd5: begin
4196                 end
4197                 3'd6: begin
4198                 end
4199                 default: begin
4200                 end
4201         endcase
4202 end
4203 always @(*) begin
4204         litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
4205         case (litedramcore_bankmachine0_state)
4206                 1'd1: begin
4207                 end
4208                 2'd2: begin
4209                 end
4210                 2'd3: begin
4211                 end
4212                 3'd4: begin
4213                 end
4214                 3'd5: begin
4215                 end
4216                 3'd6: begin
4217                 end
4218                 default: begin
4219                         if (litedramcore_bankmachine0_refresh_req) begin
4220                         end else begin
4221                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4222                                         if (litedramcore_bankmachine0_row_opened) begin
4223                                                 if (litedramcore_bankmachine0_row_hit) begin
4224                                                         if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
4225                                                         end else begin
4226                                                                 litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
4227                                                         end
4228                                                 end else begin
4229                                                 end
4230                                         end else begin
4231                                         end
4232                                 end
4233                         end
4234                 end
4235         endcase
4236 end
4237 always @(*) begin
4238         litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
4239         case (litedramcore_bankmachine0_state)
4240                 1'd1: begin
4241                 end
4242                 2'd2: begin
4243                 end
4244                 2'd3: begin
4245                 end
4246                 3'd4: begin
4247                 end
4248                 3'd5: begin
4249                 end
4250                 3'd6: begin
4251                 end
4252                 default: begin
4253                         if (litedramcore_bankmachine0_refresh_req) begin
4254                         end else begin
4255                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4256                                         if (litedramcore_bankmachine0_row_opened) begin
4257                                                 if (litedramcore_bankmachine0_row_hit) begin
4258                                                         if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
4259                                                                 litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
4260                                                         end else begin
4261                                                         end
4262                                                 end else begin
4263                                                 end
4264                                         end else begin
4265                                         end
4266                                 end
4267                         end
4268                 end
4269         endcase
4270 end
4271 always @(*) begin
4272         litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
4273         case (litedramcore_bankmachine0_state)
4274                 1'd1: begin
4275                 end
4276                 2'd2: begin
4277                 end
4278                 2'd3: begin
4279                 end
4280                 3'd4: begin
4281                 end
4282                 3'd5: begin
4283                 end
4284                 3'd6: begin
4285                 end
4286                 default: begin
4287                         if (litedramcore_bankmachine0_refresh_req) begin
4288                         end else begin
4289                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4290                                         if (litedramcore_bankmachine0_row_opened) begin
4291                                                 if (litedramcore_bankmachine0_row_hit) begin
4292                                                         if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
4293                                                                 litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
4294                                                         end else begin
4295                                                         end
4296                                                 end else begin
4297                                                 end
4298                                         end else begin
4299                                         end
4300                                 end
4301                         end
4302                 end
4303         endcase
4304 end
4305 always @(*) begin
4306         litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
4307         case (litedramcore_bankmachine0_state)
4308                 1'd1: begin
4309                 end
4310                 2'd2: begin
4311                 end
4312                 2'd3: begin
4313                 end
4314                 3'd4: begin
4315                 end
4316                 3'd5: begin
4317                 end
4318                 3'd6: begin
4319                 end
4320                 default: begin
4321                         if (litedramcore_bankmachine0_refresh_req) begin
4322                         end else begin
4323                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4324                                         if (litedramcore_bankmachine0_row_opened) begin
4325                                                 if (litedramcore_bankmachine0_row_hit) begin
4326                                                         if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
4327                                                         end else begin
4328                                                                 litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
4329                                                         end
4330                                                 end else begin
4331                                                 end
4332                                         end else begin
4333                                         end
4334                                 end
4335                         end
4336                 end
4337         endcase
4338 end
4339 always @(*) begin
4340         litedramcore_bankmachine0_refresh_gnt <= 1'd0;
4341         case (litedramcore_bankmachine0_state)
4342                 1'd1: begin
4343                 end
4344                 2'd2: begin
4345                 end
4346                 2'd3: begin
4347                 end
4348                 3'd4: begin
4349                         if (litedramcore_bankmachine0_twtpcon_ready) begin
4350                                 litedramcore_bankmachine0_refresh_gnt <= 1'd1;
4351                         end
4352                 end
4353                 3'd5: begin
4354                 end
4355                 3'd6: begin
4356                 end
4357                 default: begin
4358                 end
4359         endcase
4360 end
4361 always @(*) begin
4362         litedramcore_bankmachine0_cmd_valid <= 1'd0;
4363         case (litedramcore_bankmachine0_state)
4364                 1'd1: begin
4365                         if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
4366                                 litedramcore_bankmachine0_cmd_valid <= 1'd1;
4367                         end
4368                 end
4369                 2'd2: begin
4370                 end
4371                 2'd3: begin
4372                         if (litedramcore_bankmachine0_trccon_ready) begin
4373                                 litedramcore_bankmachine0_cmd_valid <= 1'd1;
4374                         end
4375                 end
4376                 3'd4: begin
4377                 end
4378                 3'd5: begin
4379                 end
4380                 3'd6: begin
4381                 end
4382                 default: begin
4383                         if (litedramcore_bankmachine0_refresh_req) begin
4384                         end else begin
4385                                 if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
4386                                         if (litedramcore_bankmachine0_row_opened) begin
4387                                                 if (litedramcore_bankmachine0_row_hit) begin
4388                                                         litedramcore_bankmachine0_cmd_valid <= 1'd1;
4389                                                 end else begin
4390                                                 end
4391                                         end else begin
4392                                         end
4393                                 end
4394                         end
4395                 end
4396         endcase
4397 end
4398 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
4399 assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
4400 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
4401 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
4402 assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
4403 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
4404 assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
4405 assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
4406 assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
4407 assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
4408 assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
4409 assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
4410 assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
4411 assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
4412 always @(*) begin
4413         litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
4414         if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
4415                 litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
4416         end else begin
4417                 litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
4418         end
4419 end
4420 assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
4421 assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
4422 assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
4423 always @(*) begin
4424         litedramcore_bankmachine1_auto_precharge <= 1'd0;
4425         if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
4426                 if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
4427                         litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
4428                 end
4429         end
4430 end
4431 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
4432 assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
4433 assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
4434 assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
4435 assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
4436 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
4437 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
4438 assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
4439 assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
4440 assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
4441 assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
4442 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
4443 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
4444 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
4445 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
4446 assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
4447 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
4448 always @(*) begin
4449         litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
4450         if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
4451                 litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
4452         end else begin
4453                 litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
4454         end
4455 end
4456 assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
4457 assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
4458 assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
4459 assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
4460 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
4461 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
4462 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
4463 assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
4464 always @(*) begin
4465         litedramcore_bankmachine1_next_state <= 3'd0;
4466         litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
4467         case (litedramcore_bankmachine1_state)
4468                 1'd1: begin
4469                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4470                                 if (litedramcore_bankmachine1_cmd_ready) begin
4471                                         litedramcore_bankmachine1_next_state <= 3'd5;
4472                                 end
4473                         end
4474                 end
4475                 2'd2: begin
4476                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4477                                 litedramcore_bankmachine1_next_state <= 3'd5;
4478                         end
4479                 end
4480                 2'd3: begin
4481                         if (litedramcore_bankmachine1_trccon_ready) begin
4482                                 if (litedramcore_bankmachine1_cmd_ready) begin
4483                                         litedramcore_bankmachine1_next_state <= 3'd6;
4484                                 end
4485                         end
4486                 end
4487                 3'd4: begin
4488                         if ((~litedramcore_bankmachine1_refresh_req)) begin
4489                                 litedramcore_bankmachine1_next_state <= 1'd0;
4490                         end
4491                 end
4492                 3'd5: begin
4493                         litedramcore_bankmachine1_next_state <= 2'd3;
4494                 end
4495                 3'd6: begin
4496                         litedramcore_bankmachine1_next_state <= 1'd0;
4497                 end
4498                 default: begin
4499                         if (litedramcore_bankmachine1_refresh_req) begin
4500                                 litedramcore_bankmachine1_next_state <= 3'd4;
4501                         end else begin
4502                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4503                                         if (litedramcore_bankmachine1_row_opened) begin
4504                                                 if (litedramcore_bankmachine1_row_hit) begin
4505                                                         if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
4506                                                                 litedramcore_bankmachine1_next_state <= 2'd2;
4507                                                         end
4508                                                 end else begin
4509                                                         litedramcore_bankmachine1_next_state <= 1'd1;
4510                                                 end
4511                                         end else begin
4512                                                 litedramcore_bankmachine1_next_state <= 2'd3;
4513                                         end
4514                                 end
4515                         end
4516                 end
4517         endcase
4518 end
4519 always @(*) begin
4520         litedramcore_bankmachine1_row_open <= 1'd0;
4521         case (litedramcore_bankmachine1_state)
4522                 1'd1: begin
4523                 end
4524                 2'd2: begin
4525                 end
4526                 2'd3: begin
4527                         if (litedramcore_bankmachine1_trccon_ready) begin
4528                                 litedramcore_bankmachine1_row_open <= 1'd1;
4529                         end
4530                 end
4531                 3'd4: begin
4532                 end
4533                 3'd5: begin
4534                 end
4535                 3'd6: begin
4536                 end
4537                 default: begin
4538                 end
4539         endcase
4540 end
4541 always @(*) begin
4542         litedramcore_bankmachine1_row_close <= 1'd0;
4543         case (litedramcore_bankmachine1_state)
4544                 1'd1: begin
4545                         litedramcore_bankmachine1_row_close <= 1'd1;
4546                 end
4547                 2'd2: begin
4548                         litedramcore_bankmachine1_row_close <= 1'd1;
4549                 end
4550                 2'd3: begin
4551                 end
4552                 3'd4: begin
4553                         litedramcore_bankmachine1_row_close <= 1'd1;
4554                 end
4555                 3'd5: begin
4556                 end
4557                 3'd6: begin
4558                 end
4559                 default: begin
4560                 end
4561         endcase
4562 end
4563 always @(*) begin
4564         litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
4565         case (litedramcore_bankmachine1_state)
4566                 1'd1: begin
4567                 end
4568                 2'd2: begin
4569                 end
4570                 2'd3: begin
4571                 end
4572                 3'd4: begin
4573                 end
4574                 3'd5: begin
4575                 end
4576                 3'd6: begin
4577                 end
4578                 default: begin
4579                         if (litedramcore_bankmachine1_refresh_req) begin
4580                         end else begin
4581                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4582                                         if (litedramcore_bankmachine1_row_opened) begin
4583                                                 if (litedramcore_bankmachine1_row_hit) begin
4584                                                         litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
4585                                                 end else begin
4586                                                 end
4587                                         end else begin
4588                                         end
4589                                 end
4590                         end
4591                 end
4592         endcase
4593 end
4594 always @(*) begin
4595         litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
4596         case (litedramcore_bankmachine1_state)
4597                 1'd1: begin
4598                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4599                                 litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
4600                         end
4601                 end
4602                 2'd2: begin
4603                 end
4604                 2'd3: begin
4605                         if (litedramcore_bankmachine1_trccon_ready) begin
4606                                 litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
4607                         end
4608                 end
4609                 3'd4: begin
4610                 end
4611                 3'd5: begin
4612                 end
4613                 3'd6: begin
4614                 end
4615                 default: begin
4616                 end
4617         endcase
4618 end
4619 always @(*) begin
4620         litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
4621         case (litedramcore_bankmachine1_state)
4622                 1'd1: begin
4623                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4624                                 litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
4625                         end
4626                 end
4627                 2'd2: begin
4628                 end
4629                 2'd3: begin
4630                 end
4631                 3'd4: begin
4632                 end
4633                 3'd5: begin
4634                 end
4635                 3'd6: begin
4636                 end
4637                 default: begin
4638                         if (litedramcore_bankmachine1_refresh_req) begin
4639                         end else begin
4640                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4641                                         if (litedramcore_bankmachine1_row_opened) begin
4642                                                 if (litedramcore_bankmachine1_row_hit) begin
4643                                                         if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
4644                                                                 litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
4645                                                         end else begin
4646                                                         end
4647                                                 end else begin
4648                                                 end
4649                                         end else begin
4650                                         end
4651                                 end
4652                         end
4653                 end
4654         endcase
4655 end
4656 always @(*) begin
4657         litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
4658         case (litedramcore_bankmachine1_state)
4659                 1'd1: begin
4660                 end
4661                 2'd2: begin
4662                 end
4663                 2'd3: begin
4664                         if (litedramcore_bankmachine1_trccon_ready) begin
4665                                 litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
4666                         end
4667                 end
4668                 3'd4: begin
4669                 end
4670                 3'd5: begin
4671                 end
4672                 3'd6: begin
4673                 end
4674                 default: begin
4675                 end
4676         endcase
4677 end
4678 always @(*) begin
4679         litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
4680         case (litedramcore_bankmachine1_state)
4681                 1'd1: begin
4682                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4683                                 litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
4684                         end
4685                 end
4686                 2'd2: begin
4687                 end
4688                 2'd3: begin
4689                         if (litedramcore_bankmachine1_trccon_ready) begin
4690                                 litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
4691                         end
4692                 end
4693                 3'd4: begin
4694                         litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
4695                 end
4696                 3'd5: begin
4697                 end
4698                 3'd6: begin
4699                 end
4700                 default: begin
4701                 end
4702         endcase
4703 end
4704 always @(*) begin
4705         litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
4706         case (litedramcore_bankmachine1_state)
4707                 1'd1: begin
4708                 end
4709                 2'd2: begin
4710                 end
4711                 2'd3: begin
4712                 end
4713                 3'd4: begin
4714                 end
4715                 3'd5: begin
4716                 end
4717                 3'd6: begin
4718                 end
4719                 default: begin
4720                         if (litedramcore_bankmachine1_refresh_req) begin
4721                         end else begin
4722                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4723                                         if (litedramcore_bankmachine1_row_opened) begin
4724                                                 if (litedramcore_bankmachine1_row_hit) begin
4725                                                         if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
4726                                                         end else begin
4727                                                                 litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
4728                                                         end
4729                                                 end else begin
4730                                                 end
4731                                         end else begin
4732                                         end
4733                                 end
4734                         end
4735                 end
4736         endcase
4737 end
4738 always @(*) begin
4739         litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
4740         case (litedramcore_bankmachine1_state)
4741                 1'd1: begin
4742                 end
4743                 2'd2: begin
4744                 end
4745                 2'd3: begin
4746                 end
4747                 3'd4: begin
4748                 end
4749                 3'd5: begin
4750                 end
4751                 3'd6: begin
4752                 end
4753                 default: begin
4754                         if (litedramcore_bankmachine1_refresh_req) begin
4755                         end else begin
4756                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4757                                         if (litedramcore_bankmachine1_row_opened) begin
4758                                                 if (litedramcore_bankmachine1_row_hit) begin
4759                                                         if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
4760                                                                 litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
4761                                                         end else begin
4762                                                         end
4763                                                 end else begin
4764                                                 end
4765                                         end else begin
4766                                         end
4767                                 end
4768                         end
4769                 end
4770         endcase
4771 end
4772 always @(*) begin
4773         litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
4774         case (litedramcore_bankmachine1_state)
4775                 1'd1: begin
4776                 end
4777                 2'd2: begin
4778                 end
4779                 2'd3: begin
4780                 end
4781                 3'd4: begin
4782                 end
4783                 3'd5: begin
4784                 end
4785                 3'd6: begin
4786                 end
4787                 default: begin
4788                         if (litedramcore_bankmachine1_refresh_req) begin
4789                         end else begin
4790                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4791                                         if (litedramcore_bankmachine1_row_opened) begin
4792                                                 if (litedramcore_bankmachine1_row_hit) begin
4793                                                         if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
4794                                                                 litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
4795                                                         end else begin
4796                                                         end
4797                                                 end else begin
4798                                                 end
4799                                         end else begin
4800                                         end
4801                                 end
4802                         end
4803                 end
4804         endcase
4805 end
4806 always @(*) begin
4807         litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
4808         case (litedramcore_bankmachine1_state)
4809                 1'd1: begin
4810                 end
4811                 2'd2: begin
4812                 end
4813                 2'd3: begin
4814                 end
4815                 3'd4: begin
4816                 end
4817                 3'd5: begin
4818                 end
4819                 3'd6: begin
4820                 end
4821                 default: begin
4822                         if (litedramcore_bankmachine1_refresh_req) begin
4823                         end else begin
4824                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4825                                         if (litedramcore_bankmachine1_row_opened) begin
4826                                                 if (litedramcore_bankmachine1_row_hit) begin
4827                                                         if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
4828                                                         end else begin
4829                                                                 litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
4830                                                         end
4831                                                 end else begin
4832                                                 end
4833                                         end else begin
4834                                         end
4835                                 end
4836                         end
4837                 end
4838         endcase
4839 end
4840 always @(*) begin
4841         litedramcore_bankmachine1_refresh_gnt <= 1'd0;
4842         case (litedramcore_bankmachine1_state)
4843                 1'd1: begin
4844                 end
4845                 2'd2: begin
4846                 end
4847                 2'd3: begin
4848                 end
4849                 3'd4: begin
4850                         if (litedramcore_bankmachine1_twtpcon_ready) begin
4851                                 litedramcore_bankmachine1_refresh_gnt <= 1'd1;
4852                         end
4853                 end
4854                 3'd5: begin
4855                 end
4856                 3'd6: begin
4857                 end
4858                 default: begin
4859                 end
4860         endcase
4861 end
4862 always @(*) begin
4863         litedramcore_bankmachine1_cmd_valid <= 1'd0;
4864         case (litedramcore_bankmachine1_state)
4865                 1'd1: begin
4866                         if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
4867                                 litedramcore_bankmachine1_cmd_valid <= 1'd1;
4868                         end
4869                 end
4870                 2'd2: begin
4871                 end
4872                 2'd3: begin
4873                         if (litedramcore_bankmachine1_trccon_ready) begin
4874                                 litedramcore_bankmachine1_cmd_valid <= 1'd1;
4875                         end
4876                 end
4877                 3'd4: begin
4878                 end
4879                 3'd5: begin
4880                 end
4881                 3'd6: begin
4882                 end
4883                 default: begin
4884                         if (litedramcore_bankmachine1_refresh_req) begin
4885                         end else begin
4886                                 if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
4887                                         if (litedramcore_bankmachine1_row_opened) begin
4888                                                 if (litedramcore_bankmachine1_row_hit) begin
4889                                                         litedramcore_bankmachine1_cmd_valid <= 1'd1;
4890                                                 end else begin
4891                                                 end
4892                                         end else begin
4893                                         end
4894                                 end
4895                         end
4896                 end
4897         endcase
4898 end
4899 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
4900 assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
4901 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
4902 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
4903 assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
4904 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
4905 assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
4906 assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
4907 assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
4908 assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
4909 assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
4910 assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
4911 assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
4912 assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
4913 always @(*) begin
4914         litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
4915         if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
4916                 litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
4917         end else begin
4918                 litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
4919         end
4920 end
4921 assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
4922 assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
4923 assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
4924 always @(*) begin
4925         litedramcore_bankmachine2_auto_precharge <= 1'd0;
4926         if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
4927                 if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
4928                         litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
4929                 end
4930         end
4931 end
4932 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
4933 assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
4934 assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
4935 assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
4936 assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
4937 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
4938 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
4939 assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
4940 assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
4941 assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
4942 assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
4943 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
4944 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
4945 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
4946 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
4947 assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
4948 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
4949 always @(*) begin
4950         litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
4951         if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
4952                 litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
4953         end else begin
4954                 litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
4955         end
4956 end
4957 assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
4958 assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
4959 assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
4960 assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
4961 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
4962 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
4963 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
4964 assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
4965 always @(*) begin
4966         litedramcore_bankmachine2_next_state <= 3'd0;
4967         litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
4968         case (litedramcore_bankmachine2_state)
4969                 1'd1: begin
4970                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
4971                                 if (litedramcore_bankmachine2_cmd_ready) begin
4972                                         litedramcore_bankmachine2_next_state <= 3'd5;
4973                                 end
4974                         end
4975                 end
4976                 2'd2: begin
4977                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
4978                                 litedramcore_bankmachine2_next_state <= 3'd5;
4979                         end
4980                 end
4981                 2'd3: begin
4982                         if (litedramcore_bankmachine2_trccon_ready) begin
4983                                 if (litedramcore_bankmachine2_cmd_ready) begin
4984                                         litedramcore_bankmachine2_next_state <= 3'd6;
4985                                 end
4986                         end
4987                 end
4988                 3'd4: begin
4989                         if ((~litedramcore_bankmachine2_refresh_req)) begin
4990                                 litedramcore_bankmachine2_next_state <= 1'd0;
4991                         end
4992                 end
4993                 3'd5: begin
4994                         litedramcore_bankmachine2_next_state <= 2'd3;
4995                 end
4996                 3'd6: begin
4997                         litedramcore_bankmachine2_next_state <= 1'd0;
4998                 end
4999                 default: begin
5000                         if (litedramcore_bankmachine2_refresh_req) begin
5001                                 litedramcore_bankmachine2_next_state <= 3'd4;
5002                         end else begin
5003                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5004                                         if (litedramcore_bankmachine2_row_opened) begin
5005                                                 if (litedramcore_bankmachine2_row_hit) begin
5006                                                         if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
5007                                                                 litedramcore_bankmachine2_next_state <= 2'd2;
5008                                                         end
5009                                                 end else begin
5010                                                         litedramcore_bankmachine2_next_state <= 1'd1;
5011                                                 end
5012                                         end else begin
5013                                                 litedramcore_bankmachine2_next_state <= 2'd3;
5014                                         end
5015                                 end
5016                         end
5017                 end
5018         endcase
5019 end
5020 always @(*) begin
5021         litedramcore_bankmachine2_row_open <= 1'd0;
5022         case (litedramcore_bankmachine2_state)
5023                 1'd1: begin
5024                 end
5025                 2'd2: begin
5026                 end
5027                 2'd3: begin
5028                         if (litedramcore_bankmachine2_trccon_ready) begin
5029                                 litedramcore_bankmachine2_row_open <= 1'd1;
5030                         end
5031                 end
5032                 3'd4: begin
5033                 end
5034                 3'd5: begin
5035                 end
5036                 3'd6: begin
5037                 end
5038                 default: begin
5039                 end
5040         endcase
5041 end
5042 always @(*) begin
5043         litedramcore_bankmachine2_row_close <= 1'd0;
5044         case (litedramcore_bankmachine2_state)
5045                 1'd1: begin
5046                         litedramcore_bankmachine2_row_close <= 1'd1;
5047                 end
5048                 2'd2: begin
5049                         litedramcore_bankmachine2_row_close <= 1'd1;
5050                 end
5051                 2'd3: begin
5052                 end
5053                 3'd4: begin
5054                         litedramcore_bankmachine2_row_close <= 1'd1;
5055                 end
5056                 3'd5: begin
5057                 end
5058                 3'd6: begin
5059                 end
5060                 default: begin
5061                 end
5062         endcase
5063 end
5064 always @(*) begin
5065         litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
5066         case (litedramcore_bankmachine2_state)
5067                 1'd1: begin
5068                 end
5069                 2'd2: begin
5070                 end
5071                 2'd3: begin
5072                 end
5073                 3'd4: begin
5074                 end
5075                 3'd5: begin
5076                 end
5077                 3'd6: begin
5078                 end
5079                 default: begin
5080                         if (litedramcore_bankmachine2_refresh_req) begin
5081                         end else begin
5082                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5083                                         if (litedramcore_bankmachine2_row_opened) begin
5084                                                 if (litedramcore_bankmachine2_row_hit) begin
5085                                                         litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
5086                                                 end else begin
5087                                                 end
5088                                         end else begin
5089                                         end
5090                                 end
5091                         end
5092                 end
5093         endcase
5094 end
5095 always @(*) begin
5096         litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
5097         case (litedramcore_bankmachine2_state)
5098                 1'd1: begin
5099                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
5100                                 litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
5101                         end
5102                 end
5103                 2'd2: begin
5104                 end
5105                 2'd3: begin
5106                         if (litedramcore_bankmachine2_trccon_ready) begin
5107                                 litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
5108                         end
5109                 end
5110                 3'd4: begin
5111                 end
5112                 3'd5: begin
5113                 end
5114                 3'd6: begin
5115                 end
5116                 default: begin
5117                 end
5118         endcase
5119 end
5120 always @(*) begin
5121         litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
5122         case (litedramcore_bankmachine2_state)
5123                 1'd1: begin
5124                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
5125                                 litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
5126                         end
5127                 end
5128                 2'd2: begin
5129                 end
5130                 2'd3: begin
5131                 end
5132                 3'd4: begin
5133                 end
5134                 3'd5: begin
5135                 end
5136                 3'd6: begin
5137                 end
5138                 default: begin
5139                         if (litedramcore_bankmachine2_refresh_req) begin
5140                         end else begin
5141                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5142                                         if (litedramcore_bankmachine2_row_opened) begin
5143                                                 if (litedramcore_bankmachine2_row_hit) begin
5144                                                         if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
5145                                                                 litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
5146                                                         end else begin
5147                                                         end
5148                                                 end else begin
5149                                                 end
5150                                         end else begin
5151                                         end
5152                                 end
5153                         end
5154                 end
5155         endcase
5156 end
5157 always @(*) begin
5158         litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
5159         case (litedramcore_bankmachine2_state)
5160                 1'd1: begin
5161                 end
5162                 2'd2: begin
5163                 end
5164                 2'd3: begin
5165                         if (litedramcore_bankmachine2_trccon_ready) begin
5166                                 litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
5167                         end
5168                 end
5169                 3'd4: begin
5170                 end
5171                 3'd5: begin
5172                 end
5173                 3'd6: begin
5174                 end
5175                 default: begin
5176                 end
5177         endcase
5178 end
5179 always @(*) begin
5180         litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
5181         case (litedramcore_bankmachine2_state)
5182                 1'd1: begin
5183                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
5184                                 litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
5185                         end
5186                 end
5187                 2'd2: begin
5188                 end
5189                 2'd3: begin
5190                         if (litedramcore_bankmachine2_trccon_ready) begin
5191                                 litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
5192                         end
5193                 end
5194                 3'd4: begin
5195                         litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
5196                 end
5197                 3'd5: begin
5198                 end
5199                 3'd6: begin
5200                 end
5201                 default: begin
5202                 end
5203         endcase
5204 end
5205 always @(*) begin
5206         litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
5207         case (litedramcore_bankmachine2_state)
5208                 1'd1: begin
5209                 end
5210                 2'd2: begin
5211                 end
5212                 2'd3: begin
5213                 end
5214                 3'd4: begin
5215                 end
5216                 3'd5: begin
5217                 end
5218                 3'd6: begin
5219                 end
5220                 default: begin
5221                         if (litedramcore_bankmachine2_refresh_req) begin
5222                         end else begin
5223                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5224                                         if (litedramcore_bankmachine2_row_opened) begin
5225                                                 if (litedramcore_bankmachine2_row_hit) begin
5226                                                         if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
5227                                                         end else begin
5228                                                                 litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
5229                                                         end
5230                                                 end else begin
5231                                                 end
5232                                         end else begin
5233                                         end
5234                                 end
5235                         end
5236                 end
5237         endcase
5238 end
5239 always @(*) begin
5240         litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
5241         case (litedramcore_bankmachine2_state)
5242                 1'd1: begin
5243                 end
5244                 2'd2: begin
5245                 end
5246                 2'd3: begin
5247                 end
5248                 3'd4: begin
5249                 end
5250                 3'd5: begin
5251                 end
5252                 3'd6: begin
5253                 end
5254                 default: begin
5255                         if (litedramcore_bankmachine2_refresh_req) begin
5256                         end else begin
5257                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5258                                         if (litedramcore_bankmachine2_row_opened) begin
5259                                                 if (litedramcore_bankmachine2_row_hit) begin
5260                                                         if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
5261                                                                 litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
5262                                                         end else begin
5263                                                         end
5264                                                 end else begin
5265                                                 end
5266                                         end else begin
5267                                         end
5268                                 end
5269                         end
5270                 end
5271         endcase
5272 end
5273 always @(*) begin
5274         litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
5275         case (litedramcore_bankmachine2_state)
5276                 1'd1: begin
5277                 end
5278                 2'd2: begin
5279                 end
5280                 2'd3: begin
5281                 end
5282                 3'd4: begin
5283                 end
5284                 3'd5: begin
5285                 end
5286                 3'd6: begin
5287                 end
5288                 default: begin
5289                         if (litedramcore_bankmachine2_refresh_req) begin
5290                         end else begin
5291                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5292                                         if (litedramcore_bankmachine2_row_opened) begin
5293                                                 if (litedramcore_bankmachine2_row_hit) begin
5294                                                         if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
5295                                                                 litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
5296                                                         end else begin
5297                                                         end
5298                                                 end else begin
5299                                                 end
5300                                         end else begin
5301                                         end
5302                                 end
5303                         end
5304                 end
5305         endcase
5306 end
5307 always @(*) begin
5308         litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
5309         case (litedramcore_bankmachine2_state)
5310                 1'd1: begin
5311                 end
5312                 2'd2: begin
5313                 end
5314                 2'd3: begin
5315                 end
5316                 3'd4: begin
5317                 end
5318                 3'd5: begin
5319                 end
5320                 3'd6: begin
5321                 end
5322                 default: begin
5323                         if (litedramcore_bankmachine2_refresh_req) begin
5324                         end else begin
5325                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5326                                         if (litedramcore_bankmachine2_row_opened) begin
5327                                                 if (litedramcore_bankmachine2_row_hit) begin
5328                                                         if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
5329                                                         end else begin
5330                                                                 litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
5331                                                         end
5332                                                 end else begin
5333                                                 end
5334                                         end else begin
5335                                         end
5336                                 end
5337                         end
5338                 end
5339         endcase
5340 end
5341 always @(*) begin
5342         litedramcore_bankmachine2_refresh_gnt <= 1'd0;
5343         case (litedramcore_bankmachine2_state)
5344                 1'd1: begin
5345                 end
5346                 2'd2: begin
5347                 end
5348                 2'd3: begin
5349                 end
5350                 3'd4: begin
5351                         if (litedramcore_bankmachine2_twtpcon_ready) begin
5352                                 litedramcore_bankmachine2_refresh_gnt <= 1'd1;
5353                         end
5354                 end
5355                 3'd5: begin
5356                 end
5357                 3'd6: begin
5358                 end
5359                 default: begin
5360                 end
5361         endcase
5362 end
5363 always @(*) begin
5364         litedramcore_bankmachine2_cmd_valid <= 1'd0;
5365         case (litedramcore_bankmachine2_state)
5366                 1'd1: begin
5367                         if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
5368                                 litedramcore_bankmachine2_cmd_valid <= 1'd1;
5369                         end
5370                 end
5371                 2'd2: begin
5372                 end
5373                 2'd3: begin
5374                         if (litedramcore_bankmachine2_trccon_ready) begin
5375                                 litedramcore_bankmachine2_cmd_valid <= 1'd1;
5376                         end
5377                 end
5378                 3'd4: begin
5379                 end
5380                 3'd5: begin
5381                 end
5382                 3'd6: begin
5383                 end
5384                 default: begin
5385                         if (litedramcore_bankmachine2_refresh_req) begin
5386                         end else begin
5387                                 if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
5388                                         if (litedramcore_bankmachine2_row_opened) begin
5389                                                 if (litedramcore_bankmachine2_row_hit) begin
5390                                                         litedramcore_bankmachine2_cmd_valid <= 1'd1;
5391                                                 end else begin
5392                                                 end
5393                                         end else begin
5394                                         end
5395                                 end
5396                         end
5397                 end
5398         endcase
5399 end
5400 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
5401 assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
5402 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
5403 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
5404 assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
5405 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
5406 assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
5407 assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
5408 assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
5409 assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
5410 assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
5411 assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
5412 assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
5413 assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
5414 always @(*) begin
5415         litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
5416         if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
5417                 litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
5418         end else begin
5419                 litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
5420         end
5421 end
5422 assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
5423 assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
5424 assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
5425 always @(*) begin
5426         litedramcore_bankmachine3_auto_precharge <= 1'd0;
5427         if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
5428                 if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
5429                         litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
5430                 end
5431         end
5432 end
5433 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
5434 assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
5435 assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
5436 assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
5437 assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
5438 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
5439 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
5440 assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
5441 assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
5442 assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
5443 assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
5444 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
5445 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
5446 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
5447 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
5448 assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
5449 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
5450 always @(*) begin
5451         litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
5452         if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
5453                 litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
5454         end else begin
5455                 litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
5456         end
5457 end
5458 assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
5459 assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
5460 assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
5461 assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
5462 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
5463 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
5464 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
5465 assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
5466 always @(*) begin
5467         litedramcore_bankmachine3_next_state <= 3'd0;
5468         litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
5469         case (litedramcore_bankmachine3_state)
5470                 1'd1: begin
5471                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5472                                 if (litedramcore_bankmachine3_cmd_ready) begin
5473                                         litedramcore_bankmachine3_next_state <= 3'd5;
5474                                 end
5475                         end
5476                 end
5477                 2'd2: begin
5478                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5479                                 litedramcore_bankmachine3_next_state <= 3'd5;
5480                         end
5481                 end
5482                 2'd3: begin
5483                         if (litedramcore_bankmachine3_trccon_ready) begin
5484                                 if (litedramcore_bankmachine3_cmd_ready) begin
5485                                         litedramcore_bankmachine3_next_state <= 3'd6;
5486                                 end
5487                         end
5488                 end
5489                 3'd4: begin
5490                         if ((~litedramcore_bankmachine3_refresh_req)) begin
5491                                 litedramcore_bankmachine3_next_state <= 1'd0;
5492                         end
5493                 end
5494                 3'd5: begin
5495                         litedramcore_bankmachine3_next_state <= 2'd3;
5496                 end
5497                 3'd6: begin
5498                         litedramcore_bankmachine3_next_state <= 1'd0;
5499                 end
5500                 default: begin
5501                         if (litedramcore_bankmachine3_refresh_req) begin
5502                                 litedramcore_bankmachine3_next_state <= 3'd4;
5503                         end else begin
5504                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5505                                         if (litedramcore_bankmachine3_row_opened) begin
5506                                                 if (litedramcore_bankmachine3_row_hit) begin
5507                                                         if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
5508                                                                 litedramcore_bankmachine3_next_state <= 2'd2;
5509                                                         end
5510                                                 end else begin
5511                                                         litedramcore_bankmachine3_next_state <= 1'd1;
5512                                                 end
5513                                         end else begin
5514                                                 litedramcore_bankmachine3_next_state <= 2'd3;
5515                                         end
5516                                 end
5517                         end
5518                 end
5519         endcase
5520 end
5521 always @(*) begin
5522         litedramcore_bankmachine3_row_open <= 1'd0;
5523         case (litedramcore_bankmachine3_state)
5524                 1'd1: begin
5525                 end
5526                 2'd2: begin
5527                 end
5528                 2'd3: begin
5529                         if (litedramcore_bankmachine3_trccon_ready) begin
5530                                 litedramcore_bankmachine3_row_open <= 1'd1;
5531                         end
5532                 end
5533                 3'd4: begin
5534                 end
5535                 3'd5: begin
5536                 end
5537                 3'd6: begin
5538                 end
5539                 default: begin
5540                 end
5541         endcase
5542 end
5543 always @(*) begin
5544         litedramcore_bankmachine3_row_close <= 1'd0;
5545         case (litedramcore_bankmachine3_state)
5546                 1'd1: begin
5547                         litedramcore_bankmachine3_row_close <= 1'd1;
5548                 end
5549                 2'd2: begin
5550                         litedramcore_bankmachine3_row_close <= 1'd1;
5551                 end
5552                 2'd3: begin
5553                 end
5554                 3'd4: begin
5555                         litedramcore_bankmachine3_row_close <= 1'd1;
5556                 end
5557                 3'd5: begin
5558                 end
5559                 3'd6: begin
5560                 end
5561                 default: begin
5562                 end
5563         endcase
5564 end
5565 always @(*) begin
5566         litedramcore_bankmachine3_refresh_gnt <= 1'd0;
5567         case (litedramcore_bankmachine3_state)
5568                 1'd1: begin
5569                 end
5570                 2'd2: begin
5571                 end
5572                 2'd3: begin
5573                 end
5574                 3'd4: begin
5575                         if (litedramcore_bankmachine3_twtpcon_ready) begin
5576                                 litedramcore_bankmachine3_refresh_gnt <= 1'd1;
5577                         end
5578                 end
5579                 3'd5: begin
5580                 end
5581                 3'd6: begin
5582                 end
5583                 default: begin
5584                 end
5585         endcase
5586 end
5587 always @(*) begin
5588         litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
5589         case (litedramcore_bankmachine3_state)
5590                 1'd1: begin
5591                 end
5592                 2'd2: begin
5593                 end
5594                 2'd3: begin
5595                 end
5596                 3'd4: begin
5597                 end
5598                 3'd5: begin
5599                 end
5600                 3'd6: begin
5601                 end
5602                 default: begin
5603                         if (litedramcore_bankmachine3_refresh_req) begin
5604                         end else begin
5605                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5606                                         if (litedramcore_bankmachine3_row_opened) begin
5607                                                 if (litedramcore_bankmachine3_row_hit) begin
5608                                                         litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
5609                                                 end else begin
5610                                                 end
5611                                         end else begin
5612                                         end
5613                                 end
5614                         end
5615                 end
5616         endcase
5617 end
5618 always @(*) begin
5619         litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
5620         case (litedramcore_bankmachine3_state)
5621                 1'd1: begin
5622                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5623                                 litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
5624                         end
5625                 end
5626                 2'd2: begin
5627                 end
5628                 2'd3: begin
5629                         if (litedramcore_bankmachine3_trccon_ready) begin
5630                                 litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
5631                         end
5632                 end
5633                 3'd4: begin
5634                 end
5635                 3'd5: begin
5636                 end
5637                 3'd6: begin
5638                 end
5639                 default: begin
5640                 end
5641         endcase
5642 end
5643 always @(*) begin
5644         litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
5645         case (litedramcore_bankmachine3_state)
5646                 1'd1: begin
5647                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5648                                 litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
5649                         end
5650                 end
5651                 2'd2: begin
5652                 end
5653                 2'd3: begin
5654                 end
5655                 3'd4: begin
5656                 end
5657                 3'd5: begin
5658                 end
5659                 3'd6: begin
5660                 end
5661                 default: begin
5662                         if (litedramcore_bankmachine3_refresh_req) begin
5663                         end else begin
5664                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5665                                         if (litedramcore_bankmachine3_row_opened) begin
5666                                                 if (litedramcore_bankmachine3_row_hit) begin
5667                                                         if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
5668                                                                 litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
5669                                                         end else begin
5670                                                         end
5671                                                 end else begin
5672                                                 end
5673                                         end else begin
5674                                         end
5675                                 end
5676                         end
5677                 end
5678         endcase
5679 end
5680 always @(*) begin
5681         litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
5682         case (litedramcore_bankmachine3_state)
5683                 1'd1: begin
5684                 end
5685                 2'd2: begin
5686                 end
5687                 2'd3: begin
5688                         if (litedramcore_bankmachine3_trccon_ready) begin
5689                                 litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
5690                         end
5691                 end
5692                 3'd4: begin
5693                 end
5694                 3'd5: begin
5695                 end
5696                 3'd6: begin
5697                 end
5698                 default: begin
5699                 end
5700         endcase
5701 end
5702 always @(*) begin
5703         litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
5704         case (litedramcore_bankmachine3_state)
5705                 1'd1: begin
5706                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5707                                 litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
5708                         end
5709                 end
5710                 2'd2: begin
5711                 end
5712                 2'd3: begin
5713                         if (litedramcore_bankmachine3_trccon_ready) begin
5714                                 litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
5715                         end
5716                 end
5717                 3'd4: begin
5718                         litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
5719                 end
5720                 3'd5: begin
5721                 end
5722                 3'd6: begin
5723                 end
5724                 default: begin
5725                 end
5726         endcase
5727 end
5728 always @(*) begin
5729         litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
5730         case (litedramcore_bankmachine3_state)
5731                 1'd1: begin
5732                 end
5733                 2'd2: begin
5734                 end
5735                 2'd3: begin
5736                 end
5737                 3'd4: begin
5738                 end
5739                 3'd5: begin
5740                 end
5741                 3'd6: begin
5742                 end
5743                 default: begin
5744                         if (litedramcore_bankmachine3_refresh_req) begin
5745                         end else begin
5746                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5747                                         if (litedramcore_bankmachine3_row_opened) begin
5748                                                 if (litedramcore_bankmachine3_row_hit) begin
5749                                                         if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
5750                                                         end else begin
5751                                                                 litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
5752                                                         end
5753                                                 end else begin
5754                                                 end
5755                                         end else begin
5756                                         end
5757                                 end
5758                         end
5759                 end
5760         endcase
5761 end
5762 always @(*) begin
5763         litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
5764         case (litedramcore_bankmachine3_state)
5765                 1'd1: begin
5766                 end
5767                 2'd2: begin
5768                 end
5769                 2'd3: begin
5770                 end
5771                 3'd4: begin
5772                 end
5773                 3'd5: begin
5774                 end
5775                 3'd6: begin
5776                 end
5777                 default: begin
5778                         if (litedramcore_bankmachine3_refresh_req) begin
5779                         end else begin
5780                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5781                                         if (litedramcore_bankmachine3_row_opened) begin
5782                                                 if (litedramcore_bankmachine3_row_hit) begin
5783                                                         if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
5784                                                                 litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
5785                                                         end else begin
5786                                                         end
5787                                                 end else begin
5788                                                 end
5789                                         end else begin
5790                                         end
5791                                 end
5792                         end
5793                 end
5794         endcase
5795 end
5796 always @(*) begin
5797         litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
5798         case (litedramcore_bankmachine3_state)
5799                 1'd1: begin
5800                 end
5801                 2'd2: begin
5802                 end
5803                 2'd3: begin
5804                 end
5805                 3'd4: begin
5806                 end
5807                 3'd5: begin
5808                 end
5809                 3'd6: begin
5810                 end
5811                 default: begin
5812                         if (litedramcore_bankmachine3_refresh_req) begin
5813                         end else begin
5814                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5815                                         if (litedramcore_bankmachine3_row_opened) begin
5816                                                 if (litedramcore_bankmachine3_row_hit) begin
5817                                                         if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
5818                                                                 litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
5819                                                         end else begin
5820                                                         end
5821                                                 end else begin
5822                                                 end
5823                                         end else begin
5824                                         end
5825                                 end
5826                         end
5827                 end
5828         endcase
5829 end
5830 always @(*) begin
5831         litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
5832         case (litedramcore_bankmachine3_state)
5833                 1'd1: begin
5834                 end
5835                 2'd2: begin
5836                 end
5837                 2'd3: begin
5838                 end
5839                 3'd4: begin
5840                 end
5841                 3'd5: begin
5842                 end
5843                 3'd6: begin
5844                 end
5845                 default: begin
5846                         if (litedramcore_bankmachine3_refresh_req) begin
5847                         end else begin
5848                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5849                                         if (litedramcore_bankmachine3_row_opened) begin
5850                                                 if (litedramcore_bankmachine3_row_hit) begin
5851                                                         if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
5852                                                         end else begin
5853                                                                 litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
5854                                                         end
5855                                                 end else begin
5856                                                 end
5857                                         end else begin
5858                                         end
5859                                 end
5860                         end
5861                 end
5862         endcase
5863 end
5864 always @(*) begin
5865         litedramcore_bankmachine3_cmd_valid <= 1'd0;
5866         case (litedramcore_bankmachine3_state)
5867                 1'd1: begin
5868                         if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
5869                                 litedramcore_bankmachine3_cmd_valid <= 1'd1;
5870                         end
5871                 end
5872                 2'd2: begin
5873                 end
5874                 2'd3: begin
5875                         if (litedramcore_bankmachine3_trccon_ready) begin
5876                                 litedramcore_bankmachine3_cmd_valid <= 1'd1;
5877                         end
5878                 end
5879                 3'd4: begin
5880                 end
5881                 3'd5: begin
5882                 end
5883                 3'd6: begin
5884                 end
5885                 default: begin
5886                         if (litedramcore_bankmachine3_refresh_req) begin
5887                         end else begin
5888                                 if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
5889                                         if (litedramcore_bankmachine3_row_opened) begin
5890                                                 if (litedramcore_bankmachine3_row_hit) begin
5891                                                         litedramcore_bankmachine3_cmd_valid <= 1'd1;
5892                                                 end else begin
5893                                                 end
5894                                         end else begin
5895                                         end
5896                                 end
5897                         end
5898                 end
5899         endcase
5900 end
5901 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
5902 assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
5903 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
5904 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
5905 assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
5906 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
5907 assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
5908 assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
5909 assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
5910 assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
5911 assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
5912 assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
5913 assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
5914 assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
5915 always @(*) begin
5916         litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
5917         if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
5918                 litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
5919         end else begin
5920                 litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
5921         end
5922 end
5923 assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
5924 assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
5925 assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
5926 always @(*) begin
5927         litedramcore_bankmachine4_auto_precharge <= 1'd0;
5928         if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
5929                 if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
5930                         litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
5931                 end
5932         end
5933 end
5934 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
5935 assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
5936 assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
5937 assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
5938 assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
5939 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
5940 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
5941 assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
5942 assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
5943 assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
5944 assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
5945 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
5946 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
5947 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
5948 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
5949 assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
5950 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
5951 always @(*) begin
5952         litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
5953         if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
5954                 litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
5955         end else begin
5956                 litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
5957         end
5958 end
5959 assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
5960 assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
5961 assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
5962 assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
5963 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
5964 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
5965 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
5966 assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
5967 always @(*) begin
5968         litedramcore_bankmachine4_next_state <= 3'd0;
5969         litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
5970         case (litedramcore_bankmachine4_state)
5971                 1'd1: begin
5972                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
5973                                 if (litedramcore_bankmachine4_cmd_ready) begin
5974                                         litedramcore_bankmachine4_next_state <= 3'd5;
5975                                 end
5976                         end
5977                 end
5978                 2'd2: begin
5979                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
5980                                 litedramcore_bankmachine4_next_state <= 3'd5;
5981                         end
5982                 end
5983                 2'd3: begin
5984                         if (litedramcore_bankmachine4_trccon_ready) begin
5985                                 if (litedramcore_bankmachine4_cmd_ready) begin
5986                                         litedramcore_bankmachine4_next_state <= 3'd6;
5987                                 end
5988                         end
5989                 end
5990                 3'd4: begin
5991                         if ((~litedramcore_bankmachine4_refresh_req)) begin
5992                                 litedramcore_bankmachine4_next_state <= 1'd0;
5993                         end
5994                 end
5995                 3'd5: begin
5996                         litedramcore_bankmachine4_next_state <= 2'd3;
5997                 end
5998                 3'd6: begin
5999                         litedramcore_bankmachine4_next_state <= 1'd0;
6000                 end
6001                 default: begin
6002                         if (litedramcore_bankmachine4_refresh_req) begin
6003                                 litedramcore_bankmachine4_next_state <= 3'd4;
6004                         end else begin
6005                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6006                                         if (litedramcore_bankmachine4_row_opened) begin
6007                                                 if (litedramcore_bankmachine4_row_hit) begin
6008                                                         if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
6009                                                                 litedramcore_bankmachine4_next_state <= 2'd2;
6010                                                         end
6011                                                 end else begin
6012                                                         litedramcore_bankmachine4_next_state <= 1'd1;
6013                                                 end
6014                                         end else begin
6015                                                 litedramcore_bankmachine4_next_state <= 2'd3;
6016                                         end
6017                                 end
6018                         end
6019                 end
6020         endcase
6021 end
6022 always @(*) begin
6023         litedramcore_bankmachine4_row_open <= 1'd0;
6024         case (litedramcore_bankmachine4_state)
6025                 1'd1: begin
6026                 end
6027                 2'd2: begin
6028                 end
6029                 2'd3: begin
6030                         if (litedramcore_bankmachine4_trccon_ready) begin
6031                                 litedramcore_bankmachine4_row_open <= 1'd1;
6032                         end
6033                 end
6034                 3'd4: begin
6035                 end
6036                 3'd5: begin
6037                 end
6038                 3'd6: begin
6039                 end
6040                 default: begin
6041                 end
6042         endcase
6043 end
6044 always @(*) begin
6045         litedramcore_bankmachine4_row_close <= 1'd0;
6046         case (litedramcore_bankmachine4_state)
6047                 1'd1: begin
6048                         litedramcore_bankmachine4_row_close <= 1'd1;
6049                 end
6050                 2'd2: begin
6051                         litedramcore_bankmachine4_row_close <= 1'd1;
6052                 end
6053                 2'd3: begin
6054                 end
6055                 3'd4: begin
6056                         litedramcore_bankmachine4_row_close <= 1'd1;
6057                 end
6058                 3'd5: begin
6059                 end
6060                 3'd6: begin
6061                 end
6062                 default: begin
6063                 end
6064         endcase
6065 end
6066 always @(*) begin
6067         litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
6068         case (litedramcore_bankmachine4_state)
6069                 1'd1: begin
6070                 end
6071                 2'd2: begin
6072                 end
6073                 2'd3: begin
6074                 end
6075                 3'd4: begin
6076                 end
6077                 3'd5: begin
6078                 end
6079                 3'd6: begin
6080                 end
6081                 default: begin
6082                         if (litedramcore_bankmachine4_refresh_req) begin
6083                         end else begin
6084                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6085                                         if (litedramcore_bankmachine4_row_opened) begin
6086                                                 if (litedramcore_bankmachine4_row_hit) begin
6087                                                         litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
6088                                                 end else begin
6089                                                 end
6090                                         end else begin
6091                                         end
6092                                 end
6093                         end
6094                 end
6095         endcase
6096 end
6097 always @(*) begin
6098         litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
6099         case (litedramcore_bankmachine4_state)
6100                 1'd1: begin
6101                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
6102                                 litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
6103                         end
6104                 end
6105                 2'd2: begin
6106                 end
6107                 2'd3: begin
6108                         if (litedramcore_bankmachine4_trccon_ready) begin
6109                                 litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
6110                         end
6111                 end
6112                 3'd4: begin
6113                 end
6114                 3'd5: begin
6115                 end
6116                 3'd6: begin
6117                 end
6118                 default: begin
6119                 end
6120         endcase
6121 end
6122 always @(*) begin
6123         litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
6124         case (litedramcore_bankmachine4_state)
6125                 1'd1: begin
6126                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
6127                                 litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
6128                         end
6129                 end
6130                 2'd2: begin
6131                 end
6132                 2'd3: begin
6133                 end
6134                 3'd4: begin
6135                 end
6136                 3'd5: begin
6137                 end
6138                 3'd6: begin
6139                 end
6140                 default: begin
6141                         if (litedramcore_bankmachine4_refresh_req) begin
6142                         end else begin
6143                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6144                                         if (litedramcore_bankmachine4_row_opened) begin
6145                                                 if (litedramcore_bankmachine4_row_hit) begin
6146                                                         if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
6147                                                                 litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
6148                                                         end else begin
6149                                                         end
6150                                                 end else begin
6151                                                 end
6152                                         end else begin
6153                                         end
6154                                 end
6155                         end
6156                 end
6157         endcase
6158 end
6159 always @(*) begin
6160         litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
6161         case (litedramcore_bankmachine4_state)
6162                 1'd1: begin
6163                 end
6164                 2'd2: begin
6165                 end
6166                 2'd3: begin
6167                         if (litedramcore_bankmachine4_trccon_ready) begin
6168                                 litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
6169                         end
6170                 end
6171                 3'd4: begin
6172                 end
6173                 3'd5: begin
6174                 end
6175                 3'd6: begin
6176                 end
6177                 default: begin
6178                 end
6179         endcase
6180 end
6181 always @(*) begin
6182         litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
6183         case (litedramcore_bankmachine4_state)
6184                 1'd1: begin
6185                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
6186                                 litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
6187                         end
6188                 end
6189                 2'd2: begin
6190                 end
6191                 2'd3: begin
6192                         if (litedramcore_bankmachine4_trccon_ready) begin
6193                                 litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
6194                         end
6195                 end
6196                 3'd4: begin
6197                         litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
6198                 end
6199                 3'd5: begin
6200                 end
6201                 3'd6: begin
6202                 end
6203                 default: begin
6204                 end
6205         endcase
6206 end
6207 always @(*) begin
6208         litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
6209         case (litedramcore_bankmachine4_state)
6210                 1'd1: begin
6211                 end
6212                 2'd2: begin
6213                 end
6214                 2'd3: begin
6215                 end
6216                 3'd4: begin
6217                 end
6218                 3'd5: begin
6219                 end
6220                 3'd6: begin
6221                 end
6222                 default: begin
6223                         if (litedramcore_bankmachine4_refresh_req) begin
6224                         end else begin
6225                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6226                                         if (litedramcore_bankmachine4_row_opened) begin
6227                                                 if (litedramcore_bankmachine4_row_hit) begin
6228                                                         if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
6229                                                         end else begin
6230                                                                 litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
6231                                                         end
6232                                                 end else begin
6233                                                 end
6234                                         end else begin
6235                                         end
6236                                 end
6237                         end
6238                 end
6239         endcase
6240 end
6241 always @(*) begin
6242         litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
6243         case (litedramcore_bankmachine4_state)
6244                 1'd1: begin
6245                 end
6246                 2'd2: begin
6247                 end
6248                 2'd3: begin
6249                 end
6250                 3'd4: begin
6251                 end
6252                 3'd5: begin
6253                 end
6254                 3'd6: begin
6255                 end
6256                 default: begin
6257                         if (litedramcore_bankmachine4_refresh_req) begin
6258                         end else begin
6259                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6260                                         if (litedramcore_bankmachine4_row_opened) begin
6261                                                 if (litedramcore_bankmachine4_row_hit) begin
6262                                                         if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
6263                                                                 litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
6264                                                         end else begin
6265                                                         end
6266                                                 end else begin
6267                                                 end
6268                                         end else begin
6269                                         end
6270                                 end
6271                         end
6272                 end
6273         endcase
6274 end
6275 always @(*) begin
6276         litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
6277         case (litedramcore_bankmachine4_state)
6278                 1'd1: begin
6279                 end
6280                 2'd2: begin
6281                 end
6282                 2'd3: begin
6283                 end
6284                 3'd4: begin
6285                 end
6286                 3'd5: begin
6287                 end
6288                 3'd6: begin
6289                 end
6290                 default: begin
6291                         if (litedramcore_bankmachine4_refresh_req) begin
6292                         end else begin
6293                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6294                                         if (litedramcore_bankmachine4_row_opened) begin
6295                                                 if (litedramcore_bankmachine4_row_hit) begin
6296                                                         if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
6297                                                                 litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
6298                                                         end else begin
6299                                                         end
6300                                                 end else begin
6301                                                 end
6302                                         end else begin
6303                                         end
6304                                 end
6305                         end
6306                 end
6307         endcase
6308 end
6309 always @(*) begin
6310         litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
6311         case (litedramcore_bankmachine4_state)
6312                 1'd1: begin
6313                 end
6314                 2'd2: begin
6315                 end
6316                 2'd3: begin
6317                 end
6318                 3'd4: begin
6319                 end
6320                 3'd5: begin
6321                 end
6322                 3'd6: begin
6323                 end
6324                 default: begin
6325                         if (litedramcore_bankmachine4_refresh_req) begin
6326                         end else begin
6327                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6328                                         if (litedramcore_bankmachine4_row_opened) begin
6329                                                 if (litedramcore_bankmachine4_row_hit) begin
6330                                                         if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
6331                                                         end else begin
6332                                                                 litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
6333                                                         end
6334                                                 end else begin
6335                                                 end
6336                                         end else begin
6337                                         end
6338                                 end
6339                         end
6340                 end
6341         endcase
6342 end
6343 always @(*) begin
6344         litedramcore_bankmachine4_refresh_gnt <= 1'd0;
6345         case (litedramcore_bankmachine4_state)
6346                 1'd1: begin
6347                 end
6348                 2'd2: begin
6349                 end
6350                 2'd3: begin
6351                 end
6352                 3'd4: begin
6353                         if (litedramcore_bankmachine4_twtpcon_ready) begin
6354                                 litedramcore_bankmachine4_refresh_gnt <= 1'd1;
6355                         end
6356                 end
6357                 3'd5: begin
6358                 end
6359                 3'd6: begin
6360                 end
6361                 default: begin
6362                 end
6363         endcase
6364 end
6365 always @(*) begin
6366         litedramcore_bankmachine4_cmd_valid <= 1'd0;
6367         case (litedramcore_bankmachine4_state)
6368                 1'd1: begin
6369                         if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
6370                                 litedramcore_bankmachine4_cmd_valid <= 1'd1;
6371                         end
6372                 end
6373                 2'd2: begin
6374                 end
6375                 2'd3: begin
6376                         if (litedramcore_bankmachine4_trccon_ready) begin
6377                                 litedramcore_bankmachine4_cmd_valid <= 1'd1;
6378                         end
6379                 end
6380                 3'd4: begin
6381                 end
6382                 3'd5: begin
6383                 end
6384                 3'd6: begin
6385                 end
6386                 default: begin
6387                         if (litedramcore_bankmachine4_refresh_req) begin
6388                         end else begin
6389                                 if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
6390                                         if (litedramcore_bankmachine4_row_opened) begin
6391                                                 if (litedramcore_bankmachine4_row_hit) begin
6392                                                         litedramcore_bankmachine4_cmd_valid <= 1'd1;
6393                                                 end else begin
6394                                                 end
6395                                         end else begin
6396                                         end
6397                                 end
6398                         end
6399                 end
6400         endcase
6401 end
6402 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
6403 assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
6404 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
6405 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
6406 assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
6407 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
6408 assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
6409 assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
6410 assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
6411 assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
6412 assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
6413 assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
6414 assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
6415 assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
6416 always @(*) begin
6417         litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
6418         if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
6419                 litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
6420         end else begin
6421                 litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
6422         end
6423 end
6424 assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
6425 assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
6426 assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
6427 always @(*) begin
6428         litedramcore_bankmachine5_auto_precharge <= 1'd0;
6429         if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
6430                 if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
6431                         litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
6432                 end
6433         end
6434 end
6435 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
6436 assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
6437 assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
6438 assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
6439 assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
6440 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
6441 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
6442 assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
6443 assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
6444 assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
6445 assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
6446 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
6447 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
6448 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
6449 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
6450 assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
6451 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
6452 always @(*) begin
6453         litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
6454         if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
6455                 litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
6456         end else begin
6457                 litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
6458         end
6459 end
6460 assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
6461 assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
6462 assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
6463 assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
6464 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
6465 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
6466 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
6467 assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
6468 always @(*) begin
6469         litedramcore_bankmachine5_next_state <= 3'd0;
6470         litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
6471         case (litedramcore_bankmachine5_state)
6472                 1'd1: begin
6473                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6474                                 if (litedramcore_bankmachine5_cmd_ready) begin
6475                                         litedramcore_bankmachine5_next_state <= 3'd5;
6476                                 end
6477                         end
6478                 end
6479                 2'd2: begin
6480                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6481                                 litedramcore_bankmachine5_next_state <= 3'd5;
6482                         end
6483                 end
6484                 2'd3: begin
6485                         if (litedramcore_bankmachine5_trccon_ready) begin
6486                                 if (litedramcore_bankmachine5_cmd_ready) begin
6487                                         litedramcore_bankmachine5_next_state <= 3'd6;
6488                                 end
6489                         end
6490                 end
6491                 3'd4: begin
6492                         if ((~litedramcore_bankmachine5_refresh_req)) begin
6493                                 litedramcore_bankmachine5_next_state <= 1'd0;
6494                         end
6495                 end
6496                 3'd5: begin
6497                         litedramcore_bankmachine5_next_state <= 2'd3;
6498                 end
6499                 3'd6: begin
6500                         litedramcore_bankmachine5_next_state <= 1'd0;
6501                 end
6502                 default: begin
6503                         if (litedramcore_bankmachine5_refresh_req) begin
6504                                 litedramcore_bankmachine5_next_state <= 3'd4;
6505                         end else begin
6506                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6507                                         if (litedramcore_bankmachine5_row_opened) begin
6508                                                 if (litedramcore_bankmachine5_row_hit) begin
6509                                                         if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
6510                                                                 litedramcore_bankmachine5_next_state <= 2'd2;
6511                                                         end
6512                                                 end else begin
6513                                                         litedramcore_bankmachine5_next_state <= 1'd1;
6514                                                 end
6515                                         end else begin
6516                                                 litedramcore_bankmachine5_next_state <= 2'd3;
6517                                         end
6518                                 end
6519                         end
6520                 end
6521         endcase
6522 end
6523 always @(*) begin
6524         litedramcore_bankmachine5_row_open <= 1'd0;
6525         case (litedramcore_bankmachine5_state)
6526                 1'd1: begin
6527                 end
6528                 2'd2: begin
6529                 end
6530                 2'd3: begin
6531                         if (litedramcore_bankmachine5_trccon_ready) begin
6532                                 litedramcore_bankmachine5_row_open <= 1'd1;
6533                         end
6534                 end
6535                 3'd4: begin
6536                 end
6537                 3'd5: begin
6538                 end
6539                 3'd6: begin
6540                 end
6541                 default: begin
6542                 end
6543         endcase
6544 end
6545 always @(*) begin
6546         litedramcore_bankmachine5_row_close <= 1'd0;
6547         case (litedramcore_bankmachine5_state)
6548                 1'd1: begin
6549                         litedramcore_bankmachine5_row_close <= 1'd1;
6550                 end
6551                 2'd2: begin
6552                         litedramcore_bankmachine5_row_close <= 1'd1;
6553                 end
6554                 2'd3: begin
6555                 end
6556                 3'd4: begin
6557                         litedramcore_bankmachine5_row_close <= 1'd1;
6558                 end
6559                 3'd5: begin
6560                 end
6561                 3'd6: begin
6562                 end
6563                 default: begin
6564                 end
6565         endcase
6566 end
6567 always @(*) begin
6568         litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
6569         case (litedramcore_bankmachine5_state)
6570                 1'd1: begin
6571                 end
6572                 2'd2: begin
6573                 end
6574                 2'd3: begin
6575                 end
6576                 3'd4: begin
6577                 end
6578                 3'd5: begin
6579                 end
6580                 3'd6: begin
6581                 end
6582                 default: begin
6583                         if (litedramcore_bankmachine5_refresh_req) begin
6584                         end else begin
6585                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6586                                         if (litedramcore_bankmachine5_row_opened) begin
6587                                                 if (litedramcore_bankmachine5_row_hit) begin
6588                                                         litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
6589                                                 end else begin
6590                                                 end
6591                                         end else begin
6592                                         end
6593                                 end
6594                         end
6595                 end
6596         endcase
6597 end
6598 always @(*) begin
6599         litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
6600         case (litedramcore_bankmachine5_state)
6601                 1'd1: begin
6602                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6603                                 litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
6604                         end
6605                 end
6606                 2'd2: begin
6607                 end
6608                 2'd3: begin
6609                         if (litedramcore_bankmachine5_trccon_ready) begin
6610                                 litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
6611                         end
6612                 end
6613                 3'd4: begin
6614                 end
6615                 3'd5: begin
6616                 end
6617                 3'd6: begin
6618                 end
6619                 default: begin
6620                 end
6621         endcase
6622 end
6623 always @(*) begin
6624         litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
6625         case (litedramcore_bankmachine5_state)
6626                 1'd1: begin
6627                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6628                                 litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
6629                         end
6630                 end
6631                 2'd2: begin
6632                 end
6633                 2'd3: begin
6634                 end
6635                 3'd4: begin
6636                 end
6637                 3'd5: begin
6638                 end
6639                 3'd6: begin
6640                 end
6641                 default: begin
6642                         if (litedramcore_bankmachine5_refresh_req) begin
6643                         end else begin
6644                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6645                                         if (litedramcore_bankmachine5_row_opened) begin
6646                                                 if (litedramcore_bankmachine5_row_hit) begin
6647                                                         if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
6648                                                                 litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
6649                                                         end else begin
6650                                                         end
6651                                                 end else begin
6652                                                 end
6653                                         end else begin
6654                                         end
6655                                 end
6656                         end
6657                 end
6658         endcase
6659 end
6660 always @(*) begin
6661         litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
6662         case (litedramcore_bankmachine5_state)
6663                 1'd1: begin
6664                 end
6665                 2'd2: begin
6666                 end
6667                 2'd3: begin
6668                         if (litedramcore_bankmachine5_trccon_ready) begin
6669                                 litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
6670                         end
6671                 end
6672                 3'd4: begin
6673                 end
6674                 3'd5: begin
6675                 end
6676                 3'd6: begin
6677                 end
6678                 default: begin
6679                 end
6680         endcase
6681 end
6682 always @(*) begin
6683         litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
6684         case (litedramcore_bankmachine5_state)
6685                 1'd1: begin
6686                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6687                                 litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
6688                         end
6689                 end
6690                 2'd2: begin
6691                 end
6692                 2'd3: begin
6693                         if (litedramcore_bankmachine5_trccon_ready) begin
6694                                 litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
6695                         end
6696                 end
6697                 3'd4: begin
6698                         litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
6699                 end
6700                 3'd5: begin
6701                 end
6702                 3'd6: begin
6703                 end
6704                 default: begin
6705                 end
6706         endcase
6707 end
6708 always @(*) begin
6709         litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
6710         case (litedramcore_bankmachine5_state)
6711                 1'd1: begin
6712                 end
6713                 2'd2: begin
6714                 end
6715                 2'd3: begin
6716                 end
6717                 3'd4: begin
6718                 end
6719                 3'd5: begin
6720                 end
6721                 3'd6: begin
6722                 end
6723                 default: begin
6724                         if (litedramcore_bankmachine5_refresh_req) begin
6725                         end else begin
6726                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6727                                         if (litedramcore_bankmachine5_row_opened) begin
6728                                                 if (litedramcore_bankmachine5_row_hit) begin
6729                                                         if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
6730                                                         end else begin
6731                                                                 litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
6732                                                         end
6733                                                 end else begin
6734                                                 end
6735                                         end else begin
6736                                         end
6737                                 end
6738                         end
6739                 end
6740         endcase
6741 end
6742 always @(*) begin
6743         litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
6744         case (litedramcore_bankmachine5_state)
6745                 1'd1: begin
6746                 end
6747                 2'd2: begin
6748                 end
6749                 2'd3: begin
6750                 end
6751                 3'd4: begin
6752                 end
6753                 3'd5: begin
6754                 end
6755                 3'd6: begin
6756                 end
6757                 default: begin
6758                         if (litedramcore_bankmachine5_refresh_req) begin
6759                         end else begin
6760                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6761                                         if (litedramcore_bankmachine5_row_opened) begin
6762                                                 if (litedramcore_bankmachine5_row_hit) begin
6763                                                         if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
6764                                                                 litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
6765                                                         end else begin
6766                                                         end
6767                                                 end else begin
6768                                                 end
6769                                         end else begin
6770                                         end
6771                                 end
6772                         end
6773                 end
6774         endcase
6775 end
6776 always @(*) begin
6777         litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
6778         case (litedramcore_bankmachine5_state)
6779                 1'd1: begin
6780                 end
6781                 2'd2: begin
6782                 end
6783                 2'd3: begin
6784                 end
6785                 3'd4: begin
6786                 end
6787                 3'd5: begin
6788                 end
6789                 3'd6: begin
6790                 end
6791                 default: begin
6792                         if (litedramcore_bankmachine5_refresh_req) begin
6793                         end else begin
6794                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6795                                         if (litedramcore_bankmachine5_row_opened) begin
6796                                                 if (litedramcore_bankmachine5_row_hit) begin
6797                                                         if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
6798                                                                 litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
6799                                                         end else begin
6800                                                         end
6801                                                 end else begin
6802                                                 end
6803                                         end else begin
6804                                         end
6805                                 end
6806                         end
6807                 end
6808         endcase
6809 end
6810 always @(*) begin
6811         litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
6812         case (litedramcore_bankmachine5_state)
6813                 1'd1: begin
6814                 end
6815                 2'd2: begin
6816                 end
6817                 2'd3: begin
6818                 end
6819                 3'd4: begin
6820                 end
6821                 3'd5: begin
6822                 end
6823                 3'd6: begin
6824                 end
6825                 default: begin
6826                         if (litedramcore_bankmachine5_refresh_req) begin
6827                         end else begin
6828                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6829                                         if (litedramcore_bankmachine5_row_opened) begin
6830                                                 if (litedramcore_bankmachine5_row_hit) begin
6831                                                         if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
6832                                                         end else begin
6833                                                                 litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
6834                                                         end
6835                                                 end else begin
6836                                                 end
6837                                         end else begin
6838                                         end
6839                                 end
6840                         end
6841                 end
6842         endcase
6843 end
6844 always @(*) begin
6845         litedramcore_bankmachine5_refresh_gnt <= 1'd0;
6846         case (litedramcore_bankmachine5_state)
6847                 1'd1: begin
6848                 end
6849                 2'd2: begin
6850                 end
6851                 2'd3: begin
6852                 end
6853                 3'd4: begin
6854                         if (litedramcore_bankmachine5_twtpcon_ready) begin
6855                                 litedramcore_bankmachine5_refresh_gnt <= 1'd1;
6856                         end
6857                 end
6858                 3'd5: begin
6859                 end
6860                 3'd6: begin
6861                 end
6862                 default: begin
6863                 end
6864         endcase
6865 end
6866 always @(*) begin
6867         litedramcore_bankmachine5_cmd_valid <= 1'd0;
6868         case (litedramcore_bankmachine5_state)
6869                 1'd1: begin
6870                         if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
6871                                 litedramcore_bankmachine5_cmd_valid <= 1'd1;
6872                         end
6873                 end
6874                 2'd2: begin
6875                 end
6876                 2'd3: begin
6877                         if (litedramcore_bankmachine5_trccon_ready) begin
6878                                 litedramcore_bankmachine5_cmd_valid <= 1'd1;
6879                         end
6880                 end
6881                 3'd4: begin
6882                 end
6883                 3'd5: begin
6884                 end
6885                 3'd6: begin
6886                 end
6887                 default: begin
6888                         if (litedramcore_bankmachine5_refresh_req) begin
6889                         end else begin
6890                                 if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
6891                                         if (litedramcore_bankmachine5_row_opened) begin
6892                                                 if (litedramcore_bankmachine5_row_hit) begin
6893                                                         litedramcore_bankmachine5_cmd_valid <= 1'd1;
6894                                                 end else begin
6895                                                 end
6896                                         end else begin
6897                                         end
6898                                 end
6899                         end
6900                 end
6901         endcase
6902 end
6903 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
6904 assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
6905 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
6906 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
6907 assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
6908 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
6909 assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
6910 assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
6911 assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
6912 assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
6913 assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
6914 assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
6915 assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
6916 assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
6917 always @(*) begin
6918         litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
6919         if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
6920                 litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
6921         end else begin
6922                 litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
6923         end
6924 end
6925 assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
6926 assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
6927 assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
6928 always @(*) begin
6929         litedramcore_bankmachine6_auto_precharge <= 1'd0;
6930         if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
6931                 if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
6932                         litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
6933                 end
6934         end
6935 end
6936 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
6937 assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
6938 assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
6939 assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
6940 assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
6941 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
6942 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
6943 assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
6944 assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
6945 assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
6946 assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
6947 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
6948 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
6949 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
6950 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
6951 assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
6952 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
6953 always @(*) begin
6954         litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
6955         if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
6956                 litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
6957         end else begin
6958                 litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
6959         end
6960 end
6961 assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
6962 assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
6963 assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
6964 assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
6965 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
6966 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
6967 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
6968 assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
6969 always @(*) begin
6970         litedramcore_bankmachine6_next_state <= 3'd0;
6971         litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
6972         case (litedramcore_bankmachine6_state)
6973                 1'd1: begin
6974                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
6975                                 if (litedramcore_bankmachine6_cmd_ready) begin
6976                                         litedramcore_bankmachine6_next_state <= 3'd5;
6977                                 end
6978                         end
6979                 end
6980                 2'd2: begin
6981                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
6982                                 litedramcore_bankmachine6_next_state <= 3'd5;
6983                         end
6984                 end
6985                 2'd3: begin
6986                         if (litedramcore_bankmachine6_trccon_ready) begin
6987                                 if (litedramcore_bankmachine6_cmd_ready) begin
6988                                         litedramcore_bankmachine6_next_state <= 3'd6;
6989                                 end
6990                         end
6991                 end
6992                 3'd4: begin
6993                         if ((~litedramcore_bankmachine6_refresh_req)) begin
6994                                 litedramcore_bankmachine6_next_state <= 1'd0;
6995                         end
6996                 end
6997                 3'd5: begin
6998                         litedramcore_bankmachine6_next_state <= 2'd3;
6999                 end
7000                 3'd6: begin
7001                         litedramcore_bankmachine6_next_state <= 1'd0;
7002                 end
7003                 default: begin
7004                         if (litedramcore_bankmachine6_refresh_req) begin
7005                                 litedramcore_bankmachine6_next_state <= 3'd4;
7006                         end else begin
7007                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7008                                         if (litedramcore_bankmachine6_row_opened) begin
7009                                                 if (litedramcore_bankmachine6_row_hit) begin
7010                                                         if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
7011                                                                 litedramcore_bankmachine6_next_state <= 2'd2;
7012                                                         end
7013                                                 end else begin
7014                                                         litedramcore_bankmachine6_next_state <= 1'd1;
7015                                                 end
7016                                         end else begin
7017                                                 litedramcore_bankmachine6_next_state <= 2'd3;
7018                                         end
7019                                 end
7020                         end
7021                 end
7022         endcase
7023 end
7024 always @(*) begin
7025         litedramcore_bankmachine6_row_open <= 1'd0;
7026         case (litedramcore_bankmachine6_state)
7027                 1'd1: begin
7028                 end
7029                 2'd2: begin
7030                 end
7031                 2'd3: begin
7032                         if (litedramcore_bankmachine6_trccon_ready) begin
7033                                 litedramcore_bankmachine6_row_open <= 1'd1;
7034                         end
7035                 end
7036                 3'd4: begin
7037                 end
7038                 3'd5: begin
7039                 end
7040                 3'd6: begin
7041                 end
7042                 default: begin
7043                 end
7044         endcase
7045 end
7046 always @(*) begin
7047         litedramcore_bankmachine6_row_close <= 1'd0;
7048         case (litedramcore_bankmachine6_state)
7049                 1'd1: begin
7050                         litedramcore_bankmachine6_row_close <= 1'd1;
7051                 end
7052                 2'd2: begin
7053                         litedramcore_bankmachine6_row_close <= 1'd1;
7054                 end
7055                 2'd3: begin
7056                 end
7057                 3'd4: begin
7058                         litedramcore_bankmachine6_row_close <= 1'd1;
7059                 end
7060                 3'd5: begin
7061                 end
7062                 3'd6: begin
7063                 end
7064                 default: begin
7065                 end
7066         endcase
7067 end
7068 always @(*) begin
7069         litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
7070         case (litedramcore_bankmachine6_state)
7071                 1'd1: begin
7072                 end
7073                 2'd2: begin
7074                 end
7075                 2'd3: begin
7076                 end
7077                 3'd4: begin
7078                 end
7079                 3'd5: begin
7080                 end
7081                 3'd6: begin
7082                 end
7083                 default: begin
7084                         if (litedramcore_bankmachine6_refresh_req) begin
7085                         end else begin
7086                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7087                                         if (litedramcore_bankmachine6_row_opened) begin
7088                                                 if (litedramcore_bankmachine6_row_hit) begin
7089                                                         litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
7090                                                 end else begin
7091                                                 end
7092                                         end else begin
7093                                         end
7094                                 end
7095                         end
7096                 end
7097         endcase
7098 end
7099 always @(*) begin
7100         litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
7101         case (litedramcore_bankmachine6_state)
7102                 1'd1: begin
7103                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
7104                                 litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
7105                         end
7106                 end
7107                 2'd2: begin
7108                 end
7109                 2'd3: begin
7110                         if (litedramcore_bankmachine6_trccon_ready) begin
7111                                 litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
7112                         end
7113                 end
7114                 3'd4: begin
7115                 end
7116                 3'd5: begin
7117                 end
7118                 3'd6: begin
7119                 end
7120                 default: begin
7121                 end
7122         endcase
7123 end
7124 always @(*) begin
7125         litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
7126         case (litedramcore_bankmachine6_state)
7127                 1'd1: begin
7128                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
7129                                 litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
7130                         end
7131                 end
7132                 2'd2: begin
7133                 end
7134                 2'd3: begin
7135                 end
7136                 3'd4: begin
7137                 end
7138                 3'd5: begin
7139                 end
7140                 3'd6: begin
7141                 end
7142                 default: begin
7143                         if (litedramcore_bankmachine6_refresh_req) begin
7144                         end else begin
7145                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7146                                         if (litedramcore_bankmachine6_row_opened) begin
7147                                                 if (litedramcore_bankmachine6_row_hit) begin
7148                                                         if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
7149                                                                 litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
7150                                                         end else begin
7151                                                         end
7152                                                 end else begin
7153                                                 end
7154                                         end else begin
7155                                         end
7156                                 end
7157                         end
7158                 end
7159         endcase
7160 end
7161 always @(*) begin
7162         litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
7163         case (litedramcore_bankmachine6_state)
7164                 1'd1: begin
7165                 end
7166                 2'd2: begin
7167                 end
7168                 2'd3: begin
7169                         if (litedramcore_bankmachine6_trccon_ready) begin
7170                                 litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
7171                         end
7172                 end
7173                 3'd4: begin
7174                 end
7175                 3'd5: begin
7176                 end
7177                 3'd6: begin
7178                 end
7179                 default: begin
7180                 end
7181         endcase
7182 end
7183 always @(*) begin
7184         litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
7185         case (litedramcore_bankmachine6_state)
7186                 1'd1: begin
7187                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
7188                                 litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
7189                         end
7190                 end
7191                 2'd2: begin
7192                 end
7193                 2'd3: begin
7194                         if (litedramcore_bankmachine6_trccon_ready) begin
7195                                 litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
7196                         end
7197                 end
7198                 3'd4: begin
7199                         litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
7200                 end
7201                 3'd5: begin
7202                 end
7203                 3'd6: begin
7204                 end
7205                 default: begin
7206                 end
7207         endcase
7208 end
7209 always @(*) begin
7210         litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
7211         case (litedramcore_bankmachine6_state)
7212                 1'd1: begin
7213                 end
7214                 2'd2: begin
7215                 end
7216                 2'd3: begin
7217                 end
7218                 3'd4: begin
7219                 end
7220                 3'd5: begin
7221                 end
7222                 3'd6: begin
7223                 end
7224                 default: begin
7225                         if (litedramcore_bankmachine6_refresh_req) begin
7226                         end else begin
7227                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7228                                         if (litedramcore_bankmachine6_row_opened) begin
7229                                                 if (litedramcore_bankmachine6_row_hit) begin
7230                                                         if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
7231                                                         end else begin
7232                                                                 litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
7233                                                         end
7234                                                 end else begin
7235                                                 end
7236                                         end else begin
7237                                         end
7238                                 end
7239                         end
7240                 end
7241         endcase
7242 end
7243 always @(*) begin
7244         litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
7245         case (litedramcore_bankmachine6_state)
7246                 1'd1: begin
7247                 end
7248                 2'd2: begin
7249                 end
7250                 2'd3: begin
7251                 end
7252                 3'd4: begin
7253                 end
7254                 3'd5: begin
7255                 end
7256                 3'd6: begin
7257                 end
7258                 default: begin
7259                         if (litedramcore_bankmachine6_refresh_req) begin
7260                         end else begin
7261                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7262                                         if (litedramcore_bankmachine6_row_opened) begin
7263                                                 if (litedramcore_bankmachine6_row_hit) begin
7264                                                         if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
7265                                                                 litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
7266                                                         end else begin
7267                                                         end
7268                                                 end else begin
7269                                                 end
7270                                         end else begin
7271                                         end
7272                                 end
7273                         end
7274                 end
7275         endcase
7276 end
7277 always @(*) begin
7278         litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
7279         case (litedramcore_bankmachine6_state)
7280                 1'd1: begin
7281                 end
7282                 2'd2: begin
7283                 end
7284                 2'd3: begin
7285                 end
7286                 3'd4: begin
7287                 end
7288                 3'd5: begin
7289                 end
7290                 3'd6: begin
7291                 end
7292                 default: begin
7293                         if (litedramcore_bankmachine6_refresh_req) begin
7294                         end else begin
7295                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7296                                         if (litedramcore_bankmachine6_row_opened) begin
7297                                                 if (litedramcore_bankmachine6_row_hit) begin
7298                                                         if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
7299                                                                 litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
7300                                                         end else begin
7301                                                         end
7302                                                 end else begin
7303                                                 end
7304                                         end else begin
7305                                         end
7306                                 end
7307                         end
7308                 end
7309         endcase
7310 end
7311 always @(*) begin
7312         litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
7313         case (litedramcore_bankmachine6_state)
7314                 1'd1: begin
7315                 end
7316                 2'd2: begin
7317                 end
7318                 2'd3: begin
7319                 end
7320                 3'd4: begin
7321                 end
7322                 3'd5: begin
7323                 end
7324                 3'd6: begin
7325                 end
7326                 default: begin
7327                         if (litedramcore_bankmachine6_refresh_req) begin
7328                         end else begin
7329                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7330                                         if (litedramcore_bankmachine6_row_opened) begin
7331                                                 if (litedramcore_bankmachine6_row_hit) begin
7332                                                         if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
7333                                                         end else begin
7334                                                                 litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
7335                                                         end
7336                                                 end else begin
7337                                                 end
7338                                         end else begin
7339                                         end
7340                                 end
7341                         end
7342                 end
7343         endcase
7344 end
7345 always @(*) begin
7346         litedramcore_bankmachine6_refresh_gnt <= 1'd0;
7347         case (litedramcore_bankmachine6_state)
7348                 1'd1: begin
7349                 end
7350                 2'd2: begin
7351                 end
7352                 2'd3: begin
7353                 end
7354                 3'd4: begin
7355                         if (litedramcore_bankmachine6_twtpcon_ready) begin
7356                                 litedramcore_bankmachine6_refresh_gnt <= 1'd1;
7357                         end
7358                 end
7359                 3'd5: begin
7360                 end
7361                 3'd6: begin
7362                 end
7363                 default: begin
7364                 end
7365         endcase
7366 end
7367 always @(*) begin
7368         litedramcore_bankmachine6_cmd_valid <= 1'd0;
7369         case (litedramcore_bankmachine6_state)
7370                 1'd1: begin
7371                         if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
7372                                 litedramcore_bankmachine6_cmd_valid <= 1'd1;
7373                         end
7374                 end
7375                 2'd2: begin
7376                 end
7377                 2'd3: begin
7378                         if (litedramcore_bankmachine6_trccon_ready) begin
7379                                 litedramcore_bankmachine6_cmd_valid <= 1'd1;
7380                         end
7381                 end
7382                 3'd4: begin
7383                 end
7384                 3'd5: begin
7385                 end
7386                 3'd6: begin
7387                 end
7388                 default: begin
7389                         if (litedramcore_bankmachine6_refresh_req) begin
7390                         end else begin
7391                                 if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
7392                                         if (litedramcore_bankmachine6_row_opened) begin
7393                                                 if (litedramcore_bankmachine6_row_hit) begin
7394                                                         litedramcore_bankmachine6_cmd_valid <= 1'd1;
7395                                                 end else begin
7396                                                 end
7397                                         end else begin
7398                                         end
7399                                 end
7400                         end
7401                 end
7402         endcase
7403 end
7404 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
7405 assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
7406 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
7407 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
7408 assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
7409 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
7410 assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
7411 assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
7412 assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
7413 assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
7414 assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
7415 assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
7416 assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
7417 assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
7418 always @(*) begin
7419         litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
7420         if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
7421                 litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
7422         end else begin
7423                 litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
7424         end
7425 end
7426 assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
7427 assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
7428 assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
7429 always @(*) begin
7430         litedramcore_bankmachine7_auto_precharge <= 1'd0;
7431         if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
7432                 if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
7433                         litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
7434                 end
7435         end
7436 end
7437 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
7438 assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
7439 assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
7440 assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
7441 assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
7442 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
7443 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
7444 assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
7445 assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
7446 assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
7447 assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
7448 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
7449 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
7450 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
7451 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
7452 assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
7453 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
7454 always @(*) begin
7455         litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
7456         if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
7457                 litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
7458         end else begin
7459                 litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
7460         end
7461 end
7462 assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
7463 assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
7464 assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
7465 assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
7466 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
7467 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
7468 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
7469 assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
7470 always @(*) begin
7471         litedramcore_bankmachine7_next_state <= 3'd0;
7472         litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
7473         case (litedramcore_bankmachine7_state)
7474                 1'd1: begin
7475                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7476                                 if (litedramcore_bankmachine7_cmd_ready) begin
7477                                         litedramcore_bankmachine7_next_state <= 3'd5;
7478                                 end
7479                         end
7480                 end
7481                 2'd2: begin
7482                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7483                                 litedramcore_bankmachine7_next_state <= 3'd5;
7484                         end
7485                 end
7486                 2'd3: begin
7487                         if (litedramcore_bankmachine7_trccon_ready) begin
7488                                 if (litedramcore_bankmachine7_cmd_ready) begin
7489                                         litedramcore_bankmachine7_next_state <= 3'd6;
7490                                 end
7491                         end
7492                 end
7493                 3'd4: begin
7494                         if ((~litedramcore_bankmachine7_refresh_req)) begin
7495                                 litedramcore_bankmachine7_next_state <= 1'd0;
7496                         end
7497                 end
7498                 3'd5: begin
7499                         litedramcore_bankmachine7_next_state <= 2'd3;
7500                 end
7501                 3'd6: begin
7502                         litedramcore_bankmachine7_next_state <= 1'd0;
7503                 end
7504                 default: begin
7505                         if (litedramcore_bankmachine7_refresh_req) begin
7506                                 litedramcore_bankmachine7_next_state <= 3'd4;
7507                         end else begin
7508                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7509                                         if (litedramcore_bankmachine7_row_opened) begin
7510                                                 if (litedramcore_bankmachine7_row_hit) begin
7511                                                         if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
7512                                                                 litedramcore_bankmachine7_next_state <= 2'd2;
7513                                                         end
7514                                                 end else begin
7515                                                         litedramcore_bankmachine7_next_state <= 1'd1;
7516                                                 end
7517                                         end else begin
7518                                                 litedramcore_bankmachine7_next_state <= 2'd3;
7519                                         end
7520                                 end
7521                         end
7522                 end
7523         endcase
7524 end
7525 always @(*) begin
7526         litedramcore_bankmachine7_row_open <= 1'd0;
7527         case (litedramcore_bankmachine7_state)
7528                 1'd1: begin
7529                 end
7530                 2'd2: begin
7531                 end
7532                 2'd3: begin
7533                         if (litedramcore_bankmachine7_trccon_ready) begin
7534                                 litedramcore_bankmachine7_row_open <= 1'd1;
7535                         end
7536                 end
7537                 3'd4: begin
7538                 end
7539                 3'd5: begin
7540                 end
7541                 3'd6: begin
7542                 end
7543                 default: begin
7544                 end
7545         endcase
7546 end
7547 always @(*) begin
7548         litedramcore_bankmachine7_row_close <= 1'd0;
7549         case (litedramcore_bankmachine7_state)
7550                 1'd1: begin
7551                         litedramcore_bankmachine7_row_close <= 1'd1;
7552                 end
7553                 2'd2: begin
7554                         litedramcore_bankmachine7_row_close <= 1'd1;
7555                 end
7556                 2'd3: begin
7557                 end
7558                 3'd4: begin
7559                         litedramcore_bankmachine7_row_close <= 1'd1;
7560                 end
7561                 3'd5: begin
7562                 end
7563                 3'd6: begin
7564                 end
7565                 default: begin
7566                 end
7567         endcase
7568 end
7569 always @(*) begin
7570         litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
7571         case (litedramcore_bankmachine7_state)
7572                 1'd1: begin
7573                 end
7574                 2'd2: begin
7575                 end
7576                 2'd3: begin
7577                 end
7578                 3'd4: begin
7579                 end
7580                 3'd5: begin
7581                 end
7582                 3'd6: begin
7583                 end
7584                 default: begin
7585                         if (litedramcore_bankmachine7_refresh_req) begin
7586                         end else begin
7587                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7588                                         if (litedramcore_bankmachine7_row_opened) begin
7589                                                 if (litedramcore_bankmachine7_row_hit) begin
7590                                                         litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
7591                                                 end else begin
7592                                                 end
7593                                         end else begin
7594                                         end
7595                                 end
7596                         end
7597                 end
7598         endcase
7599 end
7600 always @(*) begin
7601         litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
7602         case (litedramcore_bankmachine7_state)
7603                 1'd1: begin
7604                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7605                                 litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
7606                         end
7607                 end
7608                 2'd2: begin
7609                 end
7610                 2'd3: begin
7611                         if (litedramcore_bankmachine7_trccon_ready) begin
7612                                 litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
7613                         end
7614                 end
7615                 3'd4: begin
7616                 end
7617                 3'd5: begin
7618                 end
7619                 3'd6: begin
7620                 end
7621                 default: begin
7622                 end
7623         endcase
7624 end
7625 always @(*) begin
7626         litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
7627         case (litedramcore_bankmachine7_state)
7628                 1'd1: begin
7629                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7630                                 litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
7631                         end
7632                 end
7633                 2'd2: begin
7634                 end
7635                 2'd3: begin
7636                 end
7637                 3'd4: begin
7638                 end
7639                 3'd5: begin
7640                 end
7641                 3'd6: begin
7642                 end
7643                 default: begin
7644                         if (litedramcore_bankmachine7_refresh_req) begin
7645                         end else begin
7646                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7647                                         if (litedramcore_bankmachine7_row_opened) begin
7648                                                 if (litedramcore_bankmachine7_row_hit) begin
7649                                                         if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
7650                                                                 litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
7651                                                         end else begin
7652                                                         end
7653                                                 end else begin
7654                                                 end
7655                                         end else begin
7656                                         end
7657                                 end
7658                         end
7659                 end
7660         endcase
7661 end
7662 always @(*) begin
7663         litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
7664         case (litedramcore_bankmachine7_state)
7665                 1'd1: begin
7666                 end
7667                 2'd2: begin
7668                 end
7669                 2'd3: begin
7670                         if (litedramcore_bankmachine7_trccon_ready) begin
7671                                 litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
7672                         end
7673                 end
7674                 3'd4: begin
7675                 end
7676                 3'd5: begin
7677                 end
7678                 3'd6: begin
7679                 end
7680                 default: begin
7681                 end
7682         endcase
7683 end
7684 always @(*) begin
7685         litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
7686         case (litedramcore_bankmachine7_state)
7687                 1'd1: begin
7688                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7689                                 litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
7690                         end
7691                 end
7692                 2'd2: begin
7693                 end
7694                 2'd3: begin
7695                         if (litedramcore_bankmachine7_trccon_ready) begin
7696                                 litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
7697                         end
7698                 end
7699                 3'd4: begin
7700                         litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
7701                 end
7702                 3'd5: begin
7703                 end
7704                 3'd6: begin
7705                 end
7706                 default: begin
7707                 end
7708         endcase
7709 end
7710 always @(*) begin
7711         litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
7712         case (litedramcore_bankmachine7_state)
7713                 1'd1: begin
7714                 end
7715                 2'd2: begin
7716                 end
7717                 2'd3: begin
7718                 end
7719                 3'd4: begin
7720                 end
7721                 3'd5: begin
7722                 end
7723                 3'd6: begin
7724                 end
7725                 default: begin
7726                         if (litedramcore_bankmachine7_refresh_req) begin
7727                         end else begin
7728                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7729                                         if (litedramcore_bankmachine7_row_opened) begin
7730                                                 if (litedramcore_bankmachine7_row_hit) begin
7731                                                         if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
7732                                                         end else begin
7733                                                                 litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
7734                                                         end
7735                                                 end else begin
7736                                                 end
7737                                         end else begin
7738                                         end
7739                                 end
7740                         end
7741                 end
7742         endcase
7743 end
7744 always @(*) begin
7745         litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
7746         case (litedramcore_bankmachine7_state)
7747                 1'd1: begin
7748                 end
7749                 2'd2: begin
7750                 end
7751                 2'd3: begin
7752                 end
7753                 3'd4: begin
7754                 end
7755                 3'd5: begin
7756                 end
7757                 3'd6: begin
7758                 end
7759                 default: begin
7760                         if (litedramcore_bankmachine7_refresh_req) begin
7761                         end else begin
7762                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7763                                         if (litedramcore_bankmachine7_row_opened) begin
7764                                                 if (litedramcore_bankmachine7_row_hit) begin
7765                                                         if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
7766                                                                 litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
7767                                                         end else begin
7768                                                         end
7769                                                 end else begin
7770                                                 end
7771                                         end else begin
7772                                         end
7773                                 end
7774                         end
7775                 end
7776         endcase
7777 end
7778 always @(*) begin
7779         litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
7780         case (litedramcore_bankmachine7_state)
7781                 1'd1: begin
7782                 end
7783                 2'd2: begin
7784                 end
7785                 2'd3: begin
7786                 end
7787                 3'd4: begin
7788                 end
7789                 3'd5: begin
7790                 end
7791                 3'd6: begin
7792                 end
7793                 default: begin
7794                         if (litedramcore_bankmachine7_refresh_req) begin
7795                         end else begin
7796                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7797                                         if (litedramcore_bankmachine7_row_opened) begin
7798                                                 if (litedramcore_bankmachine7_row_hit) begin
7799                                                         if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
7800                                                                 litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
7801                                                         end else begin
7802                                                         end
7803                                                 end else begin
7804                                                 end
7805                                         end else begin
7806                                         end
7807                                 end
7808                         end
7809                 end
7810         endcase
7811 end
7812 always @(*) begin
7813         litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
7814         case (litedramcore_bankmachine7_state)
7815                 1'd1: begin
7816                 end
7817                 2'd2: begin
7818                 end
7819                 2'd3: begin
7820                 end
7821                 3'd4: begin
7822                 end
7823                 3'd5: begin
7824                 end
7825                 3'd6: begin
7826                 end
7827                 default: begin
7828                         if (litedramcore_bankmachine7_refresh_req) begin
7829                         end else begin
7830                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7831                                         if (litedramcore_bankmachine7_row_opened) begin
7832                                                 if (litedramcore_bankmachine7_row_hit) begin
7833                                                         if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
7834                                                         end else begin
7835                                                                 litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
7836                                                         end
7837                                                 end else begin
7838                                                 end
7839                                         end else begin
7840                                         end
7841                                 end
7842                         end
7843                 end
7844         endcase
7845 end
7846 always @(*) begin
7847         litedramcore_bankmachine7_refresh_gnt <= 1'd0;
7848         case (litedramcore_bankmachine7_state)
7849                 1'd1: begin
7850                 end
7851                 2'd2: begin
7852                 end
7853                 2'd3: begin
7854                 end
7855                 3'd4: begin
7856                         if (litedramcore_bankmachine7_twtpcon_ready) begin
7857                                 litedramcore_bankmachine7_refresh_gnt <= 1'd1;
7858                         end
7859                 end
7860                 3'd5: begin
7861                 end
7862                 3'd6: begin
7863                 end
7864                 default: begin
7865                 end
7866         endcase
7867 end
7868 always @(*) begin
7869         litedramcore_bankmachine7_cmd_valid <= 1'd0;
7870         case (litedramcore_bankmachine7_state)
7871                 1'd1: begin
7872                         if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
7873                                 litedramcore_bankmachine7_cmd_valid <= 1'd1;
7874                         end
7875                 end
7876                 2'd2: begin
7877                 end
7878                 2'd3: begin
7879                         if (litedramcore_bankmachine7_trccon_ready) begin
7880                                 litedramcore_bankmachine7_cmd_valid <= 1'd1;
7881                         end
7882                 end
7883                 3'd4: begin
7884                 end
7885                 3'd5: begin
7886                 end
7887                 3'd6: begin
7888                 end
7889                 default: begin
7890                         if (litedramcore_bankmachine7_refresh_req) begin
7891                         end else begin
7892                                 if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
7893                                         if (litedramcore_bankmachine7_row_opened) begin
7894                                                 if (litedramcore_bankmachine7_row_hit) begin
7895                                                         litedramcore_bankmachine7_cmd_valid <= 1'd1;
7896                                                 end else begin
7897                                                 end
7898                                         end else begin
7899                                         end
7900                                 end
7901                         end
7902                 end
7903         endcase
7904 end
7905 assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
7906 assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
7907 assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
7908 assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
7909 assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
7910 assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
7911 assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
7912 assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
7913 assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
7914 assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
7915 assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
7916 assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
7917 assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
7918 assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
7919 assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
7920 assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
7921 assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
7922 assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
7923 assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
7924 assign litedramcore_interface_rdata = {litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
7925 assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
7926 assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
7927 assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
7928 assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
7929 always @(*) begin
7930         litedramcore_choose_cmd_valids <= 8'd0;
7931         litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7932         litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7933         litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7934         litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7935         litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7936         litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7937         litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7938         litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
7939 end
7940 assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
7941 assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
7942 assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
7943 assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
7944 assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
7945 assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
7946 assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
7947 always @(*) begin
7948         litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
7949         if (litedramcore_choose_cmd_cmd_valid) begin
7950                 litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
7951         end
7952 end
7953 always @(*) begin
7954         litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
7955         if (litedramcore_choose_cmd_cmd_valid) begin
7956                 litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
7957         end
7958 end
7959 always @(*) begin
7960         litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
7961         if (litedramcore_choose_cmd_cmd_valid) begin
7962                 litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
7963         end
7964 end
7965 always @(*) begin
7966         litedramcore_bankmachine0_cmd_ready <= 1'd0;
7967         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
7968                 litedramcore_bankmachine0_cmd_ready <= 1'd1;
7969         end
7970         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
7971                 litedramcore_bankmachine0_cmd_ready <= 1'd1;
7972         end
7973 end
7974 always @(*) begin
7975         litedramcore_bankmachine1_cmd_ready <= 1'd0;
7976         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
7977                 litedramcore_bankmachine1_cmd_ready <= 1'd1;
7978         end
7979         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
7980                 litedramcore_bankmachine1_cmd_ready <= 1'd1;
7981         end
7982 end
7983 always @(*) begin
7984         litedramcore_bankmachine2_cmd_ready <= 1'd0;
7985         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
7986                 litedramcore_bankmachine2_cmd_ready <= 1'd1;
7987         end
7988         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
7989                 litedramcore_bankmachine2_cmd_ready <= 1'd1;
7990         end
7991 end
7992 always @(*) begin
7993         litedramcore_bankmachine3_cmd_ready <= 1'd0;
7994         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
7995                 litedramcore_bankmachine3_cmd_ready <= 1'd1;
7996         end
7997         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
7998                 litedramcore_bankmachine3_cmd_ready <= 1'd1;
7999         end
8000 end
8001 always @(*) begin
8002         litedramcore_bankmachine4_cmd_ready <= 1'd0;
8003         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
8004                 litedramcore_bankmachine4_cmd_ready <= 1'd1;
8005         end
8006         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
8007                 litedramcore_bankmachine4_cmd_ready <= 1'd1;
8008         end
8009 end
8010 always @(*) begin
8011         litedramcore_bankmachine5_cmd_ready <= 1'd0;
8012         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
8013                 litedramcore_bankmachine5_cmd_ready <= 1'd1;
8014         end
8015         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
8016                 litedramcore_bankmachine5_cmd_ready <= 1'd1;
8017         end
8018 end
8019 always @(*) begin
8020         litedramcore_bankmachine6_cmd_ready <= 1'd0;
8021         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
8022                 litedramcore_bankmachine6_cmd_ready <= 1'd1;
8023         end
8024         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
8025                 litedramcore_bankmachine6_cmd_ready <= 1'd1;
8026         end
8027 end
8028 always @(*) begin
8029         litedramcore_bankmachine7_cmd_ready <= 1'd0;
8030         if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
8031                 litedramcore_bankmachine7_cmd_ready <= 1'd1;
8032         end
8033         if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
8034                 litedramcore_bankmachine7_cmd_ready <= 1'd1;
8035         end
8036 end
8037 assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
8038 always @(*) begin
8039         litedramcore_choose_req_valids <= 8'd0;
8040         litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8041         litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8042         litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8043         litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8044         litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8045         litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8046         litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8047         litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
8048 end
8049 assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
8050 assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
8051 assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
8052 assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
8053 assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
8054 assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
8055 assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
8056 always @(*) begin
8057         litedramcore_choose_req_cmd_payload_cas <= 1'd0;
8058         if (litedramcore_choose_req_cmd_valid) begin
8059                 litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
8060         end
8061 end
8062 always @(*) begin
8063         litedramcore_choose_req_cmd_payload_ras <= 1'd0;
8064         if (litedramcore_choose_req_cmd_valid) begin
8065                 litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
8066         end
8067 end
8068 always @(*) begin
8069         litedramcore_choose_req_cmd_payload_we <= 1'd0;
8070         if (litedramcore_choose_req_cmd_valid) begin
8071                 litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
8072         end
8073 end
8074 assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
8075 assign litedramcore_dfi_p0_reset_n = 1'd1;
8076 assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
8077 assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
8078 assign litedramcore_dfi_p1_reset_n = 1'd1;
8079 assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
8080 assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
8081 assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]);
8082 always @(*) begin
8083         litedramcore_multiplexer_next_state <= 4'd0;
8084         litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
8085         case (litedramcore_multiplexer_state)
8086                 1'd1: begin
8087                         if (litedramcore_read_available) begin
8088                                 if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
8089                                         litedramcore_multiplexer_next_state <= 2'd3;
8090                                 end
8091                         end
8092                         if (litedramcore_go_to_refresh) begin
8093                                 litedramcore_multiplexer_next_state <= 2'd2;
8094                         end
8095                 end
8096                 2'd2: begin
8097                         if (litedramcore_cmd_last) begin
8098                                 litedramcore_multiplexer_next_state <= 1'd0;
8099                         end
8100                 end
8101                 2'd3: begin
8102                         if (litedramcore_twtrcon_ready) begin
8103                                 litedramcore_multiplexer_next_state <= 1'd0;
8104                         end
8105                 end
8106                 3'd4: begin
8107                         litedramcore_multiplexer_next_state <= 3'd5;
8108                 end
8109                 3'd5: begin
8110                         litedramcore_multiplexer_next_state <= 3'd6;
8111                 end
8112                 3'd6: begin
8113                         litedramcore_multiplexer_next_state <= 3'd7;
8114                 end
8115                 3'd7: begin
8116                         litedramcore_multiplexer_next_state <= 4'd8;
8117                 end
8118                 4'd8: begin
8119                         litedramcore_multiplexer_next_state <= 4'd9;
8120                 end
8121                 4'd9: begin
8122                         litedramcore_multiplexer_next_state <= 4'd10;
8123                 end
8124                 4'd10: begin
8125                         litedramcore_multiplexer_next_state <= 4'd11;
8126                 end
8127                 4'd11: begin
8128                         litedramcore_multiplexer_next_state <= 4'd12;
8129                 end
8130                 4'd12: begin
8131                         litedramcore_multiplexer_next_state <= 4'd13;
8132                 end
8133                 4'd13: begin
8134                         litedramcore_multiplexer_next_state <= 4'd14;
8135                 end
8136                 4'd14: begin
8137                         litedramcore_multiplexer_next_state <= 4'd15;
8138                 end
8139                 4'd15: begin
8140                         litedramcore_multiplexer_next_state <= 1'd1;
8141                 end
8142                 default: begin
8143                         if (litedramcore_write_available) begin
8144                                 if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
8145                                         litedramcore_multiplexer_next_state <= 3'd4;
8146                                 end
8147                         end
8148                         if (litedramcore_go_to_refresh) begin
8149                                 litedramcore_multiplexer_next_state <= 2'd2;
8150                         end
8151                 end
8152         endcase
8153 end
8154 always @(*) begin
8155         litedramcore_choose_req_cmd_ready <= 1'd0;
8156         case (litedramcore_multiplexer_state)
8157                 1'd1: begin
8158                         if (1'd0) begin
8159                                 litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
8160                         end else begin
8161                                 litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
8162                         end
8163                 end
8164                 2'd2: begin
8165                 end
8166                 2'd3: begin
8167                 end
8168                 3'd4: begin
8169                 end
8170                 3'd5: begin
8171                 end
8172                 3'd6: begin
8173                 end
8174                 3'd7: begin
8175                 end
8176                 4'd8: begin
8177                 end
8178                 4'd9: begin
8179                 end
8180                 4'd10: begin
8181                 end
8182                 4'd11: begin
8183                 end
8184                 4'd12: begin
8185                 end
8186                 4'd13: begin
8187                 end
8188                 4'd14: begin
8189                 end
8190                 4'd15: begin
8191                 end
8192                 default: begin
8193                         if (1'd0) begin
8194                                 litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
8195                         end else begin
8196                                 litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
8197                         end
8198                 end
8199         endcase
8200 end
8201 always @(*) begin
8202         litedramcore_en1 <= 1'd0;
8203         case (litedramcore_multiplexer_state)
8204                 1'd1: begin
8205                         litedramcore_en1 <= 1'd1;
8206                 end
8207                 2'd2: begin
8208                 end
8209                 2'd3: begin
8210                 end
8211                 3'd4: begin
8212                 end
8213                 3'd5: begin
8214                 end
8215                 3'd6: begin
8216                 end
8217                 3'd7: begin
8218                 end
8219                 4'd8: begin
8220                 end
8221                 4'd9: begin
8222                 end
8223                 4'd10: begin
8224                 end
8225                 4'd11: begin
8226                 end
8227                 4'd12: begin
8228                 end
8229                 4'd13: begin
8230                 end
8231                 4'd14: begin
8232                 end
8233                 4'd15: begin
8234                 end
8235                 default: begin
8236                 end
8237         endcase
8238 end
8239 always @(*) begin
8240         litedramcore_steerer_sel0 <= 2'd0;
8241         case (litedramcore_multiplexer_state)
8242                 1'd1: begin
8243                         litedramcore_steerer_sel0 <= 1'd0;
8244                         if (1'd0) begin
8245                                 litedramcore_steerer_sel0 <= 2'd2;
8246                         end
8247                         if (1'd1) begin
8248                                 litedramcore_steerer_sel0 <= 1'd1;
8249                         end
8250                 end
8251                 2'd2: begin
8252                         litedramcore_steerer_sel0 <= 2'd3;
8253                 end
8254                 2'd3: begin
8255                 end
8256                 3'd4: begin
8257                 end
8258                 3'd5: begin
8259                 end
8260                 3'd6: begin
8261                 end
8262                 3'd7: begin
8263                 end
8264                 4'd8: begin
8265                 end
8266                 4'd9: begin
8267                 end
8268                 4'd10: begin
8269                 end
8270                 4'd11: begin
8271                 end
8272                 4'd12: begin
8273                 end
8274                 4'd13: begin
8275                 end
8276                 4'd14: begin
8277                 end
8278                 4'd15: begin
8279                 end
8280                 default: begin
8281                         litedramcore_steerer_sel0 <= 1'd0;
8282                         if (1'd1) begin
8283                                 litedramcore_steerer_sel0 <= 2'd2;
8284                         end
8285                         if (1'd0) begin
8286                                 litedramcore_steerer_sel0 <= 1'd1;
8287                         end
8288                 end
8289         endcase
8290 end
8291 always @(*) begin
8292         litedramcore_steerer_sel1 <= 2'd0;
8293         case (litedramcore_multiplexer_state)
8294                 1'd1: begin
8295                         litedramcore_steerer_sel1 <= 1'd0;
8296                         if (1'd1) begin
8297                                 litedramcore_steerer_sel1 <= 2'd2;
8298                         end
8299                         if (1'd0) begin
8300                                 litedramcore_steerer_sel1 <= 1'd1;
8301                         end
8302                 end
8303                 2'd2: begin
8304                 end
8305                 2'd3: begin
8306                 end
8307                 3'd4: begin
8308                 end
8309                 3'd5: begin
8310                 end
8311                 3'd6: begin
8312                 end
8313                 3'd7: begin
8314                 end
8315                 4'd8: begin
8316                 end
8317                 4'd9: begin
8318                 end
8319                 4'd10: begin
8320                 end
8321                 4'd11: begin
8322                 end
8323                 4'd12: begin
8324                 end
8325                 4'd13: begin
8326                 end
8327                 4'd14: begin
8328                 end
8329                 4'd15: begin
8330                 end
8331                 default: begin
8332                         litedramcore_steerer_sel1 <= 1'd0;
8333                         if (1'd0) begin
8334                                 litedramcore_steerer_sel1 <= 2'd2;
8335                         end
8336                         if (1'd1) begin
8337                                 litedramcore_steerer_sel1 <= 1'd1;
8338                         end
8339                 end
8340         endcase
8341 end
8342 always @(*) begin
8343         litedramcore_choose_cmd_want_activates <= 1'd0;
8344         case (litedramcore_multiplexer_state)
8345                 1'd1: begin
8346                         if (1'd0) begin
8347                         end else begin
8348                                 litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
8349                         end
8350                 end
8351                 2'd2: begin
8352                 end
8353                 2'd3: begin
8354                 end
8355                 3'd4: begin
8356                 end
8357                 3'd5: begin
8358                 end
8359                 3'd6: begin
8360                 end
8361                 3'd7: begin
8362                 end
8363                 4'd8: begin
8364                 end
8365                 4'd9: begin
8366                 end
8367                 4'd10: begin
8368                 end
8369                 4'd11: begin
8370                 end
8371                 4'd12: begin
8372                 end
8373                 4'd13: begin
8374                 end
8375                 4'd14: begin
8376                 end
8377                 4'd15: begin
8378                 end
8379                 default: begin
8380                         if (1'd0) begin
8381                         end else begin
8382                                 litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
8383                         end
8384                 end
8385         endcase
8386 end
8387 always @(*) begin
8388         litedramcore_cmd_ready <= 1'd0;
8389         case (litedramcore_multiplexer_state)
8390                 1'd1: begin
8391                 end
8392                 2'd2: begin
8393                         litedramcore_cmd_ready <= 1'd1;
8394                 end
8395                 2'd3: begin
8396                 end
8397                 3'd4: begin
8398                 end
8399                 3'd5: begin
8400                 end
8401                 3'd6: begin
8402                 end
8403                 3'd7: begin
8404                 end
8405                 4'd8: begin
8406                 end
8407                 4'd9: begin
8408                 end
8409                 4'd10: begin
8410                 end
8411                 4'd11: begin
8412                 end
8413                 4'd12: begin
8414                 end
8415                 4'd13: begin
8416                 end
8417                 4'd14: begin
8418                 end
8419                 4'd15: begin
8420                 end
8421                 default: begin
8422                 end
8423         endcase
8424 end
8425 always @(*) begin
8426         litedramcore_choose_cmd_cmd_ready <= 1'd0;
8427         case (litedramcore_multiplexer_state)
8428                 1'd1: begin
8429                         if (1'd0) begin
8430                         end else begin
8431                                 litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
8432                         end
8433                 end
8434                 2'd2: begin
8435                 end
8436                 2'd3: begin
8437                 end
8438                 3'd4: begin
8439                 end
8440                 3'd5: begin
8441                 end
8442                 3'd6: begin
8443                 end
8444                 3'd7: begin
8445                 end
8446                 4'd8: begin
8447                 end
8448                 4'd9: begin
8449                 end
8450                 4'd10: begin
8451                 end
8452                 4'd11: begin
8453                 end
8454                 4'd12: begin
8455                 end
8456                 4'd13: begin
8457                 end
8458                 4'd14: begin
8459                 end
8460                 4'd15: begin
8461                 end
8462                 default: begin
8463                         if (1'd0) begin
8464                         end else begin
8465                                 litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
8466                         end
8467                 end
8468         endcase
8469 end
8470 always @(*) begin
8471         litedramcore_choose_req_want_reads <= 1'd0;
8472         case (litedramcore_multiplexer_state)
8473                 1'd1: begin
8474                 end
8475                 2'd2: begin
8476                 end
8477                 2'd3: begin
8478                 end
8479                 3'd4: begin
8480                 end
8481                 3'd5: begin
8482                 end
8483                 3'd6: begin
8484                 end
8485                 3'd7: begin
8486                 end
8487                 4'd8: begin
8488                 end
8489                 4'd9: begin
8490                 end
8491                 4'd10: begin
8492                 end
8493                 4'd11: begin
8494                 end
8495                 4'd12: begin
8496                 end
8497                 4'd13: begin
8498                 end
8499                 4'd14: begin
8500                 end
8501                 4'd15: begin
8502                 end
8503                 default: begin
8504                         litedramcore_choose_req_want_reads <= 1'd1;
8505                 end
8506         endcase
8507 end
8508 always @(*) begin
8509         litedramcore_choose_req_want_writes <= 1'd0;
8510         case (litedramcore_multiplexer_state)
8511                 1'd1: begin
8512                         litedramcore_choose_req_want_writes <= 1'd1;
8513                 end
8514                 2'd2: begin
8515                 end
8516                 2'd3: begin
8517                 end
8518                 3'd4: begin
8519                 end
8520                 3'd5: begin
8521                 end
8522                 3'd6: begin
8523                 end
8524                 3'd7: begin
8525                 end
8526                 4'd8: begin
8527                 end
8528                 4'd9: begin
8529                 end
8530                 4'd10: begin
8531                 end
8532                 4'd11: begin
8533                 end
8534                 4'd12: begin
8535                 end
8536                 4'd13: begin
8537                 end
8538                 4'd14: begin
8539                 end
8540                 4'd15: begin
8541                 end
8542                 default: begin
8543                 end
8544         endcase
8545 end
8546 always @(*) begin
8547         litedramcore_en0 <= 1'd0;
8548         case (litedramcore_multiplexer_state)
8549                 1'd1: begin
8550                 end
8551                 2'd2: begin
8552                 end
8553                 2'd3: begin
8554                 end
8555                 3'd4: begin
8556                 end
8557                 3'd5: begin
8558                 end
8559                 3'd6: begin
8560                 end
8561                 3'd7: begin
8562                 end
8563                 4'd8: begin
8564                 end
8565                 4'd9: begin
8566                 end
8567                 4'd10: begin
8568                 end
8569                 4'd11: begin
8570                 end
8571                 4'd12: begin
8572                 end
8573                 4'd13: begin
8574                 end
8575                 4'd14: begin
8576                 end
8577                 4'd15: begin
8578                 end
8579                 default: begin
8580                         litedramcore_en0 <= 1'd1;
8581                 end
8582         endcase
8583 end
8584 assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8585 assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
8586 assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
8587 assign litedramcore_interface_bank0_we = rhs_array_muxed13;
8588 assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
8589 assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8590 assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
8591 assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
8592 assign litedramcore_interface_bank1_we = rhs_array_muxed16;
8593 assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
8594 assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8595 assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
8596 assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
8597 assign litedramcore_interface_bank2_we = rhs_array_muxed19;
8598 assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
8599 assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8600 assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
8601 assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
8602 assign litedramcore_interface_bank3_we = rhs_array_muxed22;
8603 assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
8604 assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8605 assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
8606 assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
8607 assign litedramcore_interface_bank4_we = rhs_array_muxed25;
8608 assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
8609 assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8610 assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
8611 assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
8612 assign litedramcore_interface_bank5_we = rhs_array_muxed28;
8613 assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
8614 assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
8615 assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
8616 assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
8617 assign litedramcore_interface_bank6_we = rhs_array_muxed31;
8618 assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
8619 assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
8620 assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
8621 assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
8622 assign litedramcore_interface_bank7_we = rhs_array_muxed34;
8623 assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
8624 assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
8625 assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3;
8626 assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13;
8627 always @(*) begin
8628         litedramcore_interface_wdata <= 256'd0;
8629         case ({litedramcore_new_master_wdata_ready3})
8630                 1'd1: begin
8631                         litedramcore_interface_wdata <= user_port_wdata_payload_data;
8632                 end
8633                 default: begin
8634                         litedramcore_interface_wdata <= 1'd0;
8635                 end
8636         endcase
8637 end
8638 always @(*) begin
8639         litedramcore_interface_wdata_we <= 32'd0;
8640         case ({litedramcore_new_master_wdata_ready3})
8641                 1'd1: begin
8642                         litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
8643                 end
8644                 default: begin
8645                         litedramcore_interface_wdata_we <= 1'd0;
8646                 end
8647         endcase
8648 end
8649 assign user_port_rdata_payload_data = litedramcore_interface_rdata;
8650 assign litedramcore_roundrobin0_grant = 1'd0;
8651 assign litedramcore_roundrobin1_grant = 1'd0;
8652 assign litedramcore_roundrobin2_grant = 1'd0;
8653 assign litedramcore_roundrobin3_grant = 1'd0;
8654 assign litedramcore_roundrobin4_grant = 1'd0;
8655 assign litedramcore_roundrobin5_grant = 1'd0;
8656 assign litedramcore_roundrobin6_grant = 1'd0;
8657 assign litedramcore_roundrobin7_grant = 1'd0;
8658 always @(*) begin
8659         next_state <= 2'd0;
8660         next_state <= state;
8661         case (state)
8662                 1'd1: begin
8663                         next_state <= 2'd2;
8664                 end
8665                 2'd2: begin
8666                         next_state <= 1'd0;
8667                 end
8668                 default: begin
8669                         if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
8670                                 next_state <= 1'd1;
8671                         end
8672                 end
8673         endcase
8674 end
8675 always @(*) begin
8676         litedramcore_dat_w_next_value0 <= 32'd0;
8677         case (state)
8678                 1'd1: begin
8679                 end
8680                 2'd2: begin
8681                 end
8682                 default: begin
8683                         litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
8684                 end
8685         endcase
8686 end
8687 always @(*) begin
8688         litedramcore_wishbone_dat_r <= 32'd0;
8689         case (state)
8690                 1'd1: begin
8691                 end
8692                 2'd2: begin
8693                         litedramcore_wishbone_dat_r <= litedramcore_dat_r;
8694                 end
8695                 default: begin
8696                 end
8697         endcase
8698 end
8699 always @(*) begin
8700         litedramcore_dat_w_next_value_ce0 <= 1'd0;
8701         case (state)
8702                 1'd1: begin
8703                 end
8704                 2'd2: begin
8705                 end
8706                 default: begin
8707                         litedramcore_dat_w_next_value_ce0 <= 1'd1;
8708                 end
8709         endcase
8710 end
8711 always @(*) begin
8712         litedramcore_adr_next_value1 <= 14'd0;
8713         case (state)
8714                 1'd1: begin
8715                         litedramcore_adr_next_value1 <= 1'd0;
8716                 end
8717                 2'd2: begin
8718                 end
8719                 default: begin
8720                         if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
8721                                 litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
8722                         end
8723                 end
8724         endcase
8725 end
8726 always @(*) begin
8727         litedramcore_adr_next_value_ce1 <= 1'd0;
8728         case (state)
8729                 1'd1: begin
8730                         litedramcore_adr_next_value_ce1 <= 1'd1;
8731                 end
8732                 2'd2: begin
8733                 end
8734                 default: begin
8735                         if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
8736                                 litedramcore_adr_next_value_ce1 <= 1'd1;
8737                         end
8738                 end
8739         endcase
8740 end
8741 always @(*) begin
8742         litedramcore_wishbone_ack <= 1'd0;
8743         case (state)
8744                 1'd1: begin
8745                 end
8746                 2'd2: begin
8747                         litedramcore_wishbone_ack <= 1'd1;
8748                 end
8749                 default: begin
8750                 end
8751         endcase
8752 end
8753 always @(*) begin
8754         litedramcore_we_next_value2 <= 1'd0;
8755         case (state)
8756                 1'd1: begin
8757                         litedramcore_we_next_value2 <= 1'd0;
8758                 end
8759                 2'd2: begin
8760                 end
8761                 default: begin
8762                         if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
8763                                 litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
8764                         end
8765                 end
8766         endcase
8767 end
8768 always @(*) begin
8769         litedramcore_we_next_value_ce2 <= 1'd0;
8770         case (state)
8771                 1'd1: begin
8772                         litedramcore_we_next_value_ce2 <= 1'd1;
8773                 end
8774                 2'd2: begin
8775                 end
8776                 default: begin
8777                         if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
8778                                 litedramcore_we_next_value_ce2 <= 1'd1;
8779                         end
8780                 end
8781         endcase
8782 end
8783 assign litedramcore_wishbone_adr = wb_bus_adr;
8784 assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
8785 assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
8786 assign litedramcore_wishbone_sel = wb_bus_sel;
8787 assign litedramcore_wishbone_cyc = wb_bus_cyc;
8788 assign litedramcore_wishbone_stb = wb_bus_stb;
8789 assign wb_bus_ack = litedramcore_wishbone_ack;
8790 assign litedramcore_wishbone_we = wb_bus_we;
8791 assign litedramcore_wishbone_cti = wb_bus_cti;
8792 assign litedramcore_wishbone_bte = wb_bus_bte;
8793 assign wb_bus_err = litedramcore_wishbone_err;
8794 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
8795 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
8796 always @(*) begin
8797         csrbank0_init_done0_we <= 1'd0;
8798         if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
8799                 csrbank0_init_done0_we <= (~interface0_bank_bus_we);
8800         end
8801 end
8802 always @(*) begin
8803         csrbank0_init_done0_re <= 1'd0;
8804         if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
8805                 csrbank0_init_done0_re <= interface0_bank_bus_we;
8806         end
8807 end
8808 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
8809 always @(*) begin
8810         csrbank0_init_error0_re <= 1'd0;
8811         if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
8812                 csrbank0_init_error0_re <= interface0_bank_bus_we;
8813         end
8814 end
8815 always @(*) begin
8816         csrbank0_init_error0_we <= 1'd0;
8817         if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
8818                 csrbank0_init_error0_we <= (~interface0_bank_bus_we);
8819         end
8820 end
8821 assign csrbank0_init_done0_w = init_done_storage;
8822 assign csrbank0_init_error0_w = init_error_storage;
8823 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
8824 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0];
8825 always @(*) begin
8826         csrbank1_dly_sel0_re <= 1'd0;
8827         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
8828                 csrbank1_dly_sel0_re <= interface1_bank_bus_we;
8829         end
8830 end
8831 always @(*) begin
8832         csrbank1_dly_sel0_we <= 1'd0;
8833         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
8834                 csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
8835         end
8836 end
8837 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
8838 always @(*) begin
8839         ddrphy_rdly_dq_rst_we <= 1'd0;
8840         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
8841                 ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
8842         end
8843 end
8844 always @(*) begin
8845         ddrphy_rdly_dq_rst_re <= 1'd0;
8846         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
8847                 ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
8848         end
8849 end
8850 assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
8851 always @(*) begin
8852         ddrphy_rdly_dq_inc_we <= 1'd0;
8853         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
8854                 ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
8855         end
8856 end
8857 always @(*) begin
8858         ddrphy_rdly_dq_inc_re <= 1'd0;
8859         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
8860                 ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
8861         end
8862 end
8863 assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
8864 always @(*) begin
8865         ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
8866         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
8867                 ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
8868         end
8869 end
8870 always @(*) begin
8871         ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
8872         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
8873                 ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
8874         end
8875 end
8876 assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
8877 always @(*) begin
8878         ddrphy_rdly_dq_bitslip_re <= 1'd0;
8879         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
8880                 ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
8881         end
8882 end
8883 always @(*) begin
8884         ddrphy_rdly_dq_bitslip_we <= 1'd0;
8885         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
8886                 ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
8887         end
8888 end
8889 assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0];
8890 always @(*) begin
8891         ddrphy_burstdet_clr_re <= 1'd0;
8892         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
8893                 ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
8894         end
8895 end
8896 always @(*) begin
8897         ddrphy_burstdet_clr_we <= 1'd0;
8898         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
8899                 ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
8900         end
8901 end
8902 assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[3:0];
8903 always @(*) begin
8904         csrbank1_burstdet_seen_re <= 1'd0;
8905         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
8906                 csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
8907         end
8908 end
8909 always @(*) begin
8910         csrbank1_burstdet_seen_we <= 1'd0;
8911         if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
8912                 csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
8913         end
8914 end
8915 assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[3:0];
8916 assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[3:0];
8917 assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
8918 assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
8919 assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
8920 always @(*) begin
8921         csrbank2_dfii_control0_we <= 1'd0;
8922         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
8923                 csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
8924         end
8925 end
8926 always @(*) begin
8927         csrbank2_dfii_control0_re <= 1'd0;
8928         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
8929                 csrbank2_dfii_control0_re <= interface2_bank_bus_we;
8930         end
8931 end
8932 assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
8933 always @(*) begin
8934         csrbank2_dfii_pi0_command0_re <= 1'd0;
8935         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
8936                 csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
8937         end
8938 end
8939 always @(*) begin
8940         csrbank2_dfii_pi0_command0_we <= 1'd0;
8941         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
8942                 csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
8943         end
8944 end
8945 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
8946 always @(*) begin
8947         litedramcore_phaseinjector0_command_issue_re <= 1'd0;
8948         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
8949                 litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
8950         end
8951 end
8952 always @(*) begin
8953         litedramcore_phaseinjector0_command_issue_we <= 1'd0;
8954         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
8955                 litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
8956         end
8957 end
8958 assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
8959 always @(*) begin
8960         csrbank2_dfii_pi0_address0_re <= 1'd0;
8961         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
8962                 csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
8963         end
8964 end
8965 always @(*) begin
8966         csrbank2_dfii_pi0_address0_we <= 1'd0;
8967         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
8968                 csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
8969         end
8970 end
8971 assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
8972 always @(*) begin
8973         csrbank2_dfii_pi0_baddress0_we <= 1'd0;
8974         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
8975                 csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
8976         end
8977 end
8978 always @(*) begin
8979         csrbank2_dfii_pi0_baddress0_re <= 1'd0;
8980         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
8981                 csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
8982         end
8983 end
8984 assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[31:0];
8985 always @(*) begin
8986         csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
8987         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
8988                 csrbank2_dfii_pi0_wrdata3_re <= interface2_bank_bus_we;
8989         end
8990 end
8991 always @(*) begin
8992         csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
8993         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
8994                 csrbank2_dfii_pi0_wrdata3_we <= (~interface2_bank_bus_we);
8995         end
8996 end
8997 assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[31:0];
8998 always @(*) begin
8999         csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
9000         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
9001                 csrbank2_dfii_pi0_wrdata2_we <= (~interface2_bank_bus_we);
9002         end
9003 end
9004 always @(*) begin
9005         csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
9006         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
9007                 csrbank2_dfii_pi0_wrdata2_re <= interface2_bank_bus_we;
9008         end
9009 end
9010 assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
9011 always @(*) begin
9012         csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
9013         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
9014                 csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
9015         end
9016 end
9017 always @(*) begin
9018         csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
9019         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
9020                 csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
9021         end
9022 end
9023 assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
9024 always @(*) begin
9025         csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
9026         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
9027                 csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
9028         end
9029 end
9030 always @(*) begin
9031         csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
9032         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
9033                 csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
9034         end
9035 end
9036 assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[31:0];
9037 always @(*) begin
9038         csrbank2_dfii_pi0_rddata3_we <= 1'd0;
9039         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
9040                 csrbank2_dfii_pi0_rddata3_we <= (~interface2_bank_bus_we);
9041         end
9042 end
9043 always @(*) begin
9044         csrbank2_dfii_pi0_rddata3_re <= 1'd0;
9045         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
9046                 csrbank2_dfii_pi0_rddata3_re <= interface2_bank_bus_we;
9047         end
9048 end
9049 assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[31:0];
9050 always @(*) begin
9051         csrbank2_dfii_pi0_rddata2_we <= 1'd0;
9052         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
9053                 csrbank2_dfii_pi0_rddata2_we <= (~interface2_bank_bus_we);
9054         end
9055 end
9056 always @(*) begin
9057         csrbank2_dfii_pi0_rddata2_re <= 1'd0;
9058         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
9059                 csrbank2_dfii_pi0_rddata2_re <= interface2_bank_bus_we;
9060         end
9061 end
9062 assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
9063 always @(*) begin
9064         csrbank2_dfii_pi0_rddata1_re <= 1'd0;
9065         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
9066                 csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
9067         end
9068 end
9069 always @(*) begin
9070         csrbank2_dfii_pi0_rddata1_we <= 1'd0;
9071         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
9072                 csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
9073         end
9074 end
9075 assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
9076 always @(*) begin
9077         csrbank2_dfii_pi0_rddata0_re <= 1'd0;
9078         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
9079                 csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
9080         end
9081 end
9082 always @(*) begin
9083         csrbank2_dfii_pi0_rddata0_we <= 1'd0;
9084         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
9085                 csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
9086         end
9087 end
9088 assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
9089 always @(*) begin
9090         csrbank2_dfii_pi1_command0_we <= 1'd0;
9091         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
9092                 csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
9093         end
9094 end
9095 always @(*) begin
9096         csrbank2_dfii_pi1_command0_re <= 1'd0;
9097         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
9098                 csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
9099         end
9100 end
9101 assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
9102 always @(*) begin
9103         litedramcore_phaseinjector1_command_issue_we <= 1'd0;
9104         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
9105                 litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
9106         end
9107 end
9108 always @(*) begin
9109         litedramcore_phaseinjector1_command_issue_re <= 1'd0;
9110         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
9111                 litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
9112         end
9113 end
9114 assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
9115 always @(*) begin
9116         csrbank2_dfii_pi1_address0_re <= 1'd0;
9117         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
9118                 csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
9119         end
9120 end
9121 always @(*) begin
9122         csrbank2_dfii_pi1_address0_we <= 1'd0;
9123         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
9124                 csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
9125         end
9126 end
9127 assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
9128 always @(*) begin
9129         csrbank2_dfii_pi1_baddress0_re <= 1'd0;
9130         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
9131                 csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
9132         end
9133 end
9134 always @(*) begin
9135         csrbank2_dfii_pi1_baddress0_we <= 1'd0;
9136         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
9137                 csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
9138         end
9139 end
9140 assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[31:0];
9141 always @(*) begin
9142         csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
9143         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
9144                 csrbank2_dfii_pi1_wrdata3_we <= (~interface2_bank_bus_we);
9145         end
9146 end
9147 always @(*) begin
9148         csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
9149         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
9150                 csrbank2_dfii_pi1_wrdata3_re <= interface2_bank_bus_we;
9151         end
9152 end
9153 assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[31:0];
9154 always @(*) begin
9155         csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
9156         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
9157                 csrbank2_dfii_pi1_wrdata2_re <= interface2_bank_bus_we;
9158         end
9159 end
9160 always @(*) begin
9161         csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
9162         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
9163                 csrbank2_dfii_pi1_wrdata2_we <= (~interface2_bank_bus_we);
9164         end
9165 end
9166 assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
9167 always @(*) begin
9168         csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
9169         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
9170                 csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
9171         end
9172 end
9173 always @(*) begin
9174         csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
9175         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
9176                 csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
9177         end
9178 end
9179 assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
9180 always @(*) begin
9181         csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
9182         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
9183                 csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
9184         end
9185 end
9186 always @(*) begin
9187         csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
9188         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
9189                 csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
9190         end
9191 end
9192 assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[31:0];
9193 always @(*) begin
9194         csrbank2_dfii_pi1_rddata3_re <= 1'd0;
9195         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
9196                 csrbank2_dfii_pi1_rddata3_re <= interface2_bank_bus_we;
9197         end
9198 end
9199 always @(*) begin
9200         csrbank2_dfii_pi1_rddata3_we <= 1'd0;
9201         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
9202                 csrbank2_dfii_pi1_rddata3_we <= (~interface2_bank_bus_we);
9203         end
9204 end
9205 assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[31:0];
9206 always @(*) begin
9207         csrbank2_dfii_pi1_rddata2_we <= 1'd0;
9208         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
9209                 csrbank2_dfii_pi1_rddata2_we <= (~interface2_bank_bus_we);
9210         end
9211 end
9212 always @(*) begin
9213         csrbank2_dfii_pi1_rddata2_re <= 1'd0;
9214         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
9215                 csrbank2_dfii_pi1_rddata2_re <= interface2_bank_bus_we;
9216         end
9217 end
9218 assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
9219 always @(*) begin
9220         csrbank2_dfii_pi1_rddata1_we <= 1'd0;
9221         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
9222                 csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
9223         end
9224 end
9225 always @(*) begin
9226         csrbank2_dfii_pi1_rddata1_re <= 1'd0;
9227         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
9228                 csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
9229         end
9230 end
9231 assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
9232 always @(*) begin
9233         csrbank2_dfii_pi1_rddata0_re <= 1'd0;
9234         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
9235                 csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
9236         end
9237 end
9238 always @(*) begin
9239         csrbank2_dfii_pi1_rddata0_we <= 1'd0;
9240         if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
9241                 csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
9242         end
9243 end
9244 assign litedramcore_sel = litedramcore_storage[0];
9245 assign litedramcore_cke = litedramcore_storage[1];
9246 assign litedramcore_odt = litedramcore_storage[2];
9247 assign litedramcore_reset_n = litedramcore_storage[3];
9248 assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
9249 assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
9250 assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
9251 assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
9252 assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[127:96];
9253 assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[95:64];
9254 assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
9255 assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
9256 assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_rddata_status[127:96];
9257 assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_rddata_status[95:64];
9258 assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
9259 assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0];
9260 assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we;
9261 assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
9262 assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
9263 assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
9264 assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[127:96];
9265 assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[95:64];
9266 assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
9267 assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
9268 assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_rddata_status[127:96];
9269 assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_rddata_status[95:64];
9270 assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
9271 assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
9272 assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
9273 assign csr_interconnect_adr = litedramcore_adr;
9274 assign csr_interconnect_we = litedramcore_we;
9275 assign csr_interconnect_dat_w = litedramcore_dat_w;
9276 assign litedramcore_dat_r = csr_interconnect_dat_r;
9277 assign interface0_bank_bus_adr = csr_interconnect_adr;
9278 assign interface1_bank_bus_adr = csr_interconnect_adr;
9279 assign interface2_bank_bus_adr = csr_interconnect_adr;
9280 assign interface0_bank_bus_we = csr_interconnect_we;
9281 assign interface1_bank_bus_we = csr_interconnect_we;
9282 assign interface2_bank_bus_we = csr_interconnect_we;
9283 assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
9284 assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
9285 assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
9286 assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
9287 always @(*) begin
9288         rhs_array_muxed0 <= 1'd0;
9289         case (litedramcore_choose_cmd_grant)
9290                 1'd0: begin
9291                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
9292                 end
9293                 1'd1: begin
9294                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
9295                 end
9296                 2'd2: begin
9297                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
9298                 end
9299                 2'd3: begin
9300                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
9301                 end
9302                 3'd4: begin
9303                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
9304                 end
9305                 3'd5: begin
9306                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
9307                 end
9308                 3'd6: begin
9309                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
9310                 end
9311                 default: begin
9312                         rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
9313                 end
9314         endcase
9315 end
9316 always @(*) begin
9317         rhs_array_muxed1 <= 15'd0;
9318         case (litedramcore_choose_cmd_grant)
9319                 1'd0: begin
9320                         rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
9321                 end
9322                 1'd1: begin
9323                         rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
9324                 end
9325                 2'd2: begin
9326                         rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
9327                 end
9328                 2'd3: begin
9329                         rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
9330                 end
9331                 3'd4: begin
9332                         rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
9333                 end
9334                 3'd5: begin
9335                         rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
9336                 end
9337                 3'd6: begin
9338                         rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
9339                 end
9340                 default: begin
9341                         rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
9342                 end
9343         endcase
9344 end
9345 always @(*) begin
9346         rhs_array_muxed2 <= 3'd0;
9347         case (litedramcore_choose_cmd_grant)
9348                 1'd0: begin
9349                         rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
9350                 end
9351                 1'd1: begin
9352                         rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
9353                 end
9354                 2'd2: begin
9355                         rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
9356                 end
9357                 2'd3: begin
9358                         rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
9359                 end
9360                 3'd4: begin
9361                         rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
9362                 end
9363                 3'd5: begin
9364                         rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
9365                 end
9366                 3'd6: begin
9367                         rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
9368                 end
9369                 default: begin
9370                         rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
9371                 end
9372         endcase
9373 end
9374 always @(*) begin
9375         rhs_array_muxed3 <= 1'd0;
9376         case (litedramcore_choose_cmd_grant)
9377                 1'd0: begin
9378                         rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
9379                 end
9380                 1'd1: begin
9381                         rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
9382                 end
9383                 2'd2: begin
9384                         rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
9385                 end
9386                 2'd3: begin
9387                         rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
9388                 end
9389                 3'd4: begin
9390                         rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
9391                 end
9392                 3'd5: begin
9393                         rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
9394                 end
9395                 3'd6: begin
9396                         rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
9397                 end
9398                 default: begin
9399                         rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
9400                 end
9401         endcase
9402 end
9403 always @(*) begin
9404         rhs_array_muxed4 <= 1'd0;
9405         case (litedramcore_choose_cmd_grant)
9406                 1'd0: begin
9407                         rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
9408                 end
9409                 1'd1: begin
9410                         rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
9411                 end
9412                 2'd2: begin
9413                         rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
9414                 end
9415                 2'd3: begin
9416                         rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
9417                 end
9418                 3'd4: begin
9419                         rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
9420                 end
9421                 3'd5: begin
9422                         rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
9423                 end
9424                 3'd6: begin
9425                         rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
9426                 end
9427                 default: begin
9428                         rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
9429                 end
9430         endcase
9431 end
9432 always @(*) begin
9433         rhs_array_muxed5 <= 1'd0;
9434         case (litedramcore_choose_cmd_grant)
9435                 1'd0: begin
9436                         rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
9437                 end
9438                 1'd1: begin
9439                         rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
9440                 end
9441                 2'd2: begin
9442                         rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
9443                 end
9444                 2'd3: begin
9445                         rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
9446                 end
9447                 3'd4: begin
9448                         rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
9449                 end
9450                 3'd5: begin
9451                         rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
9452                 end
9453                 3'd6: begin
9454                         rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
9455                 end
9456                 default: begin
9457                         rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
9458                 end
9459         endcase
9460 end
9461 always @(*) begin
9462         t_array_muxed0 <= 1'd0;
9463         case (litedramcore_choose_cmd_grant)
9464                 1'd0: begin
9465                         t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
9466                 end
9467                 1'd1: begin
9468                         t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
9469                 end
9470                 2'd2: begin
9471                         t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
9472                 end
9473                 2'd3: begin
9474                         t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
9475                 end
9476                 3'd4: begin
9477                         t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
9478                 end
9479                 3'd5: begin
9480                         t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
9481                 end
9482                 3'd6: begin
9483                         t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
9484                 end
9485                 default: begin
9486                         t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
9487                 end
9488         endcase
9489 end
9490 always @(*) begin
9491         t_array_muxed1 <= 1'd0;
9492         case (litedramcore_choose_cmd_grant)
9493                 1'd0: begin
9494                         t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
9495                 end
9496                 1'd1: begin
9497                         t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
9498                 end
9499                 2'd2: begin
9500                         t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
9501                 end
9502                 2'd3: begin
9503                         t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
9504                 end
9505                 3'd4: begin
9506                         t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
9507                 end
9508                 3'd5: begin
9509                         t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
9510                 end
9511                 3'd6: begin
9512                         t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
9513                 end
9514                 default: begin
9515                         t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
9516                 end
9517         endcase
9518 end
9519 always @(*) begin
9520         t_array_muxed2 <= 1'd0;
9521         case (litedramcore_choose_cmd_grant)
9522                 1'd0: begin
9523                         t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
9524                 end
9525                 1'd1: begin
9526                         t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
9527                 end
9528                 2'd2: begin
9529                         t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
9530                 end
9531                 2'd3: begin
9532                         t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
9533                 end
9534                 3'd4: begin
9535                         t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
9536                 end
9537                 3'd5: begin
9538                         t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
9539                 end
9540                 3'd6: begin
9541                         t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
9542                 end
9543                 default: begin
9544                         t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
9545                 end
9546         endcase
9547 end
9548 always @(*) begin
9549         rhs_array_muxed6 <= 1'd0;
9550         case (litedramcore_choose_req_grant)
9551                 1'd0: begin
9552                         rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
9553                 end
9554                 1'd1: begin
9555                         rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
9556                 end
9557                 2'd2: begin
9558                         rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
9559                 end
9560                 2'd3: begin
9561                         rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
9562                 end
9563                 3'd4: begin
9564                         rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
9565                 end
9566                 3'd5: begin
9567                         rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
9568                 end
9569                 3'd6: begin
9570                         rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
9571                 end
9572                 default: begin
9573                         rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
9574                 end
9575         endcase
9576 end
9577 always @(*) begin
9578         rhs_array_muxed7 <= 15'd0;
9579         case (litedramcore_choose_req_grant)
9580                 1'd0: begin
9581                         rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
9582                 end
9583                 1'd1: begin
9584                         rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
9585                 end
9586                 2'd2: begin
9587                         rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
9588                 end
9589                 2'd3: begin
9590                         rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
9591                 end
9592                 3'd4: begin
9593                         rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
9594                 end
9595                 3'd5: begin
9596                         rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
9597                 end
9598                 3'd6: begin
9599                         rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
9600                 end
9601                 default: begin
9602                         rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
9603                 end
9604         endcase
9605 end
9606 always @(*) begin
9607         rhs_array_muxed8 <= 3'd0;
9608         case (litedramcore_choose_req_grant)
9609                 1'd0: begin
9610                         rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
9611                 end
9612                 1'd1: begin
9613                         rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
9614                 end
9615                 2'd2: begin
9616                         rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
9617                 end
9618                 2'd3: begin
9619                         rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
9620                 end
9621                 3'd4: begin
9622                         rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
9623                 end
9624                 3'd5: begin
9625                         rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
9626                 end
9627                 3'd6: begin
9628                         rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
9629                 end
9630                 default: begin
9631                         rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
9632                 end
9633         endcase
9634 end
9635 always @(*) begin
9636         rhs_array_muxed9 <= 1'd0;
9637         case (litedramcore_choose_req_grant)
9638                 1'd0: begin
9639                         rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
9640                 end
9641                 1'd1: begin
9642                         rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
9643                 end
9644                 2'd2: begin
9645                         rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
9646                 end
9647                 2'd3: begin
9648                         rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
9649                 end
9650                 3'd4: begin
9651                         rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
9652                 end
9653                 3'd5: begin
9654                         rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
9655                 end
9656                 3'd6: begin
9657                         rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
9658                 end
9659                 default: begin
9660                         rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
9661                 end
9662         endcase
9663 end
9664 always @(*) begin
9665         rhs_array_muxed10 <= 1'd0;
9666         case (litedramcore_choose_req_grant)
9667                 1'd0: begin
9668                         rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
9669                 end
9670                 1'd1: begin
9671                         rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
9672                 end
9673                 2'd2: begin
9674                         rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
9675                 end
9676                 2'd3: begin
9677                         rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
9678                 end
9679                 3'd4: begin
9680                         rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
9681                 end
9682                 3'd5: begin
9683                         rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
9684                 end
9685                 3'd6: begin
9686                         rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
9687                 end
9688                 default: begin
9689                         rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
9690                 end
9691         endcase
9692 end
9693 always @(*) begin
9694         rhs_array_muxed11 <= 1'd0;
9695         case (litedramcore_choose_req_grant)
9696                 1'd0: begin
9697                         rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
9698                 end
9699                 1'd1: begin
9700                         rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
9701                 end
9702                 2'd2: begin
9703                         rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
9704                 end
9705                 2'd3: begin
9706                         rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
9707                 end
9708                 3'd4: begin
9709                         rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
9710                 end
9711                 3'd5: begin
9712                         rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
9713                 end
9714                 3'd6: begin
9715                         rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
9716                 end
9717                 default: begin
9718                         rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
9719                 end
9720         endcase
9721 end
9722 always @(*) begin
9723         t_array_muxed3 <= 1'd0;
9724         case (litedramcore_choose_req_grant)
9725                 1'd0: begin
9726                         t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
9727                 end
9728                 1'd1: begin
9729                         t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
9730                 end
9731                 2'd2: begin
9732                         t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
9733                 end
9734                 2'd3: begin
9735                         t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
9736                 end
9737                 3'd4: begin
9738                         t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
9739                 end
9740                 3'd5: begin
9741                         t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
9742                 end
9743                 3'd6: begin
9744                         t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
9745                 end
9746                 default: begin
9747                         t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
9748                 end
9749         endcase
9750 end
9751 always @(*) begin
9752         t_array_muxed4 <= 1'd0;
9753         case (litedramcore_choose_req_grant)
9754                 1'd0: begin
9755                         t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
9756                 end
9757                 1'd1: begin
9758                         t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
9759                 end
9760                 2'd2: begin
9761                         t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
9762                 end
9763                 2'd3: begin
9764                         t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
9765                 end
9766                 3'd4: begin
9767                         t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
9768                 end
9769                 3'd5: begin
9770                         t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
9771                 end
9772                 3'd6: begin
9773                         t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
9774                 end
9775                 default: begin
9776                         t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
9777                 end
9778         endcase
9779 end
9780 always @(*) begin
9781         t_array_muxed5 <= 1'd0;
9782         case (litedramcore_choose_req_grant)
9783                 1'd0: begin
9784                         t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
9785                 end
9786                 1'd1: begin
9787                         t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
9788                 end
9789                 2'd2: begin
9790                         t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
9791                 end
9792                 2'd3: begin
9793                         t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
9794                 end
9795                 3'd4: begin
9796                         t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
9797                 end
9798                 3'd5: begin
9799                         t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
9800                 end
9801                 3'd6: begin
9802                         t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
9803                 end
9804                 default: begin
9805                         t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
9806                 end
9807         endcase
9808 end
9809 always @(*) begin
9810         rhs_array_muxed12 <= 22'd0;
9811         case (litedramcore_roundrobin0_grant)
9812                 default: begin
9813                         rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9814                 end
9815         endcase
9816 end
9817 always @(*) begin
9818         rhs_array_muxed13 <= 1'd0;
9819         case (litedramcore_roundrobin0_grant)
9820                 default: begin
9821                         rhs_array_muxed13 <= user_port_cmd_payload_we;
9822                 end
9823         endcase
9824 end
9825 always @(*) begin
9826         rhs_array_muxed14 <= 1'd0;
9827         case (litedramcore_roundrobin0_grant)
9828                 default: begin
9829                         rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9830                 end
9831         endcase
9832 end
9833 always @(*) begin
9834         rhs_array_muxed15 <= 22'd0;
9835         case (litedramcore_roundrobin1_grant)
9836                 default: begin
9837                         rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9838                 end
9839         endcase
9840 end
9841 always @(*) begin
9842         rhs_array_muxed16 <= 1'd0;
9843         case (litedramcore_roundrobin1_grant)
9844                 default: begin
9845                         rhs_array_muxed16 <= user_port_cmd_payload_we;
9846                 end
9847         endcase
9848 end
9849 always @(*) begin
9850         rhs_array_muxed17 <= 1'd0;
9851         case (litedramcore_roundrobin1_grant)
9852                 default: begin
9853                         rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9854                 end
9855         endcase
9856 end
9857 always @(*) begin
9858         rhs_array_muxed18 <= 22'd0;
9859         case (litedramcore_roundrobin2_grant)
9860                 default: begin
9861                         rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9862                 end
9863         endcase
9864 end
9865 always @(*) begin
9866         rhs_array_muxed19 <= 1'd0;
9867         case (litedramcore_roundrobin2_grant)
9868                 default: begin
9869                         rhs_array_muxed19 <= user_port_cmd_payload_we;
9870                 end
9871         endcase
9872 end
9873 always @(*) begin
9874         rhs_array_muxed20 <= 1'd0;
9875         case (litedramcore_roundrobin2_grant)
9876                 default: begin
9877                         rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9878                 end
9879         endcase
9880 end
9881 always @(*) begin
9882         rhs_array_muxed21 <= 22'd0;
9883         case (litedramcore_roundrobin3_grant)
9884                 default: begin
9885                         rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9886                 end
9887         endcase
9888 end
9889 always @(*) begin
9890         rhs_array_muxed22 <= 1'd0;
9891         case (litedramcore_roundrobin3_grant)
9892                 default: begin
9893                         rhs_array_muxed22 <= user_port_cmd_payload_we;
9894                 end
9895         endcase
9896 end
9897 always @(*) begin
9898         rhs_array_muxed23 <= 1'd0;
9899         case (litedramcore_roundrobin3_grant)
9900                 default: begin
9901                         rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9902                 end
9903         endcase
9904 end
9905 always @(*) begin
9906         rhs_array_muxed24 <= 22'd0;
9907         case (litedramcore_roundrobin4_grant)
9908                 default: begin
9909                         rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9910                 end
9911         endcase
9912 end
9913 always @(*) begin
9914         rhs_array_muxed25 <= 1'd0;
9915         case (litedramcore_roundrobin4_grant)
9916                 default: begin
9917                         rhs_array_muxed25 <= user_port_cmd_payload_we;
9918                 end
9919         endcase
9920 end
9921 always @(*) begin
9922         rhs_array_muxed26 <= 1'd0;
9923         case (litedramcore_roundrobin4_grant)
9924                 default: begin
9925                         rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9926                 end
9927         endcase
9928 end
9929 always @(*) begin
9930         rhs_array_muxed27 <= 22'd0;
9931         case (litedramcore_roundrobin5_grant)
9932                 default: begin
9933                         rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9934                 end
9935         endcase
9936 end
9937 always @(*) begin
9938         rhs_array_muxed28 <= 1'd0;
9939         case (litedramcore_roundrobin5_grant)
9940                 default: begin
9941                         rhs_array_muxed28 <= user_port_cmd_payload_we;
9942                 end
9943         endcase
9944 end
9945 always @(*) begin
9946         rhs_array_muxed29 <= 1'd0;
9947         case (litedramcore_roundrobin5_grant)
9948                 default: begin
9949                         rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9950                 end
9951         endcase
9952 end
9953 always @(*) begin
9954         rhs_array_muxed30 <= 22'd0;
9955         case (litedramcore_roundrobin6_grant)
9956                 default: begin
9957                         rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9958                 end
9959         endcase
9960 end
9961 always @(*) begin
9962         rhs_array_muxed31 <= 1'd0;
9963         case (litedramcore_roundrobin6_grant)
9964                 default: begin
9965                         rhs_array_muxed31 <= user_port_cmd_payload_we;
9966                 end
9967         endcase
9968 end
9969 always @(*) begin
9970         rhs_array_muxed32 <= 1'd0;
9971         case (litedramcore_roundrobin6_grant)
9972                 default: begin
9973                         rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
9974                 end
9975         endcase
9976 end
9977 always @(*) begin
9978         rhs_array_muxed33 <= 22'd0;
9979         case (litedramcore_roundrobin7_grant)
9980                 default: begin
9981                         rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
9982                 end
9983         endcase
9984 end
9985 always @(*) begin
9986         rhs_array_muxed34 <= 1'd0;
9987         case (litedramcore_roundrobin7_grant)
9988                 default: begin
9989                         rhs_array_muxed34 <= user_port_cmd_payload_we;
9990                 end
9991         endcase
9992 end
9993 always @(*) begin
9994         rhs_array_muxed35 <= 1'd0;
9995         case (litedramcore_roundrobin7_grant)
9996                 default: begin
9997                         rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
9998                 end
9999         endcase
10000 end
10001 always @(*) begin
10002         array_muxed0 <= 3'd0;
10003         case (litedramcore_steerer_sel0)
10004                 1'd0: begin
10005                         array_muxed0 <= litedramcore_nop_ba[2:0];
10006                 end
10007                 1'd1: begin
10008                         array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
10009                 end
10010                 2'd2: begin
10011                         array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
10012                 end
10013                 default: begin
10014                         array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
10015                 end
10016         endcase
10017 end
10018 always @(*) begin
10019         array_muxed1 <= 15'd0;
10020         case (litedramcore_steerer_sel0)
10021                 1'd0: begin
10022                         array_muxed1 <= litedramcore_nop_a;
10023                 end
10024                 1'd1: begin
10025                         array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
10026                 end
10027                 2'd2: begin
10028                         array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
10029                 end
10030                 default: begin
10031                         array_muxed1 <= litedramcore_cmd_payload_a;
10032                 end
10033         endcase
10034 end
10035 always @(*) begin
10036         array_muxed2 <= 1'd0;
10037         case (litedramcore_steerer_sel0)
10038                 1'd0: begin
10039                         array_muxed2 <= 1'd0;
10040                 end
10041                 1'd1: begin
10042                         array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
10043                 end
10044                 2'd2: begin
10045                         array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
10046                 end
10047                 default: begin
10048                         array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
10049                 end
10050         endcase
10051 end
10052 always @(*) begin
10053         array_muxed3 <= 1'd0;
10054         case (litedramcore_steerer_sel0)
10055                 1'd0: begin
10056                         array_muxed3 <= 1'd0;
10057                 end
10058                 1'd1: begin
10059                         array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
10060                 end
10061                 2'd2: begin
10062                         array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
10063                 end
10064                 default: begin
10065                         array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
10066                 end
10067         endcase
10068 end
10069 always @(*) begin
10070         array_muxed4 <= 1'd0;
10071         case (litedramcore_steerer_sel0)
10072                 1'd0: begin
10073                         array_muxed4 <= 1'd0;
10074                 end
10075                 1'd1: begin
10076                         array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
10077                 end
10078                 2'd2: begin
10079                         array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
10080                 end
10081                 default: begin
10082                         array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
10083                 end
10084         endcase
10085 end
10086 always @(*) begin
10087         array_muxed5 <= 1'd0;
10088         case (litedramcore_steerer_sel0)
10089                 1'd0: begin
10090                         array_muxed5 <= 1'd0;
10091                 end
10092                 1'd1: begin
10093                         array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
10094                 end
10095                 2'd2: begin
10096                         array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
10097                 end
10098                 default: begin
10099                         array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
10100                 end
10101         endcase
10102 end
10103 always @(*) begin
10104         array_muxed6 <= 1'd0;
10105         case (litedramcore_steerer_sel0)
10106                 1'd0: begin
10107                         array_muxed6 <= 1'd0;
10108                 end
10109                 1'd1: begin
10110                         array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
10111                 end
10112                 2'd2: begin
10113                         array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
10114                 end
10115                 default: begin
10116                         array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
10117                 end
10118         endcase
10119 end
10120 always @(*) begin
10121         array_muxed7 <= 3'd0;
10122         case (litedramcore_steerer_sel1)
10123                 1'd0: begin
10124                         array_muxed7 <= litedramcore_nop_ba[2:0];
10125                 end
10126                 1'd1: begin
10127                         array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
10128                 end
10129                 2'd2: begin
10130                         array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
10131                 end
10132                 default: begin
10133                         array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
10134                 end
10135         endcase
10136 end
10137 always @(*) begin
10138         array_muxed8 <= 15'd0;
10139         case (litedramcore_steerer_sel1)
10140                 1'd0: begin
10141                         array_muxed8 <= litedramcore_nop_a;
10142                 end
10143                 1'd1: begin
10144                         array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
10145                 end
10146                 2'd2: begin
10147                         array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
10148                 end
10149                 default: begin
10150                         array_muxed8 <= litedramcore_cmd_payload_a;
10151                 end
10152         endcase
10153 end
10154 always @(*) begin
10155         array_muxed9 <= 1'd0;
10156         case (litedramcore_steerer_sel1)
10157                 1'd0: begin
10158                         array_muxed9 <= 1'd0;
10159                 end
10160                 1'd1: begin
10161                         array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
10162                 end
10163                 2'd2: begin
10164                         array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
10165                 end
10166                 default: begin
10167                         array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
10168                 end
10169         endcase
10170 end
10171 always @(*) begin
10172         array_muxed10 <= 1'd0;
10173         case (litedramcore_steerer_sel1)
10174                 1'd0: begin
10175                         array_muxed10 <= 1'd0;
10176                 end
10177                 1'd1: begin
10178                         array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
10179                 end
10180                 2'd2: begin
10181                         array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
10182                 end
10183                 default: begin
10184                         array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
10185                 end
10186         endcase
10187 end
10188 always @(*) begin
10189         array_muxed11 <= 1'd0;
10190         case (litedramcore_steerer_sel1)
10191                 1'd0: begin
10192                         array_muxed11 <= 1'd0;
10193                 end
10194                 1'd1: begin
10195                         array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
10196                 end
10197                 2'd2: begin
10198                         array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
10199                 end
10200                 default: begin
10201                         array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
10202                 end
10203         endcase
10204 end
10205 always @(*) begin
10206         array_muxed12 <= 1'd0;
10207         case (litedramcore_steerer_sel1)
10208                 1'd0: begin
10209                         array_muxed12 <= 1'd0;
10210                 end
10211                 1'd1: begin
10212                         array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
10213                 end
10214                 2'd2: begin
10215                         array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
10216                 end
10217                 default: begin
10218                         array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
10219                 end
10220         endcase
10221 end
10222 always @(*) begin
10223         array_muxed13 <= 1'd0;
10224         case (litedramcore_steerer_sel1)
10225                 1'd0: begin
10226                         array_muxed13 <= 1'd0;
10227                 end
10228                 1'd1: begin
10229                         array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
10230                 end
10231                 2'd2: begin
10232                         array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
10233                 end
10234                 default: begin
10235                         array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
10236                 end
10237         endcase
10238 end
10239 assign ddrphy_lock1 = regs1;
10240
10241
10242 //------------------------------------------------------------------------------
10243 // Synchronous Logic
10244 //------------------------------------------------------------------------------
10245
10246 always @(posedge init_clk) begin
10247         ddrphy_lock_d <= ddrphy_lock1;
10248         if ((ddrphy_counter == 4'd8)) begin
10249                 ddrphy_freeze <= 1'd1;
10250         end
10251         if ((ddrphy_counter == 5'd16)) begin
10252                 ddrphy_stop1 <= 1'd1;
10253         end
10254         if ((ddrphy_counter == 5'd24)) begin
10255                 ddrphy_reset1 <= 1'd1;
10256         end
10257         if ((ddrphy_counter == 6'd32)) begin
10258                 ddrphy_reset1 <= 1'd0;
10259         end
10260         if ((ddrphy_counter == 6'd40)) begin
10261                 ddrphy_stop1 <= 1'd0;
10262         end
10263         if ((ddrphy_counter == 6'd48)) begin
10264                 ddrphy_freeze <= 1'd0;
10265         end
10266         if ((ddrphy_counter == 6'd56)) begin
10267                 ddrphy_pause1 <= 1'd1;
10268         end
10269         if ((ddrphy_counter == 7'd64)) begin
10270                 ddrphy_update <= 1'd1;
10271         end
10272         if ((ddrphy_counter == 7'd72)) begin
10273                 ddrphy_update <= 1'd0;
10274         end
10275         if ((ddrphy_counter == 7'd80)) begin
10276                 ddrphy_pause1 <= 1'd0;
10277         end
10278         if ((ddrphy_counter == 7'd80)) begin
10279                 ddrphy_counter <= 1'd0;
10280         end else begin
10281                 if ((ddrphy_counter != 1'd0)) begin
10282                         ddrphy_counter <= (ddrphy_counter + 1'd1);
10283                 end else begin
10284                         if (ddrphy_new_lock) begin
10285                                 ddrphy_counter <= 1'd1;
10286                         end
10287                 end
10288         end
10289         if (init_rst) begin
10290                 ddrphy_update <= 1'd0;
10291                 ddrphy_stop1 <= 1'd0;
10292                 ddrphy_freeze <= 1'd0;
10293                 ddrphy_pause1 <= 1'd0;
10294                 ddrphy_reset1 <= 1'd0;
10295                 ddrphy_lock_d <= 1'd0;
10296                 ddrphy_counter <= 7'd0;
10297         end
10298         regs0 <= ddrphy_lock0;
10299         regs1 <= regs0;
10300 end
10301
10302 always @(posedge por_clk) begin
10303         if ((~crg_por_done)) begin
10304                 crg_por_count <= (crg_por_count - 1'd1);
10305         end
10306 end
10307
10308 always @(posedge sys_clk) begin
10309         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin
10310                 ddrphy_rdly0 <= 1'd0;
10311         end
10312         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin
10313                 ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1);
10314         end
10315         ddrphy_burstdet_d0 <= ddrphy_burstdet0;
10316         if (ddrphy_burstdet_clr_re) begin
10317                 ddrphy_burstdet_seen_status[0] <= 1'd0;
10318         end
10319         if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin
10320                 ddrphy_burstdet_seen_status[0] <= 1'd1;
10321         end
10322         ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0;
10323         case (ddrphy_bl8_chunk)
10324                 1'd0: begin
10325                         ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0];
10326                 end
10327                 1'd1: begin
10328                         ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4];
10329                 end
10330         endcase
10331         ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0;
10332         case (ddrphy_bl8_chunk)
10333                 1'd0: begin
10334                         ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0];
10335                 end
10336                 1'd1: begin
10337                         ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4];
10338                 end
10339         endcase
10340         ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o;
10341         ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1;
10342         case (ddrphy_bl8_chunk)
10343                 1'd0: begin
10344                         ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0];
10345                 end
10346                 1'd1: begin
10347                         ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4];
10348                 end
10349         endcase
10350         ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o;
10351         ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2;
10352         case (ddrphy_bl8_chunk)
10353                 1'd0: begin
10354                         ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0];
10355                 end
10356                 1'd1: begin
10357                         ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4];
10358                 end
10359         endcase
10360         ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o;
10361         ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3;
10362         case (ddrphy_bl8_chunk)
10363                 1'd0: begin
10364                         ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0];
10365                 end
10366                 1'd1: begin
10367                         ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4];
10368                 end
10369         endcase
10370         ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o;
10371         ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4;
10372         case (ddrphy_bl8_chunk)
10373                 1'd0: begin
10374                         ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0];
10375                 end
10376                 1'd1: begin
10377                         ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4];
10378                 end
10379         endcase
10380         ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o;
10381         ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5;
10382         case (ddrphy_bl8_chunk)
10383                 1'd0: begin
10384                         ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0];
10385                 end
10386                 1'd1: begin
10387                         ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4];
10388                 end
10389         endcase
10390         ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o;
10391         ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6;
10392         case (ddrphy_bl8_chunk)
10393                 1'd0: begin
10394                         ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0];
10395                 end
10396                 1'd1: begin
10397                         ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4];
10398                 end
10399         endcase
10400         ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o;
10401         ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7;
10402         case (ddrphy_bl8_chunk)
10403                 1'd0: begin
10404                         ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0];
10405                 end
10406                 1'd1: begin
10407                         ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4];
10408                 end
10409         endcase
10410         ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o;
10411         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin
10412                 ddrphy_rdly1 <= 1'd0;
10413         end
10414         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin
10415                 ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1);
10416         end
10417         ddrphy_burstdet_d1 <= ddrphy_burstdet1;
10418         if (ddrphy_burstdet_clr_re) begin
10419                 ddrphy_burstdet_seen_status[1] <= 1'd0;
10420         end
10421         if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin
10422                 ddrphy_burstdet_seen_status[1] <= 1'd1;
10423         end
10424         ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1;
10425         case (ddrphy_bl8_chunk)
10426                 1'd0: begin
10427                         ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0];
10428                 end
10429                 1'd1: begin
10430                         ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4];
10431                 end
10432         endcase
10433         ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8;
10434         case (ddrphy_bl8_chunk)
10435                 1'd0: begin
10436                         ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0];
10437                 end
10438                 1'd1: begin
10439                         ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4];
10440                 end
10441         endcase
10442         ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o;
10443         ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9;
10444         case (ddrphy_bl8_chunk)
10445                 1'd0: begin
10446                         ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0];
10447                 end
10448                 1'd1: begin
10449                         ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4];
10450                 end
10451         endcase
10452         ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o;
10453         ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10;
10454         case (ddrphy_bl8_chunk)
10455                 1'd0: begin
10456                         ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0];
10457                 end
10458                 1'd1: begin
10459                         ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4];
10460                 end
10461         endcase
10462         ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o;
10463         ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11;
10464         case (ddrphy_bl8_chunk)
10465                 1'd0: begin
10466                         ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0];
10467                 end
10468                 1'd1: begin
10469                         ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4];
10470                 end
10471         endcase
10472         ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o;
10473         ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12;
10474         case (ddrphy_bl8_chunk)
10475                 1'd0: begin
10476                         ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0];
10477                 end
10478                 1'd1: begin
10479                         ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4];
10480                 end
10481         endcase
10482         ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o;
10483         ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13;
10484         case (ddrphy_bl8_chunk)
10485                 1'd0: begin
10486                         ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0];
10487                 end
10488                 1'd1: begin
10489                         ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4];
10490                 end
10491         endcase
10492         ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o;
10493         ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14;
10494         case (ddrphy_bl8_chunk)
10495                 1'd0: begin
10496                         ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0];
10497                 end
10498                 1'd1: begin
10499                         ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4];
10500                 end
10501         endcase
10502         ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o;
10503         ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15;
10504         case (ddrphy_bl8_chunk)
10505                 1'd0: begin
10506                         ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0];
10507                 end
10508                 1'd1: begin
10509                         ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4];
10510                 end
10511         endcase
10512         ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o;
10513         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_rst_re)) begin
10514                 ddrphy_rdly2 <= 1'd0;
10515         end
10516         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_inc_re)) begin
10517                 ddrphy_rdly2 <= (ddrphy_rdly2 + 1'd1);
10518         end
10519         ddrphy_burstdet_d2 <= ddrphy_burstdet2;
10520         if (ddrphy_burstdet_clr_re) begin
10521                 ddrphy_burstdet_seen_status[2] <= 1'd0;
10522         end
10523         if ((ddrphy_burstdet2 & (~ddrphy_burstdet_d2))) begin
10524                 ddrphy_burstdet_seen_status[2] <= 1'd1;
10525         end
10526         ddrphy_dm_o_data_d2 <= ddrphy_dm_o_data2;
10527         case (ddrphy_bl8_chunk)
10528                 1'd0: begin
10529                         ddrphy_dm_o_data_muxed2 <= ddrphy_dm_o_data2[3:0];
10530                 end
10531                 1'd1: begin
10532                         ddrphy_dm_o_data_muxed2 <= ddrphy_dm_o_data_d2[7:4];
10533                 end
10534         endcase
10535         ddrphy_dq_o_data_d16 <= ddrphy_dq_o_data16;
10536         case (ddrphy_bl8_chunk)
10537                 1'd0: begin
10538                         ddrphy_dq_o_data_muxed16 <= ddrphy_dq_o_data16[3:0];
10539                 end
10540                 1'd1: begin
10541                         ddrphy_dq_o_data_muxed16 <= ddrphy_dq_o_data_d16[7:4];
10542                 end
10543         endcase
10544         ddrphy_dq_i_bitslip_o_d16 <= ddrphy_bitslip16_o;
10545         ddrphy_dq_o_data_d17 <= ddrphy_dq_o_data17;
10546         case (ddrphy_bl8_chunk)
10547                 1'd0: begin
10548                         ddrphy_dq_o_data_muxed17 <= ddrphy_dq_o_data17[3:0];
10549                 end
10550                 1'd1: begin
10551                         ddrphy_dq_o_data_muxed17 <= ddrphy_dq_o_data_d17[7:4];
10552                 end
10553         endcase
10554         ddrphy_dq_i_bitslip_o_d17 <= ddrphy_bitslip17_o;
10555         ddrphy_dq_o_data_d18 <= ddrphy_dq_o_data18;
10556         case (ddrphy_bl8_chunk)
10557                 1'd0: begin
10558                         ddrphy_dq_o_data_muxed18 <= ddrphy_dq_o_data18[3:0];
10559                 end
10560                 1'd1: begin
10561                         ddrphy_dq_o_data_muxed18 <= ddrphy_dq_o_data_d18[7:4];
10562                 end
10563         endcase
10564         ddrphy_dq_i_bitslip_o_d18 <= ddrphy_bitslip18_o;
10565         ddrphy_dq_o_data_d19 <= ddrphy_dq_o_data19;
10566         case (ddrphy_bl8_chunk)
10567                 1'd0: begin
10568                         ddrphy_dq_o_data_muxed19 <= ddrphy_dq_o_data19[3:0];
10569                 end
10570                 1'd1: begin
10571                         ddrphy_dq_o_data_muxed19 <= ddrphy_dq_o_data_d19[7:4];
10572                 end
10573         endcase
10574         ddrphy_dq_i_bitslip_o_d19 <= ddrphy_bitslip19_o;
10575         ddrphy_dq_o_data_d20 <= ddrphy_dq_o_data20;
10576         case (ddrphy_bl8_chunk)
10577                 1'd0: begin
10578                         ddrphy_dq_o_data_muxed20 <= ddrphy_dq_o_data20[3:0];
10579                 end
10580                 1'd1: begin
10581                         ddrphy_dq_o_data_muxed20 <= ddrphy_dq_o_data_d20[7:4];
10582                 end
10583         endcase
10584         ddrphy_dq_i_bitslip_o_d20 <= ddrphy_bitslip20_o;
10585         ddrphy_dq_o_data_d21 <= ddrphy_dq_o_data21;
10586         case (ddrphy_bl8_chunk)
10587                 1'd0: begin
10588                         ddrphy_dq_o_data_muxed21 <= ddrphy_dq_o_data21[3:0];
10589                 end
10590                 1'd1: begin
10591                         ddrphy_dq_o_data_muxed21 <= ddrphy_dq_o_data_d21[7:4];
10592                 end
10593         endcase
10594         ddrphy_dq_i_bitslip_o_d21 <= ddrphy_bitslip21_o;
10595         ddrphy_dq_o_data_d22 <= ddrphy_dq_o_data22;
10596         case (ddrphy_bl8_chunk)
10597                 1'd0: begin
10598                         ddrphy_dq_o_data_muxed22 <= ddrphy_dq_o_data22[3:0];
10599                 end
10600                 1'd1: begin
10601                         ddrphy_dq_o_data_muxed22 <= ddrphy_dq_o_data_d22[7:4];
10602                 end
10603         endcase
10604         ddrphy_dq_i_bitslip_o_d22 <= ddrphy_bitslip22_o;
10605         ddrphy_dq_o_data_d23 <= ddrphy_dq_o_data23;
10606         case (ddrphy_bl8_chunk)
10607                 1'd0: begin
10608                         ddrphy_dq_o_data_muxed23 <= ddrphy_dq_o_data23[3:0];
10609                 end
10610                 1'd1: begin
10611                         ddrphy_dq_o_data_muxed23 <= ddrphy_dq_o_data_d23[7:4];
10612                 end
10613         endcase
10614         ddrphy_dq_i_bitslip_o_d23 <= ddrphy_bitslip23_o;
10615         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_rst_re)) begin
10616                 ddrphy_rdly3 <= 1'd0;
10617         end
10618         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_inc_re)) begin
10619                 ddrphy_rdly3 <= (ddrphy_rdly3 + 1'd1);
10620         end
10621         ddrphy_burstdet_d3 <= ddrphy_burstdet3;
10622         if (ddrphy_burstdet_clr_re) begin
10623                 ddrphy_burstdet_seen_status[3] <= 1'd0;
10624         end
10625         if ((ddrphy_burstdet3 & (~ddrphy_burstdet_d3))) begin
10626                 ddrphy_burstdet_seen_status[3] <= 1'd1;
10627         end
10628         ddrphy_dm_o_data_d3 <= ddrphy_dm_o_data3;
10629         case (ddrphy_bl8_chunk)
10630                 1'd0: begin
10631                         ddrphy_dm_o_data_muxed3 <= ddrphy_dm_o_data3[3:0];
10632                 end
10633                 1'd1: begin
10634                         ddrphy_dm_o_data_muxed3 <= ddrphy_dm_o_data_d3[7:4];
10635                 end
10636         endcase
10637         ddrphy_dq_o_data_d24 <= ddrphy_dq_o_data24;
10638         case (ddrphy_bl8_chunk)
10639                 1'd0: begin
10640                         ddrphy_dq_o_data_muxed24 <= ddrphy_dq_o_data24[3:0];
10641                 end
10642                 1'd1: begin
10643                         ddrphy_dq_o_data_muxed24 <= ddrphy_dq_o_data_d24[7:4];
10644                 end
10645         endcase
10646         ddrphy_dq_i_bitslip_o_d24 <= ddrphy_bitslip24_o;
10647         ddrphy_dq_o_data_d25 <= ddrphy_dq_o_data25;
10648         case (ddrphy_bl8_chunk)
10649                 1'd0: begin
10650                         ddrphy_dq_o_data_muxed25 <= ddrphy_dq_o_data25[3:0];
10651                 end
10652                 1'd1: begin
10653                         ddrphy_dq_o_data_muxed25 <= ddrphy_dq_o_data_d25[7:4];
10654                 end
10655         endcase
10656         ddrphy_dq_i_bitslip_o_d25 <= ddrphy_bitslip25_o;
10657         ddrphy_dq_o_data_d26 <= ddrphy_dq_o_data26;
10658         case (ddrphy_bl8_chunk)
10659                 1'd0: begin
10660                         ddrphy_dq_o_data_muxed26 <= ddrphy_dq_o_data26[3:0];
10661                 end
10662                 1'd1: begin
10663                         ddrphy_dq_o_data_muxed26 <= ddrphy_dq_o_data_d26[7:4];
10664                 end
10665         endcase
10666         ddrphy_dq_i_bitslip_o_d26 <= ddrphy_bitslip26_o;
10667         ddrphy_dq_o_data_d27 <= ddrphy_dq_o_data27;
10668         case (ddrphy_bl8_chunk)
10669                 1'd0: begin
10670                         ddrphy_dq_o_data_muxed27 <= ddrphy_dq_o_data27[3:0];
10671                 end
10672                 1'd1: begin
10673                         ddrphy_dq_o_data_muxed27 <= ddrphy_dq_o_data_d27[7:4];
10674                 end
10675         endcase
10676         ddrphy_dq_i_bitslip_o_d27 <= ddrphy_bitslip27_o;
10677         ddrphy_dq_o_data_d28 <= ddrphy_dq_o_data28;
10678         case (ddrphy_bl8_chunk)
10679                 1'd0: begin
10680                         ddrphy_dq_o_data_muxed28 <= ddrphy_dq_o_data28[3:0];
10681                 end
10682                 1'd1: begin
10683                         ddrphy_dq_o_data_muxed28 <= ddrphy_dq_o_data_d28[7:4];
10684                 end
10685         endcase
10686         ddrphy_dq_i_bitslip_o_d28 <= ddrphy_bitslip28_o;
10687         ddrphy_dq_o_data_d29 <= ddrphy_dq_o_data29;
10688         case (ddrphy_bl8_chunk)
10689                 1'd0: begin
10690                         ddrphy_dq_o_data_muxed29 <= ddrphy_dq_o_data29[3:0];
10691                 end
10692                 1'd1: begin
10693                         ddrphy_dq_o_data_muxed29 <= ddrphy_dq_o_data_d29[7:4];
10694                 end
10695         endcase
10696         ddrphy_dq_i_bitslip_o_d29 <= ddrphy_bitslip29_o;
10697         ddrphy_dq_o_data_d30 <= ddrphy_dq_o_data30;
10698         case (ddrphy_bl8_chunk)
10699                 1'd0: begin
10700                         ddrphy_dq_o_data_muxed30 <= ddrphy_dq_o_data30[3:0];
10701                 end
10702                 1'd1: begin
10703                         ddrphy_dq_o_data_muxed30 <= ddrphy_dq_o_data_d30[7:4];
10704                 end
10705         endcase
10706         ddrphy_dq_i_bitslip_o_d30 <= ddrphy_bitslip30_o;
10707         ddrphy_dq_o_data_d31 <= ddrphy_dq_o_data31;
10708         case (ddrphy_bl8_chunk)
10709                 1'd0: begin
10710                         ddrphy_dq_o_data_muxed31 <= ddrphy_dq_o_data31[3:0];
10711                 end
10712                 1'd1: begin
10713                         ddrphy_dq_o_data_muxed31 <= ddrphy_dq_o_data_d31[7:4];
10714                 end
10715         endcase
10716         ddrphy_dq_i_bitslip_o_d31 <= ddrphy_bitslip31_o;
10717         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10718                 ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1);
10719         end
10720         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10721                 ddrphy_bitslip0_value <= 1'd0;
10722         end
10723         ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]};
10724         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10725                 ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1);
10726         end
10727         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10728                 ddrphy_bitslip1_value <= 1'd0;
10729         end
10730         ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]};
10731         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10732                 ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1);
10733         end
10734         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10735                 ddrphy_bitslip2_value <= 1'd0;
10736         end
10737         ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]};
10738         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10739                 ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1);
10740         end
10741         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10742                 ddrphy_bitslip3_value <= 1'd0;
10743         end
10744         ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]};
10745         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10746                 ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1);
10747         end
10748         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10749                 ddrphy_bitslip4_value <= 1'd0;
10750         end
10751         ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]};
10752         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10753                 ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1);
10754         end
10755         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10756                 ddrphy_bitslip5_value <= 1'd0;
10757         end
10758         ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]};
10759         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10760                 ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1);
10761         end
10762         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10763                 ddrphy_bitslip6_value <= 1'd0;
10764         end
10765         ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]};
10766         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
10767                 ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1);
10768         end
10769         if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10770                 ddrphy_bitslip7_value <= 1'd0;
10771         end
10772         ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]};
10773         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10774                 ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1);
10775         end
10776         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10777                 ddrphy_bitslip8_value <= 1'd0;
10778         end
10779         ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]};
10780         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10781                 ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1);
10782         end
10783         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10784                 ddrphy_bitslip9_value <= 1'd0;
10785         end
10786         ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]};
10787         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10788                 ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1);
10789         end
10790         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10791                 ddrphy_bitslip10_value <= 1'd0;
10792         end
10793         ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]};
10794         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10795                 ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1);
10796         end
10797         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10798                 ddrphy_bitslip11_value <= 1'd0;
10799         end
10800         ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]};
10801         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10802                 ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1);
10803         end
10804         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10805                 ddrphy_bitslip12_value <= 1'd0;
10806         end
10807         ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]};
10808         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10809                 ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1);
10810         end
10811         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10812                 ddrphy_bitslip13_value <= 1'd0;
10813         end
10814         ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]};
10815         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10816                 ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1);
10817         end
10818         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10819                 ddrphy_bitslip14_value <= 1'd0;
10820         end
10821         ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]};
10822         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
10823                 ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1);
10824         end
10825         if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10826                 ddrphy_bitslip15_value <= 1'd0;
10827         end
10828         ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]};
10829         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10830                 ddrphy_bitslip16_value <= (ddrphy_bitslip16_value + 1'd1);
10831         end
10832         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10833                 ddrphy_bitslip16_value <= 1'd0;
10834         end
10835         ddrphy_bitslip16_r <= {ddrphy_bitslip16_i, ddrphy_bitslip16_r[7:4]};
10836         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10837                 ddrphy_bitslip17_value <= (ddrphy_bitslip17_value + 1'd1);
10838         end
10839         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10840                 ddrphy_bitslip17_value <= 1'd0;
10841         end
10842         ddrphy_bitslip17_r <= {ddrphy_bitslip17_i, ddrphy_bitslip17_r[7:4]};
10843         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10844                 ddrphy_bitslip18_value <= (ddrphy_bitslip18_value + 1'd1);
10845         end
10846         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10847                 ddrphy_bitslip18_value <= 1'd0;
10848         end
10849         ddrphy_bitslip18_r <= {ddrphy_bitslip18_i, ddrphy_bitslip18_r[7:4]};
10850         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10851                 ddrphy_bitslip19_value <= (ddrphy_bitslip19_value + 1'd1);
10852         end
10853         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10854                 ddrphy_bitslip19_value <= 1'd0;
10855         end
10856         ddrphy_bitslip19_r <= {ddrphy_bitslip19_i, ddrphy_bitslip19_r[7:4]};
10857         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10858                 ddrphy_bitslip20_value <= (ddrphy_bitslip20_value + 1'd1);
10859         end
10860         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10861                 ddrphy_bitslip20_value <= 1'd0;
10862         end
10863         ddrphy_bitslip20_r <= {ddrphy_bitslip20_i, ddrphy_bitslip20_r[7:4]};
10864         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10865                 ddrphy_bitslip21_value <= (ddrphy_bitslip21_value + 1'd1);
10866         end
10867         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10868                 ddrphy_bitslip21_value <= 1'd0;
10869         end
10870         ddrphy_bitslip21_r <= {ddrphy_bitslip21_i, ddrphy_bitslip21_r[7:4]};
10871         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10872                 ddrphy_bitslip22_value <= (ddrphy_bitslip22_value + 1'd1);
10873         end
10874         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10875                 ddrphy_bitslip22_value <= 1'd0;
10876         end
10877         ddrphy_bitslip22_r <= {ddrphy_bitslip22_i, ddrphy_bitslip22_r[7:4]};
10878         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_re)) begin
10879                 ddrphy_bitslip23_value <= (ddrphy_bitslip23_value + 1'd1);
10880         end
10881         if ((ddrphy_dly_sel_storage[2] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10882                 ddrphy_bitslip23_value <= 1'd0;
10883         end
10884         ddrphy_bitslip23_r <= {ddrphy_bitslip23_i, ddrphy_bitslip23_r[7:4]};
10885         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10886                 ddrphy_bitslip24_value <= (ddrphy_bitslip24_value + 1'd1);
10887         end
10888         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10889                 ddrphy_bitslip24_value <= 1'd0;
10890         end
10891         ddrphy_bitslip24_r <= {ddrphy_bitslip24_i, ddrphy_bitslip24_r[7:4]};
10892         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10893                 ddrphy_bitslip25_value <= (ddrphy_bitslip25_value + 1'd1);
10894         end
10895         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10896                 ddrphy_bitslip25_value <= 1'd0;
10897         end
10898         ddrphy_bitslip25_r <= {ddrphy_bitslip25_i, ddrphy_bitslip25_r[7:4]};
10899         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10900                 ddrphy_bitslip26_value <= (ddrphy_bitslip26_value + 1'd1);
10901         end
10902         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10903                 ddrphy_bitslip26_value <= 1'd0;
10904         end
10905         ddrphy_bitslip26_r <= {ddrphy_bitslip26_i, ddrphy_bitslip26_r[7:4]};
10906         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10907                 ddrphy_bitslip27_value <= (ddrphy_bitslip27_value + 1'd1);
10908         end
10909         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10910                 ddrphy_bitslip27_value <= 1'd0;
10911         end
10912         ddrphy_bitslip27_r <= {ddrphy_bitslip27_i, ddrphy_bitslip27_r[7:4]};
10913         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10914                 ddrphy_bitslip28_value <= (ddrphy_bitslip28_value + 1'd1);
10915         end
10916         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10917                 ddrphy_bitslip28_value <= 1'd0;
10918         end
10919         ddrphy_bitslip28_r <= {ddrphy_bitslip28_i, ddrphy_bitslip28_r[7:4]};
10920         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10921                 ddrphy_bitslip29_value <= (ddrphy_bitslip29_value + 1'd1);
10922         end
10923         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10924                 ddrphy_bitslip29_value <= 1'd0;
10925         end
10926         ddrphy_bitslip29_r <= {ddrphy_bitslip29_i, ddrphy_bitslip29_r[7:4]};
10927         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10928                 ddrphy_bitslip30_value <= (ddrphy_bitslip30_value + 1'd1);
10929         end
10930         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10931                 ddrphy_bitslip30_value <= 1'd0;
10932         end
10933         ddrphy_bitslip30_r <= {ddrphy_bitslip30_i, ddrphy_bitslip30_r[7:4]};
10934         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_re)) begin
10935                 ddrphy_bitslip31_value <= (ddrphy_bitslip31_value + 1'd1);
10936         end
10937         if ((ddrphy_dly_sel_storage[3] & ddrphy_rdly_dq_bitslip_rst_re)) begin
10938                 ddrphy_bitslip31_value <= 1'd0;
10939         end
10940         ddrphy_bitslip31_r <= {ddrphy_bitslip31_i, ddrphy_bitslip31_r[7:4]};
10941         ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en);
10942         ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0;
10943         ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1;
10944         ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2;
10945         ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3;
10946         ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4;
10947         ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5;
10948         ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6;
10949         ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7;
10950         ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8;
10951         ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9;
10952         ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10;
10953         ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11;
10954         ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en);
10955         ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0;
10956         ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1;
10957         ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2;
10958         ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3;
10959         ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4;
10960         ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5;
10961         if (litedramcore_inti_p0_rddata_valid) begin
10962                 litedramcore_phaseinjector0_rddata_status <= litedramcore_inti_p0_rddata;
10963         end
10964         if (litedramcore_inti_p1_rddata_valid) begin
10965                 litedramcore_phaseinjector1_rddata_status <= litedramcore_inti_p1_rddata;
10966         end
10967         if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
10968                 litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
10969         end else begin
10970                 litedramcore_timer_count1 <= 9'd374;
10971         end
10972         litedramcore_postponer_req_o <= 1'd0;
10973         if (litedramcore_postponer_req_i) begin
10974                 litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
10975                 if ((litedramcore_postponer_count == 1'd0)) begin
10976                         litedramcore_postponer_count <= 1'd0;
10977                         litedramcore_postponer_req_o <= 1'd1;
10978                 end
10979         end
10980         if (litedramcore_sequencer_start0) begin
10981                 litedramcore_sequencer_count <= 1'd0;
10982         end else begin
10983                 if (litedramcore_sequencer_done1) begin
10984                         if ((litedramcore_sequencer_count != 1'd0)) begin
10985                                 litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
10986                         end
10987                 end
10988         end
10989         litedramcore_cmd_payload_a <= 1'd0;
10990         litedramcore_cmd_payload_ba <= 1'd0;
10991         litedramcore_cmd_payload_cas <= 1'd0;
10992         litedramcore_cmd_payload_ras <= 1'd0;
10993         litedramcore_cmd_payload_we <= 1'd0;
10994         litedramcore_sequencer_done1 <= 1'd0;
10995         if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
10996                 litedramcore_cmd_payload_a <= 11'd1024;
10997                 litedramcore_cmd_payload_ba <= 1'd0;
10998                 litedramcore_cmd_payload_cas <= 1'd0;
10999                 litedramcore_cmd_payload_ras <= 1'd1;
11000                 litedramcore_cmd_payload_we <= 1'd1;
11001         end
11002         if ((litedramcore_sequencer_counter == 2'd2)) begin
11003                 litedramcore_cmd_payload_a <= 11'd1024;
11004                 litedramcore_cmd_payload_ba <= 1'd0;
11005                 litedramcore_cmd_payload_cas <= 1'd1;
11006                 litedramcore_cmd_payload_ras <= 1'd1;
11007                 litedramcore_cmd_payload_we <= 1'd0;
11008         end
11009         if ((litedramcore_sequencer_counter == 7'd106)) begin
11010                 litedramcore_cmd_payload_a <= 1'd0;
11011                 litedramcore_cmd_payload_ba <= 1'd0;
11012                 litedramcore_cmd_payload_cas <= 1'd0;
11013                 litedramcore_cmd_payload_ras <= 1'd0;
11014                 litedramcore_cmd_payload_we <= 1'd0;
11015                 litedramcore_sequencer_done1 <= 1'd1;
11016         end
11017         if ((litedramcore_sequencer_counter == 7'd106)) begin
11018                 litedramcore_sequencer_counter <= 1'd0;
11019         end else begin
11020                 if ((litedramcore_sequencer_counter != 1'd0)) begin
11021                         litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
11022                 end else begin
11023                         if (litedramcore_sequencer_start1) begin
11024                                 litedramcore_sequencer_counter <= 1'd1;
11025                         end
11026                 end
11027         end
11028         if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
11029                 litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
11030         end else begin
11031                 litedramcore_zqcs_timer_count1 <= 26'd47999999;
11032         end
11033         litedramcore_zqcs_executer_done <= 1'd0;
11034         if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
11035                 litedramcore_cmd_payload_a <= 11'd1024;
11036                 litedramcore_cmd_payload_ba <= 1'd0;
11037                 litedramcore_cmd_payload_cas <= 1'd0;
11038                 litedramcore_cmd_payload_ras <= 1'd1;
11039                 litedramcore_cmd_payload_we <= 1'd1;
11040         end
11041         if ((litedramcore_zqcs_executer_counter == 2'd2)) begin
11042                 litedramcore_cmd_payload_a <= 1'd0;
11043                 litedramcore_cmd_payload_ba <= 1'd0;
11044                 litedramcore_cmd_payload_cas <= 1'd0;
11045                 litedramcore_cmd_payload_ras <= 1'd0;
11046                 litedramcore_cmd_payload_we <= 1'd1;
11047         end
11048         if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
11049                 litedramcore_cmd_payload_a <= 1'd0;
11050                 litedramcore_cmd_payload_ba <= 1'd0;
11051                 litedramcore_cmd_payload_cas <= 1'd0;
11052                 litedramcore_cmd_payload_ras <= 1'd0;
11053                 litedramcore_cmd_payload_we <= 1'd0;
11054                 litedramcore_zqcs_executer_done <= 1'd1;
11055         end
11056         if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
11057                 litedramcore_zqcs_executer_counter <= 1'd0;
11058         end else begin
11059                 if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
11060                         litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
11061                 end else begin
11062                         if (litedramcore_zqcs_executer_start) begin
11063                                 litedramcore_zqcs_executer_counter <= 1'd1;
11064                         end
11065                 end
11066         end
11067         litedramcore_refresher_state <= litedramcore_refresher_next_state;
11068         if (litedramcore_bankmachine0_row_close) begin
11069                 litedramcore_bankmachine0_row_opened <= 1'd0;
11070         end else begin
11071                 if (litedramcore_bankmachine0_row_open) begin
11072                         litedramcore_bankmachine0_row_opened <= 1'd1;
11073                         litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
11074                 end
11075         end
11076         if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
11077                 litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
11078         end
11079         if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
11080                 litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
11081         end
11082         if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
11083                 if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
11084                         litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
11085                 end
11086         end else begin
11087                 if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
11088                         litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
11089                 end
11090         end
11091         if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
11092                 litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
11093                 litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
11094                 litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
11095                 litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
11096                 litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
11097         end
11098         if (litedramcore_bankmachine0_twtpcon_valid) begin
11099                 litedramcore_bankmachine0_twtpcon_count <= 3'd6;
11100                 if (1'd0) begin
11101                         litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
11102                 end else begin
11103                         litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
11104                 end
11105         end else begin
11106                 if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
11107                         litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
11108                         if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
11109                                 litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
11110                         end
11111                 end
11112         end
11113         if (litedramcore_bankmachine0_trccon_valid) begin
11114                 litedramcore_bankmachine0_trccon_count <= 2'd2;
11115                 if (1'd0) begin
11116                         litedramcore_bankmachine0_trccon_ready <= 1'd1;
11117                 end else begin
11118                         litedramcore_bankmachine0_trccon_ready <= 1'd0;
11119                 end
11120         end else begin
11121                 if ((~litedramcore_bankmachine0_trccon_ready)) begin
11122                         litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
11123                         if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
11124                                 litedramcore_bankmachine0_trccon_ready <= 1'd1;
11125                         end
11126                 end
11127         end
11128         if (litedramcore_bankmachine0_trascon_valid) begin
11129                 litedramcore_bankmachine0_trascon_count <= 2'd2;
11130                 if (1'd0) begin
11131                         litedramcore_bankmachine0_trascon_ready <= 1'd1;
11132                 end else begin
11133                         litedramcore_bankmachine0_trascon_ready <= 1'd0;
11134                 end
11135         end else begin
11136                 if ((~litedramcore_bankmachine0_trascon_ready)) begin
11137                         litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
11138                         if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
11139                                 litedramcore_bankmachine0_trascon_ready <= 1'd1;
11140                         end
11141                 end
11142         end
11143         litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
11144         if (litedramcore_bankmachine1_row_close) begin
11145                 litedramcore_bankmachine1_row_opened <= 1'd0;
11146         end else begin
11147                 if (litedramcore_bankmachine1_row_open) begin
11148                         litedramcore_bankmachine1_row_opened <= 1'd1;
11149                         litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
11150                 end
11151         end
11152         if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
11153                 litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
11154         end
11155         if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
11156                 litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
11157         end
11158         if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
11159                 if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
11160                         litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
11161                 end
11162         end else begin
11163                 if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
11164                         litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
11165                 end
11166         end
11167         if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
11168                 litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
11169                 litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
11170                 litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
11171                 litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
11172                 litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
11173         end
11174         if (litedramcore_bankmachine1_twtpcon_valid) begin
11175                 litedramcore_bankmachine1_twtpcon_count <= 3'd6;
11176                 if (1'd0) begin
11177                         litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
11178                 end else begin
11179                         litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
11180                 end
11181         end else begin
11182                 if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
11183                         litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
11184                         if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
11185                                 litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
11186                         end
11187                 end
11188         end
11189         if (litedramcore_bankmachine1_trccon_valid) begin
11190                 litedramcore_bankmachine1_trccon_count <= 2'd2;
11191                 if (1'd0) begin
11192                         litedramcore_bankmachine1_trccon_ready <= 1'd1;
11193                 end else begin
11194                         litedramcore_bankmachine1_trccon_ready <= 1'd0;
11195                 end
11196         end else begin
11197                 if ((~litedramcore_bankmachine1_trccon_ready)) begin
11198                         litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
11199                         if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
11200                                 litedramcore_bankmachine1_trccon_ready <= 1'd1;
11201                         end
11202                 end
11203         end
11204         if (litedramcore_bankmachine1_trascon_valid) begin
11205                 litedramcore_bankmachine1_trascon_count <= 2'd2;
11206                 if (1'd0) begin
11207                         litedramcore_bankmachine1_trascon_ready <= 1'd1;
11208                 end else begin
11209                         litedramcore_bankmachine1_trascon_ready <= 1'd0;
11210                 end
11211         end else begin
11212                 if ((~litedramcore_bankmachine1_trascon_ready)) begin
11213                         litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
11214                         if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
11215                                 litedramcore_bankmachine1_trascon_ready <= 1'd1;
11216                         end
11217                 end
11218         end
11219         litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
11220         if (litedramcore_bankmachine2_row_close) begin
11221                 litedramcore_bankmachine2_row_opened <= 1'd0;
11222         end else begin
11223                 if (litedramcore_bankmachine2_row_open) begin
11224                         litedramcore_bankmachine2_row_opened <= 1'd1;
11225                         litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
11226                 end
11227         end
11228         if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
11229                 litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
11230         end
11231         if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
11232                 litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
11233         end
11234         if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
11235                 if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
11236                         litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
11237                 end
11238         end else begin
11239                 if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
11240                         litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
11241                 end
11242         end
11243         if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
11244                 litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
11245                 litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
11246                 litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
11247                 litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
11248                 litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
11249         end
11250         if (litedramcore_bankmachine2_twtpcon_valid) begin
11251                 litedramcore_bankmachine2_twtpcon_count <= 3'd6;
11252                 if (1'd0) begin
11253                         litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
11254                 end else begin
11255                         litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
11256                 end
11257         end else begin
11258                 if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
11259                         litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
11260                         if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
11261                                 litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
11262                         end
11263                 end
11264         end
11265         if (litedramcore_bankmachine2_trccon_valid) begin
11266                 litedramcore_bankmachine2_trccon_count <= 2'd2;
11267                 if (1'd0) begin
11268                         litedramcore_bankmachine2_trccon_ready <= 1'd1;
11269                 end else begin
11270                         litedramcore_bankmachine2_trccon_ready <= 1'd0;
11271                 end
11272         end else begin
11273                 if ((~litedramcore_bankmachine2_trccon_ready)) begin
11274                         litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
11275                         if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
11276                                 litedramcore_bankmachine2_trccon_ready <= 1'd1;
11277                         end
11278                 end
11279         end
11280         if (litedramcore_bankmachine2_trascon_valid) begin
11281                 litedramcore_bankmachine2_trascon_count <= 2'd2;
11282                 if (1'd0) begin
11283                         litedramcore_bankmachine2_trascon_ready <= 1'd1;
11284                 end else begin
11285                         litedramcore_bankmachine2_trascon_ready <= 1'd0;
11286                 end
11287         end else begin
11288                 if ((~litedramcore_bankmachine2_trascon_ready)) begin
11289                         litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
11290                         if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
11291                                 litedramcore_bankmachine2_trascon_ready <= 1'd1;
11292                         end
11293                 end
11294         end
11295         litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
11296         if (litedramcore_bankmachine3_row_close) begin
11297                 litedramcore_bankmachine3_row_opened <= 1'd0;
11298         end else begin
11299                 if (litedramcore_bankmachine3_row_open) begin
11300                         litedramcore_bankmachine3_row_opened <= 1'd1;
11301                         litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
11302                 end
11303         end
11304         if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
11305                 litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
11306         end
11307         if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
11308                 litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
11309         end
11310         if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
11311                 if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
11312                         litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
11313                 end
11314         end else begin
11315                 if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
11316                         litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
11317                 end
11318         end
11319         if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
11320                 litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
11321                 litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
11322                 litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
11323                 litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
11324                 litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
11325         end
11326         if (litedramcore_bankmachine3_twtpcon_valid) begin
11327                 litedramcore_bankmachine3_twtpcon_count <= 3'd6;
11328                 if (1'd0) begin
11329                         litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
11330                 end else begin
11331                         litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
11332                 end
11333         end else begin
11334                 if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
11335                         litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
11336                         if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
11337                                 litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
11338                         end
11339                 end
11340         end
11341         if (litedramcore_bankmachine3_trccon_valid) begin
11342                 litedramcore_bankmachine3_trccon_count <= 2'd2;
11343                 if (1'd0) begin
11344                         litedramcore_bankmachine3_trccon_ready <= 1'd1;
11345                 end else begin
11346                         litedramcore_bankmachine3_trccon_ready <= 1'd0;
11347                 end
11348         end else begin
11349                 if ((~litedramcore_bankmachine3_trccon_ready)) begin
11350                         litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
11351                         if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
11352                                 litedramcore_bankmachine3_trccon_ready <= 1'd1;
11353                         end
11354                 end
11355         end
11356         if (litedramcore_bankmachine3_trascon_valid) begin
11357                 litedramcore_bankmachine3_trascon_count <= 2'd2;
11358                 if (1'd0) begin
11359                         litedramcore_bankmachine3_trascon_ready <= 1'd1;
11360                 end else begin
11361                         litedramcore_bankmachine3_trascon_ready <= 1'd0;
11362                 end
11363         end else begin
11364                 if ((~litedramcore_bankmachine3_trascon_ready)) begin
11365                         litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
11366                         if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
11367                                 litedramcore_bankmachine3_trascon_ready <= 1'd1;
11368                         end
11369                 end
11370         end
11371         litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
11372         if (litedramcore_bankmachine4_row_close) begin
11373                 litedramcore_bankmachine4_row_opened <= 1'd0;
11374         end else begin
11375                 if (litedramcore_bankmachine4_row_open) begin
11376                         litedramcore_bankmachine4_row_opened <= 1'd1;
11377                         litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
11378                 end
11379         end
11380         if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
11381                 litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
11382         end
11383         if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
11384                 litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
11385         end
11386         if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
11387                 if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
11388                         litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
11389                 end
11390         end else begin
11391                 if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
11392                         litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
11393                 end
11394         end
11395         if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
11396                 litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
11397                 litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
11398                 litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
11399                 litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
11400                 litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
11401         end
11402         if (litedramcore_bankmachine4_twtpcon_valid) begin
11403                 litedramcore_bankmachine4_twtpcon_count <= 3'd6;
11404                 if (1'd0) begin
11405                         litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
11406                 end else begin
11407                         litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
11408                 end
11409         end else begin
11410                 if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
11411                         litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
11412                         if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
11413                                 litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
11414                         end
11415                 end
11416         end
11417         if (litedramcore_bankmachine4_trccon_valid) begin
11418                 litedramcore_bankmachine4_trccon_count <= 2'd2;
11419                 if (1'd0) begin
11420                         litedramcore_bankmachine4_trccon_ready <= 1'd1;
11421                 end else begin
11422                         litedramcore_bankmachine4_trccon_ready <= 1'd0;
11423                 end
11424         end else begin
11425                 if ((~litedramcore_bankmachine4_trccon_ready)) begin
11426                         litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
11427                         if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
11428                                 litedramcore_bankmachine4_trccon_ready <= 1'd1;
11429                         end
11430                 end
11431         end
11432         if (litedramcore_bankmachine4_trascon_valid) begin
11433                 litedramcore_bankmachine4_trascon_count <= 2'd2;
11434                 if (1'd0) begin
11435                         litedramcore_bankmachine4_trascon_ready <= 1'd1;
11436                 end else begin
11437                         litedramcore_bankmachine4_trascon_ready <= 1'd0;
11438                 end
11439         end else begin
11440                 if ((~litedramcore_bankmachine4_trascon_ready)) begin
11441                         litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
11442                         if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
11443                                 litedramcore_bankmachine4_trascon_ready <= 1'd1;
11444                         end
11445                 end
11446         end
11447         litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
11448         if (litedramcore_bankmachine5_row_close) begin
11449                 litedramcore_bankmachine5_row_opened <= 1'd0;
11450         end else begin
11451                 if (litedramcore_bankmachine5_row_open) begin
11452                         litedramcore_bankmachine5_row_opened <= 1'd1;
11453                         litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
11454                 end
11455         end
11456         if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
11457                 litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
11458         end
11459         if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
11460                 litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
11461         end
11462         if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
11463                 if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
11464                         litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
11465                 end
11466         end else begin
11467                 if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
11468                         litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
11469                 end
11470         end
11471         if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
11472                 litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
11473                 litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
11474                 litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
11475                 litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
11476                 litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
11477         end
11478         if (litedramcore_bankmachine5_twtpcon_valid) begin
11479                 litedramcore_bankmachine5_twtpcon_count <= 3'd6;
11480                 if (1'd0) begin
11481                         litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
11482                 end else begin
11483                         litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
11484                 end
11485         end else begin
11486                 if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
11487                         litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
11488                         if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
11489                                 litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
11490                         end
11491                 end
11492         end
11493         if (litedramcore_bankmachine5_trccon_valid) begin
11494                 litedramcore_bankmachine5_trccon_count <= 2'd2;
11495                 if (1'd0) begin
11496                         litedramcore_bankmachine5_trccon_ready <= 1'd1;
11497                 end else begin
11498                         litedramcore_bankmachine5_trccon_ready <= 1'd0;
11499                 end
11500         end else begin
11501                 if ((~litedramcore_bankmachine5_trccon_ready)) begin
11502                         litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
11503                         if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
11504                                 litedramcore_bankmachine5_trccon_ready <= 1'd1;
11505                         end
11506                 end
11507         end
11508         if (litedramcore_bankmachine5_trascon_valid) begin
11509                 litedramcore_bankmachine5_trascon_count <= 2'd2;
11510                 if (1'd0) begin
11511                         litedramcore_bankmachine5_trascon_ready <= 1'd1;
11512                 end else begin
11513                         litedramcore_bankmachine5_trascon_ready <= 1'd0;
11514                 end
11515         end else begin
11516                 if ((~litedramcore_bankmachine5_trascon_ready)) begin
11517                         litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
11518                         if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
11519                                 litedramcore_bankmachine5_trascon_ready <= 1'd1;
11520                         end
11521                 end
11522         end
11523         litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
11524         if (litedramcore_bankmachine6_row_close) begin
11525                 litedramcore_bankmachine6_row_opened <= 1'd0;
11526         end else begin
11527                 if (litedramcore_bankmachine6_row_open) begin
11528                         litedramcore_bankmachine6_row_opened <= 1'd1;
11529                         litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
11530                 end
11531         end
11532         if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
11533                 litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
11534         end
11535         if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
11536                 litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
11537         end
11538         if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
11539                 if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
11540                         litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
11541                 end
11542         end else begin
11543                 if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
11544                         litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
11545                 end
11546         end
11547         if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
11548                 litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
11549                 litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
11550                 litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
11551                 litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
11552                 litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
11553         end
11554         if (litedramcore_bankmachine6_twtpcon_valid) begin
11555                 litedramcore_bankmachine6_twtpcon_count <= 3'd6;
11556                 if (1'd0) begin
11557                         litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
11558                 end else begin
11559                         litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
11560                 end
11561         end else begin
11562                 if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
11563                         litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
11564                         if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
11565                                 litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
11566                         end
11567                 end
11568         end
11569         if (litedramcore_bankmachine6_trccon_valid) begin
11570                 litedramcore_bankmachine6_trccon_count <= 2'd2;
11571                 if (1'd0) begin
11572                         litedramcore_bankmachine6_trccon_ready <= 1'd1;
11573                 end else begin
11574                         litedramcore_bankmachine6_trccon_ready <= 1'd0;
11575                 end
11576         end else begin
11577                 if ((~litedramcore_bankmachine6_trccon_ready)) begin
11578                         litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
11579                         if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
11580                                 litedramcore_bankmachine6_trccon_ready <= 1'd1;
11581                         end
11582                 end
11583         end
11584         if (litedramcore_bankmachine6_trascon_valid) begin
11585                 litedramcore_bankmachine6_trascon_count <= 2'd2;
11586                 if (1'd0) begin
11587                         litedramcore_bankmachine6_trascon_ready <= 1'd1;
11588                 end else begin
11589                         litedramcore_bankmachine6_trascon_ready <= 1'd0;
11590                 end
11591         end else begin
11592                 if ((~litedramcore_bankmachine6_trascon_ready)) begin
11593                         litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
11594                         if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
11595                                 litedramcore_bankmachine6_trascon_ready <= 1'd1;
11596                         end
11597                 end
11598         end
11599         litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
11600         if (litedramcore_bankmachine7_row_close) begin
11601                 litedramcore_bankmachine7_row_opened <= 1'd0;
11602         end else begin
11603                 if (litedramcore_bankmachine7_row_open) begin
11604                         litedramcore_bankmachine7_row_opened <= 1'd1;
11605                         litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
11606                 end
11607         end
11608         if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
11609                 litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
11610         end
11611         if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
11612                 litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
11613         end
11614         if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
11615                 if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
11616                         litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
11617                 end
11618         end else begin
11619                 if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
11620                         litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
11621                 end
11622         end
11623         if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
11624                 litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
11625                 litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
11626                 litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
11627                 litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
11628                 litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
11629         end
11630         if (litedramcore_bankmachine7_twtpcon_valid) begin
11631                 litedramcore_bankmachine7_twtpcon_count <= 3'd6;
11632                 if (1'd0) begin
11633                         litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
11634                 end else begin
11635                         litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
11636                 end
11637         end else begin
11638                 if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
11639                         litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
11640                         if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
11641                                 litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
11642                         end
11643                 end
11644         end
11645         if (litedramcore_bankmachine7_trccon_valid) begin
11646                 litedramcore_bankmachine7_trccon_count <= 2'd2;
11647                 if (1'd0) begin
11648                         litedramcore_bankmachine7_trccon_ready <= 1'd1;
11649                 end else begin
11650                         litedramcore_bankmachine7_trccon_ready <= 1'd0;
11651                 end
11652         end else begin
11653                 if ((~litedramcore_bankmachine7_trccon_ready)) begin
11654                         litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
11655                         if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
11656                                 litedramcore_bankmachine7_trccon_ready <= 1'd1;
11657                         end
11658                 end
11659         end
11660         if (litedramcore_bankmachine7_trascon_valid) begin
11661                 litedramcore_bankmachine7_trascon_count <= 2'd2;
11662                 if (1'd0) begin
11663                         litedramcore_bankmachine7_trascon_ready <= 1'd1;
11664                 end else begin
11665                         litedramcore_bankmachine7_trascon_ready <= 1'd0;
11666                 end
11667         end else begin
11668                 if ((~litedramcore_bankmachine7_trascon_ready)) begin
11669                         litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
11670                         if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
11671                                 litedramcore_bankmachine7_trascon_ready <= 1'd1;
11672                         end
11673                 end
11674         end
11675         litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
11676         if ((~litedramcore_en0)) begin
11677                 litedramcore_time0 <= 5'd31;
11678         end else begin
11679                 if ((~litedramcore_max_time0)) begin
11680                         litedramcore_time0 <= (litedramcore_time0 - 1'd1);
11681                 end
11682         end
11683         if ((~litedramcore_en1)) begin
11684                 litedramcore_time1 <= 4'd15;
11685         end else begin
11686                 if ((~litedramcore_max_time1)) begin
11687                         litedramcore_time1 <= (litedramcore_time1 - 1'd1);
11688                 end
11689         end
11690         if (litedramcore_choose_cmd_ce) begin
11691                 case (litedramcore_choose_cmd_grant)
11692                         1'd0: begin
11693                                 if (litedramcore_choose_cmd_request[1]) begin
11694                                         litedramcore_choose_cmd_grant <= 1'd1;
11695                                 end else begin
11696                                         if (litedramcore_choose_cmd_request[2]) begin
11697                                                 litedramcore_choose_cmd_grant <= 2'd2;
11698                                         end else begin
11699                                                 if (litedramcore_choose_cmd_request[3]) begin
11700                                                         litedramcore_choose_cmd_grant <= 2'd3;
11701                                                 end else begin
11702                                                         if (litedramcore_choose_cmd_request[4]) begin
11703                                                                 litedramcore_choose_cmd_grant <= 3'd4;
11704                                                         end else begin
11705                                                                 if (litedramcore_choose_cmd_request[5]) begin
11706                                                                         litedramcore_choose_cmd_grant <= 3'd5;
11707                                                                 end else begin
11708                                                                         if (litedramcore_choose_cmd_request[6]) begin
11709                                                                                 litedramcore_choose_cmd_grant <= 3'd6;
11710                                                                         end else begin
11711                                                                                 if (litedramcore_choose_cmd_request[7]) begin
11712                                                                                         litedramcore_choose_cmd_grant <= 3'd7;
11713                                                                                 end
11714                                                                         end
11715                                                                 end
11716                                                         end
11717                                                 end
11718                                         end
11719                                 end
11720                         end
11721                         1'd1: begin
11722                                 if (litedramcore_choose_cmd_request[2]) begin
11723                                         litedramcore_choose_cmd_grant <= 2'd2;
11724                                 end else begin
11725                                         if (litedramcore_choose_cmd_request[3]) begin
11726                                                 litedramcore_choose_cmd_grant <= 2'd3;
11727                                         end else begin
11728                                                 if (litedramcore_choose_cmd_request[4]) begin
11729                                                         litedramcore_choose_cmd_grant <= 3'd4;
11730                                                 end else begin
11731                                                         if (litedramcore_choose_cmd_request[5]) begin
11732                                                                 litedramcore_choose_cmd_grant <= 3'd5;
11733                                                         end else begin
11734                                                                 if (litedramcore_choose_cmd_request[6]) begin
11735                                                                         litedramcore_choose_cmd_grant <= 3'd6;
11736                                                                 end else begin
11737                                                                         if (litedramcore_choose_cmd_request[7]) begin
11738                                                                                 litedramcore_choose_cmd_grant <= 3'd7;
11739                                                                         end else begin
11740                                                                                 if (litedramcore_choose_cmd_request[0]) begin
11741                                                                                         litedramcore_choose_cmd_grant <= 1'd0;
11742                                                                                 end
11743                                                                         end
11744                                                                 end
11745                                                         end
11746                                                 end
11747                                         end
11748                                 end
11749                         end
11750                         2'd2: begin
11751                                 if (litedramcore_choose_cmd_request[3]) begin
11752                                         litedramcore_choose_cmd_grant <= 2'd3;
11753                                 end else begin
11754                                         if (litedramcore_choose_cmd_request[4]) begin
11755                                                 litedramcore_choose_cmd_grant <= 3'd4;
11756                                         end else begin
11757                                                 if (litedramcore_choose_cmd_request[5]) begin
11758                                                         litedramcore_choose_cmd_grant <= 3'd5;
11759                                                 end else begin
11760                                                         if (litedramcore_choose_cmd_request[6]) begin
11761                                                                 litedramcore_choose_cmd_grant <= 3'd6;
11762                                                         end else begin
11763                                                                 if (litedramcore_choose_cmd_request[7]) begin
11764                                                                         litedramcore_choose_cmd_grant <= 3'd7;
11765                                                                 end else begin
11766                                                                         if (litedramcore_choose_cmd_request[0]) begin
11767                                                                                 litedramcore_choose_cmd_grant <= 1'd0;
11768                                                                         end else begin
11769                                                                                 if (litedramcore_choose_cmd_request[1]) begin
11770                                                                                         litedramcore_choose_cmd_grant <= 1'd1;
11771                                                                                 end
11772                                                                         end
11773                                                                 end
11774                                                         end
11775                                                 end
11776                                         end
11777                                 end
11778                         end
11779                         2'd3: begin
11780                                 if (litedramcore_choose_cmd_request[4]) begin
11781                                         litedramcore_choose_cmd_grant <= 3'd4;
11782                                 end else begin
11783                                         if (litedramcore_choose_cmd_request[5]) begin
11784                                                 litedramcore_choose_cmd_grant <= 3'd5;
11785                                         end else begin
11786                                                 if (litedramcore_choose_cmd_request[6]) begin
11787                                                         litedramcore_choose_cmd_grant <= 3'd6;
11788                                                 end else begin
11789                                                         if (litedramcore_choose_cmd_request[7]) begin
11790                                                                 litedramcore_choose_cmd_grant <= 3'd7;
11791                                                         end else begin
11792                                                                 if (litedramcore_choose_cmd_request[0]) begin
11793                                                                         litedramcore_choose_cmd_grant <= 1'd0;
11794                                                                 end else begin
11795                                                                         if (litedramcore_choose_cmd_request[1]) begin
11796                                                                                 litedramcore_choose_cmd_grant <= 1'd1;
11797                                                                         end else begin
11798                                                                                 if (litedramcore_choose_cmd_request[2]) begin
11799                                                                                         litedramcore_choose_cmd_grant <= 2'd2;
11800                                                                                 end
11801                                                                         end
11802                                                                 end
11803                                                         end
11804                                                 end
11805                                         end
11806                                 end
11807                         end
11808                         3'd4: begin
11809                                 if (litedramcore_choose_cmd_request[5]) begin
11810                                         litedramcore_choose_cmd_grant <= 3'd5;
11811                                 end else begin
11812                                         if (litedramcore_choose_cmd_request[6]) begin
11813                                                 litedramcore_choose_cmd_grant <= 3'd6;
11814                                         end else begin
11815                                                 if (litedramcore_choose_cmd_request[7]) begin
11816                                                         litedramcore_choose_cmd_grant <= 3'd7;
11817                                                 end else begin
11818                                                         if (litedramcore_choose_cmd_request[0]) begin
11819                                                                 litedramcore_choose_cmd_grant <= 1'd0;
11820                                                         end else begin
11821                                                                 if (litedramcore_choose_cmd_request[1]) begin
11822                                                                         litedramcore_choose_cmd_grant <= 1'd1;
11823                                                                 end else begin
11824                                                                         if (litedramcore_choose_cmd_request[2]) begin
11825                                                                                 litedramcore_choose_cmd_grant <= 2'd2;
11826                                                                         end else begin
11827                                                                                 if (litedramcore_choose_cmd_request[3]) begin
11828                                                                                         litedramcore_choose_cmd_grant <= 2'd3;
11829                                                                                 end
11830                                                                         end
11831                                                                 end
11832                                                         end
11833                                                 end
11834                                         end
11835                                 end
11836                         end
11837                         3'd5: begin
11838                                 if (litedramcore_choose_cmd_request[6]) begin
11839                                         litedramcore_choose_cmd_grant <= 3'd6;
11840                                 end else begin
11841                                         if (litedramcore_choose_cmd_request[7]) begin
11842                                                 litedramcore_choose_cmd_grant <= 3'd7;
11843                                         end else begin
11844                                                 if (litedramcore_choose_cmd_request[0]) begin
11845                                                         litedramcore_choose_cmd_grant <= 1'd0;
11846                                                 end else begin
11847                                                         if (litedramcore_choose_cmd_request[1]) begin
11848                                                                 litedramcore_choose_cmd_grant <= 1'd1;
11849                                                         end else begin
11850                                                                 if (litedramcore_choose_cmd_request[2]) begin
11851                                                                         litedramcore_choose_cmd_grant <= 2'd2;
11852                                                                 end else begin
11853                                                                         if (litedramcore_choose_cmd_request[3]) begin
11854                                                                                 litedramcore_choose_cmd_grant <= 2'd3;
11855                                                                         end else begin
11856                                                                                 if (litedramcore_choose_cmd_request[4]) begin
11857                                                                                         litedramcore_choose_cmd_grant <= 3'd4;
11858                                                                                 end
11859                                                                         end
11860                                                                 end
11861                                                         end
11862                                                 end
11863                                         end
11864                                 end
11865                         end
11866                         3'd6: begin
11867                                 if (litedramcore_choose_cmd_request[7]) begin
11868                                         litedramcore_choose_cmd_grant <= 3'd7;
11869                                 end else begin
11870                                         if (litedramcore_choose_cmd_request[0]) begin
11871                                                 litedramcore_choose_cmd_grant <= 1'd0;
11872                                         end else begin
11873                                                 if (litedramcore_choose_cmd_request[1]) begin
11874                                                         litedramcore_choose_cmd_grant <= 1'd1;
11875                                                 end else begin
11876                                                         if (litedramcore_choose_cmd_request[2]) begin
11877                                                                 litedramcore_choose_cmd_grant <= 2'd2;
11878                                                         end else begin
11879                                                                 if (litedramcore_choose_cmd_request[3]) begin
11880                                                                         litedramcore_choose_cmd_grant <= 2'd3;
11881                                                                 end else begin
11882                                                                         if (litedramcore_choose_cmd_request[4]) begin
11883                                                                                 litedramcore_choose_cmd_grant <= 3'd4;
11884                                                                         end else begin
11885                                                                                 if (litedramcore_choose_cmd_request[5]) begin
11886                                                                                         litedramcore_choose_cmd_grant <= 3'd5;
11887                                                                                 end
11888                                                                         end
11889                                                                 end
11890                                                         end
11891                                                 end
11892                                         end
11893                                 end
11894                         end
11895                         3'd7: begin
11896                                 if (litedramcore_choose_cmd_request[0]) begin
11897                                         litedramcore_choose_cmd_grant <= 1'd0;
11898                                 end else begin
11899                                         if (litedramcore_choose_cmd_request[1]) begin
11900                                                 litedramcore_choose_cmd_grant <= 1'd1;
11901                                         end else begin
11902                                                 if (litedramcore_choose_cmd_request[2]) begin
11903                                                         litedramcore_choose_cmd_grant <= 2'd2;
11904                                                 end else begin
11905                                                         if (litedramcore_choose_cmd_request[3]) begin
11906                                                                 litedramcore_choose_cmd_grant <= 2'd3;
11907                                                         end else begin
11908                                                                 if (litedramcore_choose_cmd_request[4]) begin
11909                                                                         litedramcore_choose_cmd_grant <= 3'd4;
11910                                                                 end else begin
11911                                                                         if (litedramcore_choose_cmd_request[5]) begin
11912                                                                                 litedramcore_choose_cmd_grant <= 3'd5;
11913                                                                         end else begin
11914                                                                                 if (litedramcore_choose_cmd_request[6]) begin
11915                                                                                         litedramcore_choose_cmd_grant <= 3'd6;
11916                                                                                 end
11917                                                                         end
11918                                                                 end
11919                                                         end
11920                                                 end
11921                                         end
11922                                 end
11923                         end
11924                 endcase
11925         end
11926         if (litedramcore_choose_req_ce) begin
11927                 case (litedramcore_choose_req_grant)
11928                         1'd0: begin
11929                                 if (litedramcore_choose_req_request[1]) begin
11930                                         litedramcore_choose_req_grant <= 1'd1;
11931                                 end else begin
11932                                         if (litedramcore_choose_req_request[2]) begin
11933                                                 litedramcore_choose_req_grant <= 2'd2;
11934                                         end else begin
11935                                                 if (litedramcore_choose_req_request[3]) begin
11936                                                         litedramcore_choose_req_grant <= 2'd3;
11937                                                 end else begin
11938                                                         if (litedramcore_choose_req_request[4]) begin
11939                                                                 litedramcore_choose_req_grant <= 3'd4;
11940                                                         end else begin
11941                                                                 if (litedramcore_choose_req_request[5]) begin
11942                                                                         litedramcore_choose_req_grant <= 3'd5;
11943                                                                 end else begin
11944                                                                         if (litedramcore_choose_req_request[6]) begin
11945                                                                                 litedramcore_choose_req_grant <= 3'd6;
11946                                                                         end else begin
11947                                                                                 if (litedramcore_choose_req_request[7]) begin
11948                                                                                         litedramcore_choose_req_grant <= 3'd7;
11949                                                                                 end
11950                                                                         end
11951                                                                 end
11952                                                         end
11953                                                 end
11954                                         end
11955                                 end
11956                         end
11957                         1'd1: begin
11958                                 if (litedramcore_choose_req_request[2]) begin
11959                                         litedramcore_choose_req_grant <= 2'd2;
11960                                 end else begin
11961                                         if (litedramcore_choose_req_request[3]) begin
11962                                                 litedramcore_choose_req_grant <= 2'd3;
11963                                         end else begin
11964                                                 if (litedramcore_choose_req_request[4]) begin
11965                                                         litedramcore_choose_req_grant <= 3'd4;
11966                                                 end else begin
11967                                                         if (litedramcore_choose_req_request[5]) begin
11968                                                                 litedramcore_choose_req_grant <= 3'd5;
11969                                                         end else begin
11970                                                                 if (litedramcore_choose_req_request[6]) begin
11971                                                                         litedramcore_choose_req_grant <= 3'd6;
11972                                                                 end else begin
11973                                                                         if (litedramcore_choose_req_request[7]) begin
11974                                                                                 litedramcore_choose_req_grant <= 3'd7;
11975                                                                         end else begin
11976                                                                                 if (litedramcore_choose_req_request[0]) begin
11977                                                                                         litedramcore_choose_req_grant <= 1'd0;
11978                                                                                 end
11979                                                                         end
11980                                                                 end
11981                                                         end
11982                                                 end
11983                                         end
11984                                 end
11985                         end
11986                         2'd2: begin
11987                                 if (litedramcore_choose_req_request[3]) begin
11988                                         litedramcore_choose_req_grant <= 2'd3;
11989                                 end else begin
11990                                         if (litedramcore_choose_req_request[4]) begin
11991                                                 litedramcore_choose_req_grant <= 3'd4;
11992                                         end else begin
11993                                                 if (litedramcore_choose_req_request[5]) begin
11994                                                         litedramcore_choose_req_grant <= 3'd5;
11995                                                 end else begin
11996                                                         if (litedramcore_choose_req_request[6]) begin
11997                                                                 litedramcore_choose_req_grant <= 3'd6;
11998                                                         end else begin
11999                                                                 if (litedramcore_choose_req_request[7]) begin
12000                                                                         litedramcore_choose_req_grant <= 3'd7;
12001                                                                 end else begin
12002                                                                         if (litedramcore_choose_req_request[0]) begin
12003                                                                                 litedramcore_choose_req_grant <= 1'd0;
12004                                                                         end else begin
12005                                                                                 if (litedramcore_choose_req_request[1]) begin
12006                                                                                         litedramcore_choose_req_grant <= 1'd1;
12007                                                                                 end
12008                                                                         end
12009                                                                 end
12010                                                         end
12011                                                 end
12012                                         end
12013                                 end
12014                         end
12015                         2'd3: begin
12016                                 if (litedramcore_choose_req_request[4]) begin
12017                                         litedramcore_choose_req_grant <= 3'd4;
12018                                 end else begin
12019                                         if (litedramcore_choose_req_request[5]) begin
12020                                                 litedramcore_choose_req_grant <= 3'd5;
12021                                         end else begin
12022                                                 if (litedramcore_choose_req_request[6]) begin
12023                                                         litedramcore_choose_req_grant <= 3'd6;
12024                                                 end else begin
12025                                                         if (litedramcore_choose_req_request[7]) begin
12026                                                                 litedramcore_choose_req_grant <= 3'd7;
12027                                                         end else begin
12028                                                                 if (litedramcore_choose_req_request[0]) begin
12029                                                                         litedramcore_choose_req_grant <= 1'd0;
12030                                                                 end else begin
12031                                                                         if (litedramcore_choose_req_request[1]) begin
12032                                                                                 litedramcore_choose_req_grant <= 1'd1;
12033                                                                         end else begin
12034                                                                                 if (litedramcore_choose_req_request[2]) begin
12035                                                                                         litedramcore_choose_req_grant <= 2'd2;
12036                                                                                 end
12037                                                                         end
12038                                                                 end
12039                                                         end
12040                                                 end
12041                                         end
12042                                 end
12043                         end
12044                         3'd4: begin
12045                                 if (litedramcore_choose_req_request[5]) begin
12046                                         litedramcore_choose_req_grant <= 3'd5;
12047                                 end else begin
12048                                         if (litedramcore_choose_req_request[6]) begin
12049                                                 litedramcore_choose_req_grant <= 3'd6;
12050                                         end else begin
12051                                                 if (litedramcore_choose_req_request[7]) begin
12052                                                         litedramcore_choose_req_grant <= 3'd7;
12053                                                 end else begin
12054                                                         if (litedramcore_choose_req_request[0]) begin
12055                                                                 litedramcore_choose_req_grant <= 1'd0;
12056                                                         end else begin
12057                                                                 if (litedramcore_choose_req_request[1]) begin
12058                                                                         litedramcore_choose_req_grant <= 1'd1;
12059                                                                 end else begin
12060                                                                         if (litedramcore_choose_req_request[2]) begin
12061                                                                                 litedramcore_choose_req_grant <= 2'd2;
12062                                                                         end else begin
12063                                                                                 if (litedramcore_choose_req_request[3]) begin
12064                                                                                         litedramcore_choose_req_grant <= 2'd3;
12065                                                                                 end
12066                                                                         end
12067                                                                 end
12068                                                         end
12069                                                 end
12070                                         end
12071                                 end
12072                         end
12073                         3'd5: begin
12074                                 if (litedramcore_choose_req_request[6]) begin
12075                                         litedramcore_choose_req_grant <= 3'd6;
12076                                 end else begin
12077                                         if (litedramcore_choose_req_request[7]) begin
12078                                                 litedramcore_choose_req_grant <= 3'd7;
12079                                         end else begin
12080                                                 if (litedramcore_choose_req_request[0]) begin
12081                                                         litedramcore_choose_req_grant <= 1'd0;
12082                                                 end else begin
12083                                                         if (litedramcore_choose_req_request[1]) begin
12084                                                                 litedramcore_choose_req_grant <= 1'd1;
12085                                                         end else begin
12086                                                                 if (litedramcore_choose_req_request[2]) begin
12087                                                                         litedramcore_choose_req_grant <= 2'd2;
12088                                                                 end else begin
12089                                                                         if (litedramcore_choose_req_request[3]) begin
12090                                                                                 litedramcore_choose_req_grant <= 2'd3;
12091                                                                         end else begin
12092                                                                                 if (litedramcore_choose_req_request[4]) begin
12093                                                                                         litedramcore_choose_req_grant <= 3'd4;
12094                                                                                 end
12095                                                                         end
12096                                                                 end
12097                                                         end
12098                                                 end
12099                                         end
12100                                 end
12101                         end
12102                         3'd6: begin
12103                                 if (litedramcore_choose_req_request[7]) begin
12104                                         litedramcore_choose_req_grant <= 3'd7;
12105                                 end else begin
12106                                         if (litedramcore_choose_req_request[0]) begin
12107                                                 litedramcore_choose_req_grant <= 1'd0;
12108                                         end else begin
12109                                                 if (litedramcore_choose_req_request[1]) begin
12110                                                         litedramcore_choose_req_grant <= 1'd1;
12111                                                 end else begin
12112                                                         if (litedramcore_choose_req_request[2]) begin
12113                                                                 litedramcore_choose_req_grant <= 2'd2;
12114                                                         end else begin
12115                                                                 if (litedramcore_choose_req_request[3]) begin
12116                                                                         litedramcore_choose_req_grant <= 2'd3;
12117                                                                 end else begin
12118                                                                         if (litedramcore_choose_req_request[4]) begin
12119                                                                                 litedramcore_choose_req_grant <= 3'd4;
12120                                                                         end else begin
12121                                                                                 if (litedramcore_choose_req_request[5]) begin
12122                                                                                         litedramcore_choose_req_grant <= 3'd5;
12123                                                                                 end
12124                                                                         end
12125                                                                 end
12126                                                         end
12127                                                 end
12128                                         end
12129                                 end
12130                         end
12131                         3'd7: begin
12132                                 if (litedramcore_choose_req_request[0]) begin
12133                                         litedramcore_choose_req_grant <= 1'd0;
12134                                 end else begin
12135                                         if (litedramcore_choose_req_request[1]) begin
12136                                                 litedramcore_choose_req_grant <= 1'd1;
12137                                         end else begin
12138                                                 if (litedramcore_choose_req_request[2]) begin
12139                                                         litedramcore_choose_req_grant <= 2'd2;
12140                                                 end else begin
12141                                                         if (litedramcore_choose_req_request[3]) begin
12142                                                                 litedramcore_choose_req_grant <= 2'd3;
12143                                                         end else begin
12144                                                                 if (litedramcore_choose_req_request[4]) begin
12145                                                                         litedramcore_choose_req_grant <= 3'd4;
12146                                                                 end else begin
12147                                                                         if (litedramcore_choose_req_request[5]) begin
12148                                                                                 litedramcore_choose_req_grant <= 3'd5;
12149                                                                         end else begin
12150                                                                                 if (litedramcore_choose_req_request[6]) begin
12151                                                                                         litedramcore_choose_req_grant <= 3'd6;
12152                                                                                 end
12153                                                                         end
12154                                                                 end
12155                                                         end
12156                                                 end
12157                                         end
12158                                 end
12159                         end
12160                 endcase
12161         end
12162         litedramcore_dfi_p0_cs_n <= 1'd0;
12163         litedramcore_dfi_p0_bank <= array_muxed0;
12164         litedramcore_dfi_p0_address <= array_muxed1;
12165         litedramcore_dfi_p0_cas_n <= (~array_muxed2);
12166         litedramcore_dfi_p0_ras_n <= (~array_muxed3);
12167         litedramcore_dfi_p0_we_n <= (~array_muxed4);
12168         litedramcore_dfi_p0_rddata_en <= array_muxed5;
12169         litedramcore_dfi_p0_wrdata_en <= array_muxed6;
12170         litedramcore_dfi_p1_cs_n <= 1'd0;
12171         litedramcore_dfi_p1_bank <= array_muxed7;
12172         litedramcore_dfi_p1_address <= array_muxed8;
12173         litedramcore_dfi_p1_cas_n <= (~array_muxed9);
12174         litedramcore_dfi_p1_ras_n <= (~array_muxed10);
12175         litedramcore_dfi_p1_we_n <= (~array_muxed11);
12176         litedramcore_dfi_p1_rddata_en <= array_muxed12;
12177         litedramcore_dfi_p1_wrdata_en <= array_muxed13;
12178         if (litedramcore_trrdcon_valid) begin
12179                 litedramcore_trrdcon_count <= 1'd1;
12180                 if (1'd0) begin
12181                         litedramcore_trrdcon_ready <= 1'd1;
12182                 end else begin
12183                         litedramcore_trrdcon_ready <= 1'd0;
12184                 end
12185         end else begin
12186                 if ((~litedramcore_trrdcon_ready)) begin
12187                         litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
12188                         if ((litedramcore_trrdcon_count == 1'd1)) begin
12189                                 litedramcore_trrdcon_ready <= 1'd1;
12190                         end
12191                 end
12192         end
12193         litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
12194         if ((litedramcore_tfawcon_count < 3'd4)) begin
12195                 if ((litedramcore_tfawcon_count == 2'd3)) begin
12196                         litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
12197                 end else begin
12198                         litedramcore_tfawcon_ready <= 1'd1;
12199                 end
12200         end
12201         if (litedramcore_tccdcon_valid) begin
12202                 litedramcore_tccdcon_count <= 1'd1;
12203                 if (1'd0) begin
12204                         litedramcore_tccdcon_ready <= 1'd1;
12205                 end else begin
12206                         litedramcore_tccdcon_ready <= 1'd0;
12207                 end
12208         end else begin
12209                 if ((~litedramcore_tccdcon_ready)) begin
12210                         litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
12211                         if ((litedramcore_tccdcon_count == 1'd1)) begin
12212                                 litedramcore_tccdcon_ready <= 1'd1;
12213                         end
12214                 end
12215         end
12216         if (litedramcore_twtrcon_valid) begin
12217                 litedramcore_twtrcon_count <= 3'd6;
12218                 if (1'd0) begin
12219                         litedramcore_twtrcon_ready <= 1'd1;
12220                 end else begin
12221                         litedramcore_twtrcon_ready <= 1'd0;
12222                 end
12223         end else begin
12224                 if ((~litedramcore_twtrcon_ready)) begin
12225                         litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
12226                         if ((litedramcore_twtrcon_count == 1'd1)) begin
12227                                 litedramcore_twtrcon_ready <= 1'd1;
12228                         end
12229                 end
12230         end
12231         litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
12232         litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
12233         litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
12234         litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1;
12235         litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2;
12236         litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
12237         litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
12238         litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
12239         litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
12240         litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
12241         litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
12242         litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
12243         litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
12244         litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
12245         litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8;
12246         litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9;
12247         litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
12248         litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
12249         litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
12250         state <= next_state;
12251         if (litedramcore_dat_w_next_value_ce0) begin
12252                 litedramcore_dat_w <= litedramcore_dat_w_next_value0;
12253         end
12254         if (litedramcore_adr_next_value_ce1) begin
12255                 litedramcore_adr <= litedramcore_adr_next_value1;
12256         end
12257         if (litedramcore_we_next_value_ce2) begin
12258                 litedramcore_we <= litedramcore_we_next_value2;
12259         end
12260         interface0_bank_bus_dat_r <= 1'd0;
12261         if (csrbank0_sel) begin
12262                 case (interface0_bank_bus_adr[8:0])
12263                         1'd0: begin
12264                                 interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
12265                         end
12266                         1'd1: begin
12267                                 interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
12268                         end
12269                 endcase
12270         end
12271         if (csrbank0_init_done0_re) begin
12272                 init_done_storage <= csrbank0_init_done0_r;
12273         end
12274         init_done_re <= csrbank0_init_done0_re;
12275         if (csrbank0_init_error0_re) begin
12276                 init_error_storage <= csrbank0_init_error0_r;
12277         end
12278         init_error_re <= csrbank0_init_error0_re;
12279         interface1_bank_bus_dat_r <= 1'd0;
12280         if (csrbank1_sel) begin
12281                 case (interface1_bank_bus_adr[8:0])
12282                         1'd0: begin
12283                                 interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
12284                         end
12285                         1'd1: begin
12286                                 interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w;
12287                         end
12288                         2'd2: begin
12289                                 interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w;
12290                         end
12291                         2'd3: begin
12292                                 interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w;
12293                         end
12294                         3'd4: begin
12295                                 interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w;
12296                         end
12297                         3'd5: begin
12298                                 interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w;
12299                         end
12300                         3'd6: begin
12301                                 interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w;
12302                         end
12303                 endcase
12304         end
12305         if (csrbank1_dly_sel0_re) begin
12306                 ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
12307         end
12308         ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
12309         ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
12310         interface2_bank_bus_dat_r <= 1'd0;
12311         if (csrbank2_sel) begin
12312                 case (interface2_bank_bus_adr[8:0])
12313                         1'd0: begin
12314                                 interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
12315                         end
12316                         1'd1: begin
12317                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
12318                         end
12319                         2'd2: begin
12320                                 interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
12321                         end
12322                         2'd3: begin
12323                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
12324                         end
12325                         3'd4: begin
12326                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
12327                         end
12328                         3'd5: begin
12329                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
12330                         end
12331                         3'd6: begin
12332                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
12333                         end
12334                         3'd7: begin
12335                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
12336                         end
12337                         4'd8: begin
12338                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
12339                         end
12340                         4'd9: begin
12341                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
12342                         end
12343                         4'd10: begin
12344                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
12345                         end
12346                         4'd11: begin
12347                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
12348                         end
12349                         4'd12: begin
12350                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
12351                         end
12352                         4'd13: begin
12353                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
12354                         end
12355                         4'd14: begin
12356                                 interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
12357                         end
12358                         4'd15: begin
12359                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
12360                         end
12361                         5'd16: begin
12362                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
12363                         end
12364                         5'd17: begin
12365                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
12366                         end
12367                         5'd18: begin
12368                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
12369                         end
12370                         5'd19: begin
12371                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
12372                         end
12373                         5'd20: begin
12374                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
12375                         end
12376                         5'd21: begin
12377                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
12378                         end
12379                         5'd22: begin
12380                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
12381                         end
12382                         5'd23: begin
12383                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
12384                         end
12385                         5'd24: begin
12386                                 interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
12387                         end
12388                 endcase
12389         end
12390         if (csrbank2_dfii_control0_re) begin
12391                 litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
12392         end
12393         litedramcore_re <= csrbank2_dfii_control0_re;
12394         if (csrbank2_dfii_pi0_command0_re) begin
12395                 litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
12396         end
12397         litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
12398         if (csrbank2_dfii_pi0_address0_re) begin
12399                 litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
12400         end
12401         litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
12402         if (csrbank2_dfii_pi0_baddress0_re) begin
12403                 litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
12404         end
12405         litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
12406         if (csrbank2_dfii_pi0_wrdata3_re) begin
12407                 litedramcore_phaseinjector0_wrdata_storage[127:96] <= csrbank2_dfii_pi0_wrdata3_r;
12408         end
12409         if (csrbank2_dfii_pi0_wrdata2_re) begin
12410                 litedramcore_phaseinjector0_wrdata_storage[95:64] <= csrbank2_dfii_pi0_wrdata2_r;
12411         end
12412         if (csrbank2_dfii_pi0_wrdata1_re) begin
12413                 litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
12414         end
12415         if (csrbank2_dfii_pi0_wrdata0_re) begin
12416                 litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
12417         end
12418         litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
12419         litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
12420         if (csrbank2_dfii_pi1_command0_re) begin
12421                 litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
12422         end
12423         litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
12424         if (csrbank2_dfii_pi1_address0_re) begin
12425                 litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
12426         end
12427         litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
12428         if (csrbank2_dfii_pi1_baddress0_re) begin
12429                 litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
12430         end
12431         litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
12432         if (csrbank2_dfii_pi1_wrdata3_re) begin
12433                 litedramcore_phaseinjector1_wrdata_storage[127:96] <= csrbank2_dfii_pi1_wrdata3_r;
12434         end
12435         if (csrbank2_dfii_pi1_wrdata2_re) begin
12436                 litedramcore_phaseinjector1_wrdata_storage[95:64] <= csrbank2_dfii_pi1_wrdata2_r;
12437         end
12438         if (csrbank2_dfii_pi1_wrdata1_re) begin
12439                 litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
12440         end
12441         if (csrbank2_dfii_pi1_wrdata0_re) begin
12442                 litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
12443         end
12444         litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
12445         litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
12446         if (sys_rst) begin
12447                 ddrphy_dly_sel_storage <= 4'd0;
12448                 ddrphy_dly_sel_re <= 1'd0;
12449                 ddrphy_burstdet_seen_status <= 4'd0;
12450                 ddrphy_burstdet_seen_re <= 1'd0;
12451                 ddrphy_rdly0 <= 7'd0;
12452                 ddrphy_burstdet_d0 <= 1'd0;
12453                 ddrphy_dm_o_data_d0 <= 8'd0;
12454                 ddrphy_dm_o_data_muxed0 <= 4'd0;
12455                 ddrphy_dq_o_data_d0 <= 8'd0;
12456                 ddrphy_dq_o_data_muxed0 <= 4'd0;
12457                 ddrphy_bitslip0_value <= 2'd0;
12458                 ddrphy_dq_i_bitslip_o_d0 <= 4'd0;
12459                 ddrphy_dq_o_data_d1 <= 8'd0;
12460                 ddrphy_dq_o_data_muxed1 <= 4'd0;
12461                 ddrphy_bitslip1_value <= 2'd0;
12462                 ddrphy_dq_i_bitslip_o_d1 <= 4'd0;
12463                 ddrphy_dq_o_data_d2 <= 8'd0;
12464                 ddrphy_dq_o_data_muxed2 <= 4'd0;
12465                 ddrphy_bitslip2_value <= 2'd0;
12466                 ddrphy_dq_i_bitslip_o_d2 <= 4'd0;
12467                 ddrphy_dq_o_data_d3 <= 8'd0;
12468                 ddrphy_dq_o_data_muxed3 <= 4'd0;
12469                 ddrphy_bitslip3_value <= 2'd0;
12470                 ddrphy_dq_i_bitslip_o_d3 <= 4'd0;
12471                 ddrphy_dq_o_data_d4 <= 8'd0;
12472                 ddrphy_dq_o_data_muxed4 <= 4'd0;
12473                 ddrphy_bitslip4_value <= 2'd0;
12474                 ddrphy_dq_i_bitslip_o_d4 <= 4'd0;
12475                 ddrphy_dq_o_data_d5 <= 8'd0;
12476                 ddrphy_dq_o_data_muxed5 <= 4'd0;
12477                 ddrphy_bitslip5_value <= 2'd0;
12478                 ddrphy_dq_i_bitslip_o_d5 <= 4'd0;
12479                 ddrphy_dq_o_data_d6 <= 8'd0;
12480                 ddrphy_dq_o_data_muxed6 <= 4'd0;
12481                 ddrphy_bitslip6_value <= 2'd0;
12482                 ddrphy_dq_i_bitslip_o_d6 <= 4'd0;
12483                 ddrphy_dq_o_data_d7 <= 8'd0;
12484                 ddrphy_dq_o_data_muxed7 <= 4'd0;
12485                 ddrphy_bitslip7_value <= 2'd0;
12486                 ddrphy_dq_i_bitslip_o_d7 <= 4'd0;
12487                 ddrphy_rdly1 <= 7'd0;
12488                 ddrphy_burstdet_d1 <= 1'd0;
12489                 ddrphy_dm_o_data_d1 <= 8'd0;
12490                 ddrphy_dm_o_data_muxed1 <= 4'd0;
12491                 ddrphy_dq_o_data_d8 <= 8'd0;
12492                 ddrphy_dq_o_data_muxed8 <= 4'd0;
12493                 ddrphy_bitslip8_value <= 2'd0;
12494                 ddrphy_dq_i_bitslip_o_d8 <= 4'd0;
12495                 ddrphy_dq_o_data_d9 <= 8'd0;
12496                 ddrphy_dq_o_data_muxed9 <= 4'd0;
12497                 ddrphy_bitslip9_value <= 2'd0;
12498                 ddrphy_dq_i_bitslip_o_d9 <= 4'd0;
12499                 ddrphy_dq_o_data_d10 <= 8'd0;
12500                 ddrphy_dq_o_data_muxed10 <= 4'd0;
12501                 ddrphy_bitslip10_value <= 2'd0;
12502                 ddrphy_dq_i_bitslip_o_d10 <= 4'd0;
12503                 ddrphy_dq_o_data_d11 <= 8'd0;
12504                 ddrphy_dq_o_data_muxed11 <= 4'd0;
12505                 ddrphy_bitslip11_value <= 2'd0;
12506                 ddrphy_dq_i_bitslip_o_d11 <= 4'd0;
12507                 ddrphy_dq_o_data_d12 <= 8'd0;
12508                 ddrphy_dq_o_data_muxed12 <= 4'd0;
12509                 ddrphy_bitslip12_value <= 2'd0;
12510                 ddrphy_dq_i_bitslip_o_d12 <= 4'd0;
12511                 ddrphy_dq_o_data_d13 <= 8'd0;
12512                 ddrphy_dq_o_data_muxed13 <= 4'd0;
12513                 ddrphy_bitslip13_value <= 2'd0;
12514                 ddrphy_dq_i_bitslip_o_d13 <= 4'd0;
12515                 ddrphy_dq_o_data_d14 <= 8'd0;
12516                 ddrphy_dq_o_data_muxed14 <= 4'd0;
12517                 ddrphy_bitslip14_value <= 2'd0;
12518                 ddrphy_dq_i_bitslip_o_d14 <= 4'd0;
12519                 ddrphy_dq_o_data_d15 <= 8'd0;
12520                 ddrphy_dq_o_data_muxed15 <= 4'd0;
12521                 ddrphy_bitslip15_value <= 2'd0;
12522                 ddrphy_dq_i_bitslip_o_d15 <= 4'd0;
12523                 ddrphy_rdly2 <= 7'd0;
12524                 ddrphy_burstdet_d2 <= 1'd0;
12525                 ddrphy_dm_o_data_d2 <= 8'd0;
12526                 ddrphy_dm_o_data_muxed2 <= 4'd0;
12527                 ddrphy_dq_o_data_d16 <= 8'd0;
12528                 ddrphy_dq_o_data_muxed16 <= 4'd0;
12529                 ddrphy_bitslip16_value <= 2'd0;
12530                 ddrphy_dq_i_bitslip_o_d16 <= 4'd0;
12531                 ddrphy_dq_o_data_d17 <= 8'd0;
12532                 ddrphy_dq_o_data_muxed17 <= 4'd0;
12533                 ddrphy_bitslip17_value <= 2'd0;
12534                 ddrphy_dq_i_bitslip_o_d17 <= 4'd0;
12535                 ddrphy_dq_o_data_d18 <= 8'd0;
12536                 ddrphy_dq_o_data_muxed18 <= 4'd0;
12537                 ddrphy_bitslip18_value <= 2'd0;
12538                 ddrphy_dq_i_bitslip_o_d18 <= 4'd0;
12539                 ddrphy_dq_o_data_d19 <= 8'd0;
12540                 ddrphy_dq_o_data_muxed19 <= 4'd0;
12541                 ddrphy_bitslip19_value <= 2'd0;
12542                 ddrphy_dq_i_bitslip_o_d19 <= 4'd0;
12543                 ddrphy_dq_o_data_d20 <= 8'd0;
12544                 ddrphy_dq_o_data_muxed20 <= 4'd0;
12545                 ddrphy_bitslip20_value <= 2'd0;
12546                 ddrphy_dq_i_bitslip_o_d20 <= 4'd0;
12547                 ddrphy_dq_o_data_d21 <= 8'd0;
12548                 ddrphy_dq_o_data_muxed21 <= 4'd0;
12549                 ddrphy_bitslip21_value <= 2'd0;
12550                 ddrphy_dq_i_bitslip_o_d21 <= 4'd0;
12551                 ddrphy_dq_o_data_d22 <= 8'd0;
12552                 ddrphy_dq_o_data_muxed22 <= 4'd0;
12553                 ddrphy_bitslip22_value <= 2'd0;
12554                 ddrphy_dq_i_bitslip_o_d22 <= 4'd0;
12555                 ddrphy_dq_o_data_d23 <= 8'd0;
12556                 ddrphy_dq_o_data_muxed23 <= 4'd0;
12557                 ddrphy_bitslip23_value <= 2'd0;
12558                 ddrphy_dq_i_bitslip_o_d23 <= 4'd0;
12559                 ddrphy_rdly3 <= 7'd0;
12560                 ddrphy_burstdet_d3 <= 1'd0;
12561                 ddrphy_dm_o_data_d3 <= 8'd0;
12562                 ddrphy_dm_o_data_muxed3 <= 4'd0;
12563                 ddrphy_dq_o_data_d24 <= 8'd0;
12564                 ddrphy_dq_o_data_muxed24 <= 4'd0;
12565                 ddrphy_bitslip24_value <= 2'd0;
12566                 ddrphy_dq_i_bitslip_o_d24 <= 4'd0;
12567                 ddrphy_dq_o_data_d25 <= 8'd0;
12568                 ddrphy_dq_o_data_muxed25 <= 4'd0;
12569                 ddrphy_bitslip25_value <= 2'd0;
12570                 ddrphy_dq_i_bitslip_o_d25 <= 4'd0;
12571                 ddrphy_dq_o_data_d26 <= 8'd0;
12572                 ddrphy_dq_o_data_muxed26 <= 4'd0;
12573                 ddrphy_bitslip26_value <= 2'd0;
12574                 ddrphy_dq_i_bitslip_o_d26 <= 4'd0;
12575                 ddrphy_dq_o_data_d27 <= 8'd0;
12576                 ddrphy_dq_o_data_muxed27 <= 4'd0;
12577                 ddrphy_bitslip27_value <= 2'd0;
12578                 ddrphy_dq_i_bitslip_o_d27 <= 4'd0;
12579                 ddrphy_dq_o_data_d28 <= 8'd0;
12580                 ddrphy_dq_o_data_muxed28 <= 4'd0;
12581                 ddrphy_bitslip28_value <= 2'd0;
12582                 ddrphy_dq_i_bitslip_o_d28 <= 4'd0;
12583                 ddrphy_dq_o_data_d29 <= 8'd0;
12584                 ddrphy_dq_o_data_muxed29 <= 4'd0;
12585                 ddrphy_bitslip29_value <= 2'd0;
12586                 ddrphy_dq_i_bitslip_o_d29 <= 4'd0;
12587                 ddrphy_dq_o_data_d30 <= 8'd0;
12588                 ddrphy_dq_o_data_muxed30 <= 4'd0;
12589                 ddrphy_bitslip30_value <= 2'd0;
12590                 ddrphy_dq_i_bitslip_o_d30 <= 4'd0;
12591                 ddrphy_dq_o_data_d31 <= 8'd0;
12592                 ddrphy_dq_o_data_muxed31 <= 4'd0;
12593                 ddrphy_bitslip31_value <= 2'd0;
12594                 ddrphy_dq_i_bitslip_o_d31 <= 4'd0;
12595                 ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
12596                 ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
12597                 ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
12598                 ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
12599                 ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
12600                 ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
12601                 ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
12602                 ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
12603                 ddrphy_rddata_en_tappeddelayline8 <= 1'd0;
12604                 ddrphy_rddata_en_tappeddelayline9 <= 1'd0;
12605                 ddrphy_rddata_en_tappeddelayline10 <= 1'd0;
12606                 ddrphy_rddata_en_tappeddelayline11 <= 1'd0;
12607                 ddrphy_rddata_en_tappeddelayline12 <= 1'd0;
12608                 ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
12609                 ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
12610                 ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
12611                 ddrphy_wrdata_en_tappeddelayline3 <= 1'd0;
12612                 ddrphy_wrdata_en_tappeddelayline4 <= 1'd0;
12613                 ddrphy_wrdata_en_tappeddelayline5 <= 1'd0;
12614                 ddrphy_wrdata_en_tappeddelayline6 <= 1'd0;
12615                 litedramcore_storage <= 4'd1;
12616                 litedramcore_re <= 1'd0;
12617                 litedramcore_phaseinjector0_command_storage <= 6'd0;
12618                 litedramcore_phaseinjector0_command_re <= 1'd0;
12619                 litedramcore_phaseinjector0_address_re <= 1'd0;
12620                 litedramcore_phaseinjector0_baddress_re <= 1'd0;
12621                 litedramcore_phaseinjector0_wrdata_re <= 1'd0;
12622                 litedramcore_phaseinjector0_rddata_status <= 128'd0;
12623                 litedramcore_phaseinjector0_rddata_re <= 1'd0;
12624                 litedramcore_phaseinjector1_command_storage <= 6'd0;
12625                 litedramcore_phaseinjector1_command_re <= 1'd0;
12626                 litedramcore_phaseinjector1_address_re <= 1'd0;
12627                 litedramcore_phaseinjector1_baddress_re <= 1'd0;
12628                 litedramcore_phaseinjector1_wrdata_re <= 1'd0;
12629                 litedramcore_phaseinjector1_rddata_status <= 128'd0;
12630                 litedramcore_phaseinjector1_rddata_re <= 1'd0;
12631                 litedramcore_dfi_p0_address <= 15'd0;
12632                 litedramcore_dfi_p0_bank <= 3'd0;
12633                 litedramcore_dfi_p0_cas_n <= 1'd1;
12634                 litedramcore_dfi_p0_cs_n <= 1'd1;
12635                 litedramcore_dfi_p0_ras_n <= 1'd1;
12636                 litedramcore_dfi_p0_we_n <= 1'd1;
12637                 litedramcore_dfi_p0_wrdata_en <= 1'd0;
12638                 litedramcore_dfi_p0_rddata_en <= 1'd0;
12639                 litedramcore_dfi_p1_address <= 15'd0;
12640                 litedramcore_dfi_p1_bank <= 3'd0;
12641                 litedramcore_dfi_p1_cas_n <= 1'd1;
12642                 litedramcore_dfi_p1_cs_n <= 1'd1;
12643                 litedramcore_dfi_p1_ras_n <= 1'd1;
12644                 litedramcore_dfi_p1_we_n <= 1'd1;
12645                 litedramcore_dfi_p1_wrdata_en <= 1'd0;
12646                 litedramcore_dfi_p1_rddata_en <= 1'd0;
12647                 litedramcore_cmd_payload_a <= 15'd0;
12648                 litedramcore_cmd_payload_ba <= 3'd0;
12649                 litedramcore_cmd_payload_cas <= 1'd0;
12650                 litedramcore_cmd_payload_ras <= 1'd0;
12651                 litedramcore_cmd_payload_we <= 1'd0;
12652                 litedramcore_timer_count1 <= 9'd374;
12653                 litedramcore_postponer_req_o <= 1'd0;
12654                 litedramcore_postponer_count <= 1'd0;
12655                 litedramcore_sequencer_done1 <= 1'd0;
12656                 litedramcore_sequencer_counter <= 7'd0;
12657                 litedramcore_sequencer_count <= 1'd0;
12658                 litedramcore_zqcs_timer_count1 <= 26'd47999999;
12659                 litedramcore_zqcs_executer_done <= 1'd0;
12660                 litedramcore_zqcs_executer_counter <= 6'd0;
12661                 litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
12662                 litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
12663                 litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
12664                 litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
12665                 litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
12666                 litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
12667                 litedramcore_bankmachine0_row <= 15'd0;
12668                 litedramcore_bankmachine0_row_opened <= 1'd0;
12669                 litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
12670                 litedramcore_bankmachine0_twtpcon_count <= 3'd0;
12671                 litedramcore_bankmachine0_trccon_ready <= 1'd0;
12672                 litedramcore_bankmachine0_trccon_count <= 2'd0;
12673                 litedramcore_bankmachine0_trascon_ready <= 1'd0;
12674                 litedramcore_bankmachine0_trascon_count <= 2'd0;
12675                 litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
12676                 litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
12677                 litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
12678                 litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
12679                 litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
12680                 litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
12681                 litedramcore_bankmachine1_row <= 15'd0;
12682                 litedramcore_bankmachine1_row_opened <= 1'd0;
12683                 litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
12684                 litedramcore_bankmachine1_twtpcon_count <= 3'd0;
12685                 litedramcore_bankmachine1_trccon_ready <= 1'd0;
12686                 litedramcore_bankmachine1_trccon_count <= 2'd0;
12687                 litedramcore_bankmachine1_trascon_ready <= 1'd0;
12688                 litedramcore_bankmachine1_trascon_count <= 2'd0;
12689                 litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
12690                 litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
12691                 litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
12692                 litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
12693                 litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
12694                 litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
12695                 litedramcore_bankmachine2_row <= 15'd0;
12696                 litedramcore_bankmachine2_row_opened <= 1'd0;
12697                 litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
12698                 litedramcore_bankmachine2_twtpcon_count <= 3'd0;
12699                 litedramcore_bankmachine2_trccon_ready <= 1'd0;
12700                 litedramcore_bankmachine2_trccon_count <= 2'd0;
12701                 litedramcore_bankmachine2_trascon_ready <= 1'd0;
12702                 litedramcore_bankmachine2_trascon_count <= 2'd0;
12703                 litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
12704                 litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
12705                 litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
12706                 litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
12707                 litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
12708                 litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
12709                 litedramcore_bankmachine3_row <= 15'd0;
12710                 litedramcore_bankmachine3_row_opened <= 1'd0;
12711                 litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
12712                 litedramcore_bankmachine3_twtpcon_count <= 3'd0;
12713                 litedramcore_bankmachine3_trccon_ready <= 1'd0;
12714                 litedramcore_bankmachine3_trccon_count <= 2'd0;
12715                 litedramcore_bankmachine3_trascon_ready <= 1'd0;
12716                 litedramcore_bankmachine3_trascon_count <= 2'd0;
12717                 litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
12718                 litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
12719                 litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
12720                 litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
12721                 litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
12722                 litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
12723                 litedramcore_bankmachine4_row <= 15'd0;
12724                 litedramcore_bankmachine4_row_opened <= 1'd0;
12725                 litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
12726                 litedramcore_bankmachine4_twtpcon_count <= 3'd0;
12727                 litedramcore_bankmachine4_trccon_ready <= 1'd0;
12728                 litedramcore_bankmachine4_trccon_count <= 2'd0;
12729                 litedramcore_bankmachine4_trascon_ready <= 1'd0;
12730                 litedramcore_bankmachine4_trascon_count <= 2'd0;
12731                 litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
12732                 litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
12733                 litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
12734                 litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
12735                 litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
12736                 litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
12737                 litedramcore_bankmachine5_row <= 15'd0;
12738                 litedramcore_bankmachine5_row_opened <= 1'd0;
12739                 litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
12740                 litedramcore_bankmachine5_twtpcon_count <= 3'd0;
12741                 litedramcore_bankmachine5_trccon_ready <= 1'd0;
12742                 litedramcore_bankmachine5_trccon_count <= 2'd0;
12743                 litedramcore_bankmachine5_trascon_ready <= 1'd0;
12744                 litedramcore_bankmachine5_trascon_count <= 2'd0;
12745                 litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
12746                 litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
12747                 litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
12748                 litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
12749                 litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
12750                 litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
12751                 litedramcore_bankmachine6_row <= 15'd0;
12752                 litedramcore_bankmachine6_row_opened <= 1'd0;
12753                 litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
12754                 litedramcore_bankmachine6_twtpcon_count <= 3'd0;
12755                 litedramcore_bankmachine6_trccon_ready <= 1'd0;
12756                 litedramcore_bankmachine6_trccon_count <= 2'd0;
12757                 litedramcore_bankmachine6_trascon_ready <= 1'd0;
12758                 litedramcore_bankmachine6_trascon_count <= 2'd0;
12759                 litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
12760                 litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
12761                 litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
12762                 litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
12763                 litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
12764                 litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
12765                 litedramcore_bankmachine7_row <= 15'd0;
12766                 litedramcore_bankmachine7_row_opened <= 1'd0;
12767                 litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
12768                 litedramcore_bankmachine7_twtpcon_count <= 3'd0;
12769                 litedramcore_bankmachine7_trccon_ready <= 1'd0;
12770                 litedramcore_bankmachine7_trccon_count <= 2'd0;
12771                 litedramcore_bankmachine7_trascon_ready <= 1'd0;
12772                 litedramcore_bankmachine7_trascon_count <= 2'd0;
12773                 litedramcore_choose_cmd_grant <= 3'd0;
12774                 litedramcore_choose_req_grant <= 3'd0;
12775                 litedramcore_trrdcon_ready <= 1'd0;
12776                 litedramcore_trrdcon_count <= 1'd0;
12777                 litedramcore_tfawcon_ready <= 1'd1;
12778                 litedramcore_tfawcon_window <= 3'd0;
12779                 litedramcore_tccdcon_ready <= 1'd0;
12780                 litedramcore_tccdcon_count <= 1'd0;
12781                 litedramcore_twtrcon_ready <= 1'd0;
12782                 litedramcore_twtrcon_count <= 3'd0;
12783                 litedramcore_time0 <= 5'd0;
12784                 litedramcore_time1 <= 4'd0;
12785                 init_done_storage <= 1'd0;
12786                 init_done_re <= 1'd0;
12787                 init_error_storage <= 1'd0;
12788                 init_error_re <= 1'd0;
12789                 litedramcore_refresher_state <= 2'd0;
12790                 litedramcore_bankmachine0_state <= 3'd0;
12791                 litedramcore_bankmachine1_state <= 3'd0;
12792                 litedramcore_bankmachine2_state <= 3'd0;
12793                 litedramcore_bankmachine3_state <= 3'd0;
12794                 litedramcore_bankmachine4_state <= 3'd0;
12795                 litedramcore_bankmachine5_state <= 3'd0;
12796                 litedramcore_bankmachine6_state <= 3'd0;
12797                 litedramcore_bankmachine7_state <= 3'd0;
12798                 litedramcore_multiplexer_state <= 4'd0;
12799                 litedramcore_new_master_wdata_ready0 <= 1'd0;
12800                 litedramcore_new_master_wdata_ready1 <= 1'd0;
12801                 litedramcore_new_master_wdata_ready2 <= 1'd0;
12802                 litedramcore_new_master_wdata_ready3 <= 1'd0;
12803                 litedramcore_new_master_rdata_valid0 <= 1'd0;
12804                 litedramcore_new_master_rdata_valid1 <= 1'd0;
12805                 litedramcore_new_master_rdata_valid2 <= 1'd0;
12806                 litedramcore_new_master_rdata_valid3 <= 1'd0;
12807                 litedramcore_new_master_rdata_valid4 <= 1'd0;
12808                 litedramcore_new_master_rdata_valid5 <= 1'd0;
12809                 litedramcore_new_master_rdata_valid6 <= 1'd0;
12810                 litedramcore_new_master_rdata_valid7 <= 1'd0;
12811                 litedramcore_new_master_rdata_valid8 <= 1'd0;
12812                 litedramcore_new_master_rdata_valid9 <= 1'd0;
12813                 litedramcore_new_master_rdata_valid10 <= 1'd0;
12814                 litedramcore_new_master_rdata_valid11 <= 1'd0;
12815                 litedramcore_new_master_rdata_valid12 <= 1'd0;
12816                 litedramcore_new_master_rdata_valid13 <= 1'd0;
12817                 litedramcore_we <= 1'd0;
12818                 state <= 2'd0;
12819         end
12820 end
12821
12822
12823 //------------------------------------------------------------------------------
12824 // Specialized Logic
12825 //------------------------------------------------------------------------------
12826
12827 ECLKBRIDGECS ECLKBRIDGECS(
12828         .CLK0(sys2x_i_clk),
12829         .SEL(1'd0),
12830         .ECSOUT(crg_sys2x_clk_ecsout)
12831 );
12832
12833 ECLKSYNCB ECLKSYNCB(
12834         .ECLKI(crg_sys2x_clk_ecsout),
12835         .STOP(crg_stop),
12836         .ECLKO(sys2x_clk)
12837 );
12838
12839 CLKDIVF #(
12840         .DIV("2.0")
12841 ) CLKDIVF (
12842         .ALIGNWD(1'd0),
12843         .CLKI(sys2x_clk),
12844         .RST(crg_reset0),
12845         .CDIVX(sys_clk)
12846 );
12847
12848 DDRDLLA DDRDLLA(
12849         .CLK(sys2x_clk),
12850         .FREEZE(ddrphy_freeze),
12851         .RST(init_rst),
12852         .UDDCNTLN((~ddrphy_update)),
12853         .DDRDEL(ddrphy_delay1),
12854         .LOCK(ddrphy_lock0)
12855 );
12856
12857 ODDRX2F ODDRX2F(
12858         .D0(1'd0),
12859         .D1(1'd1),
12860         .D2(1'd0),
12861         .D3(1'd1),
12862         .ECLK(sys2x_clk),
12863         .RST(sys_rst),
12864         .SCLK(sys_clk),
12865         .Q(ddrphy_pad_oddrx2f0)
12866 );
12867
12868 DELAYG #(
12869         .DEL_VALUE(7'd100)
12870 ) DELAYG (
12871         .A(ddrphy_pad_oddrx2f0),
12872         .Z(ddram_clk_p[0])
12873 );
12874
12875 ODDRX2F ODDRX2F_1(
12876         .D0(1'd0),
12877         .D1(1'd1),
12878         .D2(1'd0),
12879         .D3(1'd1),
12880         .ECLK(sys2x_clk),
12881         .RST(sys_rst),
12882         .SCLK(sys_clk),
12883         .Q(ddrphy_pad_oddrx2f1)
12884 );
12885
12886 DELAYG #(
12887         .DEL_VALUE(7'd100)
12888 ) DELAYG_1 (
12889         .A(ddrphy_pad_oddrx2f1),
12890         .Z(ddram_clk_p[1])
12891 );
12892
12893 ODDRX2F ODDRX2F_2(
12894         .D0(ddrphy_dfi_p0_reset_n),
12895         .D1(ddrphy_dfi_p0_reset_n),
12896         .D2(ddrphy_dfi_p1_reset_n),
12897         .D3(ddrphy_dfi_p1_reset_n),
12898         .ECLK(sys2x_clk),
12899         .RST(sys_rst),
12900         .SCLK(sys_clk),
12901         .Q(ddrphy_pad_oddrx2f2)
12902 );
12903
12904 DELAYG #(
12905         .DEL_VALUE(7'd100)
12906 ) DELAYG_2 (
12907         .A(ddrphy_pad_oddrx2f2),
12908         .Z(ddram_reset_n)
12909 );
12910
12911 ODDRX2F ODDRX2F_3(
12912         .D0(ddrphy_dfi_p0_cs_n),
12913         .D1(ddrphy_dfi_p0_cs_n),
12914         .D2(ddrphy_dfi_p1_cs_n),
12915         .D3(ddrphy_dfi_p1_cs_n),
12916         .ECLK(sys2x_clk),
12917         .RST(sys_rst),
12918         .SCLK(sys_clk),
12919         .Q(ddrphy_pad_oddrx2f3)
12920 );
12921
12922 DELAYG #(
12923         .DEL_VALUE(7'd100)
12924 ) DELAYG_3 (
12925         .A(ddrphy_pad_oddrx2f3),
12926         .Z(ddram_cs_n)
12927 );
12928
12929 ODDRX2F ODDRX2F_4(
12930         .D0(ddrphy_dfi_p0_address[0]),
12931         .D1(ddrphy_dfi_p0_address[0]),
12932         .D2(ddrphy_dfi_p1_address[0]),
12933         .D3(ddrphy_dfi_p1_address[0]),
12934         .ECLK(sys2x_clk),
12935         .RST(sys_rst),
12936         .SCLK(sys_clk),
12937         .Q(ddrphy_pad_oddrx2f4)
12938 );
12939
12940 DELAYG #(
12941         .DEL_VALUE(7'd100)
12942 ) DELAYG_4 (
12943         .A(ddrphy_pad_oddrx2f4),
12944         .Z(ddram_a[0])
12945 );
12946
12947 ODDRX2F ODDRX2F_5(
12948         .D0(ddrphy_dfi_p0_address[1]),
12949         .D1(ddrphy_dfi_p0_address[1]),
12950         .D2(ddrphy_dfi_p1_address[1]),
12951         .D3(ddrphy_dfi_p1_address[1]),
12952         .ECLK(sys2x_clk),
12953         .RST(sys_rst),
12954         .SCLK(sys_clk),
12955         .Q(ddrphy_pad_oddrx2f5)
12956 );
12957
12958 DELAYG #(
12959         .DEL_VALUE(7'd100)
12960 ) DELAYG_5 (
12961         .A(ddrphy_pad_oddrx2f5),
12962         .Z(ddram_a[1])
12963 );
12964
12965 ODDRX2F ODDRX2F_6(
12966         .D0(ddrphy_dfi_p0_address[2]),
12967         .D1(ddrphy_dfi_p0_address[2]),
12968         .D2(ddrphy_dfi_p1_address[2]),
12969         .D3(ddrphy_dfi_p1_address[2]),
12970         .ECLK(sys2x_clk),
12971         .RST(sys_rst),
12972         .SCLK(sys_clk),
12973         .Q(ddrphy_pad_oddrx2f6)
12974 );
12975
12976 DELAYG #(
12977         .DEL_VALUE(7'd100)
12978 ) DELAYG_6 (
12979         .A(ddrphy_pad_oddrx2f6),
12980         .Z(ddram_a[2])
12981 );
12982
12983 ODDRX2F ODDRX2F_7(
12984         .D0(ddrphy_dfi_p0_address[3]),
12985         .D1(ddrphy_dfi_p0_address[3]),
12986         .D2(ddrphy_dfi_p1_address[3]),
12987         .D3(ddrphy_dfi_p1_address[3]),
12988         .ECLK(sys2x_clk),
12989         .RST(sys_rst),
12990         .SCLK(sys_clk),
12991         .Q(ddrphy_pad_oddrx2f7)
12992 );
12993
12994 DELAYG #(
12995         .DEL_VALUE(7'd100)
12996 ) DELAYG_7 (
12997         .A(ddrphy_pad_oddrx2f7),
12998         .Z(ddram_a[3])
12999 );
13000
13001 ODDRX2F ODDRX2F_8(
13002         .D0(ddrphy_dfi_p0_address[4]),
13003         .D1(ddrphy_dfi_p0_address[4]),
13004         .D2(ddrphy_dfi_p1_address[4]),
13005         .D3(ddrphy_dfi_p1_address[4]),
13006         .ECLK(sys2x_clk),
13007         .RST(sys_rst),
13008         .SCLK(sys_clk),
13009         .Q(ddrphy_pad_oddrx2f8)
13010 );
13011
13012 DELAYG #(
13013         .DEL_VALUE(7'd100)
13014 ) DELAYG_8 (
13015         .A(ddrphy_pad_oddrx2f8),
13016         .Z(ddram_a[4])
13017 );
13018
13019 ODDRX2F ODDRX2F_9(
13020         .D0(ddrphy_dfi_p0_address[5]),
13021         .D1(ddrphy_dfi_p0_address[5]),
13022         .D2(ddrphy_dfi_p1_address[5]),
13023         .D3(ddrphy_dfi_p1_address[5]),
13024         .ECLK(sys2x_clk),
13025         .RST(sys_rst),
13026         .SCLK(sys_clk),
13027         .Q(ddrphy_pad_oddrx2f9)
13028 );
13029
13030 DELAYG #(
13031         .DEL_VALUE(7'd100)
13032 ) DELAYG_9 (
13033         .A(ddrphy_pad_oddrx2f9),
13034         .Z(ddram_a[5])
13035 );
13036
13037 ODDRX2F ODDRX2F_10(
13038         .D0(ddrphy_dfi_p0_address[6]),
13039         .D1(ddrphy_dfi_p0_address[6]),
13040         .D2(ddrphy_dfi_p1_address[6]),
13041         .D3(ddrphy_dfi_p1_address[6]),
13042         .ECLK(sys2x_clk),
13043         .RST(sys_rst),
13044         .SCLK(sys_clk),
13045         .Q(ddrphy_pad_oddrx2f10)
13046 );
13047
13048 DELAYG #(
13049         .DEL_VALUE(7'd100)
13050 ) DELAYG_10 (
13051         .A(ddrphy_pad_oddrx2f10),
13052         .Z(ddram_a[6])
13053 );
13054
13055 ODDRX2F ODDRX2F_11(
13056         .D0(ddrphy_dfi_p0_address[7]),
13057         .D1(ddrphy_dfi_p0_address[7]),
13058         .D2(ddrphy_dfi_p1_address[7]),
13059         .D3(ddrphy_dfi_p1_address[7]),
13060         .ECLK(sys2x_clk),
13061         .RST(sys_rst),
13062         .SCLK(sys_clk),
13063         .Q(ddrphy_pad_oddrx2f11)
13064 );
13065
13066 DELAYG #(
13067         .DEL_VALUE(7'd100)
13068 ) DELAYG_11 (
13069         .A(ddrphy_pad_oddrx2f11),
13070         .Z(ddram_a[7])
13071 );
13072
13073 ODDRX2F ODDRX2F_12(
13074         .D0(ddrphy_dfi_p0_address[8]),
13075         .D1(ddrphy_dfi_p0_address[8]),
13076         .D2(ddrphy_dfi_p1_address[8]),
13077         .D3(ddrphy_dfi_p1_address[8]),
13078         .ECLK(sys2x_clk),
13079         .RST(sys_rst),
13080         .SCLK(sys_clk),
13081         .Q(ddrphy_pad_oddrx2f12)
13082 );
13083
13084 DELAYG #(
13085         .DEL_VALUE(7'd100)
13086 ) DELAYG_12 (
13087         .A(ddrphy_pad_oddrx2f12),
13088         .Z(ddram_a[8])
13089 );
13090
13091 ODDRX2F ODDRX2F_13(
13092         .D0(ddrphy_dfi_p0_address[9]),
13093         .D1(ddrphy_dfi_p0_address[9]),
13094         .D2(ddrphy_dfi_p1_address[9]),
13095         .D3(ddrphy_dfi_p1_address[9]),
13096         .ECLK(sys2x_clk),
13097         .RST(sys_rst),
13098         .SCLK(sys_clk),
13099         .Q(ddrphy_pad_oddrx2f13)
13100 );
13101
13102 DELAYG #(
13103         .DEL_VALUE(7'd100)
13104 ) DELAYG_13 (
13105         .A(ddrphy_pad_oddrx2f13),
13106         .Z(ddram_a[9])
13107 );
13108
13109 ODDRX2F ODDRX2F_14(
13110         .D0(ddrphy_dfi_p0_address[10]),
13111         .D1(ddrphy_dfi_p0_address[10]),
13112         .D2(ddrphy_dfi_p1_address[10]),
13113         .D3(ddrphy_dfi_p1_address[10]),
13114         .ECLK(sys2x_clk),
13115         .RST(sys_rst),
13116         .SCLK(sys_clk),
13117         .Q(ddrphy_pad_oddrx2f14)
13118 );
13119
13120 DELAYG #(
13121         .DEL_VALUE(7'd100)
13122 ) DELAYG_14 (
13123         .A(ddrphy_pad_oddrx2f14),
13124         .Z(ddram_a[10])
13125 );
13126
13127 ODDRX2F ODDRX2F_15(
13128         .D0(ddrphy_dfi_p0_address[11]),
13129         .D1(ddrphy_dfi_p0_address[11]),
13130         .D2(ddrphy_dfi_p1_address[11]),
13131         .D3(ddrphy_dfi_p1_address[11]),
13132         .ECLK(sys2x_clk),
13133         .RST(sys_rst),
13134         .SCLK(sys_clk),
13135         .Q(ddrphy_pad_oddrx2f15)
13136 );
13137
13138 DELAYG #(
13139         .DEL_VALUE(7'd100)
13140 ) DELAYG_15 (
13141         .A(ddrphy_pad_oddrx2f15),
13142         .Z(ddram_a[11])
13143 );
13144
13145 ODDRX2F ODDRX2F_16(
13146         .D0(ddrphy_dfi_p0_address[12]),
13147         .D1(ddrphy_dfi_p0_address[12]),
13148         .D2(ddrphy_dfi_p1_address[12]),
13149         .D3(ddrphy_dfi_p1_address[12]),
13150         .ECLK(sys2x_clk),
13151         .RST(sys_rst),
13152         .SCLK(sys_clk),
13153         .Q(ddrphy_pad_oddrx2f16)
13154 );
13155
13156 DELAYG #(
13157         .DEL_VALUE(7'd100)
13158 ) DELAYG_16 (
13159         .A(ddrphy_pad_oddrx2f16),
13160         .Z(ddram_a[12])
13161 );
13162
13163 ODDRX2F ODDRX2F_17(
13164         .D0(ddrphy_dfi_p0_address[13]),
13165         .D1(ddrphy_dfi_p0_address[13]),
13166         .D2(ddrphy_dfi_p1_address[13]),
13167         .D3(ddrphy_dfi_p1_address[13]),
13168         .ECLK(sys2x_clk),
13169         .RST(sys_rst),
13170         .SCLK(sys_clk),
13171         .Q(ddrphy_pad_oddrx2f17)
13172 );
13173
13174 DELAYG #(
13175         .DEL_VALUE(7'd100)
13176 ) DELAYG_17 (
13177         .A(ddrphy_pad_oddrx2f17),
13178         .Z(ddram_a[13])
13179 );
13180
13181 ODDRX2F ODDRX2F_18(
13182         .D0(ddrphy_dfi_p0_address[14]),
13183         .D1(ddrphy_dfi_p0_address[14]),
13184         .D2(ddrphy_dfi_p1_address[14]),
13185         .D3(ddrphy_dfi_p1_address[14]),
13186         .ECLK(sys2x_clk),
13187         .RST(sys_rst),
13188         .SCLK(sys_clk),
13189         .Q(ddrphy_pad_oddrx2f18)
13190 );
13191
13192 DELAYG #(
13193         .DEL_VALUE(7'd100)
13194 ) DELAYG_18 (
13195         .A(ddrphy_pad_oddrx2f18),
13196         .Z(ddram_a[14])
13197 );
13198
13199 ODDRX2F ODDRX2F_19(
13200         .D0(ddrphy_dfi_p0_bank[0]),
13201         .D1(ddrphy_dfi_p0_bank[0]),
13202         .D2(ddrphy_dfi_p1_bank[0]),
13203         .D3(ddrphy_dfi_p1_bank[0]),
13204         .ECLK(sys2x_clk),
13205         .RST(sys_rst),
13206         .SCLK(sys_clk),
13207         .Q(ddrphy_pad_oddrx2f19)
13208 );
13209
13210 DELAYG #(
13211         .DEL_VALUE(7'd100)
13212 ) DELAYG_19 (
13213         .A(ddrphy_pad_oddrx2f19),
13214         .Z(ddram_ba[0])
13215 );
13216
13217 ODDRX2F ODDRX2F_20(
13218         .D0(ddrphy_dfi_p0_bank[1]),
13219         .D1(ddrphy_dfi_p0_bank[1]),
13220         .D2(ddrphy_dfi_p1_bank[1]),
13221         .D3(ddrphy_dfi_p1_bank[1]),
13222         .ECLK(sys2x_clk),
13223         .RST(sys_rst),
13224         .SCLK(sys_clk),
13225         .Q(ddrphy_pad_oddrx2f20)
13226 );
13227
13228 DELAYG #(
13229         .DEL_VALUE(7'd100)
13230 ) DELAYG_20 (
13231         .A(ddrphy_pad_oddrx2f20),
13232         .Z(ddram_ba[1])
13233 );
13234
13235 ODDRX2F ODDRX2F_21(
13236         .D0(ddrphy_dfi_p0_bank[2]),
13237         .D1(ddrphy_dfi_p0_bank[2]),
13238         .D2(ddrphy_dfi_p1_bank[2]),
13239         .D3(ddrphy_dfi_p1_bank[2]),
13240         .ECLK(sys2x_clk),
13241         .RST(sys_rst),
13242         .SCLK(sys_clk),
13243         .Q(ddrphy_pad_oddrx2f21)
13244 );
13245
13246 DELAYG #(
13247         .DEL_VALUE(7'd100)
13248 ) DELAYG_21 (
13249         .A(ddrphy_pad_oddrx2f21),
13250         .Z(ddram_ba[2])
13251 );
13252
13253 ODDRX2F ODDRX2F_22(
13254         .D0(ddrphy_dfi_p0_ras_n),
13255         .D1(ddrphy_dfi_p0_ras_n),
13256         .D2(ddrphy_dfi_p1_ras_n),
13257         .D3(ddrphy_dfi_p1_ras_n),
13258         .ECLK(sys2x_clk),
13259         .RST(sys_rst),
13260         .SCLK(sys_clk),
13261         .Q(ddrphy_pad_oddrx2f22)
13262 );
13263
13264 DELAYG #(
13265         .DEL_VALUE(7'd100)
13266 ) DELAYG_22 (
13267         .A(ddrphy_pad_oddrx2f22),
13268         .Z(ddram_ras_n)
13269 );
13270
13271 ODDRX2F ODDRX2F_23(
13272         .D0(ddrphy_dfi_p0_cas_n),
13273         .D1(ddrphy_dfi_p0_cas_n),
13274         .D2(ddrphy_dfi_p1_cas_n),
13275         .D3(ddrphy_dfi_p1_cas_n),
13276         .ECLK(sys2x_clk),
13277         .RST(sys_rst),
13278         .SCLK(sys_clk),
13279         .Q(ddrphy_pad_oddrx2f23)
13280 );
13281
13282 DELAYG #(
13283         .DEL_VALUE(7'd100)
13284 ) DELAYG_23 (
13285         .A(ddrphy_pad_oddrx2f23),
13286         .Z(ddram_cas_n)
13287 );
13288
13289 ODDRX2F ODDRX2F_24(
13290         .D0(ddrphy_dfi_p0_we_n),
13291         .D1(ddrphy_dfi_p0_we_n),
13292         .D2(ddrphy_dfi_p1_we_n),
13293         .D3(ddrphy_dfi_p1_we_n),
13294         .ECLK(sys2x_clk),
13295         .RST(sys_rst),
13296         .SCLK(sys_clk),
13297         .Q(ddrphy_pad_oddrx2f24)
13298 );
13299
13300 DELAYG #(
13301         .DEL_VALUE(7'd100)
13302 ) DELAYG_24 (
13303         .A(ddrphy_pad_oddrx2f24),
13304         .Z(ddram_we_n)
13305 );
13306
13307 ODDRX2F ODDRX2F_25(
13308         .D0(ddrphy_dfi_p0_cke),
13309         .D1(ddrphy_dfi_p0_cke),
13310         .D2(ddrphy_dfi_p1_cke),
13311         .D3(ddrphy_dfi_p1_cke),
13312         .ECLK(sys2x_clk),
13313         .RST(sys_rst),
13314         .SCLK(sys_clk),
13315         .Q(ddrphy_pad_oddrx2f25)
13316 );
13317
13318 DELAYG #(
13319         .DEL_VALUE(7'd100)
13320 ) DELAYG_25 (
13321         .A(ddrphy_pad_oddrx2f25),
13322         .Z(ddram_cke)
13323 );
13324
13325 ODDRX2F ODDRX2F_26(
13326         .D0(ddrphy_dfi_p0_odt),
13327         .D1(ddrphy_dfi_p0_odt),
13328         .D2(ddrphy_dfi_p1_odt),
13329         .D3(ddrphy_dfi_p1_odt),
13330         .ECLK(sys2x_clk),
13331         .RST(sys_rst),
13332         .SCLK(sys_clk),
13333         .Q(ddrphy_pad_oddrx2f26)
13334 );
13335
13336 DELAYG #(
13337         .DEL_VALUE(7'd100)
13338 ) DELAYG_26 (
13339         .A(ddrphy_pad_oddrx2f26),
13340         .Z(ddram_odt)
13341 );
13342
13343 DQSBUFM #(
13344         .DQS_LI_DEL_ADJ("MINUS"),
13345         .DQS_LI_DEL_VAL(1'd1),
13346         .DQS_LO_DEL_ADJ("MINUS"),
13347         .DQS_LO_DEL_VAL(3'd4)
13348 ) DQSBUFM (
13349         .DDRDEL(ddrphy_delay0),
13350         .DQSI(ddrphy_dqs_i0),
13351         .ECLK(sys2x_clk),
13352         .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[0])),
13353         .RDDIRECTION(1'd1),
13354         .RDLOADN(1'd0),
13355         .RDMOVE(1'd0),
13356         .READ0(ddrphy_dqs_re),
13357         .READ1(ddrphy_dqs_re),
13358         .READCLKSEL0(ddrphy_rdly0[0]),
13359         .READCLKSEL1(ddrphy_rdly0[1]),
13360         .READCLKSEL2(ddrphy_rdly0[2]),
13361         .RST(sys_rst),
13362         .SCLK(sys_clk),
13363         .WRDIRECTION(1'd1),
13364         .WRLOADN(1'd0),
13365         .WRMOVE(1'd0),
13366         .BURSTDET(ddrphy_burstdet0),
13367         .DATAVALID(ddrphy_datavalid[0]),
13368         .DQSR90(ddrphy_dqsr900),
13369         .DQSW(ddrphy_dqsw0),
13370         .DQSW270(ddrphy_dqsw2700),
13371         .RDPNTR0(ddrphy_rdpntr0[0]),
13372         .RDPNTR1(ddrphy_rdpntr0[1]),
13373         .RDPNTR2(ddrphy_rdpntr0[2]),
13374         .WRPNTR0(ddrphy_wrpntr0[0]),
13375         .WRPNTR1(ddrphy_wrpntr0[1]),
13376         .WRPNTR2(ddrphy_wrpntr0[2])
13377 );
13378
13379 ODDRX2DQSB ODDRX2DQSB(
13380         .D0(1'd0),
13381         .D1(1'd1),
13382         .D2(1'd0),
13383         .D3(1'd1),
13384         .DQSW(ddrphy_dqsw0),
13385         .ECLK(sys2x_clk),
13386         .RST(sys_rst),
13387         .SCLK(sys_clk),
13388         .Q(ddrphy_dqs0)
13389 );
13390
13391 TSHX2DQSA TSHX2DQSA(
13392         .DQSW(ddrphy_dqsw0),
13393         .ECLK(sys2x_clk),
13394         .RST(sys_rst),
13395         .SCLK(sys_clk),
13396         .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
13397         .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
13398         .Q(ddrphy_dqs_oe_n0)
13399 );
13400
13401 ODDRX2DQA ODDRX2DQA(
13402         .D0(ddrphy_dm_o_data_muxed0[0]),
13403         .D1(ddrphy_dm_o_data_muxed0[1]),
13404         .D2(ddrphy_dm_o_data_muxed0[2]),
13405         .D3(ddrphy_dm_o_data_muxed0[3]),
13406         .DQSW270(ddrphy_dqsw2700),
13407         .ECLK(sys2x_clk),
13408         .RST(sys_rst),
13409         .SCLK(sys_clk),
13410         .Q(ddram_dm[0])
13411 );
13412
13413 ODDRX2DQA ODDRX2DQA_1(
13414         .D0(ddrphy_dq_o_data_muxed0[0]),
13415         .D1(ddrphy_dq_o_data_muxed0[1]),
13416         .D2(ddrphy_dq_o_data_muxed0[2]),
13417         .D3(ddrphy_dq_o_data_muxed0[3]),
13418         .DQSW270(ddrphy_dqsw2700),
13419         .ECLK(sys2x_clk),
13420         .RST(sys_rst),
13421         .SCLK(sys_clk),
13422         .Q(ddrphy_dq_o0)
13423 );
13424
13425 DELAYG #(
13426         .DEL_MODE("DQS_ALIGNED_X2")
13427 ) DELAYG_27 (
13428         .A(ddrphy_dq_i0),
13429         .Z(ddrphy_dq_i_delayed0)
13430 );
13431
13432 IDDRX2DQA IDDRX2DQA(
13433         .D(ddrphy_dq_i_delayed0),
13434         .DQSR90(ddrphy_dqsr900),
13435         .ECLK(sys2x_clk),
13436         .RDPNTR0(ddrphy_rdpntr0[0]),
13437         .RDPNTR1(ddrphy_rdpntr0[1]),
13438         .RDPNTR2(ddrphy_rdpntr0[2]),
13439         .RST(sys_rst),
13440         .SCLK(sys_clk),
13441         .WRPNTR0(ddrphy_wrpntr0[0]),
13442         .WRPNTR1(ddrphy_wrpntr0[1]),
13443         .WRPNTR2(ddrphy_wrpntr0[2]),
13444         .Q0(ddrphy_bitslip0_i[0]),
13445         .Q1(ddrphy_bitslip0_i[1]),
13446         .Q2(ddrphy_bitslip0_i[2]),
13447         .Q3(ddrphy_bitslip0_i[3])
13448 );
13449
13450 TSHX2DQA TSHX2DQA(
13451         .DQSW270(ddrphy_dqsw2700),
13452         .ECLK(sys2x_clk),
13453         .RST(sys_rst),
13454         .SCLK(sys_clk),
13455         .T0((~ddrphy_dq_oe)),
13456         .T1((~ddrphy_dq_oe)),
13457         .Q(ddrphy_dq_oe_n0)
13458 );
13459
13460 ODDRX2DQA ODDRX2DQA_2(
13461         .D0(ddrphy_dq_o_data_muxed1[0]),
13462         .D1(ddrphy_dq_o_data_muxed1[1]),
13463         .D2(ddrphy_dq_o_data_muxed1[2]),
13464         .D3(ddrphy_dq_o_data_muxed1[3]),
13465         .DQSW270(ddrphy_dqsw2700),
13466         .ECLK(sys2x_clk),
13467         .RST(sys_rst),
13468         .SCLK(sys_clk),
13469         .Q(ddrphy_dq_o1)
13470 );
13471
13472 DELAYG #(
13473         .DEL_MODE("DQS_ALIGNED_X2")
13474 ) DELAYG_28 (
13475         .A(ddrphy_dq_i1),
13476         .Z(ddrphy_dq_i_delayed1)
13477 );
13478
13479 IDDRX2DQA IDDRX2DQA_1(
13480         .D(ddrphy_dq_i_delayed1),
13481         .DQSR90(ddrphy_dqsr900),
13482         .ECLK(sys2x_clk),
13483         .RDPNTR0(ddrphy_rdpntr0[0]),
13484         .RDPNTR1(ddrphy_rdpntr0[1]),
13485         .RDPNTR2(ddrphy_rdpntr0[2]),
13486         .RST(sys_rst),
13487         .SCLK(sys_clk),
13488         .WRPNTR0(ddrphy_wrpntr0[0]),
13489         .WRPNTR1(ddrphy_wrpntr0[1]),
13490         .WRPNTR2(ddrphy_wrpntr0[2]),
13491         .Q0(ddrphy_bitslip1_i[0]),
13492         .Q1(ddrphy_bitslip1_i[1]),
13493         .Q2(ddrphy_bitslip1_i[2]),
13494         .Q3(ddrphy_bitslip1_i[3])
13495 );
13496
13497 TSHX2DQA TSHX2DQA_1(
13498         .DQSW270(ddrphy_dqsw2700),
13499         .ECLK(sys2x_clk),
13500         .RST(sys_rst),
13501         .SCLK(sys_clk),
13502         .T0((~ddrphy_dq_oe)),
13503         .T1((~ddrphy_dq_oe)),
13504         .Q(ddrphy_dq_oe_n1)
13505 );
13506
13507 ODDRX2DQA ODDRX2DQA_3(
13508         .D0(ddrphy_dq_o_data_muxed2[0]),
13509         .D1(ddrphy_dq_o_data_muxed2[1]),
13510         .D2(ddrphy_dq_o_data_muxed2[2]),
13511         .D3(ddrphy_dq_o_data_muxed2[3]),
13512         .DQSW270(ddrphy_dqsw2700),
13513         .ECLK(sys2x_clk),
13514         .RST(sys_rst),
13515         .SCLK(sys_clk),
13516         .Q(ddrphy_dq_o2)
13517 );
13518
13519 DELAYG #(
13520         .DEL_MODE("DQS_ALIGNED_X2")
13521 ) DELAYG_29 (
13522         .A(ddrphy_dq_i2),
13523         .Z(ddrphy_dq_i_delayed2)
13524 );
13525
13526 IDDRX2DQA IDDRX2DQA_2(
13527         .D(ddrphy_dq_i_delayed2),
13528         .DQSR90(ddrphy_dqsr900),
13529         .ECLK(sys2x_clk),
13530         .RDPNTR0(ddrphy_rdpntr0[0]),
13531         .RDPNTR1(ddrphy_rdpntr0[1]),
13532         .RDPNTR2(ddrphy_rdpntr0[2]),
13533         .RST(sys_rst),
13534         .SCLK(sys_clk),
13535         .WRPNTR0(ddrphy_wrpntr0[0]),
13536         .WRPNTR1(ddrphy_wrpntr0[1]),
13537         .WRPNTR2(ddrphy_wrpntr0[2]),
13538         .Q0(ddrphy_bitslip2_i[0]),
13539         .Q1(ddrphy_bitslip2_i[1]),
13540         .Q2(ddrphy_bitslip2_i[2]),
13541         .Q3(ddrphy_bitslip2_i[3])
13542 );
13543
13544 TSHX2DQA TSHX2DQA_2(
13545         .DQSW270(ddrphy_dqsw2700),
13546         .ECLK(sys2x_clk),
13547         .RST(sys_rst),
13548         .SCLK(sys_clk),
13549         .T0((~ddrphy_dq_oe)),
13550         .T1((~ddrphy_dq_oe)),
13551         .Q(ddrphy_dq_oe_n2)
13552 );
13553
13554 ODDRX2DQA ODDRX2DQA_4(
13555         .D0(ddrphy_dq_o_data_muxed3[0]),
13556         .D1(ddrphy_dq_o_data_muxed3[1]),
13557         .D2(ddrphy_dq_o_data_muxed3[2]),
13558         .D3(ddrphy_dq_o_data_muxed3[3]),
13559         .DQSW270(ddrphy_dqsw2700),
13560         .ECLK(sys2x_clk),
13561         .RST(sys_rst),
13562         .SCLK(sys_clk),
13563         .Q(ddrphy_dq_o3)
13564 );
13565
13566 DELAYG #(
13567         .DEL_MODE("DQS_ALIGNED_X2")
13568 ) DELAYG_30 (
13569         .A(ddrphy_dq_i3),
13570         .Z(ddrphy_dq_i_delayed3)
13571 );
13572
13573 IDDRX2DQA IDDRX2DQA_3(
13574         .D(ddrphy_dq_i_delayed3),
13575         .DQSR90(ddrphy_dqsr900),
13576         .ECLK(sys2x_clk),
13577         .RDPNTR0(ddrphy_rdpntr0[0]),
13578         .RDPNTR1(ddrphy_rdpntr0[1]),
13579         .RDPNTR2(ddrphy_rdpntr0[2]),
13580         .RST(sys_rst),
13581         .SCLK(sys_clk),
13582         .WRPNTR0(ddrphy_wrpntr0[0]),
13583         .WRPNTR1(ddrphy_wrpntr0[1]),
13584         .WRPNTR2(ddrphy_wrpntr0[2]),
13585         .Q0(ddrphy_bitslip3_i[0]),
13586         .Q1(ddrphy_bitslip3_i[1]),
13587         .Q2(ddrphy_bitslip3_i[2]),
13588         .Q3(ddrphy_bitslip3_i[3])
13589 );
13590
13591 TSHX2DQA TSHX2DQA_3(
13592         .DQSW270(ddrphy_dqsw2700),
13593         .ECLK(sys2x_clk),
13594         .RST(sys_rst),
13595         .SCLK(sys_clk),
13596         .T0((~ddrphy_dq_oe)),
13597         .T1((~ddrphy_dq_oe)),
13598         .Q(ddrphy_dq_oe_n3)
13599 );
13600
13601 ODDRX2DQA ODDRX2DQA_5(
13602         .D0(ddrphy_dq_o_data_muxed4[0]),
13603         .D1(ddrphy_dq_o_data_muxed4[1]),
13604         .D2(ddrphy_dq_o_data_muxed4[2]),
13605         .D3(ddrphy_dq_o_data_muxed4[3]),
13606         .DQSW270(ddrphy_dqsw2700),
13607         .ECLK(sys2x_clk),
13608         .RST(sys_rst),
13609         .SCLK(sys_clk),
13610         .Q(ddrphy_dq_o4)
13611 );
13612
13613 DELAYG #(
13614         .DEL_MODE("DQS_ALIGNED_X2")
13615 ) DELAYG_31 (
13616         .A(ddrphy_dq_i4),
13617         .Z(ddrphy_dq_i_delayed4)
13618 );
13619
13620 IDDRX2DQA IDDRX2DQA_4(
13621         .D(ddrphy_dq_i_delayed4),
13622         .DQSR90(ddrphy_dqsr900),
13623         .ECLK(sys2x_clk),
13624         .RDPNTR0(ddrphy_rdpntr0[0]),
13625         .RDPNTR1(ddrphy_rdpntr0[1]),
13626         .RDPNTR2(ddrphy_rdpntr0[2]),
13627         .RST(sys_rst),
13628         .SCLK(sys_clk),
13629         .WRPNTR0(ddrphy_wrpntr0[0]),
13630         .WRPNTR1(ddrphy_wrpntr0[1]),
13631         .WRPNTR2(ddrphy_wrpntr0[2]),
13632         .Q0(ddrphy_bitslip4_i[0]),
13633         .Q1(ddrphy_bitslip4_i[1]),
13634         .Q2(ddrphy_bitslip4_i[2]),
13635         .Q3(ddrphy_bitslip4_i[3])
13636 );
13637
13638 TSHX2DQA TSHX2DQA_4(
13639         .DQSW270(ddrphy_dqsw2700),
13640         .ECLK(sys2x_clk),
13641         .RST(sys_rst),
13642         .SCLK(sys_clk),
13643         .T0((~ddrphy_dq_oe)),
13644         .T1((~ddrphy_dq_oe)),
13645         .Q(ddrphy_dq_oe_n4)
13646 );
13647
13648 ODDRX2DQA ODDRX2DQA_6(
13649         .D0(ddrphy_dq_o_data_muxed5[0]),
13650         .D1(ddrphy_dq_o_data_muxed5[1]),
13651         .D2(ddrphy_dq_o_data_muxed5[2]),
13652         .D3(ddrphy_dq_o_data_muxed5[3]),
13653         .DQSW270(ddrphy_dqsw2700),
13654         .ECLK(sys2x_clk),
13655         .RST(sys_rst),
13656         .SCLK(sys_clk),
13657         .Q(ddrphy_dq_o5)
13658 );
13659
13660 DELAYG #(
13661         .DEL_MODE("DQS_ALIGNED_X2")
13662 ) DELAYG_32 (
13663         .A(ddrphy_dq_i5),
13664         .Z(ddrphy_dq_i_delayed5)
13665 );
13666
13667 IDDRX2DQA IDDRX2DQA_5(
13668         .D(ddrphy_dq_i_delayed5),
13669         .DQSR90(ddrphy_dqsr900),
13670         .ECLK(sys2x_clk),
13671         .RDPNTR0(ddrphy_rdpntr0[0]),
13672         .RDPNTR1(ddrphy_rdpntr0[1]),
13673         .RDPNTR2(ddrphy_rdpntr0[2]),
13674         .RST(sys_rst),
13675         .SCLK(sys_clk),
13676         .WRPNTR0(ddrphy_wrpntr0[0]),
13677         .WRPNTR1(ddrphy_wrpntr0[1]),
13678         .WRPNTR2(ddrphy_wrpntr0[2]),
13679         .Q0(ddrphy_bitslip5_i[0]),
13680         .Q1(ddrphy_bitslip5_i[1]),
13681         .Q2(ddrphy_bitslip5_i[2]),
13682         .Q3(ddrphy_bitslip5_i[3])
13683 );
13684
13685 TSHX2DQA TSHX2DQA_5(
13686         .DQSW270(ddrphy_dqsw2700),
13687         .ECLK(sys2x_clk),
13688         .RST(sys_rst),
13689         .SCLK(sys_clk),
13690         .T0((~ddrphy_dq_oe)),
13691         .T1((~ddrphy_dq_oe)),
13692         .Q(ddrphy_dq_oe_n5)
13693 );
13694
13695 ODDRX2DQA ODDRX2DQA_7(
13696         .D0(ddrphy_dq_o_data_muxed6[0]),
13697         .D1(ddrphy_dq_o_data_muxed6[1]),
13698         .D2(ddrphy_dq_o_data_muxed6[2]),
13699         .D3(ddrphy_dq_o_data_muxed6[3]),
13700         .DQSW270(ddrphy_dqsw2700),
13701         .ECLK(sys2x_clk),
13702         .RST(sys_rst),
13703         .SCLK(sys_clk),
13704         .Q(ddrphy_dq_o6)
13705 );
13706
13707 DELAYG #(
13708         .DEL_MODE("DQS_ALIGNED_X2")
13709 ) DELAYG_33 (
13710         .A(ddrphy_dq_i6),
13711         .Z(ddrphy_dq_i_delayed6)
13712 );
13713
13714 IDDRX2DQA IDDRX2DQA_6(
13715         .D(ddrphy_dq_i_delayed6),
13716         .DQSR90(ddrphy_dqsr900),
13717         .ECLK(sys2x_clk),
13718         .RDPNTR0(ddrphy_rdpntr0[0]),
13719         .RDPNTR1(ddrphy_rdpntr0[1]),
13720         .RDPNTR2(ddrphy_rdpntr0[2]),
13721         .RST(sys_rst),
13722         .SCLK(sys_clk),
13723         .WRPNTR0(ddrphy_wrpntr0[0]),
13724         .WRPNTR1(ddrphy_wrpntr0[1]),
13725         .WRPNTR2(ddrphy_wrpntr0[2]),
13726         .Q0(ddrphy_bitslip6_i[0]),
13727         .Q1(ddrphy_bitslip6_i[1]),
13728         .Q2(ddrphy_bitslip6_i[2]),
13729         .Q3(ddrphy_bitslip6_i[3])
13730 );
13731
13732 TSHX2DQA TSHX2DQA_6(
13733         .DQSW270(ddrphy_dqsw2700),
13734         .ECLK(sys2x_clk),
13735         .RST(sys_rst),
13736         .SCLK(sys_clk),
13737         .T0((~ddrphy_dq_oe)),
13738         .T1((~ddrphy_dq_oe)),
13739         .Q(ddrphy_dq_oe_n6)
13740 );
13741
13742 ODDRX2DQA ODDRX2DQA_8(
13743         .D0(ddrphy_dq_o_data_muxed7[0]),
13744         .D1(ddrphy_dq_o_data_muxed7[1]),
13745         .D2(ddrphy_dq_o_data_muxed7[2]),
13746         .D3(ddrphy_dq_o_data_muxed7[3]),
13747         .DQSW270(ddrphy_dqsw2700),
13748         .ECLK(sys2x_clk),
13749         .RST(sys_rst),
13750         .SCLK(sys_clk),
13751         .Q(ddrphy_dq_o7)
13752 );
13753
13754 DELAYG #(
13755         .DEL_MODE("DQS_ALIGNED_X2")
13756 ) DELAYG_34 (
13757         .A(ddrphy_dq_i7),
13758         .Z(ddrphy_dq_i_delayed7)
13759 );
13760
13761 IDDRX2DQA IDDRX2DQA_7(
13762         .D(ddrphy_dq_i_delayed7),
13763         .DQSR90(ddrphy_dqsr900),
13764         .ECLK(sys2x_clk),
13765         .RDPNTR0(ddrphy_rdpntr0[0]),
13766         .RDPNTR1(ddrphy_rdpntr0[1]),
13767         .RDPNTR2(ddrphy_rdpntr0[2]),
13768         .RST(sys_rst),
13769         .SCLK(sys_clk),
13770         .WRPNTR0(ddrphy_wrpntr0[0]),
13771         .WRPNTR1(ddrphy_wrpntr0[1]),
13772         .WRPNTR2(ddrphy_wrpntr0[2]),
13773         .Q0(ddrphy_bitslip7_i[0]),
13774         .Q1(ddrphy_bitslip7_i[1]),
13775         .Q2(ddrphy_bitslip7_i[2]),
13776         .Q3(ddrphy_bitslip7_i[3])
13777 );
13778
13779 TSHX2DQA TSHX2DQA_7(
13780         .DQSW270(ddrphy_dqsw2700),
13781         .ECLK(sys2x_clk),
13782         .RST(sys_rst),
13783         .SCLK(sys_clk),
13784         .T0((~ddrphy_dq_oe)),
13785         .T1((~ddrphy_dq_oe)),
13786         .Q(ddrphy_dq_oe_n7)
13787 );
13788
13789 DQSBUFM #(
13790         .DQS_LI_DEL_ADJ("MINUS"),
13791         .DQS_LI_DEL_VAL(1'd1),
13792         .DQS_LO_DEL_ADJ("MINUS"),
13793         .DQS_LO_DEL_VAL(3'd4)
13794 ) DQSBUFM_1 (
13795         .DDRDEL(ddrphy_delay0),
13796         .DQSI(ddrphy_dqs_i1),
13797         .ECLK(sys2x_clk),
13798         .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[1])),
13799         .RDDIRECTION(1'd1),
13800         .RDLOADN(1'd0),
13801         .RDMOVE(1'd0),
13802         .READ0(ddrphy_dqs_re),
13803         .READ1(ddrphy_dqs_re),
13804         .READCLKSEL0(ddrphy_rdly1[0]),
13805         .READCLKSEL1(ddrphy_rdly1[1]),
13806         .READCLKSEL2(ddrphy_rdly1[2]),
13807         .RST(sys_rst),
13808         .SCLK(sys_clk),
13809         .WRDIRECTION(1'd1),
13810         .WRLOADN(1'd0),
13811         .WRMOVE(1'd0),
13812         .BURSTDET(ddrphy_burstdet1),
13813         .DATAVALID(ddrphy_datavalid[1]),
13814         .DQSR90(ddrphy_dqsr901),
13815         .DQSW(ddrphy_dqsw1),
13816         .DQSW270(ddrphy_dqsw2701),
13817         .RDPNTR0(ddrphy_rdpntr1[0]),
13818         .RDPNTR1(ddrphy_rdpntr1[1]),
13819         .RDPNTR2(ddrphy_rdpntr1[2]),
13820         .WRPNTR0(ddrphy_wrpntr1[0]),
13821         .WRPNTR1(ddrphy_wrpntr1[1]),
13822         .WRPNTR2(ddrphy_wrpntr1[2])
13823 );
13824
13825 ODDRX2DQSB ODDRX2DQSB_1(
13826         .D0(1'd0),
13827         .D1(1'd1),
13828         .D2(1'd0),
13829         .D3(1'd1),
13830         .DQSW(ddrphy_dqsw1),
13831         .ECLK(sys2x_clk),
13832         .RST(sys_rst),
13833         .SCLK(sys_clk),
13834         .Q(ddrphy_dqs1)
13835 );
13836
13837 TSHX2DQSA TSHX2DQSA_1(
13838         .DQSW(ddrphy_dqsw1),
13839         .ECLK(sys2x_clk),
13840         .RST(sys_rst),
13841         .SCLK(sys_clk),
13842         .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
13843         .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
13844         .Q(ddrphy_dqs_oe_n1)
13845 );
13846
13847 ODDRX2DQA ODDRX2DQA_9(
13848         .D0(ddrphy_dm_o_data_muxed1[0]),
13849         .D1(ddrphy_dm_o_data_muxed1[1]),
13850         .D2(ddrphy_dm_o_data_muxed1[2]),
13851         .D3(ddrphy_dm_o_data_muxed1[3]),
13852         .DQSW270(ddrphy_dqsw2701),
13853         .ECLK(sys2x_clk),
13854         .RST(sys_rst),
13855         .SCLK(sys_clk),
13856         .Q(ddram_dm[1])
13857 );
13858
13859 ODDRX2DQA ODDRX2DQA_10(
13860         .D0(ddrphy_dq_o_data_muxed8[0]),
13861         .D1(ddrphy_dq_o_data_muxed8[1]),
13862         .D2(ddrphy_dq_o_data_muxed8[2]),
13863         .D3(ddrphy_dq_o_data_muxed8[3]),
13864         .DQSW270(ddrphy_dqsw2701),
13865         .ECLK(sys2x_clk),
13866         .RST(sys_rst),
13867         .SCLK(sys_clk),
13868         .Q(ddrphy_dq_o8)
13869 );
13870
13871 DELAYG #(
13872         .DEL_MODE("DQS_ALIGNED_X2")
13873 ) DELAYG_35 (
13874         .A(ddrphy_dq_i8),
13875         .Z(ddrphy_dq_i_delayed8)
13876 );
13877
13878 IDDRX2DQA IDDRX2DQA_8(
13879         .D(ddrphy_dq_i_delayed8),
13880         .DQSR90(ddrphy_dqsr901),
13881         .ECLK(sys2x_clk),
13882         .RDPNTR0(ddrphy_rdpntr1[0]),
13883         .RDPNTR1(ddrphy_rdpntr1[1]),
13884         .RDPNTR2(ddrphy_rdpntr1[2]),
13885         .RST(sys_rst),
13886         .SCLK(sys_clk),
13887         .WRPNTR0(ddrphy_wrpntr1[0]),
13888         .WRPNTR1(ddrphy_wrpntr1[1]),
13889         .WRPNTR2(ddrphy_wrpntr1[2]),
13890         .Q0(ddrphy_bitslip8_i[0]),
13891         .Q1(ddrphy_bitslip8_i[1]),
13892         .Q2(ddrphy_bitslip8_i[2]),
13893         .Q3(ddrphy_bitslip8_i[3])
13894 );
13895
13896 TSHX2DQA TSHX2DQA_8(
13897         .DQSW270(ddrphy_dqsw2701),
13898         .ECLK(sys2x_clk),
13899         .RST(sys_rst),
13900         .SCLK(sys_clk),
13901         .T0((~ddrphy_dq_oe)),
13902         .T1((~ddrphy_dq_oe)),
13903         .Q(ddrphy_dq_oe_n8)
13904 );
13905
13906 ODDRX2DQA ODDRX2DQA_11(
13907         .D0(ddrphy_dq_o_data_muxed9[0]),
13908         .D1(ddrphy_dq_o_data_muxed9[1]),
13909         .D2(ddrphy_dq_o_data_muxed9[2]),
13910         .D3(ddrphy_dq_o_data_muxed9[3]),
13911         .DQSW270(ddrphy_dqsw2701),
13912         .ECLK(sys2x_clk),
13913         .RST(sys_rst),
13914         .SCLK(sys_clk),
13915         .Q(ddrphy_dq_o9)
13916 );
13917
13918 DELAYG #(
13919         .DEL_MODE("DQS_ALIGNED_X2")
13920 ) DELAYG_36 (
13921         .A(ddrphy_dq_i9),
13922         .Z(ddrphy_dq_i_delayed9)
13923 );
13924
13925 IDDRX2DQA IDDRX2DQA_9(
13926         .D(ddrphy_dq_i_delayed9),
13927         .DQSR90(ddrphy_dqsr901),
13928         .ECLK(sys2x_clk),
13929         .RDPNTR0(ddrphy_rdpntr1[0]),
13930         .RDPNTR1(ddrphy_rdpntr1[1]),
13931         .RDPNTR2(ddrphy_rdpntr1[2]),
13932         .RST(sys_rst),
13933         .SCLK(sys_clk),
13934         .WRPNTR0(ddrphy_wrpntr1[0]),
13935         .WRPNTR1(ddrphy_wrpntr1[1]),
13936         .WRPNTR2(ddrphy_wrpntr1[2]),
13937         .Q0(ddrphy_bitslip9_i[0]),
13938         .Q1(ddrphy_bitslip9_i[1]),
13939         .Q2(ddrphy_bitslip9_i[2]),
13940         .Q3(ddrphy_bitslip9_i[3])
13941 );
13942
13943 TSHX2DQA TSHX2DQA_9(
13944         .DQSW270(ddrphy_dqsw2701),
13945         .ECLK(sys2x_clk),
13946         .RST(sys_rst),
13947         .SCLK(sys_clk),
13948         .T0((~ddrphy_dq_oe)),
13949         .T1((~ddrphy_dq_oe)),
13950         .Q(ddrphy_dq_oe_n9)
13951 );
13952
13953 ODDRX2DQA ODDRX2DQA_12(
13954         .D0(ddrphy_dq_o_data_muxed10[0]),
13955         .D1(ddrphy_dq_o_data_muxed10[1]),
13956         .D2(ddrphy_dq_o_data_muxed10[2]),
13957         .D3(ddrphy_dq_o_data_muxed10[3]),
13958         .DQSW270(ddrphy_dqsw2701),
13959         .ECLK(sys2x_clk),
13960         .RST(sys_rst),
13961         .SCLK(sys_clk),
13962         .Q(ddrphy_dq_o10)
13963 );
13964
13965 DELAYG #(
13966         .DEL_MODE("DQS_ALIGNED_X2")
13967 ) DELAYG_37 (
13968         .A(ddrphy_dq_i10),
13969         .Z(ddrphy_dq_i_delayed10)
13970 );
13971
13972 IDDRX2DQA IDDRX2DQA_10(
13973         .D(ddrphy_dq_i_delayed10),
13974         .DQSR90(ddrphy_dqsr901),
13975         .ECLK(sys2x_clk),
13976         .RDPNTR0(ddrphy_rdpntr1[0]),
13977         .RDPNTR1(ddrphy_rdpntr1[1]),
13978         .RDPNTR2(ddrphy_rdpntr1[2]),
13979         .RST(sys_rst),
13980         .SCLK(sys_clk),
13981         .WRPNTR0(ddrphy_wrpntr1[0]),
13982         .WRPNTR1(ddrphy_wrpntr1[1]),
13983         .WRPNTR2(ddrphy_wrpntr1[2]),
13984         .Q0(ddrphy_bitslip10_i[0]),
13985         .Q1(ddrphy_bitslip10_i[1]),
13986         .Q2(ddrphy_bitslip10_i[2]),
13987         .Q3(ddrphy_bitslip10_i[3])
13988 );
13989
13990 TSHX2DQA TSHX2DQA_10(
13991         .DQSW270(ddrphy_dqsw2701),
13992         .ECLK(sys2x_clk),
13993         .RST(sys_rst),
13994         .SCLK(sys_clk),
13995         .T0((~ddrphy_dq_oe)),
13996         .T1((~ddrphy_dq_oe)),
13997         .Q(ddrphy_dq_oe_n10)
13998 );
13999
14000 ODDRX2DQA ODDRX2DQA_13(
14001         .D0(ddrphy_dq_o_data_muxed11[0]),
14002         .D1(ddrphy_dq_o_data_muxed11[1]),
14003         .D2(ddrphy_dq_o_data_muxed11[2]),
14004         .D3(ddrphy_dq_o_data_muxed11[3]),
14005         .DQSW270(ddrphy_dqsw2701),
14006         .ECLK(sys2x_clk),
14007         .RST(sys_rst),
14008         .SCLK(sys_clk),
14009         .Q(ddrphy_dq_o11)
14010 );
14011
14012 DELAYG #(
14013         .DEL_MODE("DQS_ALIGNED_X2")
14014 ) DELAYG_38 (
14015         .A(ddrphy_dq_i11),
14016         .Z(ddrphy_dq_i_delayed11)
14017 );
14018
14019 IDDRX2DQA IDDRX2DQA_11(
14020         .D(ddrphy_dq_i_delayed11),
14021         .DQSR90(ddrphy_dqsr901),
14022         .ECLK(sys2x_clk),
14023         .RDPNTR0(ddrphy_rdpntr1[0]),
14024         .RDPNTR1(ddrphy_rdpntr1[1]),
14025         .RDPNTR2(ddrphy_rdpntr1[2]),
14026         .RST(sys_rst),
14027         .SCLK(sys_clk),
14028         .WRPNTR0(ddrphy_wrpntr1[0]),
14029         .WRPNTR1(ddrphy_wrpntr1[1]),
14030         .WRPNTR2(ddrphy_wrpntr1[2]),
14031         .Q0(ddrphy_bitslip11_i[0]),
14032         .Q1(ddrphy_bitslip11_i[1]),
14033         .Q2(ddrphy_bitslip11_i[2]),
14034         .Q3(ddrphy_bitslip11_i[3])
14035 );
14036
14037 TSHX2DQA TSHX2DQA_11(
14038         .DQSW270(ddrphy_dqsw2701),
14039         .ECLK(sys2x_clk),
14040         .RST(sys_rst),
14041         .SCLK(sys_clk),
14042         .T0((~ddrphy_dq_oe)),
14043         .T1((~ddrphy_dq_oe)),
14044         .Q(ddrphy_dq_oe_n11)
14045 );
14046
14047 ODDRX2DQA ODDRX2DQA_14(
14048         .D0(ddrphy_dq_o_data_muxed12[0]),
14049         .D1(ddrphy_dq_o_data_muxed12[1]),
14050         .D2(ddrphy_dq_o_data_muxed12[2]),
14051         .D3(ddrphy_dq_o_data_muxed12[3]),
14052         .DQSW270(ddrphy_dqsw2701),
14053         .ECLK(sys2x_clk),
14054         .RST(sys_rst),
14055         .SCLK(sys_clk),
14056         .Q(ddrphy_dq_o12)
14057 );
14058
14059 DELAYG #(
14060         .DEL_MODE("DQS_ALIGNED_X2")
14061 ) DELAYG_39 (
14062         .A(ddrphy_dq_i12),
14063         .Z(ddrphy_dq_i_delayed12)
14064 );
14065
14066 IDDRX2DQA IDDRX2DQA_12(
14067         .D(ddrphy_dq_i_delayed12),
14068         .DQSR90(ddrphy_dqsr901),
14069         .ECLK(sys2x_clk),
14070         .RDPNTR0(ddrphy_rdpntr1[0]),
14071         .RDPNTR1(ddrphy_rdpntr1[1]),
14072         .RDPNTR2(ddrphy_rdpntr1[2]),
14073         .RST(sys_rst),
14074         .SCLK(sys_clk),
14075         .WRPNTR0(ddrphy_wrpntr1[0]),
14076         .WRPNTR1(ddrphy_wrpntr1[1]),
14077         .WRPNTR2(ddrphy_wrpntr1[2]),
14078         .Q0(ddrphy_bitslip12_i[0]),
14079         .Q1(ddrphy_bitslip12_i[1]),
14080         .Q2(ddrphy_bitslip12_i[2]),
14081         .Q3(ddrphy_bitslip12_i[3])
14082 );
14083
14084 TSHX2DQA TSHX2DQA_12(
14085         .DQSW270(ddrphy_dqsw2701),
14086         .ECLK(sys2x_clk),
14087         .RST(sys_rst),
14088         .SCLK(sys_clk),
14089         .T0((~ddrphy_dq_oe)),
14090         .T1((~ddrphy_dq_oe)),
14091         .Q(ddrphy_dq_oe_n12)
14092 );
14093
14094 ODDRX2DQA ODDRX2DQA_15(
14095         .D0(ddrphy_dq_o_data_muxed13[0]),
14096         .D1(ddrphy_dq_o_data_muxed13[1]),
14097         .D2(ddrphy_dq_o_data_muxed13[2]),
14098         .D3(ddrphy_dq_o_data_muxed13[3]),
14099         .DQSW270(ddrphy_dqsw2701),
14100         .ECLK(sys2x_clk),
14101         .RST(sys_rst),
14102         .SCLK(sys_clk),
14103         .Q(ddrphy_dq_o13)
14104 );
14105
14106 DELAYG #(
14107         .DEL_MODE("DQS_ALIGNED_X2")
14108 ) DELAYG_40 (
14109         .A(ddrphy_dq_i13),
14110         .Z(ddrphy_dq_i_delayed13)
14111 );
14112
14113 IDDRX2DQA IDDRX2DQA_13(
14114         .D(ddrphy_dq_i_delayed13),
14115         .DQSR90(ddrphy_dqsr901),
14116         .ECLK(sys2x_clk),
14117         .RDPNTR0(ddrphy_rdpntr1[0]),
14118         .RDPNTR1(ddrphy_rdpntr1[1]),
14119         .RDPNTR2(ddrphy_rdpntr1[2]),
14120         .RST(sys_rst),
14121         .SCLK(sys_clk),
14122         .WRPNTR0(ddrphy_wrpntr1[0]),
14123         .WRPNTR1(ddrphy_wrpntr1[1]),
14124         .WRPNTR2(ddrphy_wrpntr1[2]),
14125         .Q0(ddrphy_bitslip13_i[0]),
14126         .Q1(ddrphy_bitslip13_i[1]),
14127         .Q2(ddrphy_bitslip13_i[2]),
14128         .Q3(ddrphy_bitslip13_i[3])
14129 );
14130
14131 TSHX2DQA TSHX2DQA_13(
14132         .DQSW270(ddrphy_dqsw2701),
14133         .ECLK(sys2x_clk),
14134         .RST(sys_rst),
14135         .SCLK(sys_clk),
14136         .T0((~ddrphy_dq_oe)),
14137         .T1((~ddrphy_dq_oe)),
14138         .Q(ddrphy_dq_oe_n13)
14139 );
14140
14141 ODDRX2DQA ODDRX2DQA_16(
14142         .D0(ddrphy_dq_o_data_muxed14[0]),
14143         .D1(ddrphy_dq_o_data_muxed14[1]),
14144         .D2(ddrphy_dq_o_data_muxed14[2]),
14145         .D3(ddrphy_dq_o_data_muxed14[3]),
14146         .DQSW270(ddrphy_dqsw2701),
14147         .ECLK(sys2x_clk),
14148         .RST(sys_rst),
14149         .SCLK(sys_clk),
14150         .Q(ddrphy_dq_o14)
14151 );
14152
14153 DELAYG #(
14154         .DEL_MODE("DQS_ALIGNED_X2")
14155 ) DELAYG_41 (
14156         .A(ddrphy_dq_i14),
14157         .Z(ddrphy_dq_i_delayed14)
14158 );
14159
14160 IDDRX2DQA IDDRX2DQA_14(
14161         .D(ddrphy_dq_i_delayed14),
14162         .DQSR90(ddrphy_dqsr901),
14163         .ECLK(sys2x_clk),
14164         .RDPNTR0(ddrphy_rdpntr1[0]),
14165         .RDPNTR1(ddrphy_rdpntr1[1]),
14166         .RDPNTR2(ddrphy_rdpntr1[2]),
14167         .RST(sys_rst),
14168         .SCLK(sys_clk),
14169         .WRPNTR0(ddrphy_wrpntr1[0]),
14170         .WRPNTR1(ddrphy_wrpntr1[1]),
14171         .WRPNTR2(ddrphy_wrpntr1[2]),
14172         .Q0(ddrphy_bitslip14_i[0]),
14173         .Q1(ddrphy_bitslip14_i[1]),
14174         .Q2(ddrphy_bitslip14_i[2]),
14175         .Q3(ddrphy_bitslip14_i[3])
14176 );
14177
14178 TSHX2DQA TSHX2DQA_14(
14179         .DQSW270(ddrphy_dqsw2701),
14180         .ECLK(sys2x_clk),
14181         .RST(sys_rst),
14182         .SCLK(sys_clk),
14183         .T0((~ddrphy_dq_oe)),
14184         .T1((~ddrphy_dq_oe)),
14185         .Q(ddrphy_dq_oe_n14)
14186 );
14187
14188 ODDRX2DQA ODDRX2DQA_17(
14189         .D0(ddrphy_dq_o_data_muxed15[0]),
14190         .D1(ddrphy_dq_o_data_muxed15[1]),
14191         .D2(ddrphy_dq_o_data_muxed15[2]),
14192         .D3(ddrphy_dq_o_data_muxed15[3]),
14193         .DQSW270(ddrphy_dqsw2701),
14194         .ECLK(sys2x_clk),
14195         .RST(sys_rst),
14196         .SCLK(sys_clk),
14197         .Q(ddrphy_dq_o15)
14198 );
14199
14200 DELAYG #(
14201         .DEL_MODE("DQS_ALIGNED_X2")
14202 ) DELAYG_42 (
14203         .A(ddrphy_dq_i15),
14204         .Z(ddrphy_dq_i_delayed15)
14205 );
14206
14207 IDDRX2DQA IDDRX2DQA_15(
14208         .D(ddrphy_dq_i_delayed15),
14209         .DQSR90(ddrphy_dqsr901),
14210         .ECLK(sys2x_clk),
14211         .RDPNTR0(ddrphy_rdpntr1[0]),
14212         .RDPNTR1(ddrphy_rdpntr1[1]),
14213         .RDPNTR2(ddrphy_rdpntr1[2]),
14214         .RST(sys_rst),
14215         .SCLK(sys_clk),
14216         .WRPNTR0(ddrphy_wrpntr1[0]),
14217         .WRPNTR1(ddrphy_wrpntr1[1]),
14218         .WRPNTR2(ddrphy_wrpntr1[2]),
14219         .Q0(ddrphy_bitslip15_i[0]),
14220         .Q1(ddrphy_bitslip15_i[1]),
14221         .Q2(ddrphy_bitslip15_i[2]),
14222         .Q3(ddrphy_bitslip15_i[3])
14223 );
14224
14225 TSHX2DQA TSHX2DQA_15(
14226         .DQSW270(ddrphy_dqsw2701),
14227         .ECLK(sys2x_clk),
14228         .RST(sys_rst),
14229         .SCLK(sys_clk),
14230         .T0((~ddrphy_dq_oe)),
14231         .T1((~ddrphy_dq_oe)),
14232         .Q(ddrphy_dq_oe_n15)
14233 );
14234
14235 DQSBUFM #(
14236         .DQS_LI_DEL_ADJ("MINUS"),
14237         .DQS_LI_DEL_VAL(1'd1),
14238         .DQS_LO_DEL_ADJ("MINUS"),
14239         .DQS_LO_DEL_VAL(3'd4)
14240 ) DQSBUFM_2 (
14241         .DDRDEL(ddrphy_delay0),
14242         .DQSI(ddrphy_dqs_i2),
14243         .ECLK(sys2x_clk),
14244         .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[2])),
14245         .RDDIRECTION(1'd1),
14246         .RDLOADN(1'd0),
14247         .RDMOVE(1'd0),
14248         .READ0(ddrphy_dqs_re),
14249         .READ1(ddrphy_dqs_re),
14250         .READCLKSEL0(ddrphy_rdly2[0]),
14251         .READCLKSEL1(ddrphy_rdly2[1]),
14252         .READCLKSEL2(ddrphy_rdly2[2]),
14253         .RST(sys_rst),
14254         .SCLK(sys_clk),
14255         .WRDIRECTION(1'd1),
14256         .WRLOADN(1'd0),
14257         .WRMOVE(1'd0),
14258         .BURSTDET(ddrphy_burstdet2),
14259         .DATAVALID(ddrphy_datavalid[2]),
14260         .DQSR90(ddrphy_dqsr902),
14261         .DQSW(ddrphy_dqsw2),
14262         .DQSW270(ddrphy_dqsw2702),
14263         .RDPNTR0(ddrphy_rdpntr2[0]),
14264         .RDPNTR1(ddrphy_rdpntr2[1]),
14265         .RDPNTR2(ddrphy_rdpntr2[2]),
14266         .WRPNTR0(ddrphy_wrpntr2[0]),
14267         .WRPNTR1(ddrphy_wrpntr2[1]),
14268         .WRPNTR2(ddrphy_wrpntr2[2])
14269 );
14270
14271 ODDRX2DQSB ODDRX2DQSB_2(
14272         .D0(1'd0),
14273         .D1(1'd1),
14274         .D2(1'd0),
14275         .D3(1'd1),
14276         .DQSW(ddrphy_dqsw2),
14277         .ECLK(sys2x_clk),
14278         .RST(sys_rst),
14279         .SCLK(sys_clk),
14280         .Q(ddrphy_dqs2)
14281 );
14282
14283 TSHX2DQSA TSHX2DQSA_2(
14284         .DQSW(ddrphy_dqsw2),
14285         .ECLK(sys2x_clk),
14286         .RST(sys_rst),
14287         .SCLK(sys_clk),
14288         .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
14289         .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
14290         .Q(ddrphy_dqs_oe_n2)
14291 );
14292
14293 ODDRX2DQA ODDRX2DQA_18(
14294         .D0(ddrphy_dm_o_data_muxed2[0]),
14295         .D1(ddrphy_dm_o_data_muxed2[1]),
14296         .D2(ddrphy_dm_o_data_muxed2[2]),
14297         .D3(ddrphy_dm_o_data_muxed2[3]),
14298         .DQSW270(ddrphy_dqsw2702),
14299         .ECLK(sys2x_clk),
14300         .RST(sys_rst),
14301         .SCLK(sys_clk),
14302         .Q(ddram_dm[2])
14303 );
14304
14305 ODDRX2DQA ODDRX2DQA_19(
14306         .D0(ddrphy_dq_o_data_muxed16[0]),
14307         .D1(ddrphy_dq_o_data_muxed16[1]),
14308         .D2(ddrphy_dq_o_data_muxed16[2]),
14309         .D3(ddrphy_dq_o_data_muxed16[3]),
14310         .DQSW270(ddrphy_dqsw2702),
14311         .ECLK(sys2x_clk),
14312         .RST(sys_rst),
14313         .SCLK(sys_clk),
14314         .Q(ddrphy_dq_o16)
14315 );
14316
14317 DELAYG #(
14318         .DEL_MODE("DQS_ALIGNED_X2")
14319 ) DELAYG_43 (
14320         .A(ddrphy_dq_i16),
14321         .Z(ddrphy_dq_i_delayed16)
14322 );
14323
14324 IDDRX2DQA IDDRX2DQA_16(
14325         .D(ddrphy_dq_i_delayed16),
14326         .DQSR90(ddrphy_dqsr902),
14327         .ECLK(sys2x_clk),
14328         .RDPNTR0(ddrphy_rdpntr2[0]),
14329         .RDPNTR1(ddrphy_rdpntr2[1]),
14330         .RDPNTR2(ddrphy_rdpntr2[2]),
14331         .RST(sys_rst),
14332         .SCLK(sys_clk),
14333         .WRPNTR0(ddrphy_wrpntr2[0]),
14334         .WRPNTR1(ddrphy_wrpntr2[1]),
14335         .WRPNTR2(ddrphy_wrpntr2[2]),
14336         .Q0(ddrphy_bitslip16_i[0]),
14337         .Q1(ddrphy_bitslip16_i[1]),
14338         .Q2(ddrphy_bitslip16_i[2]),
14339         .Q3(ddrphy_bitslip16_i[3])
14340 );
14341
14342 TSHX2DQA TSHX2DQA_16(
14343         .DQSW270(ddrphy_dqsw2702),
14344         .ECLK(sys2x_clk),
14345         .RST(sys_rst),
14346         .SCLK(sys_clk),
14347         .T0((~ddrphy_dq_oe)),
14348         .T1((~ddrphy_dq_oe)),
14349         .Q(ddrphy_dq_oe_n16)
14350 );
14351
14352 ODDRX2DQA ODDRX2DQA_20(
14353         .D0(ddrphy_dq_o_data_muxed17[0]),
14354         .D1(ddrphy_dq_o_data_muxed17[1]),
14355         .D2(ddrphy_dq_o_data_muxed17[2]),
14356         .D3(ddrphy_dq_o_data_muxed17[3]),
14357         .DQSW270(ddrphy_dqsw2702),
14358         .ECLK(sys2x_clk),
14359         .RST(sys_rst),
14360         .SCLK(sys_clk),
14361         .Q(ddrphy_dq_o17)
14362 );
14363
14364 DELAYG #(
14365         .DEL_MODE("DQS_ALIGNED_X2")
14366 ) DELAYG_44 (
14367         .A(ddrphy_dq_i17),
14368         .Z(ddrphy_dq_i_delayed17)
14369 );
14370
14371 IDDRX2DQA IDDRX2DQA_17(
14372         .D(ddrphy_dq_i_delayed17),
14373         .DQSR90(ddrphy_dqsr902),
14374         .ECLK(sys2x_clk),
14375         .RDPNTR0(ddrphy_rdpntr2[0]),
14376         .RDPNTR1(ddrphy_rdpntr2[1]),
14377         .RDPNTR2(ddrphy_rdpntr2[2]),
14378         .RST(sys_rst),
14379         .SCLK(sys_clk),
14380         .WRPNTR0(ddrphy_wrpntr2[0]),
14381         .WRPNTR1(ddrphy_wrpntr2[1]),
14382         .WRPNTR2(ddrphy_wrpntr2[2]),
14383         .Q0(ddrphy_bitslip17_i[0]),
14384         .Q1(ddrphy_bitslip17_i[1]),
14385         .Q2(ddrphy_bitslip17_i[2]),
14386         .Q3(ddrphy_bitslip17_i[3])
14387 );
14388
14389 TSHX2DQA TSHX2DQA_17(
14390         .DQSW270(ddrphy_dqsw2702),
14391         .ECLK(sys2x_clk),
14392         .RST(sys_rst),
14393         .SCLK(sys_clk),
14394         .T0((~ddrphy_dq_oe)),
14395         .T1((~ddrphy_dq_oe)),
14396         .Q(ddrphy_dq_oe_n17)
14397 );
14398
14399 ODDRX2DQA ODDRX2DQA_21(
14400         .D0(ddrphy_dq_o_data_muxed18[0]),
14401         .D1(ddrphy_dq_o_data_muxed18[1]),
14402         .D2(ddrphy_dq_o_data_muxed18[2]),
14403         .D3(ddrphy_dq_o_data_muxed18[3]),
14404         .DQSW270(ddrphy_dqsw2702),
14405         .ECLK(sys2x_clk),
14406         .RST(sys_rst),
14407         .SCLK(sys_clk),
14408         .Q(ddrphy_dq_o18)
14409 );
14410
14411 DELAYG #(
14412         .DEL_MODE("DQS_ALIGNED_X2")
14413 ) DELAYG_45 (
14414         .A(ddrphy_dq_i18),
14415         .Z(ddrphy_dq_i_delayed18)
14416 );
14417
14418 IDDRX2DQA IDDRX2DQA_18(
14419         .D(ddrphy_dq_i_delayed18),
14420         .DQSR90(ddrphy_dqsr902),
14421         .ECLK(sys2x_clk),
14422         .RDPNTR0(ddrphy_rdpntr2[0]),
14423         .RDPNTR1(ddrphy_rdpntr2[1]),
14424         .RDPNTR2(ddrphy_rdpntr2[2]),
14425         .RST(sys_rst),
14426         .SCLK(sys_clk),
14427         .WRPNTR0(ddrphy_wrpntr2[0]),
14428         .WRPNTR1(ddrphy_wrpntr2[1]),
14429         .WRPNTR2(ddrphy_wrpntr2[2]),
14430         .Q0(ddrphy_bitslip18_i[0]),
14431         .Q1(ddrphy_bitslip18_i[1]),
14432         .Q2(ddrphy_bitslip18_i[2]),
14433         .Q3(ddrphy_bitslip18_i[3])
14434 );
14435
14436 TSHX2DQA TSHX2DQA_18(
14437         .DQSW270(ddrphy_dqsw2702),
14438         .ECLK(sys2x_clk),
14439         .RST(sys_rst),
14440         .SCLK(sys_clk),
14441         .T0((~ddrphy_dq_oe)),
14442         .T1((~ddrphy_dq_oe)),
14443         .Q(ddrphy_dq_oe_n18)
14444 );
14445
14446 ODDRX2DQA ODDRX2DQA_22(
14447         .D0(ddrphy_dq_o_data_muxed19[0]),
14448         .D1(ddrphy_dq_o_data_muxed19[1]),
14449         .D2(ddrphy_dq_o_data_muxed19[2]),
14450         .D3(ddrphy_dq_o_data_muxed19[3]),
14451         .DQSW270(ddrphy_dqsw2702),
14452         .ECLK(sys2x_clk),
14453         .RST(sys_rst),
14454         .SCLK(sys_clk),
14455         .Q(ddrphy_dq_o19)
14456 );
14457
14458 DELAYG #(
14459         .DEL_MODE("DQS_ALIGNED_X2")
14460 ) DELAYG_46 (
14461         .A(ddrphy_dq_i19),
14462         .Z(ddrphy_dq_i_delayed19)
14463 );
14464
14465 IDDRX2DQA IDDRX2DQA_19(
14466         .D(ddrphy_dq_i_delayed19),
14467         .DQSR90(ddrphy_dqsr902),
14468         .ECLK(sys2x_clk),
14469         .RDPNTR0(ddrphy_rdpntr2[0]),
14470         .RDPNTR1(ddrphy_rdpntr2[1]),
14471         .RDPNTR2(ddrphy_rdpntr2[2]),
14472         .RST(sys_rst),
14473         .SCLK(sys_clk),
14474         .WRPNTR0(ddrphy_wrpntr2[0]),
14475         .WRPNTR1(ddrphy_wrpntr2[1]),
14476         .WRPNTR2(ddrphy_wrpntr2[2]),
14477         .Q0(ddrphy_bitslip19_i[0]),
14478         .Q1(ddrphy_bitslip19_i[1]),
14479         .Q2(ddrphy_bitslip19_i[2]),
14480         .Q3(ddrphy_bitslip19_i[3])
14481 );
14482
14483 TSHX2DQA TSHX2DQA_19(
14484         .DQSW270(ddrphy_dqsw2702),
14485         .ECLK(sys2x_clk),
14486         .RST(sys_rst),
14487         .SCLK(sys_clk),
14488         .T0((~ddrphy_dq_oe)),
14489         .T1((~ddrphy_dq_oe)),
14490         .Q(ddrphy_dq_oe_n19)
14491 );
14492
14493 ODDRX2DQA ODDRX2DQA_23(
14494         .D0(ddrphy_dq_o_data_muxed20[0]),
14495         .D1(ddrphy_dq_o_data_muxed20[1]),
14496         .D2(ddrphy_dq_o_data_muxed20[2]),
14497         .D3(ddrphy_dq_o_data_muxed20[3]),
14498         .DQSW270(ddrphy_dqsw2702),
14499         .ECLK(sys2x_clk),
14500         .RST(sys_rst),
14501         .SCLK(sys_clk),
14502         .Q(ddrphy_dq_o20)
14503 );
14504
14505 DELAYG #(
14506         .DEL_MODE("DQS_ALIGNED_X2")
14507 ) DELAYG_47 (
14508         .A(ddrphy_dq_i20),
14509         .Z(ddrphy_dq_i_delayed20)
14510 );
14511
14512 IDDRX2DQA IDDRX2DQA_20(
14513         .D(ddrphy_dq_i_delayed20),
14514         .DQSR90(ddrphy_dqsr902),
14515         .ECLK(sys2x_clk),
14516         .RDPNTR0(ddrphy_rdpntr2[0]),
14517         .RDPNTR1(ddrphy_rdpntr2[1]),
14518         .RDPNTR2(ddrphy_rdpntr2[2]),
14519         .RST(sys_rst),
14520         .SCLK(sys_clk),
14521         .WRPNTR0(ddrphy_wrpntr2[0]),
14522         .WRPNTR1(ddrphy_wrpntr2[1]),
14523         .WRPNTR2(ddrphy_wrpntr2[2]),
14524         .Q0(ddrphy_bitslip20_i[0]),
14525         .Q1(ddrphy_bitslip20_i[1]),
14526         .Q2(ddrphy_bitslip20_i[2]),
14527         .Q3(ddrphy_bitslip20_i[3])
14528 );
14529
14530 TSHX2DQA TSHX2DQA_20(
14531         .DQSW270(ddrphy_dqsw2702),
14532         .ECLK(sys2x_clk),
14533         .RST(sys_rst),
14534         .SCLK(sys_clk),
14535         .T0((~ddrphy_dq_oe)),
14536         .T1((~ddrphy_dq_oe)),
14537         .Q(ddrphy_dq_oe_n20)
14538 );
14539
14540 ODDRX2DQA ODDRX2DQA_24(
14541         .D0(ddrphy_dq_o_data_muxed21[0]),
14542         .D1(ddrphy_dq_o_data_muxed21[1]),
14543         .D2(ddrphy_dq_o_data_muxed21[2]),
14544         .D3(ddrphy_dq_o_data_muxed21[3]),
14545         .DQSW270(ddrphy_dqsw2702),
14546         .ECLK(sys2x_clk),
14547         .RST(sys_rst),
14548         .SCLK(sys_clk),
14549         .Q(ddrphy_dq_o21)
14550 );
14551
14552 DELAYG #(
14553         .DEL_MODE("DQS_ALIGNED_X2")
14554 ) DELAYG_48 (
14555         .A(ddrphy_dq_i21),
14556         .Z(ddrphy_dq_i_delayed21)
14557 );
14558
14559 IDDRX2DQA IDDRX2DQA_21(
14560         .D(ddrphy_dq_i_delayed21),
14561         .DQSR90(ddrphy_dqsr902),
14562         .ECLK(sys2x_clk),
14563         .RDPNTR0(ddrphy_rdpntr2[0]),
14564         .RDPNTR1(ddrphy_rdpntr2[1]),
14565         .RDPNTR2(ddrphy_rdpntr2[2]),
14566         .RST(sys_rst),
14567         .SCLK(sys_clk),
14568         .WRPNTR0(ddrphy_wrpntr2[0]),
14569         .WRPNTR1(ddrphy_wrpntr2[1]),
14570         .WRPNTR2(ddrphy_wrpntr2[2]),
14571         .Q0(ddrphy_bitslip21_i[0]),
14572         .Q1(ddrphy_bitslip21_i[1]),
14573         .Q2(ddrphy_bitslip21_i[2]),
14574         .Q3(ddrphy_bitslip21_i[3])
14575 );
14576
14577 TSHX2DQA TSHX2DQA_21(
14578         .DQSW270(ddrphy_dqsw2702),
14579         .ECLK(sys2x_clk),
14580         .RST(sys_rst),
14581         .SCLK(sys_clk),
14582         .T0((~ddrphy_dq_oe)),
14583         .T1((~ddrphy_dq_oe)),
14584         .Q(ddrphy_dq_oe_n21)
14585 );
14586
14587 ODDRX2DQA ODDRX2DQA_25(
14588         .D0(ddrphy_dq_o_data_muxed22[0]),
14589         .D1(ddrphy_dq_o_data_muxed22[1]),
14590         .D2(ddrphy_dq_o_data_muxed22[2]),
14591         .D3(ddrphy_dq_o_data_muxed22[3]),
14592         .DQSW270(ddrphy_dqsw2702),
14593         .ECLK(sys2x_clk),
14594         .RST(sys_rst),
14595         .SCLK(sys_clk),
14596         .Q(ddrphy_dq_o22)
14597 );
14598
14599 DELAYG #(
14600         .DEL_MODE("DQS_ALIGNED_X2")
14601 ) DELAYG_49 (
14602         .A(ddrphy_dq_i22),
14603         .Z(ddrphy_dq_i_delayed22)
14604 );
14605
14606 IDDRX2DQA IDDRX2DQA_22(
14607         .D(ddrphy_dq_i_delayed22),
14608         .DQSR90(ddrphy_dqsr902),
14609         .ECLK(sys2x_clk),
14610         .RDPNTR0(ddrphy_rdpntr2[0]),
14611         .RDPNTR1(ddrphy_rdpntr2[1]),
14612         .RDPNTR2(ddrphy_rdpntr2[2]),
14613         .RST(sys_rst),
14614         .SCLK(sys_clk),
14615         .WRPNTR0(ddrphy_wrpntr2[0]),
14616         .WRPNTR1(ddrphy_wrpntr2[1]),
14617         .WRPNTR2(ddrphy_wrpntr2[2]),
14618         .Q0(ddrphy_bitslip22_i[0]),
14619         .Q1(ddrphy_bitslip22_i[1]),
14620         .Q2(ddrphy_bitslip22_i[2]),
14621         .Q3(ddrphy_bitslip22_i[3])
14622 );
14623
14624 TSHX2DQA TSHX2DQA_22(
14625         .DQSW270(ddrphy_dqsw2702),
14626         .ECLK(sys2x_clk),
14627         .RST(sys_rst),
14628         .SCLK(sys_clk),
14629         .T0((~ddrphy_dq_oe)),
14630         .T1((~ddrphy_dq_oe)),
14631         .Q(ddrphy_dq_oe_n22)
14632 );
14633
14634 ODDRX2DQA ODDRX2DQA_26(
14635         .D0(ddrphy_dq_o_data_muxed23[0]),
14636         .D1(ddrphy_dq_o_data_muxed23[1]),
14637         .D2(ddrphy_dq_o_data_muxed23[2]),
14638         .D3(ddrphy_dq_o_data_muxed23[3]),
14639         .DQSW270(ddrphy_dqsw2702),
14640         .ECLK(sys2x_clk),
14641         .RST(sys_rst),
14642         .SCLK(sys_clk),
14643         .Q(ddrphy_dq_o23)
14644 );
14645
14646 DELAYG #(
14647         .DEL_MODE("DQS_ALIGNED_X2")
14648 ) DELAYG_50 (
14649         .A(ddrphy_dq_i23),
14650         .Z(ddrphy_dq_i_delayed23)
14651 );
14652
14653 IDDRX2DQA IDDRX2DQA_23(
14654         .D(ddrphy_dq_i_delayed23),
14655         .DQSR90(ddrphy_dqsr902),
14656         .ECLK(sys2x_clk),
14657         .RDPNTR0(ddrphy_rdpntr2[0]),
14658         .RDPNTR1(ddrphy_rdpntr2[1]),
14659         .RDPNTR2(ddrphy_rdpntr2[2]),
14660         .RST(sys_rst),
14661         .SCLK(sys_clk),
14662         .WRPNTR0(ddrphy_wrpntr2[0]),
14663         .WRPNTR1(ddrphy_wrpntr2[1]),
14664         .WRPNTR2(ddrphy_wrpntr2[2]),
14665         .Q0(ddrphy_bitslip23_i[0]),
14666         .Q1(ddrphy_bitslip23_i[1]),
14667         .Q2(ddrphy_bitslip23_i[2]),
14668         .Q3(ddrphy_bitslip23_i[3])
14669 );
14670
14671 TSHX2DQA TSHX2DQA_23(
14672         .DQSW270(ddrphy_dqsw2702),
14673         .ECLK(sys2x_clk),
14674         .RST(sys_rst),
14675         .SCLK(sys_clk),
14676         .T0((~ddrphy_dq_oe)),
14677         .T1((~ddrphy_dq_oe)),
14678         .Q(ddrphy_dq_oe_n23)
14679 );
14680
14681 DQSBUFM #(
14682         .DQS_LI_DEL_ADJ("MINUS"),
14683         .DQS_LI_DEL_VAL(1'd1),
14684         .DQS_LO_DEL_ADJ("MINUS"),
14685         .DQS_LO_DEL_VAL(3'd4)
14686 ) DQSBUFM_3 (
14687         .DDRDEL(ddrphy_delay0),
14688         .DQSI(ddrphy_dqs_i3),
14689         .ECLK(sys2x_clk),
14690         .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[3])),
14691         .RDDIRECTION(1'd1),
14692         .RDLOADN(1'd0),
14693         .RDMOVE(1'd0),
14694         .READ0(ddrphy_dqs_re),
14695         .READ1(ddrphy_dqs_re),
14696         .READCLKSEL0(ddrphy_rdly3[0]),
14697         .READCLKSEL1(ddrphy_rdly3[1]),
14698         .READCLKSEL2(ddrphy_rdly3[2]),
14699         .RST(sys_rst),
14700         .SCLK(sys_clk),
14701         .WRDIRECTION(1'd1),
14702         .WRLOADN(1'd0),
14703         .WRMOVE(1'd0),
14704         .BURSTDET(ddrphy_burstdet3),
14705         .DATAVALID(ddrphy_datavalid[3]),
14706         .DQSR90(ddrphy_dqsr903),
14707         .DQSW(ddrphy_dqsw3),
14708         .DQSW270(ddrphy_dqsw2703),
14709         .RDPNTR0(ddrphy_rdpntr3[0]),
14710         .RDPNTR1(ddrphy_rdpntr3[1]),
14711         .RDPNTR2(ddrphy_rdpntr3[2]),
14712         .WRPNTR0(ddrphy_wrpntr3[0]),
14713         .WRPNTR1(ddrphy_wrpntr3[1]),
14714         .WRPNTR2(ddrphy_wrpntr3[2])
14715 );
14716
14717 ODDRX2DQSB ODDRX2DQSB_3(
14718         .D0(1'd0),
14719         .D1(1'd1),
14720         .D2(1'd0),
14721         .D3(1'd1),
14722         .DQSW(ddrphy_dqsw3),
14723         .ECLK(sys2x_clk),
14724         .RST(sys_rst),
14725         .SCLK(sys_clk),
14726         .Q(ddrphy_dqs3)
14727 );
14728
14729 TSHX2DQSA TSHX2DQSA_3(
14730         .DQSW(ddrphy_dqsw3),
14731         .ECLK(sys2x_clk),
14732         .RST(sys_rst),
14733         .SCLK(sys_clk),
14734         .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
14735         .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
14736         .Q(ddrphy_dqs_oe_n3)
14737 );
14738
14739 ODDRX2DQA ODDRX2DQA_27(
14740         .D0(ddrphy_dm_o_data_muxed3[0]),
14741         .D1(ddrphy_dm_o_data_muxed3[1]),
14742         .D2(ddrphy_dm_o_data_muxed3[2]),
14743         .D3(ddrphy_dm_o_data_muxed3[3]),
14744         .DQSW270(ddrphy_dqsw2703),
14745         .ECLK(sys2x_clk),
14746         .RST(sys_rst),
14747         .SCLK(sys_clk),
14748         .Q(ddram_dm[3])
14749 );
14750
14751 ODDRX2DQA ODDRX2DQA_28(
14752         .D0(ddrphy_dq_o_data_muxed24[0]),
14753         .D1(ddrphy_dq_o_data_muxed24[1]),
14754         .D2(ddrphy_dq_o_data_muxed24[2]),
14755         .D3(ddrphy_dq_o_data_muxed24[3]),
14756         .DQSW270(ddrphy_dqsw2703),
14757         .ECLK(sys2x_clk),
14758         .RST(sys_rst),
14759         .SCLK(sys_clk),
14760         .Q(ddrphy_dq_o24)
14761 );
14762
14763 DELAYG #(
14764         .DEL_MODE("DQS_ALIGNED_X2")
14765 ) DELAYG_51 (
14766         .A(ddrphy_dq_i24),
14767         .Z(ddrphy_dq_i_delayed24)
14768 );
14769
14770 IDDRX2DQA IDDRX2DQA_24(
14771         .D(ddrphy_dq_i_delayed24),
14772         .DQSR90(ddrphy_dqsr903),
14773         .ECLK(sys2x_clk),
14774         .RDPNTR0(ddrphy_rdpntr3[0]),
14775         .RDPNTR1(ddrphy_rdpntr3[1]),
14776         .RDPNTR2(ddrphy_rdpntr3[2]),
14777         .RST(sys_rst),
14778         .SCLK(sys_clk),
14779         .WRPNTR0(ddrphy_wrpntr3[0]),
14780         .WRPNTR1(ddrphy_wrpntr3[1]),
14781         .WRPNTR2(ddrphy_wrpntr3[2]),
14782         .Q0(ddrphy_bitslip24_i[0]),
14783         .Q1(ddrphy_bitslip24_i[1]),
14784         .Q2(ddrphy_bitslip24_i[2]),
14785         .Q3(ddrphy_bitslip24_i[3])
14786 );
14787
14788 TSHX2DQA TSHX2DQA_24(
14789         .DQSW270(ddrphy_dqsw2703),
14790         .ECLK(sys2x_clk),
14791         .RST(sys_rst),
14792         .SCLK(sys_clk),
14793         .T0((~ddrphy_dq_oe)),
14794         .T1((~ddrphy_dq_oe)),
14795         .Q(ddrphy_dq_oe_n24)
14796 );
14797
14798 ODDRX2DQA ODDRX2DQA_29(
14799         .D0(ddrphy_dq_o_data_muxed25[0]),
14800         .D1(ddrphy_dq_o_data_muxed25[1]),
14801         .D2(ddrphy_dq_o_data_muxed25[2]),
14802         .D3(ddrphy_dq_o_data_muxed25[3]),
14803         .DQSW270(ddrphy_dqsw2703),
14804         .ECLK(sys2x_clk),
14805         .RST(sys_rst),
14806         .SCLK(sys_clk),
14807         .Q(ddrphy_dq_o25)
14808 );
14809
14810 DELAYG #(
14811         .DEL_MODE("DQS_ALIGNED_X2")
14812 ) DELAYG_52 (
14813         .A(ddrphy_dq_i25),
14814         .Z(ddrphy_dq_i_delayed25)
14815 );
14816
14817 IDDRX2DQA IDDRX2DQA_25(
14818         .D(ddrphy_dq_i_delayed25),
14819         .DQSR90(ddrphy_dqsr903),
14820         .ECLK(sys2x_clk),
14821         .RDPNTR0(ddrphy_rdpntr3[0]),
14822         .RDPNTR1(ddrphy_rdpntr3[1]),
14823         .RDPNTR2(ddrphy_rdpntr3[2]),
14824         .RST(sys_rst),
14825         .SCLK(sys_clk),
14826         .WRPNTR0(ddrphy_wrpntr3[0]),
14827         .WRPNTR1(ddrphy_wrpntr3[1]),
14828         .WRPNTR2(ddrphy_wrpntr3[2]),
14829         .Q0(ddrphy_bitslip25_i[0]),
14830         .Q1(ddrphy_bitslip25_i[1]),
14831         .Q2(ddrphy_bitslip25_i[2]),
14832         .Q3(ddrphy_bitslip25_i[3])
14833 );
14834
14835 TSHX2DQA TSHX2DQA_25(
14836         .DQSW270(ddrphy_dqsw2703),
14837         .ECLK(sys2x_clk),
14838         .RST(sys_rst),
14839         .SCLK(sys_clk),
14840         .T0((~ddrphy_dq_oe)),
14841         .T1((~ddrphy_dq_oe)),
14842         .Q(ddrphy_dq_oe_n25)
14843 );
14844
14845 ODDRX2DQA ODDRX2DQA_30(
14846         .D0(ddrphy_dq_o_data_muxed26[0]),
14847         .D1(ddrphy_dq_o_data_muxed26[1]),
14848         .D2(ddrphy_dq_o_data_muxed26[2]),
14849         .D3(ddrphy_dq_o_data_muxed26[3]),
14850         .DQSW270(ddrphy_dqsw2703),
14851         .ECLK(sys2x_clk),
14852         .RST(sys_rst),
14853         .SCLK(sys_clk),
14854         .Q(ddrphy_dq_o26)
14855 );
14856
14857 DELAYG #(
14858         .DEL_MODE("DQS_ALIGNED_X2")
14859 ) DELAYG_53 (
14860         .A(ddrphy_dq_i26),
14861         .Z(ddrphy_dq_i_delayed26)
14862 );
14863
14864 IDDRX2DQA IDDRX2DQA_26(
14865         .D(ddrphy_dq_i_delayed26),
14866         .DQSR90(ddrphy_dqsr903),
14867         .ECLK(sys2x_clk),
14868         .RDPNTR0(ddrphy_rdpntr3[0]),
14869         .RDPNTR1(ddrphy_rdpntr3[1]),
14870         .RDPNTR2(ddrphy_rdpntr3[2]),
14871         .RST(sys_rst),
14872         .SCLK(sys_clk),
14873         .WRPNTR0(ddrphy_wrpntr3[0]),
14874         .WRPNTR1(ddrphy_wrpntr3[1]),
14875         .WRPNTR2(ddrphy_wrpntr3[2]),
14876         .Q0(ddrphy_bitslip26_i[0]),
14877         .Q1(ddrphy_bitslip26_i[1]),
14878         .Q2(ddrphy_bitslip26_i[2]),
14879         .Q3(ddrphy_bitslip26_i[3])
14880 );
14881
14882 TSHX2DQA TSHX2DQA_26(
14883         .DQSW270(ddrphy_dqsw2703),
14884         .ECLK(sys2x_clk),
14885         .RST(sys_rst),
14886         .SCLK(sys_clk),
14887         .T0((~ddrphy_dq_oe)),
14888         .T1((~ddrphy_dq_oe)),
14889         .Q(ddrphy_dq_oe_n26)
14890 );
14891
14892 ODDRX2DQA ODDRX2DQA_31(
14893         .D0(ddrphy_dq_o_data_muxed27[0]),
14894         .D1(ddrphy_dq_o_data_muxed27[1]),
14895         .D2(ddrphy_dq_o_data_muxed27[2]),
14896         .D3(ddrphy_dq_o_data_muxed27[3]),
14897         .DQSW270(ddrphy_dqsw2703),
14898         .ECLK(sys2x_clk),
14899         .RST(sys_rst),
14900         .SCLK(sys_clk),
14901         .Q(ddrphy_dq_o27)
14902 );
14903
14904 DELAYG #(
14905         .DEL_MODE("DQS_ALIGNED_X2")
14906 ) DELAYG_54 (
14907         .A(ddrphy_dq_i27),
14908         .Z(ddrphy_dq_i_delayed27)
14909 );
14910
14911 IDDRX2DQA IDDRX2DQA_27(
14912         .D(ddrphy_dq_i_delayed27),
14913         .DQSR90(ddrphy_dqsr903),
14914         .ECLK(sys2x_clk),
14915         .RDPNTR0(ddrphy_rdpntr3[0]),
14916         .RDPNTR1(ddrphy_rdpntr3[1]),
14917         .RDPNTR2(ddrphy_rdpntr3[2]),
14918         .RST(sys_rst),
14919         .SCLK(sys_clk),
14920         .WRPNTR0(ddrphy_wrpntr3[0]),
14921         .WRPNTR1(ddrphy_wrpntr3[1]),
14922         .WRPNTR2(ddrphy_wrpntr3[2]),
14923         .Q0(ddrphy_bitslip27_i[0]),
14924         .Q1(ddrphy_bitslip27_i[1]),
14925         .Q2(ddrphy_bitslip27_i[2]),
14926         .Q3(ddrphy_bitslip27_i[3])
14927 );
14928
14929 TSHX2DQA TSHX2DQA_27(
14930         .DQSW270(ddrphy_dqsw2703),
14931         .ECLK(sys2x_clk),
14932         .RST(sys_rst),
14933         .SCLK(sys_clk),
14934         .T0((~ddrphy_dq_oe)),
14935         .T1((~ddrphy_dq_oe)),
14936         .Q(ddrphy_dq_oe_n27)
14937 );
14938
14939 ODDRX2DQA ODDRX2DQA_32(
14940         .D0(ddrphy_dq_o_data_muxed28[0]),
14941         .D1(ddrphy_dq_o_data_muxed28[1]),
14942         .D2(ddrphy_dq_o_data_muxed28[2]),
14943         .D3(ddrphy_dq_o_data_muxed28[3]),
14944         .DQSW270(ddrphy_dqsw2703),
14945         .ECLK(sys2x_clk),
14946         .RST(sys_rst),
14947         .SCLK(sys_clk),
14948         .Q(ddrphy_dq_o28)
14949 );
14950
14951 DELAYG #(
14952         .DEL_MODE("DQS_ALIGNED_X2")
14953 ) DELAYG_55 (
14954         .A(ddrphy_dq_i28),
14955         .Z(ddrphy_dq_i_delayed28)
14956 );
14957
14958 IDDRX2DQA IDDRX2DQA_28(
14959         .D(ddrphy_dq_i_delayed28),
14960         .DQSR90(ddrphy_dqsr903),
14961         .ECLK(sys2x_clk),
14962         .RDPNTR0(ddrphy_rdpntr3[0]),
14963         .RDPNTR1(ddrphy_rdpntr3[1]),
14964         .RDPNTR2(ddrphy_rdpntr3[2]),
14965         .RST(sys_rst),
14966         .SCLK(sys_clk),
14967         .WRPNTR0(ddrphy_wrpntr3[0]),
14968         .WRPNTR1(ddrphy_wrpntr3[1]),
14969         .WRPNTR2(ddrphy_wrpntr3[2]),
14970         .Q0(ddrphy_bitslip28_i[0]),
14971         .Q1(ddrphy_bitslip28_i[1]),
14972         .Q2(ddrphy_bitslip28_i[2]),
14973         .Q3(ddrphy_bitslip28_i[3])
14974 );
14975
14976 TSHX2DQA TSHX2DQA_28(
14977         .DQSW270(ddrphy_dqsw2703),
14978         .ECLK(sys2x_clk),
14979         .RST(sys_rst),
14980         .SCLK(sys_clk),
14981         .T0((~ddrphy_dq_oe)),
14982         .T1((~ddrphy_dq_oe)),
14983         .Q(ddrphy_dq_oe_n28)
14984 );
14985
14986 ODDRX2DQA ODDRX2DQA_33(
14987         .D0(ddrphy_dq_o_data_muxed29[0]),
14988         .D1(ddrphy_dq_o_data_muxed29[1]),
14989         .D2(ddrphy_dq_o_data_muxed29[2]),
14990         .D3(ddrphy_dq_o_data_muxed29[3]),
14991         .DQSW270(ddrphy_dqsw2703),
14992         .ECLK(sys2x_clk),
14993         .RST(sys_rst),
14994         .SCLK(sys_clk),
14995         .Q(ddrphy_dq_o29)
14996 );
14997
14998 DELAYG #(
14999         .DEL_MODE("DQS_ALIGNED_X2")
15000 ) DELAYG_56 (
15001         .A(ddrphy_dq_i29),
15002         .Z(ddrphy_dq_i_delayed29)
15003 );
15004
15005 IDDRX2DQA IDDRX2DQA_29(
15006         .D(ddrphy_dq_i_delayed29),
15007         .DQSR90(ddrphy_dqsr903),
15008         .ECLK(sys2x_clk),
15009         .RDPNTR0(ddrphy_rdpntr3[0]),
15010         .RDPNTR1(ddrphy_rdpntr3[1]),
15011         .RDPNTR2(ddrphy_rdpntr3[2]),
15012         .RST(sys_rst),
15013         .SCLK(sys_clk),
15014         .WRPNTR0(ddrphy_wrpntr3[0]),
15015         .WRPNTR1(ddrphy_wrpntr3[1]),
15016         .WRPNTR2(ddrphy_wrpntr3[2]),
15017         .Q0(ddrphy_bitslip29_i[0]),
15018         .Q1(ddrphy_bitslip29_i[1]),
15019         .Q2(ddrphy_bitslip29_i[2]),
15020         .Q3(ddrphy_bitslip29_i[3])
15021 );
15022
15023 TSHX2DQA TSHX2DQA_29(
15024         .DQSW270(ddrphy_dqsw2703),
15025         .ECLK(sys2x_clk),
15026         .RST(sys_rst),
15027         .SCLK(sys_clk),
15028         .T0((~ddrphy_dq_oe)),
15029         .T1((~ddrphy_dq_oe)),
15030         .Q(ddrphy_dq_oe_n29)
15031 );
15032
15033 ODDRX2DQA ODDRX2DQA_34(
15034         .D0(ddrphy_dq_o_data_muxed30[0]),
15035         .D1(ddrphy_dq_o_data_muxed30[1]),
15036         .D2(ddrphy_dq_o_data_muxed30[2]),
15037         .D3(ddrphy_dq_o_data_muxed30[3]),
15038         .DQSW270(ddrphy_dqsw2703),
15039         .ECLK(sys2x_clk),
15040         .RST(sys_rst),
15041         .SCLK(sys_clk),
15042         .Q(ddrphy_dq_o30)
15043 );
15044
15045 DELAYG #(
15046         .DEL_MODE("DQS_ALIGNED_X2")
15047 ) DELAYG_57 (
15048         .A(ddrphy_dq_i30),
15049         .Z(ddrphy_dq_i_delayed30)
15050 );
15051
15052 IDDRX2DQA IDDRX2DQA_30(
15053         .D(ddrphy_dq_i_delayed30),
15054         .DQSR90(ddrphy_dqsr903),
15055         .ECLK(sys2x_clk),
15056         .RDPNTR0(ddrphy_rdpntr3[0]),
15057         .RDPNTR1(ddrphy_rdpntr3[1]),
15058         .RDPNTR2(ddrphy_rdpntr3[2]),
15059         .RST(sys_rst),
15060         .SCLK(sys_clk),
15061         .WRPNTR0(ddrphy_wrpntr3[0]),
15062         .WRPNTR1(ddrphy_wrpntr3[1]),
15063         .WRPNTR2(ddrphy_wrpntr3[2]),
15064         .Q0(ddrphy_bitslip30_i[0]),
15065         .Q1(ddrphy_bitslip30_i[1]),
15066         .Q2(ddrphy_bitslip30_i[2]),
15067         .Q3(ddrphy_bitslip30_i[3])
15068 );
15069
15070 TSHX2DQA TSHX2DQA_30(
15071         .DQSW270(ddrphy_dqsw2703),
15072         .ECLK(sys2x_clk),
15073         .RST(sys_rst),
15074         .SCLK(sys_clk),
15075         .T0((~ddrphy_dq_oe)),
15076         .T1((~ddrphy_dq_oe)),
15077         .Q(ddrphy_dq_oe_n30)
15078 );
15079
15080 ODDRX2DQA ODDRX2DQA_35(
15081         .D0(ddrphy_dq_o_data_muxed31[0]),
15082         .D1(ddrphy_dq_o_data_muxed31[1]),
15083         .D2(ddrphy_dq_o_data_muxed31[2]),
15084         .D3(ddrphy_dq_o_data_muxed31[3]),
15085         .DQSW270(ddrphy_dqsw2703),
15086         .ECLK(sys2x_clk),
15087         .RST(sys_rst),
15088         .SCLK(sys_clk),
15089         .Q(ddrphy_dq_o31)
15090 );
15091
15092 DELAYG #(
15093         .DEL_MODE("DQS_ALIGNED_X2")
15094 ) DELAYG_58 (
15095         .A(ddrphy_dq_i31),
15096         .Z(ddrphy_dq_i_delayed31)
15097 );
15098
15099 IDDRX2DQA IDDRX2DQA_31(
15100         .D(ddrphy_dq_i_delayed31),
15101         .DQSR90(ddrphy_dqsr903),
15102         .ECLK(sys2x_clk),
15103         .RDPNTR0(ddrphy_rdpntr3[0]),
15104         .RDPNTR1(ddrphy_rdpntr3[1]),
15105         .RDPNTR2(ddrphy_rdpntr3[2]),
15106         .RST(sys_rst),
15107         .SCLK(sys_clk),
15108         .WRPNTR0(ddrphy_wrpntr3[0]),
15109         .WRPNTR1(ddrphy_wrpntr3[1]),
15110         .WRPNTR2(ddrphy_wrpntr3[2]),
15111         .Q0(ddrphy_bitslip31_i[0]),
15112         .Q1(ddrphy_bitslip31_i[1]),
15113         .Q2(ddrphy_bitslip31_i[2]),
15114         .Q3(ddrphy_bitslip31_i[3])
15115 );
15116
15117 TSHX2DQA TSHX2DQA_31(
15118         .DQSW270(ddrphy_dqsw2703),
15119         .ECLK(sys2x_clk),
15120         .RST(sys_rst),
15121         .SCLK(sys_clk),
15122         .T0((~ddrphy_dq_oe)),
15123         .T1((~ddrphy_dq_oe)),
15124         .Q(ddrphy_dq_oe_n31)
15125 );
15126
15127 //------------------------------------------------------------------------------
15128 // Memory storage: 16-words x 25-bit
15129 //------------------------------------------------------------------------------
15130 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15131 // Port 1 | Read: Async | Write: ---- |
15132 reg [24:0] storage[0:15];
15133 reg [24:0] storage_dat0;
15134 always @(posedge sys_clk) begin
15135         if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
15136                 storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
15137         storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
15138 end
15139 always @(posedge sys_clk) begin
15140 end
15141 assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
15142 assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
15143
15144
15145 //------------------------------------------------------------------------------
15146 // Memory storage_1: 16-words x 25-bit
15147 //------------------------------------------------------------------------------
15148 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15149 // Port 1 | Read: Async | Write: ---- |
15150 reg [24:0] storage_1[0:15];
15151 reg [24:0] storage_1_dat0;
15152 always @(posedge sys_clk) begin
15153         if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
15154                 storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
15155         storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
15156 end
15157 always @(posedge sys_clk) begin
15158 end
15159 assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
15160 assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
15161
15162
15163 //------------------------------------------------------------------------------
15164 // Memory storage_2: 16-words x 25-bit
15165 //------------------------------------------------------------------------------
15166 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15167 // Port 1 | Read: Async | Write: ---- |
15168 reg [24:0] storage_2[0:15];
15169 reg [24:0] storage_2_dat0;
15170 always @(posedge sys_clk) begin
15171         if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
15172                 storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
15173         storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
15174 end
15175 always @(posedge sys_clk) begin
15176 end
15177 assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
15178 assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
15179
15180
15181 //------------------------------------------------------------------------------
15182 // Memory storage_3: 16-words x 25-bit
15183 //------------------------------------------------------------------------------
15184 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15185 // Port 1 | Read: Async | Write: ---- |
15186 reg [24:0] storage_3[0:15];
15187 reg [24:0] storage_3_dat0;
15188 always @(posedge sys_clk) begin
15189         if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
15190                 storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
15191         storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
15192 end
15193 always @(posedge sys_clk) begin
15194 end
15195 assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
15196 assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
15197
15198
15199 //------------------------------------------------------------------------------
15200 // Memory storage_4: 16-words x 25-bit
15201 //------------------------------------------------------------------------------
15202 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15203 // Port 1 | Read: Async | Write: ---- |
15204 reg [24:0] storage_4[0:15];
15205 reg [24:0] storage_4_dat0;
15206 always @(posedge sys_clk) begin
15207         if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
15208                 storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
15209         storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
15210 end
15211 always @(posedge sys_clk) begin
15212 end
15213 assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
15214 assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
15215
15216
15217 //------------------------------------------------------------------------------
15218 // Memory storage_5: 16-words x 25-bit
15219 //------------------------------------------------------------------------------
15220 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15221 // Port 1 | Read: Async | Write: ---- |
15222 reg [24:0] storage_5[0:15];
15223 reg [24:0] storage_5_dat0;
15224 always @(posedge sys_clk) begin
15225         if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
15226                 storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
15227         storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
15228 end
15229 always @(posedge sys_clk) begin
15230 end
15231 assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
15232 assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
15233
15234
15235 //------------------------------------------------------------------------------
15236 // Memory storage_6: 16-words x 25-bit
15237 //------------------------------------------------------------------------------
15238 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15239 // Port 1 | Read: Async | Write: ---- |
15240 reg [24:0] storage_6[0:15];
15241 reg [24:0] storage_6_dat0;
15242 always @(posedge sys_clk) begin
15243         if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
15244                 storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
15245         storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
15246 end
15247 always @(posedge sys_clk) begin
15248 end
15249 assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
15250 assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
15251
15252
15253 //------------------------------------------------------------------------------
15254 // Memory storage_7: 16-words x 25-bit
15255 //------------------------------------------------------------------------------
15256 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25
15257 // Port 1 | Read: Async | Write: ---- |
15258 reg [24:0] storage_7[0:15];
15259 reg [24:0] storage_7_dat0;
15260 always @(posedge sys_clk) begin
15261         if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
15262                 storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
15263         storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
15264 end
15265 always @(posedge sys_clk) begin
15266 end
15267 assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
15268 assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
15269
15270
15271 (* FREQUENCY_PIN_CLKI = "125.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #(
15272         .CLKFB_DIV(5'd16),
15273         .CLKI_DIV(2'd3),
15274         .CLKOP_CPHASE(3'd6),
15275         .CLKOP_DIV(3'd7),
15276         .CLKOP_ENABLE("ENABLED"),
15277         .CLKOP_FPHASE(1'd0),
15278         .CLKOS2_CPHASE(1'd0),
15279         .CLKOS2_DIV(1'd1),
15280         .CLKOS2_ENABLE("ENABLED"),
15281         .CLKOS2_FPHASE(1'd0),
15282         .CLKOS_CPHASE(5'd27),
15283         .CLKOS_DIV(5'd28),
15284         .CLKOS_ENABLE("ENABLED"),
15285         .CLKOS_FPHASE(1'd0),
15286         .FEEDBK_PATH("INT_OS2")
15287 ) EHXPLLL (
15288         .CLKI(crg_clkin),
15289         .RST(crg_reset1),
15290         .STDBY(crg_stdby),
15291         .CLKOP(crg_clkout0),
15292         .CLKOS(crg_clkout1),
15293         .CLKOS2(litedramecp5ddrphycrg_ecp5pll),
15294         .LOCK(litedramecp5ddrphycrg_locked)
15295 );
15296
15297 FD1S3BX FD1S3BX(
15298         .CK(sys2x_i_clk),
15299         .D(1'd0),
15300         .PD((~crg_locked)),
15301         .Q(latticeecp5asyncresetsynchronizerimpl0_rst1)
15302 );
15303
15304 FD1S3BX FD1S3BX_1(
15305         .CK(sys2x_i_clk),
15306         .D(latticeecp5asyncresetsynchronizerimpl0_rst1),
15307         .PD((~crg_locked)),
15308         .Q(latticeecp5asyncresetsynchronizerimpl0_expr)
15309 );
15310
15311 FD1S3BX FD1S3BX_2(
15312         .CK(init_clk),
15313         .D(1'd0),
15314         .PD((~crg_locked)),
15315         .Q(latticeecp5asyncresetsynchronizerimpl1_rst1)
15316 );
15317
15318 FD1S3BX FD1S3BX_3(
15319         .CK(init_clk),
15320         .D(latticeecp5asyncresetsynchronizerimpl1_rst1),
15321         .PD((~crg_locked)),
15322         .Q(init_rst)
15323 );
15324
15325 FD1S3BX FD1S3BX_4(
15326         .CK(sys_clk),
15327         .D(1'd0),
15328         .PD(((~crg_locked) | crg_reset0)),
15329         .Q(latticeecp5asyncresetsynchronizerimpl2_rst1)
15330 );
15331
15332 FD1S3BX FD1S3BX_5(
15333         .CK(sys_clk),
15334         .D(latticeecp5asyncresetsynchronizerimpl2_rst1),
15335         .PD(((~crg_locked) | crg_reset0)),
15336         .Q(sys_rst)
15337 );
15338
15339 FD1S3BX FD1S3BX_6(
15340         .CK(sys2x_clk),
15341         .D(1'd0),
15342         .PD(((~crg_locked) | crg_reset0)),
15343         .Q(latticeecp5asyncresetsynchronizerimpl3_rst1)
15344 );
15345
15346 FD1S3BX FD1S3BX_7(
15347         .CK(sys2x_clk),
15348         .D(latticeecp5asyncresetsynchronizerimpl3_rst1),
15349         .PD(((~crg_locked) | crg_reset0)),
15350         .Q(sys2x_rst)
15351 );
15352
15353 TRELLIS_IO #(
15354         .DIR("BIDIR")
15355 ) TRELLIS_IO (
15356         .B(ddram_dqs_p[0]),
15357         .I(ddrphy_dqs0),
15358         .T((~(~ddrphy_dqs_oe_n0))),
15359         .O(ddrphy_dqs_i0)
15360 );
15361
15362 TRELLIS_IO #(
15363         .DIR("BIDIR")
15364 ) TRELLIS_IO_1 (
15365         .B(ddram_dq[0]),
15366         .I(ddrphy_dq_o0),
15367         .T((~(~ddrphy_dq_oe_n0))),
15368         .O(ddrphy_dq_i0)
15369 );
15370
15371 TRELLIS_IO #(
15372         .DIR("BIDIR")
15373 ) TRELLIS_IO_2 (
15374         .B(ddram_dq[1]),
15375         .I(ddrphy_dq_o1),
15376         .T((~(~ddrphy_dq_oe_n1))),
15377         .O(ddrphy_dq_i1)
15378 );
15379
15380 TRELLIS_IO #(
15381         .DIR("BIDIR")
15382 ) TRELLIS_IO_3 (
15383         .B(ddram_dq[2]),
15384         .I(ddrphy_dq_o2),
15385         .T((~(~ddrphy_dq_oe_n2))),
15386         .O(ddrphy_dq_i2)
15387 );
15388
15389 TRELLIS_IO #(
15390         .DIR("BIDIR")
15391 ) TRELLIS_IO_4 (
15392         .B(ddram_dq[3]),
15393         .I(ddrphy_dq_o3),
15394         .T((~(~ddrphy_dq_oe_n3))),
15395         .O(ddrphy_dq_i3)
15396 );
15397
15398 TRELLIS_IO #(
15399         .DIR("BIDIR")
15400 ) TRELLIS_IO_5 (
15401         .B(ddram_dq[4]),
15402         .I(ddrphy_dq_o4),
15403         .T((~(~ddrphy_dq_oe_n4))),
15404         .O(ddrphy_dq_i4)
15405 );
15406
15407 TRELLIS_IO #(
15408         .DIR("BIDIR")
15409 ) TRELLIS_IO_6 (
15410         .B(ddram_dq[5]),
15411         .I(ddrphy_dq_o5),
15412         .T((~(~ddrphy_dq_oe_n5))),
15413         .O(ddrphy_dq_i5)
15414 );
15415
15416 TRELLIS_IO #(
15417         .DIR("BIDIR")
15418 ) TRELLIS_IO_7 (
15419         .B(ddram_dq[6]),
15420         .I(ddrphy_dq_o6),
15421         .T((~(~ddrphy_dq_oe_n6))),
15422         .O(ddrphy_dq_i6)
15423 );
15424
15425 TRELLIS_IO #(
15426         .DIR("BIDIR")
15427 ) TRELLIS_IO_8 (
15428         .B(ddram_dq[7]),
15429         .I(ddrphy_dq_o7),
15430         .T((~(~ddrphy_dq_oe_n7))),
15431         .O(ddrphy_dq_i7)
15432 );
15433
15434 TRELLIS_IO #(
15435         .DIR("BIDIR")
15436 ) TRELLIS_IO_9 (
15437         .B(ddram_dqs_p[1]),
15438         .I(ddrphy_dqs1),
15439         .T((~(~ddrphy_dqs_oe_n1))),
15440         .O(ddrphy_dqs_i1)
15441 );
15442
15443 TRELLIS_IO #(
15444         .DIR("BIDIR")
15445 ) TRELLIS_IO_10 (
15446         .B(ddram_dq[8]),
15447         .I(ddrphy_dq_o8),
15448         .T((~(~ddrphy_dq_oe_n8))),
15449         .O(ddrphy_dq_i8)
15450 );
15451
15452 TRELLIS_IO #(
15453         .DIR("BIDIR")
15454 ) TRELLIS_IO_11 (
15455         .B(ddram_dq[9]),
15456         .I(ddrphy_dq_o9),
15457         .T((~(~ddrphy_dq_oe_n9))),
15458         .O(ddrphy_dq_i9)
15459 );
15460
15461 TRELLIS_IO #(
15462         .DIR("BIDIR")
15463 ) TRELLIS_IO_12 (
15464         .B(ddram_dq[10]),
15465         .I(ddrphy_dq_o10),
15466         .T((~(~ddrphy_dq_oe_n10))),
15467         .O(ddrphy_dq_i10)
15468 );
15469
15470 TRELLIS_IO #(
15471         .DIR("BIDIR")
15472 ) TRELLIS_IO_13 (
15473         .B(ddram_dq[11]),
15474         .I(ddrphy_dq_o11),
15475         .T((~(~ddrphy_dq_oe_n11))),
15476         .O(ddrphy_dq_i11)
15477 );
15478
15479 TRELLIS_IO #(
15480         .DIR("BIDIR")
15481 ) TRELLIS_IO_14 (
15482         .B(ddram_dq[12]),
15483         .I(ddrphy_dq_o12),
15484         .T((~(~ddrphy_dq_oe_n12))),
15485         .O(ddrphy_dq_i12)
15486 );
15487
15488 TRELLIS_IO #(
15489         .DIR("BIDIR")
15490 ) TRELLIS_IO_15 (
15491         .B(ddram_dq[13]),
15492         .I(ddrphy_dq_o13),
15493         .T((~(~ddrphy_dq_oe_n13))),
15494         .O(ddrphy_dq_i13)
15495 );
15496
15497 TRELLIS_IO #(
15498         .DIR("BIDIR")
15499 ) TRELLIS_IO_16 (
15500         .B(ddram_dq[14]),
15501         .I(ddrphy_dq_o14),
15502         .T((~(~ddrphy_dq_oe_n14))),
15503         .O(ddrphy_dq_i14)
15504 );
15505
15506 TRELLIS_IO #(
15507         .DIR("BIDIR")
15508 ) TRELLIS_IO_17 (
15509         .B(ddram_dq[15]),
15510         .I(ddrphy_dq_o15),
15511         .T((~(~ddrphy_dq_oe_n15))),
15512         .O(ddrphy_dq_i15)
15513 );
15514
15515 TRELLIS_IO #(
15516         .DIR("BIDIR")
15517 ) TRELLIS_IO_18 (
15518         .B(ddram_dqs_p[2]),
15519         .I(ddrphy_dqs2),
15520         .T((~(~ddrphy_dqs_oe_n2))),
15521         .O(ddrphy_dqs_i2)
15522 );
15523
15524 TRELLIS_IO #(
15525         .DIR("BIDIR")
15526 ) TRELLIS_IO_19 (
15527         .B(ddram_dq[16]),
15528         .I(ddrphy_dq_o16),
15529         .T((~(~ddrphy_dq_oe_n16))),
15530         .O(ddrphy_dq_i16)
15531 );
15532
15533 TRELLIS_IO #(
15534         .DIR("BIDIR")
15535 ) TRELLIS_IO_20 (
15536         .B(ddram_dq[17]),
15537         .I(ddrphy_dq_o17),
15538         .T((~(~ddrphy_dq_oe_n17))),
15539         .O(ddrphy_dq_i17)
15540 );
15541
15542 TRELLIS_IO #(
15543         .DIR("BIDIR")
15544 ) TRELLIS_IO_21 (
15545         .B(ddram_dq[18]),
15546         .I(ddrphy_dq_o18),
15547         .T((~(~ddrphy_dq_oe_n18))),
15548         .O(ddrphy_dq_i18)
15549 );
15550
15551 TRELLIS_IO #(
15552         .DIR("BIDIR")
15553 ) TRELLIS_IO_22 (
15554         .B(ddram_dq[19]),
15555         .I(ddrphy_dq_o19),
15556         .T((~(~ddrphy_dq_oe_n19))),
15557         .O(ddrphy_dq_i19)
15558 );
15559
15560 TRELLIS_IO #(
15561         .DIR("BIDIR")
15562 ) TRELLIS_IO_23 (
15563         .B(ddram_dq[20]),
15564         .I(ddrphy_dq_o20),
15565         .T((~(~ddrphy_dq_oe_n20))),
15566         .O(ddrphy_dq_i20)
15567 );
15568
15569 TRELLIS_IO #(
15570         .DIR("BIDIR")
15571 ) TRELLIS_IO_24 (
15572         .B(ddram_dq[21]),
15573         .I(ddrphy_dq_o21),
15574         .T((~(~ddrphy_dq_oe_n21))),
15575         .O(ddrphy_dq_i21)
15576 );
15577
15578 TRELLIS_IO #(
15579         .DIR("BIDIR")
15580 ) TRELLIS_IO_25 (
15581         .B(ddram_dq[22]),
15582         .I(ddrphy_dq_o22),
15583         .T((~(~ddrphy_dq_oe_n22))),
15584         .O(ddrphy_dq_i22)
15585 );
15586
15587 TRELLIS_IO #(
15588         .DIR("BIDIR")
15589 ) TRELLIS_IO_26 (
15590         .B(ddram_dq[23]),
15591         .I(ddrphy_dq_o23),
15592         .T((~(~ddrphy_dq_oe_n23))),
15593         .O(ddrphy_dq_i23)
15594 );
15595
15596 TRELLIS_IO #(
15597         .DIR("BIDIR")
15598 ) TRELLIS_IO_27 (
15599         .B(ddram_dqs_p[3]),
15600         .I(ddrphy_dqs3),
15601         .T((~(~ddrphy_dqs_oe_n3))),
15602         .O(ddrphy_dqs_i3)
15603 );
15604
15605 TRELLIS_IO #(
15606         .DIR("BIDIR")
15607 ) TRELLIS_IO_28 (
15608         .B(ddram_dq[24]),
15609         .I(ddrphy_dq_o24),
15610         .T((~(~ddrphy_dq_oe_n24))),
15611         .O(ddrphy_dq_i24)
15612 );
15613
15614 TRELLIS_IO #(
15615         .DIR("BIDIR")
15616 ) TRELLIS_IO_29 (
15617         .B(ddram_dq[25]),
15618         .I(ddrphy_dq_o25),
15619         .T((~(~ddrphy_dq_oe_n25))),
15620         .O(ddrphy_dq_i25)
15621 );
15622
15623 TRELLIS_IO #(
15624         .DIR("BIDIR")
15625 ) TRELLIS_IO_30 (
15626         .B(ddram_dq[26]),
15627         .I(ddrphy_dq_o26),
15628         .T((~(~ddrphy_dq_oe_n26))),
15629         .O(ddrphy_dq_i26)
15630 );
15631
15632 TRELLIS_IO #(
15633         .DIR("BIDIR")
15634 ) TRELLIS_IO_31 (
15635         .B(ddram_dq[27]),
15636         .I(ddrphy_dq_o27),
15637         .T((~(~ddrphy_dq_oe_n27))),
15638         .O(ddrphy_dq_i27)
15639 );
15640
15641 TRELLIS_IO #(
15642         .DIR("BIDIR")
15643 ) TRELLIS_IO_32 (
15644         .B(ddram_dq[28]),
15645         .I(ddrphy_dq_o28),
15646         .T((~(~ddrphy_dq_oe_n28))),
15647         .O(ddrphy_dq_i28)
15648 );
15649
15650 TRELLIS_IO #(
15651         .DIR("BIDIR")
15652 ) TRELLIS_IO_33 (
15653         .B(ddram_dq[29]),
15654         .I(ddrphy_dq_o29),
15655         .T((~(~ddrphy_dq_oe_n29))),
15656         .O(ddrphy_dq_i29)
15657 );
15658
15659 TRELLIS_IO #(
15660         .DIR("BIDIR")
15661 ) TRELLIS_IO_34 (
15662         .B(ddram_dq[30]),
15663         .I(ddrphy_dq_o30),
15664         .T((~(~ddrphy_dq_oe_n30))),
15665         .O(ddrphy_dq_i30)
15666 );
15667
15668 TRELLIS_IO #(
15669         .DIR("BIDIR")
15670 ) TRELLIS_IO_35 (
15671         .B(ddram_dq[31]),
15672         .I(ddrphy_dq_o31),
15673         .T((~(~ddrphy_dq_oe_n31))),
15674         .O(ddrphy_dq_i31)
15675 );
15676
15677 endmodule
15678
15679 // -----------------------------------------------------------------------------
15680 //  Auto-Generated by LiteX on 2022-02-21 23:17:58.
15681 //------------------------------------------------------------------------------