liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v

   1 // -----------------------------------------------------------------------------
   2 // Auto-Generated by:        __   _ __      _  __
   3 //                          / /  (_) /____ | |/_/
   4 //                         / /__/ / __/ -_)>  <
   5 //                        /____/_/\__/\__/_/|_|
   6 //                     Build your hardware, easily!
   7 //                   https://github.com/enjoy-digital/litex
   8 //
   9 // Filename   : liteeth_core.v
  10 // Device     :
  11 // LiteX sha1 : 1b62f142
  12 // Date       : 2022-02-22 13:54:55
  13 //------------------------------------------------------------------------------
  14
  15
  16 //------------------------------------------------------------------------------
  17 // Module
  18 //------------------------------------------------------------------------------
  19
  20 module liteeth_core (
  21         input  wire sys_clock,
  22         input  wire sys_reset,
  23         output wire rgmii_eth_clocks_tx,
  24         input  wire rgmii_eth_clocks_rx,
  25         output wire rgmii_eth_rst_n,
  26         input  wire rgmii_eth_int_n,
  27         inout  wire rgmii_eth_mdio,
  28         output wire rgmii_eth_mdc,
  29         input  wire rgmii_eth_rx_ctl,
  30         input  wire [3:0] rgmii_eth_rx_data,
  31         output wire rgmii_eth_tx_ctl,
  32         output wire [3:0] rgmii_eth_tx_data,
  33         input  wire [29:0] wishbone_adr,
  34         input  wire [31:0] wishbone_dat_w,
  35         output wire [31:0] wishbone_dat_r,
  36         input  wire [3:0] wishbone_sel,
  37         input  wire wishbone_cyc,
  38         input  wire wishbone_stb,
  39         output wire wishbone_ack,
  40         input  wire wishbone_we,
  41         input  wire [2:0] wishbone_cti,
  42         input  wire [1:0] wishbone_bte,
  43         output wire wishbone_err,
  44         output wire interrupt
  45 );
  46
  47
  48 //------------------------------------------------------------------------------
  49 // Signals
  50 //------------------------------------------------------------------------------
  51
  52 reg  main_maccore_maccore_soc_rst = 1'd0;
  53 wire main_maccore_maccore_cpu_rst;
  54 reg  [1:0] main_maccore_maccore_reset_storage = 2'd0;
  55 reg  main_maccore_maccore_reset_re = 1'd0;
  56 reg  [31:0] main_maccore_maccore_scratch_storage = 32'd305419896;
  57 reg  main_maccore_maccore_scratch_re = 1'd0;
  58 wire [31:0] main_maccore_maccore_bus_errors_status;
  59 wire main_maccore_maccore_bus_errors_we;
  60 reg  main_maccore_maccore_bus_errors_re = 1'd0;
  61 wire main_maccore_maccore_bus_error;
  62 reg  [31:0] main_maccore_maccore_bus_errors = 32'd0;
  63 wire sys_clk;
  64 wire sys_rst;
  65 wire por_clk;
  66 reg  main_maccore_int_rst = 1'd1;
  67 reg  main_maccore_ethphy_reset_storage = 1'd0;
  68 reg  main_maccore_ethphy_reset_re = 1'd0;
  69 wire eth_rx_clk;
  70 wire eth_rx_rst;
  71 wire eth_tx_clk;
  72 wire eth_tx_rst;
  73 wire main_maccore_ethphy_eth_tx_clk_o;
  74 wire main_maccore_ethphy_reset;
  75 wire main_maccore_ethphy_sink_valid;
  76 wire main_maccore_ethphy_sink_ready;
  77 wire main_maccore_ethphy_sink_first;
  78 wire main_maccore_ethphy_sink_last;
  79 wire [7:0] main_maccore_ethphy_sink_payload_data;
  80 wire main_maccore_ethphy_sink_payload_last_be;
  81 wire main_maccore_ethphy_sink_payload_error;
  82 wire main_maccore_ethphy_tx_ctl_oddrx1f;
  83 wire [3:0] main_maccore_ethphy_tx_data_oddrx1f;
  84 reg  main_maccore_ethphy_source_valid = 1'd0;
  85 wire main_maccore_ethphy_source_ready;
  86 reg  main_maccore_ethphy_source_first = 1'd0;
  87 wire main_maccore_ethphy_source_last;
  88 reg  [7:0] main_maccore_ethphy_source_payload_data = 8'd0;
  89 reg  main_maccore_ethphy_source_payload_last_be = 1'd0;
  90 reg  main_maccore_ethphy_source_payload_error = 1'd0;
  91 reg  main_maccore_ethphy_link_status = 1'd0;
  92 reg  main_maccore_ethphy_clock_speed = 1'd0;
  93 reg  main_maccore_ethphy_duplex_status = 1'd0;
  94 reg  [2:0] main_maccore_ethphy_status = 3'd0;
  95 wire main_maccore_ethphy_we;
  96 reg  main_maccore_ethphy_re = 1'd0;
  97 wire main_maccore_ethphy_rx_ctl_delayf;
  98 wire [1:0] main_maccore_ethphy_rx_ctl;
  99 reg  [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0;
 100 wire [3:0] main_maccore_ethphy_rx_data_delayf;
 101 wire [7:0] main_maccore_ethphy_rx_data;
 102 reg  [7:0] main_maccore_ethphy_rx_data_reg = 8'd0;
 103 reg  [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0;
 104 wire main_maccore_ethphy_last;
 105 wire main_maccore_ethphy_mdc;
 106 wire main_maccore_ethphy_oe;
 107 wire main_maccore_ethphy_w;
 108 reg  [2:0] main_maccore_ethphy__w_storage = 3'd0;
 109 reg  main_maccore_ethphy__w_re = 1'd0;
 110 reg  main_maccore_ethphy_r = 1'd0;
 111 reg  main_maccore_ethphy__r_status = 1'd0;
 112 wire main_maccore_ethphy__r_we;
 113 reg  main_maccore_ethphy__r_re = 1'd0;
 114 wire main_maccore_ethphy_data_w;
 115 wire main_maccore_ethphy_data_oe;
 116 wire main_maccore_ethphy_data_r;
 117 wire main_tx_gap_inserter_sink_valid;
 118 reg  main_tx_gap_inserter_sink_ready = 1'd0;
 119 wire main_tx_gap_inserter_sink_first;
 120 wire main_tx_gap_inserter_sink_last;
 121 wire [7:0] main_tx_gap_inserter_sink_payload_data;
 122 wire main_tx_gap_inserter_sink_payload_last_be;
 123 wire main_tx_gap_inserter_sink_payload_error;
 124 reg  main_tx_gap_inserter_source_valid = 1'd0;
 125 wire main_tx_gap_inserter_source_ready;
 126 reg  main_tx_gap_inserter_source_first = 1'd0;
 127 reg  main_tx_gap_inserter_source_last = 1'd0;
 128 reg  [7:0] main_tx_gap_inserter_source_payload_data = 8'd0;
 129 reg  main_tx_gap_inserter_source_payload_last_be = 1'd0;
 130 reg  main_tx_gap_inserter_source_payload_error = 1'd0;
 131 reg  [3:0] main_tx_gap_inserter_counter = 4'd0;
 132 reg  main_preamble_crc_status = 1'd1;
 133 wire main_preamble_crc_we;
 134 reg  main_preamble_crc_re = 1'd0;
 135 reg  [31:0] main_preamble_errors_status = 32'd0;
 136 wire main_preamble_errors_we;
 137 reg  main_preamble_errors_re = 1'd0;
 138 reg  [31:0] main_crc_errors_status = 32'd0;
 139 wire main_crc_errors_we;
 140 reg  main_crc_errors_re = 1'd0;
 141 wire main_preamble_inserter_sink_valid;
 142 reg  main_preamble_inserter_sink_ready = 1'd0;
 143 wire main_preamble_inserter_sink_first;
 144 wire main_preamble_inserter_sink_last;
 145 wire [7:0] main_preamble_inserter_sink_payload_data;
 146 wire main_preamble_inserter_sink_payload_last_be;
 147 wire main_preamble_inserter_sink_payload_error;
 148 reg  main_preamble_inserter_source_valid = 1'd0;
 149 wire main_preamble_inserter_source_ready;
 150 reg  main_preamble_inserter_source_first = 1'd0;
 151 reg  main_preamble_inserter_source_last = 1'd0;
 152 reg  [7:0] main_preamble_inserter_source_payload_data = 8'd0;
 153 wire main_preamble_inserter_source_payload_last_be;
 154 reg  main_preamble_inserter_source_payload_error = 1'd0;
 155 reg  [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013;
 156 reg  [2:0] main_preamble_inserter_count = 3'd0;
 157 wire main_preamble_checker_sink_valid;
 158 reg  main_preamble_checker_sink_ready = 1'd0;
 159 wire main_preamble_checker_sink_first;
 160 wire main_preamble_checker_sink_last;
 161 wire [7:0] main_preamble_checker_sink_payload_data;
 162 wire main_preamble_checker_sink_payload_last_be;
 163 wire main_preamble_checker_sink_payload_error;
 164 reg  main_preamble_checker_source_valid = 1'd0;
 165 wire main_preamble_checker_source_ready;
 166 reg  main_preamble_checker_source_first = 1'd0;
 167 reg  main_preamble_checker_source_last = 1'd0;
 168 wire [7:0] main_preamble_checker_source_payload_data;
 169 wire main_preamble_checker_source_payload_last_be;
 170 reg  main_preamble_checker_source_payload_error = 1'd0;
 171 reg  main_preamble_checker_error = 1'd0;
 172 wire main_liteethmaccrc32inserter_sink_valid;
 173 reg  main_liteethmaccrc32inserter_sink_ready = 1'd0;
 174 wire main_liteethmaccrc32inserter_sink_first;
 175 wire main_liteethmaccrc32inserter_sink_last;
 176 wire [7:0] main_liteethmaccrc32inserter_sink_payload_data;
 177 wire main_liteethmaccrc32inserter_sink_payload_last_be;
 178 wire main_liteethmaccrc32inserter_sink_payload_error;
 179 reg  main_liteethmaccrc32inserter_source_valid = 1'd0;
 180 wire main_liteethmaccrc32inserter_source_ready;
 181 reg  main_liteethmaccrc32inserter_source_first = 1'd0;
 182 reg  main_liteethmaccrc32inserter_source_last = 1'd0;
 183 reg  [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0;
 184 reg  main_liteethmaccrc32inserter_source_payload_last_be = 1'd0;
 185 reg  main_liteethmaccrc32inserter_source_payload_error = 1'd0;
 186 reg  [7:0] main_liteethmaccrc32inserter_data0 = 8'd0;
 187 wire [31:0] main_liteethmaccrc32inserter_value;
 188 wire main_liteethmaccrc32inserter_error;
 189 wire [7:0] main_liteethmaccrc32inserter_data1;
 190 wire [31:0] main_liteethmaccrc32inserter_last;
 191 reg  [31:0] main_liteethmaccrc32inserter_next = 32'd0;
 192 reg  [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295;
 193 reg  main_liteethmaccrc32inserter_ce = 1'd0;
 194 reg  main_liteethmaccrc32inserter_reset = 1'd0;
 195 reg  [1:0] main_liteethmaccrc32inserter_cnt = 2'd3;
 196 wire main_liteethmaccrc32inserter_cnt_done;
 197 reg  main_liteethmaccrc32inserter_is_ongoing0 = 1'd0;
 198 reg  main_liteethmaccrc32inserter_is_ongoing1 = 1'd0;
 199 wire main_crc32_inserter_sink_valid;
 200 wire main_crc32_inserter_sink_ready;
 201 wire main_crc32_inserter_sink_first;
 202 wire main_crc32_inserter_sink_last;
 203 wire [7:0] main_crc32_inserter_sink_payload_data;
 204 wire main_crc32_inserter_sink_payload_last_be;
 205 wire main_crc32_inserter_sink_payload_error;
 206 reg  main_crc32_inserter_source_valid = 1'd0;
 207 wire main_crc32_inserter_source_ready;
 208 reg  main_crc32_inserter_source_first = 1'd0;
 209 reg  main_crc32_inserter_source_last = 1'd0;
 210 reg  [7:0] main_crc32_inserter_source_payload_data = 8'd0;
 211 reg  main_crc32_inserter_source_payload_last_be = 1'd0;
 212 reg  main_crc32_inserter_source_payload_error = 1'd0;
 213 wire main_liteethmaccrc32checker_sink_sink_valid;
 214 reg  main_liteethmaccrc32checker_sink_sink_ready = 1'd0;
 215 wire main_liteethmaccrc32checker_sink_sink_first;
 216 wire main_liteethmaccrc32checker_sink_sink_last;
 217 wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data;
 218 wire main_liteethmaccrc32checker_sink_sink_payload_last_be;
 219 wire main_liteethmaccrc32checker_sink_sink_payload_error;
 220 wire main_liteethmaccrc32checker_source_source_valid;
 221 wire main_liteethmaccrc32checker_source_source_ready;
 222 reg  main_liteethmaccrc32checker_source_source_first = 1'd0;
 223 wire main_liteethmaccrc32checker_source_source_last;
 224 wire [7:0] main_liteethmaccrc32checker_source_source_payload_data;
 225 wire main_liteethmaccrc32checker_source_source_payload_last_be;
 226 reg  main_liteethmaccrc32checker_source_source_payload_error = 1'd0;
 227 wire main_liteethmaccrc32checker_error;
 228 wire [7:0] main_liteethmaccrc32checker_crc_data0;
 229 wire [31:0] main_liteethmaccrc32checker_crc_value;
 230 wire main_liteethmaccrc32checker_crc_error;
 231 wire [7:0] main_liteethmaccrc32checker_crc_data1;
 232 wire [31:0] main_liteethmaccrc32checker_crc_last;
 233 reg  [31:0] main_liteethmaccrc32checker_crc_next = 32'd0;
 234 reg  [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295;
 235 reg  main_liteethmaccrc32checker_crc_ce = 1'd0;
 236 reg  main_liteethmaccrc32checker_crc_reset = 1'd0;
 237 reg  main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0;
 238 wire main_liteethmaccrc32checker_syncfifo_sink_ready;
 239 wire main_liteethmaccrc32checker_syncfifo_sink_first;
 240 wire main_liteethmaccrc32checker_syncfifo_sink_last;
 241 wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data;
 242 wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
 243 wire main_liteethmaccrc32checker_syncfifo_sink_payload_error;
 244 wire main_liteethmaccrc32checker_syncfifo_source_valid;
 245 wire main_liteethmaccrc32checker_syncfifo_source_ready;
 246 wire main_liteethmaccrc32checker_syncfifo_source_first;
 247 wire main_liteethmaccrc32checker_syncfifo_source_last;
 248 wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data;
 249 wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
 250 wire main_liteethmaccrc32checker_syncfifo_source_payload_error;
 251 wire main_liteethmaccrc32checker_syncfifo_syncfifo_we;
 252 wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
 253 wire main_liteethmaccrc32checker_syncfifo_syncfifo_re;
 254 wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
 255 wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din;
 256 wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
 257 reg  [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0;
 258 reg  main_liteethmaccrc32checker_syncfifo_replace = 1'd0;
 259 reg  [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0;
 260 reg  [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0;
 261 reg  [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0;
 262 wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r;
 263 wire main_liteethmaccrc32checker_syncfifo_wrport_we;
 264 wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w;
 265 wire main_liteethmaccrc32checker_syncfifo_do_read;
 266 wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr;
 267 wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
 268 wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data;
 269 wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be;
 270 wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error;
 271 wire main_liteethmaccrc32checker_syncfifo_fifo_in_first;
 272 wire main_liteethmaccrc32checker_syncfifo_fifo_in_last;
 273 wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
 274 wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
 275 wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
 276 wire main_liteethmaccrc32checker_syncfifo_fifo_out_first;
 277 wire main_liteethmaccrc32checker_syncfifo_fifo_out_last;
 278 reg  main_liteethmaccrc32checker_fifo_reset = 1'd0;
 279 wire main_liteethmaccrc32checker_fifo_in;
 280 wire main_liteethmaccrc32checker_fifo_out;
 281 wire main_liteethmaccrc32checker_fifo_full;
 282 wire main_crc32_checker_sink_valid;
 283 wire main_crc32_checker_sink_ready;
 284 wire main_crc32_checker_sink_first;
 285 wire main_crc32_checker_sink_last;
 286 wire [7:0] main_crc32_checker_sink_payload_data;
 287 wire main_crc32_checker_sink_payload_last_be;
 288 wire main_crc32_checker_sink_payload_error;
 289 reg  main_crc32_checker_source_valid = 1'd0;
 290 wire main_crc32_checker_source_ready;
 291 reg  main_crc32_checker_source_first = 1'd0;
 292 reg  main_crc32_checker_source_last = 1'd0;
 293 reg  [7:0] main_crc32_checker_source_payload_data = 8'd0;
 294 reg  main_crc32_checker_source_payload_last_be = 1'd0;
 295 reg  main_crc32_checker_source_payload_error = 1'd0;
 296 wire main_ps_preamble_error_i;
 297 wire main_ps_preamble_error_o;
 298 reg  main_ps_preamble_error_toggle_i = 1'd0;
 299 wire main_ps_preamble_error_toggle_o;
 300 reg  main_ps_preamble_error_toggle_o_r = 1'd0;
 301 wire main_ps_crc_error_i;
 302 wire main_ps_crc_error_o;
 303 reg  main_ps_crc_error_toggle_i = 1'd0;
 304 wire main_ps_crc_error_toggle_o;
 305 reg  main_ps_crc_error_toggle_o_r = 1'd0;
 306 wire main_padding_inserter_sink_valid;
 307 reg  main_padding_inserter_sink_ready = 1'd0;
 308 wire main_padding_inserter_sink_first;
 309 wire main_padding_inserter_sink_last;
 310 wire [7:0] main_padding_inserter_sink_payload_data;
 311 wire main_padding_inserter_sink_payload_last_be;
 312 wire main_padding_inserter_sink_payload_error;
 313 reg  main_padding_inserter_source_valid = 1'd0;
 314 wire main_padding_inserter_source_ready;
 315 reg  main_padding_inserter_source_first = 1'd0;
 316 reg  main_padding_inserter_source_last = 1'd0;
 317 reg  [7:0] main_padding_inserter_source_payload_data = 8'd0;
 318 reg  main_padding_inserter_source_payload_last_be = 1'd0;
 319 reg  main_padding_inserter_source_payload_error = 1'd0;
 320 reg  [15:0] main_padding_inserter_counter = 16'd0;
 321 wire main_padding_inserter_counter_done;
 322 wire main_padding_checker_sink_valid;
 323 wire main_padding_checker_sink_ready;
 324 wire main_padding_checker_sink_first;
 325 wire main_padding_checker_sink_last;
 326 wire [7:0] main_padding_checker_sink_payload_data;
 327 wire main_padding_checker_sink_payload_last_be;
 328 wire main_padding_checker_sink_payload_error;
 329 wire main_padding_checker_source_valid;
 330 wire main_padding_checker_source_ready;
 331 wire main_padding_checker_source_first;
 332 wire main_padding_checker_source_last;
 333 wire [7:0] main_padding_checker_source_payload_data;
 334 wire main_padding_checker_source_payload_last_be;
 335 wire main_padding_checker_source_payload_error;
 336 wire main_tx_last_be_sink_valid;
 337 reg  main_tx_last_be_sink_ready = 1'd0;
 338 wire main_tx_last_be_sink_first;
 339 wire main_tx_last_be_sink_last;
 340 wire [7:0] main_tx_last_be_sink_payload_data;
 341 wire main_tx_last_be_sink_payload_last_be;
 342 wire main_tx_last_be_sink_payload_error;
 343 reg  main_tx_last_be_source_valid = 1'd0;
 344 wire main_tx_last_be_source_ready;
 345 reg  main_tx_last_be_source_first = 1'd0;
 346 reg  main_tx_last_be_source_last = 1'd0;
 347 reg  [7:0] main_tx_last_be_source_payload_data = 8'd0;
 348 reg  main_tx_last_be_source_payload_last_be = 1'd0;
 349 reg  main_tx_last_be_source_payload_error = 1'd0;
 350 wire main_rx_last_be_sink_valid;
 351 wire main_rx_last_be_sink_ready;
 352 wire main_rx_last_be_sink_first;
 353 wire main_rx_last_be_sink_last;
 354 wire [7:0] main_rx_last_be_sink_payload_data;
 355 wire main_rx_last_be_sink_payload_last_be;
 356 wire main_rx_last_be_sink_payload_error;
 357 wire main_rx_last_be_source_valid;
 358 wire main_rx_last_be_source_ready;
 359 wire main_rx_last_be_source_first;
 360 wire main_rx_last_be_source_last;
 361 wire [7:0] main_rx_last_be_source_payload_data;
 362 reg  main_rx_last_be_source_payload_last_be = 1'd0;
 363 wire main_rx_last_be_source_payload_error;
 364 wire main_tx_converter_sink_valid;
 365 wire main_tx_converter_sink_ready;
 366 wire main_tx_converter_sink_first;
 367 wire main_tx_converter_sink_last;
 368 wire [31:0] main_tx_converter_sink_payload_data;
 369 wire [3:0] main_tx_converter_sink_payload_last_be;
 370 wire [3:0] main_tx_converter_sink_payload_error;
 371 wire main_tx_converter_source_valid;
 372 wire main_tx_converter_source_ready;
 373 wire main_tx_converter_source_first;
 374 wire main_tx_converter_source_last;
 375 wire [7:0] main_tx_converter_source_payload_data;
 376 wire main_tx_converter_source_payload_last_be;
 377 wire main_tx_converter_source_payload_error;
 378 wire main_tx_converter_converter_sink_valid;
 379 wire main_tx_converter_converter_sink_ready;
 380 wire main_tx_converter_converter_sink_first;
 381 wire main_tx_converter_converter_sink_last;
 382 reg  [39:0] main_tx_converter_converter_sink_payload_data = 40'd0;
 383 wire main_tx_converter_converter_source_valid;
 384 wire main_tx_converter_converter_source_ready;
 385 wire main_tx_converter_converter_source_first;
 386 wire main_tx_converter_converter_source_last;
 387 reg  [9:0] main_tx_converter_converter_source_payload_data = 10'd0;
 388 wire main_tx_converter_converter_source_payload_valid_token_count;
 389 reg  [1:0] main_tx_converter_converter_mux = 2'd0;
 390 wire main_tx_converter_converter_first;
 391 wire main_tx_converter_converter_last;
 392 wire main_tx_converter_source_source_valid;
 393 wire main_tx_converter_source_source_ready;
 394 wire main_tx_converter_source_source_first;
 395 wire main_tx_converter_source_source_last;
 396 wire [9:0] main_tx_converter_source_source_payload_data;
 397 wire main_rx_converter_sink_valid;
 398 wire main_rx_converter_sink_ready;
 399 wire main_rx_converter_sink_first;
 400 wire main_rx_converter_sink_last;
 401 wire [7:0] main_rx_converter_sink_payload_data;
 402 wire main_rx_converter_sink_payload_last_be;
 403 wire main_rx_converter_sink_payload_error;
 404 wire main_rx_converter_source_valid;
 405 wire main_rx_converter_source_ready;
 406 wire main_rx_converter_source_first;
 407 wire main_rx_converter_source_last;
 408 reg  [31:0] main_rx_converter_source_payload_data = 32'd0;
 409 reg  [3:0] main_rx_converter_source_payload_last_be = 4'd0;
 410 reg  [3:0] main_rx_converter_source_payload_error = 4'd0;
 411 wire main_rx_converter_converter_sink_valid;
 412 wire main_rx_converter_converter_sink_ready;
 413 wire main_rx_converter_converter_sink_first;
 414 wire main_rx_converter_converter_sink_last;
 415 wire [9:0] main_rx_converter_converter_sink_payload_data;
 416 wire main_rx_converter_converter_source_valid;
 417 wire main_rx_converter_converter_source_ready;
 418 reg  main_rx_converter_converter_source_first = 1'd0;
 419 reg  main_rx_converter_converter_source_last = 1'd0;
 420 reg  [39:0] main_rx_converter_converter_source_payload_data = 40'd0;
 421 reg  [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0;
 422 reg  [1:0] main_rx_converter_converter_demux = 2'd0;
 423 wire main_rx_converter_converter_load_part;
 424 reg  main_rx_converter_converter_strobe_all = 1'd0;
 425 wire main_rx_converter_source_source_valid;
 426 wire main_rx_converter_source_source_ready;
 427 wire main_rx_converter_source_source_first;
 428 wire main_rx_converter_source_source_last;
 429 wire [39:0] main_rx_converter_source_source_payload_data;
 430 wire main_tx_cdc_sink_sink_valid;
 431 wire main_tx_cdc_sink_sink_ready;
 432 wire main_tx_cdc_sink_sink_first;
 433 wire main_tx_cdc_sink_sink_last;
 434 wire [31:0] main_tx_cdc_sink_sink_payload_data;
 435 wire [3:0] main_tx_cdc_sink_sink_payload_last_be;
 436 wire [3:0] main_tx_cdc_sink_sink_payload_error;
 437 wire main_tx_cdc_source_source_valid;
 438 wire main_tx_cdc_source_source_ready;
 439 wire main_tx_cdc_source_source_first;
 440 wire main_tx_cdc_source_source_last;
 441 wire [31:0] main_tx_cdc_source_source_payload_data;
 442 wire [3:0] main_tx_cdc_source_source_payload_last_be;
 443 wire [3:0] main_tx_cdc_source_source_payload_error;
 444 wire main_tx_cdc_cdc_sink_valid;
 445 wire main_tx_cdc_cdc_sink_ready;
 446 wire main_tx_cdc_cdc_sink_first;
 447 wire main_tx_cdc_cdc_sink_last;
 448 wire [31:0] main_tx_cdc_cdc_sink_payload_data;
 449 wire [3:0] main_tx_cdc_cdc_sink_payload_last_be;
 450 wire [3:0] main_tx_cdc_cdc_sink_payload_error;
 451 wire main_tx_cdc_cdc_source_valid;
 452 wire main_tx_cdc_cdc_source_ready;
 453 wire main_tx_cdc_cdc_source_first;
 454 wire main_tx_cdc_cdc_source_last;
 455 wire [31:0] main_tx_cdc_cdc_source_payload_data;
 456 wire [3:0] main_tx_cdc_cdc_source_payload_last_be;
 457 wire [3:0] main_tx_cdc_cdc_source_payload_error;
 458 wire main_tx_cdc_cdc_asyncfifo_we;
 459 wire main_tx_cdc_cdc_asyncfifo_writable;
 460 wire main_tx_cdc_cdc_asyncfifo_re;
 461 wire main_tx_cdc_cdc_asyncfifo_readable;
 462 wire [41:0] main_tx_cdc_cdc_asyncfifo_din;
 463 wire [41:0] main_tx_cdc_cdc_asyncfifo_dout;
 464 wire main_tx_cdc_cdc_graycounter0_ce;
 465 (* syn_no_retiming = "true" *) reg  [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0;
 466 wire [5:0] main_tx_cdc_cdc_graycounter0_q_next;
 467 reg  [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0;
 468 reg  [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
 469 wire main_tx_cdc_cdc_graycounter1_ce;
 470 (* syn_no_retiming = "true" *) reg  [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0;
 471 wire [5:0] main_tx_cdc_cdc_graycounter1_q_next;
 472 reg  [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0;
 473 reg  [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
 474 wire [5:0] main_tx_cdc_cdc_produce_rdomain;
 475 wire [5:0] main_tx_cdc_cdc_consume_wdomain;
 476 wire [4:0] main_tx_cdc_cdc_wrport_adr;
 477 wire [41:0] main_tx_cdc_cdc_wrport_dat_r;
 478 wire main_tx_cdc_cdc_wrport_we;
 479 wire [41:0] main_tx_cdc_cdc_wrport_dat_w;
 480 wire [4:0] main_tx_cdc_cdc_rdport_adr;
 481 wire [41:0] main_tx_cdc_cdc_rdport_dat_r;
 482 wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data;
 483 wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be;
 484 wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error;
 485 wire main_tx_cdc_cdc_fifo_in_first;
 486 wire main_tx_cdc_cdc_fifo_in_last;
 487 wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data;
 488 wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be;
 489 wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error;
 490 wire main_tx_cdc_cdc_fifo_out_first;
 491 wire main_tx_cdc_cdc_fifo_out_last;
 492 wire main_rx_cdc_sink_sink_valid;
 493 wire main_rx_cdc_sink_sink_ready;
 494 wire main_rx_cdc_sink_sink_first;
 495 wire main_rx_cdc_sink_sink_last;
 496 wire [31:0] main_rx_cdc_sink_sink_payload_data;
 497 wire [3:0] main_rx_cdc_sink_sink_payload_last_be;
 498 wire [3:0] main_rx_cdc_sink_sink_payload_error;
 499 wire main_rx_cdc_source_source_valid;
 500 wire main_rx_cdc_source_source_ready;
 501 wire main_rx_cdc_source_source_first;
 502 wire main_rx_cdc_source_source_last;
 503 wire [31:0] main_rx_cdc_source_source_payload_data;
 504 wire [3:0] main_rx_cdc_source_source_payload_last_be;
 505 wire [3:0] main_rx_cdc_source_source_payload_error;
 506 wire main_rx_cdc_cdc_sink_valid;
 507 wire main_rx_cdc_cdc_sink_ready;
 508 wire main_rx_cdc_cdc_sink_first;
 509 wire main_rx_cdc_cdc_sink_last;
 510 wire [31:0] main_rx_cdc_cdc_sink_payload_data;
 511 wire [3:0] main_rx_cdc_cdc_sink_payload_last_be;
 512 wire [3:0] main_rx_cdc_cdc_sink_payload_error;
 513 wire main_rx_cdc_cdc_source_valid;
 514 wire main_rx_cdc_cdc_source_ready;
 515 wire main_rx_cdc_cdc_source_first;
 516 wire main_rx_cdc_cdc_source_last;
 517 wire [31:0] main_rx_cdc_cdc_source_payload_data;
 518 wire [3:0] main_rx_cdc_cdc_source_payload_last_be;
 519 wire [3:0] main_rx_cdc_cdc_source_payload_error;
 520 wire main_rx_cdc_cdc_asyncfifo_we;
 521 wire main_rx_cdc_cdc_asyncfifo_writable;
 522 wire main_rx_cdc_cdc_asyncfifo_re;
 523 wire main_rx_cdc_cdc_asyncfifo_readable;
 524 wire [41:0] main_rx_cdc_cdc_asyncfifo_din;
 525 wire [41:0] main_rx_cdc_cdc_asyncfifo_dout;
 526 wire main_rx_cdc_cdc_graycounter0_ce;
 527 (* syn_no_retiming = "true" *) reg  [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0;
 528 wire [5:0] main_rx_cdc_cdc_graycounter0_q_next;
 529 reg  [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0;
 530 reg  [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
 531 wire main_rx_cdc_cdc_graycounter1_ce;
 532 (* syn_no_retiming = "true" *) reg  [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0;
 533 wire [5:0] main_rx_cdc_cdc_graycounter1_q_next;
 534 reg  [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0;
 535 reg  [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
 536 wire [5:0] main_rx_cdc_cdc_produce_rdomain;
 537 wire [5:0] main_rx_cdc_cdc_consume_wdomain;
 538 wire [4:0] main_rx_cdc_cdc_wrport_adr;
 539 wire [41:0] main_rx_cdc_cdc_wrport_dat_r;
 540 wire main_rx_cdc_cdc_wrport_we;
 541 wire [41:0] main_rx_cdc_cdc_wrport_dat_w;
 542 wire [4:0] main_rx_cdc_cdc_rdport_adr;
 543 wire [41:0] main_rx_cdc_cdc_rdport_dat_r;
 544 wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data;
 545 wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be;
 546 wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error;
 547 wire main_rx_cdc_cdc_fifo_in_first;
 548 wire main_rx_cdc_cdc_fifo_in_last;
 549 wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data;
 550 wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be;
 551 wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error;
 552 wire main_rx_cdc_cdc_fifo_out_first;
 553 wire main_rx_cdc_cdc_fifo_out_last;
 554 wire main_sink_valid;
 555 wire main_sink_ready;
 556 wire main_sink_first;
 557 wire main_sink_last;
 558 wire [31:0] main_sink_payload_data;
 559 wire [3:0] main_sink_payload_last_be;
 560 wire [3:0] main_sink_payload_error;
 561 wire main_source_valid;
 562 wire main_source_ready;
 563 wire main_source_first;
 564 wire main_source_last;
 565 wire [31:0] main_source_payload_data;
 566 wire [3:0] main_source_payload_last_be;
 567 wire [3:0] main_source_payload_error;
 568 wire [29:0] main_bus_adr;
 569 wire [31:0] main_bus_dat_w;
 570 wire [31:0] main_bus_dat_r;
 571 wire [3:0] main_bus_sel;
 572 wire main_bus_cyc;
 573 wire main_bus_stb;
 574 wire main_bus_ack;
 575 wire main_bus_we;
 576 wire [2:0] main_bus_cti;
 577 wire [1:0] main_bus_bte;
 578 wire main_bus_err;
 579 wire main_writer_sink_sink_valid;
 580 reg  main_writer_sink_sink_ready = 1'd1;
 581 wire main_writer_sink_sink_first;
 582 wire main_writer_sink_sink_last;
 583 wire [31:0] main_writer_sink_sink_payload_data;
 584 wire [3:0] main_writer_sink_sink_payload_last_be;
 585 wire [3:0] main_writer_sink_sink_payload_error;
 586 wire main_writer_slot_status;
 587 wire main_writer_slot_we;
 588 reg  main_writer_slot_re = 1'd0;
 589 wire [31:0] main_writer_length_status;
 590 wire main_writer_length_we;
 591 reg  main_writer_length_re = 1'd0;
 592 reg  [31:0] main_writer_errors_status = 32'd0;
 593 wire main_writer_errors_we;
 594 reg  main_writer_errors_re = 1'd0;
 595 wire main_writer_irq;
 596 wire main_writer_available_status;
 597 wire main_writer_available_pending;
 598 wire main_writer_available_trigger;
 599 reg  main_writer_available_clear = 1'd0;
 600 wire main_writer_available0;
 601 wire main_writer_status_status;
 602 wire main_writer_status_we;
 603 reg  main_writer_status_re = 1'd0;
 604 wire main_writer_available1;
 605 wire main_writer_pending_status;
 606 wire main_writer_pending_we;
 607 reg  main_writer_pending_re = 1'd0;
 608 reg  main_writer_pending_r = 1'd0;
 609 wire main_writer_available2;
 610 reg  main_writer_enable_storage = 1'd0;
 611 reg  main_writer_enable_re = 1'd0;
 612 reg  [2:0] main_writer_decoded = 3'd0;
 613 reg  [31:0] main_writer_counter = 32'd0;
 614 reg  main_writer_slot = 1'd0;
 615 reg  main_writer_slot_ce = 1'd0;
 616 reg  main_writer_start = 1'd0;
 617 reg  main_writer_ongoing = 1'd0;
 618 reg  main_writer_stat_fifo_sink_valid = 1'd0;
 619 wire main_writer_stat_fifo_sink_ready;
 620 reg  main_writer_stat_fifo_sink_first = 1'd0;
 621 reg  main_writer_stat_fifo_sink_last = 1'd0;
 622 wire main_writer_stat_fifo_sink_payload_slot;
 623 wire [31:0] main_writer_stat_fifo_sink_payload_length;
 624 wire main_writer_stat_fifo_source_valid;
 625 wire main_writer_stat_fifo_source_ready;
 626 wire main_writer_stat_fifo_source_first;
 627 wire main_writer_stat_fifo_source_last;
 628 wire main_writer_stat_fifo_source_payload_slot;
 629 wire [31:0] main_writer_stat_fifo_source_payload_length;
 630 wire main_writer_stat_fifo_syncfifo_we;
 631 wire main_writer_stat_fifo_syncfifo_writable;
 632 wire main_writer_stat_fifo_syncfifo_re;
 633 wire main_writer_stat_fifo_syncfifo_readable;
 634 wire [34:0] main_writer_stat_fifo_syncfifo_din;
 635 wire [34:0] main_writer_stat_fifo_syncfifo_dout;
 636 reg  [1:0] main_writer_stat_fifo_level = 2'd0;
 637 reg  main_writer_stat_fifo_replace = 1'd0;
 638 reg  main_writer_stat_fifo_produce = 1'd0;
 639 reg  main_writer_stat_fifo_consume = 1'd0;
 640 reg  main_writer_stat_fifo_wrport_adr = 1'd0;
 641 wire [34:0] main_writer_stat_fifo_wrport_dat_r;
 642 wire main_writer_stat_fifo_wrport_we;
 643 wire [34:0] main_writer_stat_fifo_wrport_dat_w;
 644 wire main_writer_stat_fifo_do_read;
 645 wire main_writer_stat_fifo_rdport_adr;
 646 wire [34:0] main_writer_stat_fifo_rdport_dat_r;
 647 wire main_writer_stat_fifo_fifo_in_payload_slot;
 648 wire [31:0] main_writer_stat_fifo_fifo_in_payload_length;
 649 wire main_writer_stat_fifo_fifo_in_first;
 650 wire main_writer_stat_fifo_fifo_in_last;
 651 wire main_writer_stat_fifo_fifo_out_payload_slot;
 652 wire [31:0] main_writer_stat_fifo_fifo_out_payload_length;
 653 wire main_writer_stat_fifo_fifo_out_first;
 654 wire main_writer_stat_fifo_fifo_out_last;
 655 reg  [8:0] main_writer_memory0_adr = 9'd0;
 656 wire [31:0] main_writer_memory0_dat_r;
 657 reg  main_writer_memory0_we = 1'd0;
 658 reg  [31:0] main_writer_memory0_dat_w = 32'd0;
 659 reg  [8:0] main_writer_memory1_adr = 9'd0;
 660 wire [31:0] main_writer_memory1_dat_r;
 661 reg  main_writer_memory1_we = 1'd0;
 662 reg  [31:0] main_writer_memory1_dat_w = 32'd0;
 663 reg  main_reader_source_source_valid = 1'd0;
 664 wire main_reader_source_source_ready;
 665 reg  main_reader_source_source_first = 1'd0;
 666 reg  main_reader_source_source_last = 1'd0;
 667 reg  [31:0] main_reader_source_source_payload_data = 32'd0;
 668 reg  [3:0] main_reader_source_source_payload_last_be = 4'd0;
 669 reg  [3:0] main_reader_source_source_payload_error = 4'd0;
 670 reg  main_reader_start_start_re = 1'd0;
 671 wire main_reader_start_start_r;
 672 reg  main_reader_start_start_we = 1'd0;
 673 reg  main_reader_start_start_w = 1'd0;
 674 wire main_reader_ready_status;
 675 wire main_reader_ready_we;
 676 reg  main_reader_ready_re = 1'd0;
 677 wire [1:0] main_reader_level_status;
 678 wire main_reader_level_we;
 679 reg  main_reader_level_re = 1'd0;
 680 reg  main_reader_slot_storage = 1'd0;
 681 reg  main_reader_slot_re = 1'd0;
 682 reg  [10:0] main_reader_length_storage = 11'd0;
 683 reg  main_reader_length_re = 1'd0;
 684 wire main_reader_irq;
 685 wire main_reader_eventsourcepulse_status;
 686 reg  main_reader_eventsourcepulse_pending = 1'd0;
 687 reg  main_reader_eventsourcepulse_trigger = 1'd0;
 688 reg  main_reader_eventsourcepulse_clear = 1'd0;
 689 wire main_reader_event00;
 690 wire main_reader_status_status;
 691 wire main_reader_status_we;
 692 reg  main_reader_status_re = 1'd0;
 693 wire main_reader_event01;
 694 wire main_reader_pending_status;
 695 wire main_reader_pending_we;
 696 reg  main_reader_pending_re = 1'd0;
 697 reg  main_reader_pending_r = 1'd0;
 698 wire main_reader_event02;
 699 reg  main_reader_enable_storage = 1'd0;
 700 reg  main_reader_enable_re = 1'd0;
 701 reg  main_reader_start = 1'd0;
 702 wire main_reader_cmd_fifo_sink_valid;
 703 wire main_reader_cmd_fifo_sink_ready;
 704 reg  main_reader_cmd_fifo_sink_first = 1'd0;
 705 reg  main_reader_cmd_fifo_sink_last = 1'd0;
 706 wire main_reader_cmd_fifo_sink_payload_slot;
 707 wire [10:0] main_reader_cmd_fifo_sink_payload_length;
 708 wire main_reader_cmd_fifo_source_valid;
 709 reg  main_reader_cmd_fifo_source_ready = 1'd0;
 710 wire main_reader_cmd_fifo_source_first;
 711 wire main_reader_cmd_fifo_source_last;
 712 wire main_reader_cmd_fifo_source_payload_slot;
 713 wire [10:0] main_reader_cmd_fifo_source_payload_length;
 714 wire main_reader_cmd_fifo_syncfifo_we;
 715 wire main_reader_cmd_fifo_syncfifo_writable;
 716 wire main_reader_cmd_fifo_syncfifo_re;
 717 wire main_reader_cmd_fifo_syncfifo_readable;
 718 wire [13:0] main_reader_cmd_fifo_syncfifo_din;
 719 wire [13:0] main_reader_cmd_fifo_syncfifo_dout;
 720 reg  [1:0] main_reader_cmd_fifo_level = 2'd0;
 721 reg  main_reader_cmd_fifo_replace = 1'd0;
 722 reg  main_reader_cmd_fifo_produce = 1'd0;
 723 reg  main_reader_cmd_fifo_consume = 1'd0;
 724 reg  main_reader_cmd_fifo_wrport_adr = 1'd0;
 725 wire [13:0] main_reader_cmd_fifo_wrport_dat_r;
 726 wire main_reader_cmd_fifo_wrport_we;
 727 wire [13:0] main_reader_cmd_fifo_wrport_dat_w;
 728 wire main_reader_cmd_fifo_do_read;
 729 wire main_reader_cmd_fifo_rdport_adr;
 730 wire [13:0] main_reader_cmd_fifo_rdport_dat_r;
 731 wire main_reader_cmd_fifo_fifo_in_payload_slot;
 732 wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length;
 733 wire main_reader_cmd_fifo_fifo_in_first;
 734 wire main_reader_cmd_fifo_fifo_in_last;
 735 wire main_reader_cmd_fifo_fifo_out_payload_slot;
 736 wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length;
 737 wire main_reader_cmd_fifo_fifo_out_first;
 738 wire main_reader_cmd_fifo_fifo_out_last;
 739 reg  [10:0] main_reader_read_address = 11'd0;
 740 reg  [10:0] main_reader_counter = 11'd0;
 741 reg  [3:0] main_reader_encoded = 4'd0;
 742 wire [8:0] main_reader_memory0_adr;
 743 wire [31:0] main_reader_memory0_dat_r;
 744 wire [8:0] main_reader_memory1_adr;
 745 wire [31:0] main_reader_memory1_dat_r;
 746 wire main_ev_irq;
 747 wire [29:0] main_interface0_adr;
 748 wire [31:0] main_interface0_dat_w;
 749 wire [31:0] main_interface0_dat_r;
 750 wire [3:0] main_interface0_sel;
 751 wire main_interface0_cyc;
 752 wire main_interface0_stb;
 753 reg  main_interface0_ack = 1'd0;
 754 wire main_interface0_we;
 755 wire [2:0] main_interface0_cti;
 756 wire [1:0] main_interface0_bte;
 757 reg  main_interface0_err = 1'd0;
 758 wire [8:0] main_sram0_adr0;
 759 wire [31:0] main_sram0_dat_r0;
 760 wire [29:0] main_interface0_writer_sram_converted_width_adr;
 761 wire [31:0] main_interface0_writer_sram_converted_width_dat_w;
 762 wire [31:0] main_interface0_writer_sram_converted_width_dat_r;
 763 wire [3:0] main_interface0_writer_sram_converted_width_sel;
 764 wire main_interface0_writer_sram_converted_width_cyc;
 765 wire main_interface0_writer_sram_converted_width_stb;
 766 wire main_interface0_writer_sram_converted_width_ack;
 767 wire main_interface0_writer_sram_converted_width_we;
 768 wire [2:0] main_interface0_writer_sram_converted_width_cti;
 769 wire [1:0] main_interface0_writer_sram_converted_width_bte;
 770 wire main_interface0_writer_sram_converted_width_err;
 771 wire [29:0] main_interface1_adr;
 772 wire [31:0] main_interface1_dat_w;
 773 wire [31:0] main_interface1_dat_r;
 774 wire [3:0] main_interface1_sel;
 775 wire main_interface1_cyc;
 776 wire main_interface1_stb;
 777 reg  main_interface1_ack = 1'd0;
 778 wire main_interface1_we;
 779 wire [2:0] main_interface1_cti;
 780 wire [1:0] main_interface1_bte;
 781 reg  main_interface1_err = 1'd0;
 782 wire [8:0] main_sram1_adr0;
 783 wire [31:0] main_sram1_dat_r0;
 784 wire [29:0] main_interface1_writer_sram_converted_width_adr;
 785 wire [31:0] main_interface1_writer_sram_converted_width_dat_w;
 786 wire [31:0] main_interface1_writer_sram_converted_width_dat_r;
 787 wire [3:0] main_interface1_writer_sram_converted_width_sel;
 788 wire main_interface1_writer_sram_converted_width_cyc;
 789 wire main_interface1_writer_sram_converted_width_stb;
 790 wire main_interface1_writer_sram_converted_width_ack;
 791 wire main_interface1_writer_sram_converted_width_we;
 792 wire [2:0] main_interface1_writer_sram_converted_width_cti;
 793 wire [1:0] main_interface1_writer_sram_converted_width_bte;
 794 wire main_interface1_writer_sram_converted_width_err;
 795 wire [29:0] main_interface2_adr;
 796 wire [31:0] main_interface2_dat_w;
 797 wire [31:0] main_interface2_dat_r;
 798 wire [3:0] main_interface2_sel;
 799 wire main_interface2_cyc;
 800 wire main_interface2_stb;
 801 reg  main_interface2_ack = 1'd0;
 802 wire main_interface2_we;
 803 wire [2:0] main_interface2_cti;
 804 wire [1:0] main_interface2_bte;
 805 reg  main_interface2_err = 1'd0;
 806 wire [8:0] main_sram0_adr1;
 807 wire [31:0] main_sram0_dat_r1;
 808 reg  [3:0] main_sram0_we = 4'd0;
 809 wire [31:0] main_sram0_dat_w;
 810 wire [29:0] main_interface0_reader_sram_converted_width_adr;
 811 wire [31:0] main_interface0_reader_sram_converted_width_dat_w;
 812 wire [31:0] main_interface0_reader_sram_converted_width_dat_r;
 813 wire [3:0] main_interface0_reader_sram_converted_width_sel;
 814 wire main_interface0_reader_sram_converted_width_cyc;
 815 wire main_interface0_reader_sram_converted_width_stb;
 816 wire main_interface0_reader_sram_converted_width_ack;
 817 wire main_interface0_reader_sram_converted_width_we;
 818 wire [2:0] main_interface0_reader_sram_converted_width_cti;
 819 wire [1:0] main_interface0_reader_sram_converted_width_bte;
 820 wire main_interface0_reader_sram_converted_width_err;
 821 wire [29:0] main_interface3_adr;
 822 wire [31:0] main_interface3_dat_w;
 823 wire [31:0] main_interface3_dat_r;
 824 wire [3:0] main_interface3_sel;
 825 wire main_interface3_cyc;
 826 wire main_interface3_stb;
 827 reg  main_interface3_ack = 1'd0;
 828 wire main_interface3_we;
 829 wire [2:0] main_interface3_cti;
 830 wire [1:0] main_interface3_bte;
 831 reg  main_interface3_err = 1'd0;
 832 wire [8:0] main_sram1_adr1;
 833 wire [31:0] main_sram1_dat_r1;
 834 reg  [3:0] main_sram1_we = 4'd0;
 835 wire [31:0] main_sram1_dat_w;
 836 wire [29:0] main_interface1_reader_sram_converted_width_adr;
 837 wire [31:0] main_interface1_reader_sram_converted_width_dat_w;
 838 wire [31:0] main_interface1_reader_sram_converted_width_dat_r;
 839 wire [3:0] main_interface1_reader_sram_converted_width_sel;
 840 wire main_interface1_reader_sram_converted_width_cyc;
 841 wire main_interface1_reader_sram_converted_width_stb;
 842 wire main_interface1_reader_sram_converted_width_ack;
 843 wire main_interface1_reader_sram_converted_width_we;
 844 wire [2:0] main_interface1_reader_sram_converted_width_cti;
 845 wire [1:0] main_interface1_reader_sram_converted_width_bte;
 846 wire main_interface1_reader_sram_converted_width_err;
 847 reg  [3:0] main_slave_sel = 4'd0;
 848 reg  [3:0] main_slave_sel_r = 4'd0;
 849 wire [29:0] main_wb_bus_adr;
 850 wire [31:0] main_wb_bus_dat_w;
 851 wire [31:0] main_wb_bus_dat_r;
 852 wire [3:0] main_wb_bus_sel;
 853 wire main_wb_bus_cyc;
 854 wire main_wb_bus_stb;
 855 wire main_wb_bus_ack;
 856 wire main_wb_bus_we;
 857 wire [2:0] main_wb_bus_cti;
 858 wire [1:0] main_wb_bus_bte;
 859 wire main_wb_bus_err;
 860 reg  builder_liteethmacgap_state = 1'd0;
 861 reg  builder_liteethmacgap_next_state = 1'd0;
 862 reg  [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0;
 863 reg  main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0;
 864 reg  [1:0] builder_liteethmacpreambleinserter_state = 2'd0;
 865 reg  [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0;
 866 reg  [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0;
 867 reg  main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0;
 868 reg  builder_liteethmacpreamblechecker_state = 1'd0;
 869 reg  builder_liteethmacpreamblechecker_next_state = 1'd0;
 870 reg  [1:0] builder_liteethmaccrc32inserter_state = 2'd0;
 871 reg  [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0;
 872 reg  [1:0] builder_liteethmaccrc32checker_state = 2'd0;
 873 reg  [1:0] builder_liteethmaccrc32checker_next_state = 2'd0;
 874 reg  builder_liteethmacpaddinginserter_state = 1'd0;
 875 reg  builder_liteethmacpaddinginserter_next_state = 1'd0;
 876 reg  [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0;
 877 reg  main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0;
 878 reg  builder_liteethmactxlastbe_state = 1'd0;
 879 reg  builder_liteethmactxlastbe_next_state = 1'd0;
 880 reg  [2:0] builder_liteethmacsramwriter_state = 3'd0;
 881 reg  [2:0] builder_liteethmacsramwriter_next_state = 3'd0;
 882 reg  [31:0] main_writer_counter_t_next_value = 32'd0;
 883 reg  main_writer_counter_t_next_value_ce = 1'd0;
 884 reg  [31:0] main_writer_errors_status_f_next_value = 32'd0;
 885 reg  main_writer_errors_status_f_next_value_ce = 1'd0;
 886 reg  [1:0] builder_liteethmacsramreader_state = 2'd0;
 887 reg  [1:0] builder_liteethmacsramreader_next_state = 2'd0;
 888 reg  [10:0] main_reader_counter_next_value = 11'd0;
 889 reg  main_reader_counter_next_value_ce = 1'd0;
 890 reg  [13:0] builder_maccore_adr = 14'd0;
 891 reg  builder_maccore_we = 1'd0;
 892 reg  [31:0] builder_maccore_dat_w = 32'd0;
 893 wire [31:0] builder_maccore_dat_r;
 894 wire [29:0] builder_maccore_wishbone_adr;
 895 wire [31:0] builder_maccore_wishbone_dat_w;
 896 reg  [31:0] builder_maccore_wishbone_dat_r = 32'd0;
 897 wire [3:0] builder_maccore_wishbone_sel;
 898 wire builder_maccore_wishbone_cyc;
 899 wire builder_maccore_wishbone_stb;
 900 reg  builder_maccore_wishbone_ack = 1'd0;
 901 wire builder_maccore_wishbone_we;
 902 wire [2:0] builder_maccore_wishbone_cti;
 903 wire [1:0] builder_maccore_wishbone_bte;
 904 reg  builder_maccore_wishbone_err = 1'd0;
 905 wire [29:0] builder_shared_adr;
 906 wire [31:0] builder_shared_dat_w;
 907 reg  [31:0] builder_shared_dat_r = 32'd0;
 908 wire [3:0] builder_shared_sel;
 909 wire builder_shared_cyc;
 910 wire builder_shared_stb;
 911 reg  builder_shared_ack = 1'd0;
 912 wire builder_shared_we;
 913 wire [2:0] builder_shared_cti;
 914 wire [1:0] builder_shared_bte;
 915 wire builder_shared_err;
 916 wire builder_request;
 917 wire builder_grant;
 918 reg  [1:0] builder_slave_sel = 2'd0;
 919 reg  [1:0] builder_slave_sel_r = 2'd0;
 920 reg  builder_error = 1'd0;
 921 wire builder_wait;
 922 wire builder_done;
 923 reg  [19:0] builder_count = 20'd1000000;
 924 wire [13:0] builder_interface0_bank_bus_adr;
 925 wire builder_interface0_bank_bus_we;
 926 wire [31:0] builder_interface0_bank_bus_dat_w;
 927 reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 928 reg  builder_csrbank0_reset0_re = 1'd0;
 929 wire [1:0] builder_csrbank0_reset0_r;
 930 reg  builder_csrbank0_reset0_we = 1'd0;
 931 wire [1:0] builder_csrbank0_reset0_w;
 932 reg  builder_csrbank0_scratch0_re = 1'd0;
 933 wire [31:0] builder_csrbank0_scratch0_r;
 934 reg  builder_csrbank0_scratch0_we = 1'd0;
 935 wire [31:0] builder_csrbank0_scratch0_w;
 936 reg  builder_csrbank0_bus_errors_re = 1'd0;
 937 wire [31:0] builder_csrbank0_bus_errors_r;
 938 reg  builder_csrbank0_bus_errors_we = 1'd0;
 939 wire [31:0] builder_csrbank0_bus_errors_w;
 940 wire builder_csrbank0_sel;
 941 wire [13:0] builder_interface1_bank_bus_adr;
 942 wire builder_interface1_bank_bus_we;
 943 wire [31:0] builder_interface1_bank_bus_dat_w;
 944 reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 945 reg  builder_csrbank1_sram_writer_slot_re = 1'd0;
 946 wire builder_csrbank1_sram_writer_slot_r;
 947 reg  builder_csrbank1_sram_writer_slot_we = 1'd0;
 948 wire builder_csrbank1_sram_writer_slot_w;
 949 reg  builder_csrbank1_sram_writer_length_re = 1'd0;
 950 wire [31:0] builder_csrbank1_sram_writer_length_r;
 951 reg  builder_csrbank1_sram_writer_length_we = 1'd0;
 952 wire [31:0] builder_csrbank1_sram_writer_length_w;
 953 reg  builder_csrbank1_sram_writer_errors_re = 1'd0;
 954 wire [31:0] builder_csrbank1_sram_writer_errors_r;
 955 reg  builder_csrbank1_sram_writer_errors_we = 1'd0;
 956 wire [31:0] builder_csrbank1_sram_writer_errors_w;
 957 reg  builder_csrbank1_sram_writer_ev_status_re = 1'd0;
 958 wire builder_csrbank1_sram_writer_ev_status_r;
 959 reg  builder_csrbank1_sram_writer_ev_status_we = 1'd0;
 960 wire builder_csrbank1_sram_writer_ev_status_w;
 961 reg  builder_csrbank1_sram_writer_ev_pending_re = 1'd0;
 962 wire builder_csrbank1_sram_writer_ev_pending_r;
 963 reg  builder_csrbank1_sram_writer_ev_pending_we = 1'd0;
 964 wire builder_csrbank1_sram_writer_ev_pending_w;
 965 reg  builder_csrbank1_sram_writer_ev_enable0_re = 1'd0;
 966 wire builder_csrbank1_sram_writer_ev_enable0_r;
 967 reg  builder_csrbank1_sram_writer_ev_enable0_we = 1'd0;
 968 wire builder_csrbank1_sram_writer_ev_enable0_w;
 969 reg  builder_csrbank1_sram_reader_ready_re = 1'd0;
 970 wire builder_csrbank1_sram_reader_ready_r;
 971 reg  builder_csrbank1_sram_reader_ready_we = 1'd0;
 972 wire builder_csrbank1_sram_reader_ready_w;
 973 reg  builder_csrbank1_sram_reader_level_re = 1'd0;
 974 wire [1:0] builder_csrbank1_sram_reader_level_r;
 975 reg  builder_csrbank1_sram_reader_level_we = 1'd0;
 976 wire [1:0] builder_csrbank1_sram_reader_level_w;
 977 reg  builder_csrbank1_sram_reader_slot0_re = 1'd0;
 978 wire builder_csrbank1_sram_reader_slot0_r;
 979 reg  builder_csrbank1_sram_reader_slot0_we = 1'd0;
 980 wire builder_csrbank1_sram_reader_slot0_w;
 981 reg  builder_csrbank1_sram_reader_length0_re = 1'd0;
 982 wire [10:0] builder_csrbank1_sram_reader_length0_r;
 983 reg  builder_csrbank1_sram_reader_length0_we = 1'd0;
 984 wire [10:0] builder_csrbank1_sram_reader_length0_w;
 985 reg  builder_csrbank1_sram_reader_ev_status_re = 1'd0;
 986 wire builder_csrbank1_sram_reader_ev_status_r;
 987 reg  builder_csrbank1_sram_reader_ev_status_we = 1'd0;
 988 wire builder_csrbank1_sram_reader_ev_status_w;
 989 reg  builder_csrbank1_sram_reader_ev_pending_re = 1'd0;
 990 wire builder_csrbank1_sram_reader_ev_pending_r;
 991 reg  builder_csrbank1_sram_reader_ev_pending_we = 1'd0;
 992 wire builder_csrbank1_sram_reader_ev_pending_w;
 993 reg  builder_csrbank1_sram_reader_ev_enable0_re = 1'd0;
 994 wire builder_csrbank1_sram_reader_ev_enable0_r;
 995 reg  builder_csrbank1_sram_reader_ev_enable0_we = 1'd0;
 996 wire builder_csrbank1_sram_reader_ev_enable0_w;
 997 reg  builder_csrbank1_preamble_crc_re = 1'd0;
 998 wire builder_csrbank1_preamble_crc_r;
 999 reg  builder_csrbank1_preamble_crc_we = 1'd0;
1000 wire builder_csrbank1_preamble_crc_w;
1001 reg  builder_csrbank1_preamble_errors_re = 1'd0;
1002 wire [31:0] builder_csrbank1_preamble_errors_r;
1003 reg  builder_csrbank1_preamble_errors_we = 1'd0;
1004 wire [31:0] builder_csrbank1_preamble_errors_w;
1005 reg  builder_csrbank1_crc_errors_re = 1'd0;
1006 wire [31:0] builder_csrbank1_crc_errors_r;
1007 reg  builder_csrbank1_crc_errors_we = 1'd0;
1008 wire [31:0] builder_csrbank1_crc_errors_w;
1009 wire builder_csrbank1_sel;
1010 wire [13:0] builder_interface2_bank_bus_adr;
1011 wire builder_interface2_bank_bus_we;
1012 wire [31:0] builder_interface2_bank_bus_dat_w;
1013 reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
1014 reg  builder_csrbank2_crg_reset0_re = 1'd0;
1015 wire builder_csrbank2_crg_reset0_r;
1016 reg  builder_csrbank2_crg_reset0_we = 1'd0;
1017 wire builder_csrbank2_crg_reset0_w;
1018 reg  builder_csrbank2_rx_inband_status_re = 1'd0;
1019 wire [2:0] builder_csrbank2_rx_inband_status_r;
1020 reg  builder_csrbank2_rx_inband_status_we = 1'd0;
1021 wire [2:0] builder_csrbank2_rx_inband_status_w;
1022 reg  builder_csrbank2_mdio_w0_re = 1'd0;
1023 wire [2:0] builder_csrbank2_mdio_w0_r;
1024 reg  builder_csrbank2_mdio_w0_we = 1'd0;
1025 wire [2:0] builder_csrbank2_mdio_w0_w;
1026 reg  builder_csrbank2_mdio_r_re = 1'd0;
1027 wire builder_csrbank2_mdio_r_r;
1028 reg  builder_csrbank2_mdio_r_we = 1'd0;
1029 wire builder_csrbank2_mdio_r_w;
1030 wire builder_csrbank2_sel;
1031 wire [13:0] builder_csr_interconnect_adr;
1032 wire builder_csr_interconnect_we;
1033 wire [31:0] builder_csr_interconnect_dat_w;
1034 wire [31:0] builder_csr_interconnect_dat_r;
1035 reg  builder_state = 1'd0;
1036 reg  builder_next_state = 1'd0;
1037 reg  [29:0] builder_array_muxed0 = 30'd0;
1038 reg  [31:0] builder_array_muxed1 = 32'd0;
1039 reg  [3:0] builder_array_muxed2 = 4'd0;
1040 reg  builder_array_muxed3 = 1'd0;
1041 reg  builder_array_muxed4 = 1'd0;
1042 reg  builder_array_muxed5 = 1'd0;
1043 reg  [2:0] builder_array_muxed6 = 3'd0;
1044 reg  [1:0] builder_array_muxed7 = 2'd0;
1045 wire builder_rst10;
1046 wire builder_rst11;
1047 (* syn_no_retiming = "true" *) reg  builder_multiregimpl0_regs0 = 1'd0;
1048 (* syn_no_retiming = "true" *) reg  builder_multiregimpl0_regs1 = 1'd0;
1049 (* syn_no_retiming = "true" *) reg  builder_multiregimpl1_regs0 = 1'd0;
1050 (* syn_no_retiming = "true" *) reg  builder_multiregimpl1_regs1 = 1'd0;
1051 (* syn_no_retiming = "true" *) reg  builder_multiregimpl2_regs0 = 1'd0;
1052 (* syn_no_retiming = "true" *) reg  builder_multiregimpl2_regs1 = 1'd0;
1053 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl3_regs0 = 6'd0;
1054 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl3_regs1 = 6'd0;
1055 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl4_regs0 = 6'd0;
1056 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl4_regs1 = 6'd0;
1057 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl5_regs0 = 6'd0;
1058 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl5_regs1 = 6'd0;
1059 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl6_regs0 = 6'd0;
1060 (* syn_no_retiming = "true" *) reg  [5:0] builder_multiregimpl6_regs1 = 6'd0;
1061
1062 //------------------------------------------------------------------------------
1063 // Combinatorial Logic
1064 //------------------------------------------------------------------------------
1065
1066 assign main_wb_bus_adr = wishbone_adr;
1067 assign main_wb_bus_dat_w = wishbone_dat_w;
1068 assign wishbone_dat_r = main_wb_bus_dat_r;
1069 assign main_wb_bus_sel = wishbone_sel;
1070 assign main_wb_bus_cyc = wishbone_cyc;
1071 assign main_wb_bus_stb = wishbone_stb;
1072 assign wishbone_ack = main_wb_bus_ack;
1073 assign main_wb_bus_we = wishbone_we;
1074 assign main_wb_bus_cti = wishbone_cti;
1075 assign main_wb_bus_bte = wishbone_bte;
1076 assign wishbone_err = main_wb_bus_err;
1077 assign interrupt = main_ev_irq;
1078 assign main_maccore_maccore_bus_error = builder_error;
1079 assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors;
1080 assign sys_clk = sys_clock;
1081 assign por_clk = sys_clock;
1082 assign sys_rst = main_maccore_int_rst;
1083 assign eth_rx_clk = rgmii_eth_clocks_rx;
1084 assign eth_tx_clk = eth_rx_clk;
1085 assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage;
1086 assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset);
1087 assign main_maccore_ethphy_sink_ready = 1'd1;
1088 assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]);
1089 assign main_maccore_ethphy_source_last = main_maccore_ethphy_last;
1090 assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0];
1091 assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1];
1092 assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2];
1093 assign main_tx_cdc_sink_sink_valid = main_source_valid;
1094 assign main_source_ready = main_tx_cdc_sink_sink_ready;
1095 assign main_tx_cdc_sink_sink_first = main_source_first;
1096 assign main_tx_cdc_sink_sink_last = main_source_last;
1097 assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data;
1098 assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be;
1099 assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error;
1100 assign main_sink_valid = main_rx_cdc_source_source_valid;
1101 assign main_rx_cdc_source_source_ready = main_sink_ready;
1102 assign main_sink_first = main_rx_cdc_source_source_first;
1103 assign main_sink_last = main_rx_cdc_source_source_last;
1104 assign main_sink_payload_data = main_rx_cdc_source_source_payload_data;
1105 assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be;
1106 assign main_sink_payload_error = main_rx_cdc_source_source_payload_error;
1107 assign main_ps_preamble_error_i = main_preamble_checker_error;
1108 assign main_ps_crc_error_i = main_liteethmaccrc32checker_error;
1109 always @(*) begin
1110         main_tx_gap_inserter_sink_ready <= 1'd0;
1111         builder_liteethmacgap_next_state <= 1'd0;
1112         main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0;
1113         main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
1114         main_tx_gap_inserter_source_valid <= 1'd0;
1115         main_tx_gap_inserter_source_first <= 1'd0;
1116         main_tx_gap_inserter_source_last <= 1'd0;
1117         main_tx_gap_inserter_source_payload_data <= 8'd0;
1118         main_tx_gap_inserter_source_payload_last_be <= 1'd0;
1119         main_tx_gap_inserter_source_payload_error <= 1'd0;
1120         builder_liteethmacgap_next_state <= builder_liteethmacgap_state;
1121         case (builder_liteethmacgap_state)
1122                 1'd1: begin
1123                         main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1);
1124                         main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
1125                         if ((main_tx_gap_inserter_counter == 4'd11)) begin
1126                                 builder_liteethmacgap_next_state <= 1'd0;
1127                         end
1128                 end
1129                 default: begin
1130                         main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0;
1131                         main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
1132                         main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid;
1133                         main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready;
1134                         main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first;
1135                         main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last;
1136                         main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data;
1137                         main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be;
1138                         main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error;
1139                         if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin
1140                                 builder_liteethmacgap_next_state <= 1'd1;
1141                         end
1142                 end
1143         endcase
1144 end
1145 assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be;
1146 always @(*) begin
1147         builder_liteethmacpreambleinserter_next_state <= 2'd0;
1148         main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0;
1149         main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0;
1150         main_preamble_inserter_source_valid <= 1'd0;
1151         main_preamble_inserter_source_first <= 1'd0;
1152         main_preamble_inserter_source_last <= 1'd0;
1153         main_preamble_inserter_source_payload_data <= 8'd0;
1154         main_preamble_inserter_source_payload_error <= 1'd0;
1155         main_preamble_inserter_sink_ready <= 1'd0;
1156         main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data;
1157         builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state;
1158         case (builder_liteethmacpreambleinserter_state)
1159                 1'd1: begin
1160                         main_preamble_inserter_source_valid <= 1'd1;
1161                         case (main_preamble_inserter_count)
1162                                 1'd0: begin
1163                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0];
1164                                 end
1165                                 1'd1: begin
1166                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8];
1167                                 end
1168                                 2'd2: begin
1169                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16];
1170                                 end
1171                                 2'd3: begin
1172                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24];
1173                                 end
1174                                 3'd4: begin
1175                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32];
1176                                 end
1177                                 3'd5: begin
1178                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40];
1179                                 end
1180                                 3'd6: begin
1181                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48];
1182                                 end
1183                                 default: begin
1184                                         main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56];
1185                                 end
1186                         endcase
1187                         if (main_preamble_inserter_source_ready) begin
1188                                 if ((main_preamble_inserter_count == 3'd7)) begin
1189                                         builder_liteethmacpreambleinserter_next_state <= 2'd2;
1190                                 end else begin
1191                                         main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1);
1192                                         main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
1193                                 end
1194                         end
1195                 end
1196                 2'd2: begin
1197                         main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid;
1198                         main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready;
1199                         main_preamble_inserter_source_first <= main_preamble_inserter_sink_first;
1200                         main_preamble_inserter_source_last <= main_preamble_inserter_sink_last;
1201                         main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error;
1202                         if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin
1203                                 builder_liteethmacpreambleinserter_next_state <= 1'd0;
1204                         end
1205                 end
1206                 default: begin
1207                         main_preamble_inserter_sink_ready <= 1'd1;
1208                         main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0;
1209                         main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
1210                         if (main_preamble_inserter_sink_valid) begin
1211                                 main_preamble_inserter_sink_ready <= 1'd0;
1212                                 builder_liteethmacpreambleinserter_next_state <= 1'd1;
1213                         end
1214                 end
1215         endcase
1216 end
1217 assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data;
1218 assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be;
1219 always @(*) begin
1220         main_preamble_checker_error <= 1'd0;
1221         main_preamble_checker_source_valid <= 1'd0;
1222         main_preamble_checker_source_first <= 1'd0;
1223         main_preamble_checker_sink_ready <= 1'd0;
1224         main_preamble_checker_source_last <= 1'd0;
1225         main_preamble_checker_source_payload_error <= 1'd0;
1226         builder_liteethmacpreamblechecker_next_state <= 1'd0;
1227         builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state;
1228         case (builder_liteethmacpreamblechecker_state)
1229                 1'd1: begin
1230                         main_preamble_checker_source_valid <= main_preamble_checker_sink_valid;
1231                         main_preamble_checker_sink_ready <= main_preamble_checker_source_ready;
1232                         main_preamble_checker_source_first <= main_preamble_checker_sink_first;
1233                         main_preamble_checker_source_last <= main_preamble_checker_sink_last;
1234                         main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error;
1235                         if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin
1236                                 builder_liteethmacpreamblechecker_next_state <= 1'd0;
1237                         end
1238                 end
1239                 default: begin
1240                         main_preamble_checker_sink_ready <= 1'd1;
1241                         if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin
1242                                 builder_liteethmacpreamblechecker_next_state <= 1'd1;
1243                         end
1244                         if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin
1245                                 main_preamble_checker_error <= 1'd1;
1246                         end
1247                 end
1248         endcase
1249 end
1250 assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0);
1251 assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid;
1252 assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready;
1253 assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first;
1254 assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last;
1255 assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data;
1256 assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be;
1257 assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error;
1258 assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0;
1259 assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg;
1260 assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]});
1261 assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827);
1262 always @(*) begin
1263         main_liteethmaccrc32inserter_next <= 32'd0;
1264         main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1265         main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1266         main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1267         main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
1268         main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1269         main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1270         main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
1271         main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1272         main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1273         main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
1274         main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1275         main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1276         main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1277         main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
1278         main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
1279         main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
1280         main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1281         main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
1282         main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
1283         main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
1284         main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
1285         main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
1286         main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
1287         main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1288         main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
1289         main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
1290         main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
1291         main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
1292         main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
1293         main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
1294         main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
1295         main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
1296 end
1297 always @(*) begin
1298         main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0;
1299         main_liteethmaccrc32inserter_ce <= 1'd0;
1300         main_liteethmaccrc32inserter_reset <= 1'd0;
1301         main_liteethmaccrc32inserter_source_valid <= 1'd0;
1302         main_liteethmaccrc32inserter_source_first <= 1'd0;
1303         main_liteethmaccrc32inserter_source_last <= 1'd0;
1304         builder_liteethmaccrc32inserter_next_state <= 2'd0;
1305         main_liteethmaccrc32inserter_source_payload_data <= 8'd0;
1306         main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0;
1307         main_liteethmaccrc32inserter_source_payload_error <= 1'd0;
1308         main_liteethmaccrc32inserter_data0 <= 8'd0;
1309         main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0;
1310         main_liteethmaccrc32inserter_sink_ready <= 1'd0;
1311         builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state;
1312         case (builder_liteethmaccrc32inserter_state)
1313                 1'd1: begin
1314                         main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready);
1315                         main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data;
1316                         main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid;
1317                         main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready;
1318                         main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first;
1319                         main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last;
1320                         main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data;
1321                         main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be;
1322                         main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error;
1323                         main_liteethmaccrc32inserter_source_last <= 1'd0;
1324                         if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin
1325                                 builder_liteethmaccrc32inserter_next_state <= 2'd2;
1326                         end
1327                 end
1328                 2'd2: begin
1329                         main_liteethmaccrc32inserter_source_valid <= 1'd1;
1330                         case (main_liteethmaccrc32inserter_cnt)
1331                                 1'd0: begin
1332                                         main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24];
1333                                 end
1334                                 1'd1: begin
1335                                         main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16];
1336                                 end
1337                                 2'd2: begin
1338                                         main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8];
1339                                 end
1340                                 default: begin
1341                                         main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0];
1342                                 end
1343                         endcase
1344                         if (main_liteethmaccrc32inserter_cnt_done) begin
1345                                 main_liteethmaccrc32inserter_source_last <= 1'd1;
1346                                 if (main_liteethmaccrc32inserter_source_ready) begin
1347                                         builder_liteethmaccrc32inserter_next_state <= 1'd0;
1348                                 end
1349                         end
1350                         main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1;
1351                 end
1352                 default: begin
1353                         main_liteethmaccrc32inserter_reset <= 1'd1;
1354                         main_liteethmaccrc32inserter_sink_ready <= 1'd1;
1355                         if (main_liteethmaccrc32inserter_sink_valid) begin
1356                                 main_liteethmaccrc32inserter_sink_ready <= 1'd0;
1357                                 builder_liteethmaccrc32inserter_next_state <= 1'd1;
1358                         end
1359                         main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1;
1360                 end
1361         endcase
1362 end
1363 assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready);
1364 assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4);
1365 assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out));
1366 assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready);
1367 assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first;
1368 assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last;
1369 assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data;
1370 assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be;
1371 assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error;
1372 always @(*) begin
1373         main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0;
1374         main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid;
1375         main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in;
1376 end
1377 always @(*) begin
1378         main_liteethmaccrc32checker_sink_sink_ready <= 1'd0;
1379         main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready;
1380         main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in;
1381 end
1382 assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full);
1383 assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last;
1384 assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out;
1385 assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data;
1386 assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
1387 always @(*) begin
1388         main_liteethmaccrc32checker_source_source_payload_error <= 1'd0;
1389         main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error;
1390         main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error);
1391 end
1392 assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error);
1393 assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data;
1394 assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid;
1395 assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready;
1396 assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first;
1397 assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last;
1398 assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data;
1399 assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be;
1400 assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error;
1401 assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0;
1402 assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg;
1403 assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]});
1404 assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827);
1405 always @(*) begin
1406         main_liteethmaccrc32checker_crc_next <= 32'd0;
1407         main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1408         main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1409         main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1410         main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1411         main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1412         main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1413         main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1414         main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1415         main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1416         main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1417         main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1418         main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1419         main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1420         main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1421         main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
1422         main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
1423         main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1424         main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1425         main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
1426         main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
1427         main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
1428         main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
1429         main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1430         main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1431         main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1432         main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
1433         main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
1434         main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
1435         main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
1436         main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
1437         main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
1438         main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
1439 end
1440 assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data};
1441 assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
1442 assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
1443 assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid;
1444 assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first;
1445 assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last;
1446 assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data;
1447 assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
1448 assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error;
1449 assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
1450 assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first;
1451 assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last;
1452 assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
1453 assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
1454 assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
1455 assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready;
1456 always @(*) begin
1457         main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0;
1458         if (main_liteethmaccrc32checker_syncfifo_replace) begin
1459                 main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1);
1460         end else begin
1461                 main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce;
1462         end
1463 end
1464 assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din;
1465 assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace));
1466 assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re);
1467 assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume;
1468 assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
1469 assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5);
1470 assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0);
1471 always @(*) begin
1472         main_liteethmaccrc32checker_crc_reset <= 1'd0;
1473         builder_liteethmaccrc32checker_next_state <= 2'd0;
1474         main_liteethmaccrc32checker_fifo_reset <= 1'd0;
1475         main_liteethmaccrc32checker_crc_ce <= 1'd0;
1476         builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state;
1477         case (builder_liteethmaccrc32checker_state)
1478                 1'd1: begin
1479                         if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
1480                                 main_liteethmaccrc32checker_crc_ce <= 1'd1;
1481                                 builder_liteethmaccrc32checker_next_state <= 2'd2;
1482                         end
1483                 end
1484                 2'd2: begin
1485                         if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
1486                                 main_liteethmaccrc32checker_crc_ce <= 1'd1;
1487                                 if (main_liteethmaccrc32checker_sink_sink_last) begin
1488                                         builder_liteethmaccrc32checker_next_state <= 1'd0;
1489                                 end
1490                         end
1491                 end
1492                 default: begin
1493                         main_liteethmaccrc32checker_crc_reset <= 1'd1;
1494                         main_liteethmaccrc32checker_fifo_reset <= 1'd1;
1495                         builder_liteethmaccrc32checker_next_state <= 1'd1;
1496                 end
1497         endcase
1498 end
1499 assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready);
1500 assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r);
1501 assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r);
1502 assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59);
1503 always @(*) begin
1504         main_padding_inserter_sink_ready <= 1'd0;
1505         main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
1506         main_padding_inserter_source_valid <= 1'd0;
1507         main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
1508         main_padding_inserter_source_first <= 1'd0;
1509         main_padding_inserter_source_last <= 1'd0;
1510         builder_liteethmacpaddinginserter_next_state <= 1'd0;
1511         main_padding_inserter_source_payload_data <= 8'd0;
1512         main_padding_inserter_source_payload_last_be <= 1'd0;
1513         main_padding_inserter_source_payload_error <= 1'd0;
1514         builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state;
1515         case (builder_liteethmacpaddinginserter_state)
1516                 1'd1: begin
1517                         main_padding_inserter_source_valid <= 1'd1;
1518                         main_padding_inserter_source_last <= main_padding_inserter_counter_done;
1519                         main_padding_inserter_source_payload_data <= 1'd0;
1520                         if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
1521                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
1522                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
1523                                 if (main_padding_inserter_counter_done) begin
1524                                         main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
1525                                         main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
1526                                         builder_liteethmacpaddinginserter_next_state <= 1'd0;
1527                                 end
1528                         end
1529                 end
1530                 default: begin
1531                         main_padding_inserter_source_valid <= main_padding_inserter_sink_valid;
1532                         main_padding_inserter_sink_ready <= main_padding_inserter_source_ready;
1533                         main_padding_inserter_source_first <= main_padding_inserter_sink_first;
1534                         main_padding_inserter_source_last <= main_padding_inserter_sink_last;
1535                         main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data;
1536                         main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be;
1537                         main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error;
1538                         if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
1539                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
1540                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
1541                                 if (main_padding_inserter_sink_last) begin
1542                                         if ((~main_padding_inserter_counter_done)) begin
1543                                                 main_padding_inserter_source_last <= 1'd0;
1544                                                 builder_liteethmacpaddinginserter_next_state <= 1'd1;
1545                                         end else begin
1546                                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
1547                                                 main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
1548                                         end
1549                                 end
1550                         end
1551                 end
1552         endcase
1553 end
1554 assign main_padding_checker_source_valid = main_padding_checker_sink_valid;
1555 assign main_padding_checker_sink_ready = main_padding_checker_source_ready;
1556 assign main_padding_checker_source_first = main_padding_checker_sink_first;
1557 assign main_padding_checker_source_last = main_padding_checker_sink_last;
1558 assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data;
1559 assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be;
1560 assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error;
1561 always @(*) begin
1562         main_tx_last_be_source_payload_error <= 1'd0;
1563         main_tx_last_be_source_valid <= 1'd0;
1564         main_tx_last_be_source_last <= 1'd0;
1565         main_tx_last_be_sink_ready <= 1'd0;
1566         main_tx_last_be_source_first <= 1'd0;
1567         builder_liteethmactxlastbe_next_state <= 1'd0;
1568         main_tx_last_be_source_payload_data <= 8'd0;
1569         builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state;
1570         case (builder_liteethmactxlastbe_state)
1571                 1'd1: begin
1572                         main_tx_last_be_sink_ready <= 1'd1;
1573                         if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin
1574                                 builder_liteethmactxlastbe_next_state <= 1'd0;
1575                         end
1576                 end
1577                 default: begin
1578                         main_tx_last_be_source_valid <= main_tx_last_be_sink_valid;
1579                         main_tx_last_be_sink_ready <= main_tx_last_be_source_ready;
1580                         main_tx_last_be_source_first <= main_tx_last_be_sink_first;
1581                         main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data;
1582                         main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error;
1583                         main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be;
1584                         if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin
1585                                 if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin
1586                                         builder_liteethmactxlastbe_next_state <= 1'd1;
1587                                 end
1588                         end
1589                 end
1590         endcase
1591 end
1592 assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid;
1593 assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready;
1594 assign main_rx_last_be_source_first = main_rx_last_be_sink_first;
1595 assign main_rx_last_be_source_last = main_rx_last_be_sink_last;
1596 assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data;
1597 assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error;
1598 always @(*) begin
1599         main_rx_last_be_source_payload_last_be <= 1'd0;
1600         main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be;
1601         main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last;
1602 end
1603 assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid;
1604 assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first;
1605 assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last;
1606 assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready;
1607 always @(*) begin
1608         main_tx_converter_converter_sink_payload_data <= 40'd0;
1609         main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0];
1610         main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0];
1611         main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0];
1612         main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8];
1613         main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1];
1614         main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1];
1615         main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16];
1616         main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2];
1617         main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2];
1618         main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24];
1619         main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3];
1620         main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3];
1621 end
1622 assign main_tx_converter_source_valid = main_tx_converter_source_source_valid;
1623 assign main_tx_converter_source_first = main_tx_converter_source_source_first;
1624 assign main_tx_converter_source_last = main_tx_converter_source_source_last;
1625 assign main_tx_converter_source_source_ready = main_tx_converter_source_ready;
1626 assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data;
1627 assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid;
1628 assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready;
1629 assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first;
1630 assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last;
1631 assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data;
1632 assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0);
1633 assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3);
1634 assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid;
1635 assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first);
1636 assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last);
1637 assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready);
1638 always @(*) begin
1639         main_tx_converter_converter_source_payload_data <= 10'd0;
1640         case (main_tx_converter_converter_mux)
1641                 1'd0: begin
1642                         main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0];
1643                 end
1644                 1'd1: begin
1645                         main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10];
1646                 end
1647                 2'd2: begin
1648                         main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20];
1649                 end
1650                 default: begin
1651                         main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30];
1652                 end
1653         endcase
1654 end
1655 assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last;
1656 assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid;
1657 assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first;
1658 assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last;
1659 assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready;
1660 assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data};
1661 assign main_rx_converter_source_valid = main_rx_converter_source_source_valid;
1662 assign main_rx_converter_source_first = main_rx_converter_source_source_first;
1663 assign main_rx_converter_source_last = main_rx_converter_source_source_last;
1664 assign main_rx_converter_source_source_ready = main_rx_converter_source_ready;
1665 always @(*) begin
1666         main_rx_converter_source_payload_data <= 32'd0;
1667         main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0];
1668         main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10];
1669         main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20];
1670         main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30];
1671 end
1672 always @(*) begin
1673         main_rx_converter_source_payload_last_be <= 4'd0;
1674         main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8];
1675         main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18];
1676         main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28];
1677         main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38];
1678 end
1679 always @(*) begin
1680         main_rx_converter_source_payload_error <= 4'd0;
1681         main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9];
1682         main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19];
1683         main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29];
1684         main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39];
1685 end
1686 assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid;
1687 assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready;
1688 assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first;
1689 assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last;
1690 assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data;
1691 assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready);
1692 assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all;
1693 assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready);
1694 assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid;
1695 assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready;
1696 assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first;
1697 assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last;
1698 assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data;
1699 assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be;
1700 assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error;
1701 assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid;
1702 assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready;
1703 assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first;
1704 assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last;
1705 assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data;
1706 assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be;
1707 assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error;
1708 assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data};
1709 assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout;
1710 assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable;
1711 assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid;
1712 assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first;
1713 assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last;
1714 assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data;
1715 assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be;
1716 assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error;
1717 assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable;
1718 assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first;
1719 assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last;
1720 assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data;
1721 assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be;
1722 assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error;
1723 assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready;
1724 assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we);
1725 assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re);
1726 assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0]));
1727 assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain);
1728 assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0];
1729 assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din;
1730 assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce;
1731 assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0];
1732 assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r;
1733 always @(*) begin
1734         main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
1735         if (main_tx_cdc_cdc_graycounter0_ce) begin
1736                 main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1);
1737         end else begin
1738                 main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary;
1739         end
1740 end
1741 assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]);
1742 always @(*) begin
1743         main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
1744         if (main_tx_cdc_cdc_graycounter1_ce) begin
1745                 main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1);
1746         end else begin
1747                 main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary;
1748         end
1749 end
1750 assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]);
1751 assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid;
1752 assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready;
1753 assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first;
1754 assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last;
1755 assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data;
1756 assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be;
1757 assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error;
1758 assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid;
1759 assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready;
1760 assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first;
1761 assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last;
1762 assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data;
1763 assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be;
1764 assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error;
1765 assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data};
1766 assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout;
1767 assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable;
1768 assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid;
1769 assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first;
1770 assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last;
1771 assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data;
1772 assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be;
1773 assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error;
1774 assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable;
1775 assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first;
1776 assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last;
1777 assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data;
1778 assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be;
1779 assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error;
1780 assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready;
1781 assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we);
1782 assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re);
1783 assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0]));
1784 assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain);
1785 assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0];
1786 assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din;
1787 assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce;
1788 assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0];
1789 assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r;
1790 always @(*) begin
1791         main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
1792         if (main_rx_cdc_cdc_graycounter0_ce) begin
1793                 main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1);
1794         end else begin
1795                 main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary;
1796         end
1797 end
1798 assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]);
1799 always @(*) begin
1800         main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
1801         if (main_rx_cdc_cdc_graycounter1_ce) begin
1802                 main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1);
1803         end else begin
1804                 main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary;
1805         end
1806 end
1807 assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]);
1808 assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid;
1809 assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready;
1810 assign main_tx_converter_sink_first = main_tx_cdc_source_source_first;
1811 assign main_tx_converter_sink_last = main_tx_cdc_source_source_last;
1812 assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data;
1813 assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be;
1814 assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error;
1815 assign main_tx_last_be_sink_valid = main_tx_converter_source_valid;
1816 assign main_tx_converter_source_ready = main_tx_last_be_sink_ready;
1817 assign main_tx_last_be_sink_first = main_tx_converter_source_first;
1818 assign main_tx_last_be_sink_last = main_tx_converter_source_last;
1819 assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data;
1820 assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be;
1821 assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error;
1822 assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid;
1823 assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready;
1824 assign main_padding_inserter_sink_first = main_tx_last_be_source_first;
1825 assign main_padding_inserter_sink_last = main_tx_last_be_source_last;
1826 assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data;
1827 assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be;
1828 assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error;
1829 assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid;
1830 assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready;
1831 assign main_crc32_inserter_sink_first = main_padding_inserter_source_first;
1832 assign main_crc32_inserter_sink_last = main_padding_inserter_source_last;
1833 assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data;
1834 assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be;
1835 assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error;
1836 assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid;
1837 assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready;
1838 assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first;
1839 assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last;
1840 assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data;
1841 assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be;
1842 assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error;
1843 assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid;
1844 assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready;
1845 assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first;
1846 assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last;
1847 assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data;
1848 assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be;
1849 assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error;
1850 assign main_maccore_ethphy_sink_valid = main_tx_gap_inserter_source_valid;
1851 assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_sink_ready;
1852 assign main_maccore_ethphy_sink_first = main_tx_gap_inserter_source_first;
1853 assign main_maccore_ethphy_sink_last = main_tx_gap_inserter_source_last;
1854 assign main_maccore_ethphy_sink_payload_data = main_tx_gap_inserter_source_payload_data;
1855 assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be;
1856 assign main_maccore_ethphy_sink_payload_error = main_tx_gap_inserter_source_payload_error;
1857 assign main_preamble_checker_sink_valid = main_maccore_ethphy_source_valid;
1858 assign main_maccore_ethphy_source_ready = main_preamble_checker_sink_ready;
1859 assign main_preamble_checker_sink_first = main_maccore_ethphy_source_first;
1860 assign main_preamble_checker_sink_last = main_maccore_ethphy_source_last;
1861 assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_source_payload_data;
1862 assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be;
1863 assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_source_payload_error;
1864 assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid;
1865 assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready;
1866 assign main_crc32_checker_sink_first = main_preamble_checker_source_first;
1867 assign main_crc32_checker_sink_last = main_preamble_checker_source_last;
1868 assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data;
1869 assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be;
1870 assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error;
1871 assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid;
1872 assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready;
1873 assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first;
1874 assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last;
1875 assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data;
1876 assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be;
1877 assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error;
1878 assign main_rx_last_be_sink_valid = main_padding_checker_source_valid;
1879 assign main_padding_checker_source_ready = main_rx_last_be_sink_ready;
1880 assign main_rx_last_be_sink_first = main_padding_checker_source_first;
1881 assign main_rx_last_be_sink_last = main_padding_checker_source_last;
1882 assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data;
1883 assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be;
1884 assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error;
1885 assign main_rx_converter_sink_valid = main_rx_last_be_source_valid;
1886 assign main_rx_last_be_source_ready = main_rx_converter_sink_ready;
1887 assign main_rx_converter_sink_first = main_rx_last_be_source_first;
1888 assign main_rx_converter_sink_last = main_rx_last_be_source_last;
1889 assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data;
1890 assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be;
1891 assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error;
1892 assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid;
1893 assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready;
1894 assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first;
1895 assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last;
1896 assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data;
1897 assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be;
1898 assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error;
1899 assign main_writer_sink_sink_valid = main_sink_valid;
1900 assign main_sink_ready = main_writer_sink_sink_ready;
1901 assign main_writer_sink_sink_first = main_sink_first;
1902 assign main_writer_sink_sink_last = main_sink_last;
1903 assign main_writer_sink_sink_payload_data = main_sink_payload_data;
1904 assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be;
1905 assign main_writer_sink_sink_payload_error = main_sink_payload_error;
1906 assign main_source_valid = main_reader_source_source_valid;
1907 assign main_reader_source_source_ready = main_source_ready;
1908 assign main_source_first = main_reader_source_source_first;
1909 assign main_source_last = main_reader_source_source_last;
1910 assign main_source_payload_data = main_reader_source_source_payload_data;
1911 assign main_source_payload_last_be = main_reader_source_source_payload_last_be;
1912 assign main_source_payload_error = main_reader_source_source_payload_error;
1913 assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot;
1914 assign main_writer_stat_fifo_sink_payload_length = main_writer_counter;
1915 assign main_writer_stat_fifo_source_ready = main_writer_available_clear;
1916 assign main_writer_available_trigger = main_writer_stat_fifo_source_valid;
1917 assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot;
1918 assign main_writer_length_status = main_writer_stat_fifo_source_payload_length;
1919 always @(*) begin
1920         main_writer_memory1_we <= 1'd0;
1921         main_writer_memory0_adr <= 9'd0;
1922         main_writer_memory1_dat_w <= 32'd0;
1923         main_writer_memory0_we <= 1'd0;
1924         main_writer_memory0_dat_w <= 32'd0;
1925         main_writer_memory1_adr <= 9'd0;
1926         case (main_writer_slot)
1927                 1'd0: begin
1928                         main_writer_memory0_adr <= main_writer_counter[31:2];
1929                         main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data;
1930                         if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
1931                                 main_writer_memory0_we <= 4'd15;
1932                         end
1933                 end
1934                 1'd1: begin
1935                         main_writer_memory1_adr <= main_writer_counter[31:2];
1936                         main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data;
1937                         if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
1938                                 main_writer_memory1_we <= 4'd15;
1939                         end
1940                 end
1941         endcase
1942 end
1943 assign main_writer_available0 = main_writer_available_status;
1944 assign main_writer_available1 = main_writer_available_pending;
1945 always @(*) begin
1946         main_writer_available_clear <= 1'd0;
1947         if ((main_writer_pending_re & main_writer_pending_r)) begin
1948                 main_writer_available_clear <= 1'd1;
1949         end
1950 end
1951 assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage);
1952 assign main_writer_available_status = main_writer_available_trigger;
1953 assign main_writer_available_pending = main_writer_available_trigger;
1954 always @(*) begin
1955         main_writer_decoded <= 3'd0;
1956         case (main_writer_sink_sink_payload_last_be)
1957                 1'd1: begin
1958                         main_writer_decoded <= 1'd1;
1959                 end
1960                 2'd2: begin
1961                         main_writer_decoded <= 2'd2;
1962                 end
1963                 3'd4: begin
1964                         main_writer_decoded <= 2'd3;
1965                 end
1966                 default: begin
1967                         main_writer_decoded <= 3'd4;
1968                 end
1969         endcase
1970 end
1971 assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot};
1972 assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout;
1973 assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable;
1974 assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid;
1975 assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first;
1976 assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last;
1977 assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot;
1978 assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length;
1979 assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable;
1980 assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first;
1981 assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last;
1982 assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot;
1983 assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length;
1984 assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready;
1985 always @(*) begin
1986         main_writer_stat_fifo_wrport_adr <= 1'd0;
1987         if (main_writer_stat_fifo_replace) begin
1988                 main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1);
1989         end else begin
1990                 main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce;
1991         end
1992 end
1993 assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din;
1994 assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace));
1995 assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re);
1996 assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume;
1997 assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r;
1998 assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2);
1999 assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0);
2000 always @(*) begin
2001         main_writer_slot_ce <= 1'd0;
2002         main_writer_errors_status_f_next_value <= 32'd0;
2003         main_writer_start <= 1'd0;
2004         main_writer_errors_status_f_next_value_ce <= 1'd0;
2005         main_writer_ongoing <= 1'd0;
2006         main_writer_stat_fifo_sink_valid <= 1'd0;
2007         builder_liteethmacsramwriter_next_state <= 3'd0;
2008         main_writer_counter_t_next_value <= 32'd0;
2009         main_writer_counter_t_next_value_ce <= 1'd0;
2010         builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state;
2011         case (builder_liteethmacsramwriter_state)
2012                 1'd1: begin
2013                         if (main_writer_sink_sink_valid) begin
2014                                 if ((main_writer_counter == 11'd1530)) begin
2015                                         builder_liteethmacsramwriter_next_state <= 2'd3;
2016                                 end else begin
2017                                         main_writer_counter_t_next_value <= (main_writer_counter + main_writer_decoded);
2018                                         main_writer_counter_t_next_value_ce <= 1'd1;
2019                                         main_writer_ongoing <= 1'd1;
2020                                 end
2021                                 if (main_writer_sink_sink_last) begin
2022                                         if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin
2023                                                 builder_liteethmacsramwriter_next_state <= 2'd2;
2024                                         end else begin
2025                                                 builder_liteethmacsramwriter_next_state <= 3'd4;
2026                                         end
2027                                 end
2028                         end
2029                 end
2030                 2'd2: begin
2031                         main_writer_counter_t_next_value <= 1'd0;
2032                         main_writer_counter_t_next_value_ce <= 1'd1;
2033                         builder_liteethmacsramwriter_next_state <= 1'd0;
2034                 end
2035                 2'd3: begin
2036                         if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin
2037                                 builder_liteethmacsramwriter_next_state <= 3'd4;
2038                         end
2039                 end
2040                 3'd4: begin
2041                         main_writer_counter_t_next_value <= 1'd0;
2042                         main_writer_counter_t_next_value_ce <= 1'd1;
2043                         main_writer_slot_ce <= 1'd1;
2044                         main_writer_stat_fifo_sink_valid <= 1'd1;
2045                         builder_liteethmacsramwriter_next_state <= 1'd0;
2046                 end
2047                 default: begin
2048                         if (main_writer_sink_sink_valid) begin
2049                                 if (main_writer_stat_fifo_sink_ready) begin
2050                                         main_writer_start <= 1'd1;
2051                                         main_writer_ongoing <= 1'd1;
2052                                         main_writer_counter_t_next_value <= (main_writer_counter + main_writer_decoded);
2053                                         main_writer_counter_t_next_value_ce <= 1'd1;
2054                                         builder_liteethmacsramwriter_next_state <= 1'd1;
2055                                 end else begin
2056                                         main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1);
2057                                         main_writer_errors_status_f_next_value_ce <= 1'd1;
2058                                         builder_liteethmacsramwriter_next_state <= 2'd3;
2059                                 end
2060                         end
2061                 end
2062         endcase
2063 end
2064 assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re;
2065 assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage;
2066 assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage;
2067 assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready;
2068 assign main_reader_level_status = main_reader_cmd_fifo_level;
2069 always @(*) begin
2070         main_reader_source_source_payload_last_be <= 4'd0;
2071         if (main_reader_source_source_last) begin
2072                 main_reader_source_source_payload_last_be <= main_reader_encoded;
2073         end
2074 end
2075 assign main_reader_memory0_adr = main_reader_read_address[10:2];
2076 assign main_reader_memory1_adr = main_reader_read_address[10:2];
2077 always @(*) begin
2078         main_reader_source_source_payload_data <= 32'd0;
2079         case (main_reader_cmd_fifo_source_payload_slot)
2080                 1'd0: begin
2081                         main_reader_source_source_payload_data <= main_reader_memory0_dat_r;
2082                 end
2083                 1'd1: begin
2084                         main_reader_source_source_payload_data <= main_reader_memory1_dat_r;
2085                 end
2086         endcase
2087 end
2088 assign main_reader_event00 = main_reader_eventsourcepulse_status;
2089 assign main_reader_event01 = main_reader_eventsourcepulse_pending;
2090 always @(*) begin
2091         main_reader_eventsourcepulse_clear <= 1'd0;
2092         if ((main_reader_pending_re & main_reader_pending_r)) begin
2093                 main_reader_eventsourcepulse_clear <= 1'd1;
2094         end
2095 end
2096 assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage);
2097 assign main_reader_eventsourcepulse_status = 1'd0;
2098 assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot};
2099 assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout;
2100 assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable;
2101 assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid;
2102 assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first;
2103 assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last;
2104 assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot;
2105 assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length;
2106 assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable;
2107 assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first;
2108 assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last;
2109 assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot;
2110 assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length;
2111 assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready;
2112 always @(*) begin
2113         main_reader_cmd_fifo_wrport_adr <= 1'd0;
2114         if (main_reader_cmd_fifo_replace) begin
2115                 main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1);
2116         end else begin
2117                 main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce;
2118         end
2119 end
2120 assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din;
2121 assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace));
2122 assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re);
2123 assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume;
2124 assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r;
2125 assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2);
2126 assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0);
2127 always @(*) begin
2128         main_reader_start <= 1'd0;
2129         builder_liteethmacsramreader_next_state <= 2'd0;
2130         main_reader_counter_next_value <= 11'd0;
2131         main_reader_source_source_last <= 1'd0;
2132         main_reader_counter_next_value_ce <= 1'd0;
2133         main_reader_read_address <= 11'd0;
2134         main_reader_cmd_fifo_source_ready <= 1'd0;
2135         main_reader_eventsourcepulse_trigger <= 1'd0;
2136         main_reader_source_source_valid <= 1'd0;
2137         builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state;
2138         case (builder_liteethmacsramreader_state)
2139                 1'd1: begin
2140                         main_reader_source_source_valid <= 1'd1;
2141                         main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4));
2142                         main_reader_read_address <= main_reader_counter;
2143                         if (main_reader_source_source_ready) begin
2144                                 main_reader_read_address <= (main_reader_counter + 3'd4);
2145                                 main_reader_counter_next_value <= (main_reader_counter + 3'd4);
2146                                 main_reader_counter_next_value_ce <= 1'd1;
2147                                 if (main_reader_source_source_last) begin
2148                                         builder_liteethmacsramreader_next_state <= 2'd2;
2149                                 end
2150                         end
2151                 end
2152                 2'd2: begin
2153                         main_reader_eventsourcepulse_trigger <= 1'd1;
2154                         main_reader_cmd_fifo_source_ready <= 1'd1;
2155                         builder_liteethmacsramreader_next_state <= 1'd0;
2156                 end
2157                 default: begin
2158                         main_reader_counter_next_value <= 1'd0;
2159                         main_reader_counter_next_value_ce <= 1'd1;
2160                         if (main_reader_cmd_fifo_source_valid) begin
2161                                 main_reader_start <= 1'd1;
2162                                 builder_liteethmacsramreader_next_state <= 1'd1;
2163                         end
2164                 end
2165         endcase
2166 end
2167 always @(*) begin
2168         main_reader_encoded <= 4'd0;
2169         case (main_reader_cmd_fifo_source_payload_length[1:0])
2170                 1'd0: begin
2171                         main_reader_encoded <= 4'd8;
2172                 end
2173                 1'd1: begin
2174                         main_reader_encoded <= 1'd1;
2175                 end
2176                 2'd2: begin
2177                         main_reader_encoded <= 2'd2;
2178                 end
2179                 2'd3: begin
2180                         main_reader_encoded <= 3'd4;
2181                 end
2182         endcase
2183 end
2184 assign main_ev_irq = (main_writer_irq | main_reader_irq);
2185 assign main_sram0_adr0 = main_interface0_adr[8:0];
2186 assign main_interface0_dat_r = main_sram0_dat_r0;
2187 assign main_interface0_adr = main_interface0_writer_sram_converted_width_adr;
2188 assign main_interface0_dat_w = main_interface0_writer_sram_converted_width_dat_w;
2189 assign main_interface0_writer_sram_converted_width_dat_r = main_interface0_dat_r;
2190 assign main_interface0_sel = main_interface0_writer_sram_converted_width_sel;
2191 assign main_interface0_cyc = main_interface0_writer_sram_converted_width_cyc;
2192 assign main_interface0_stb = main_interface0_writer_sram_converted_width_stb;
2193 assign main_interface0_writer_sram_converted_width_ack = main_interface0_ack;
2194 assign main_interface0_we = main_interface0_writer_sram_converted_width_we;
2195 assign main_interface0_cti = main_interface0_writer_sram_converted_width_cti;
2196 assign main_interface0_bte = main_interface0_writer_sram_converted_width_bte;
2197 assign main_interface0_writer_sram_converted_width_err = main_interface0_err;
2198 assign main_sram1_adr0 = main_interface1_adr[8:0];
2199 assign main_interface1_dat_r = main_sram1_dat_r0;
2200 assign main_interface1_adr = main_interface1_writer_sram_converted_width_adr;
2201 assign main_interface1_dat_w = main_interface1_writer_sram_converted_width_dat_w;
2202 assign main_interface1_writer_sram_converted_width_dat_r = main_interface1_dat_r;
2203 assign main_interface1_sel = main_interface1_writer_sram_converted_width_sel;
2204 assign main_interface1_cyc = main_interface1_writer_sram_converted_width_cyc;
2205 assign main_interface1_stb = main_interface1_writer_sram_converted_width_stb;
2206 assign main_interface1_writer_sram_converted_width_ack = main_interface1_ack;
2207 assign main_interface1_we = main_interface1_writer_sram_converted_width_we;
2208 assign main_interface1_cti = main_interface1_writer_sram_converted_width_cti;
2209 assign main_interface1_bte = main_interface1_writer_sram_converted_width_bte;
2210 assign main_interface1_writer_sram_converted_width_err = main_interface1_err;
2211 always @(*) begin
2212         main_sram0_we <= 4'd0;
2213         main_sram0_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]);
2214         main_sram0_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]);
2215         main_sram0_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]);
2216         main_sram0_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]);
2217 end
2218 assign main_sram0_adr1 = main_interface2_adr[8:0];
2219 assign main_interface2_dat_r = main_sram0_dat_r1;
2220 assign main_sram0_dat_w = main_interface2_dat_w;
2221 assign main_interface2_adr = main_interface0_reader_sram_converted_width_adr;
2222 assign main_interface2_dat_w = main_interface0_reader_sram_converted_width_dat_w;
2223 assign main_interface0_reader_sram_converted_width_dat_r = main_interface2_dat_r;
2224 assign main_interface2_sel = main_interface0_reader_sram_converted_width_sel;
2225 assign main_interface2_cyc = main_interface0_reader_sram_converted_width_cyc;
2226 assign main_interface2_stb = main_interface0_reader_sram_converted_width_stb;
2227 assign main_interface0_reader_sram_converted_width_ack = main_interface2_ack;
2228 assign main_interface2_we = main_interface0_reader_sram_converted_width_we;
2229 assign main_interface2_cti = main_interface0_reader_sram_converted_width_cti;
2230 assign main_interface2_bte = main_interface0_reader_sram_converted_width_bte;
2231 assign main_interface0_reader_sram_converted_width_err = main_interface2_err;
2232 always @(*) begin
2233         main_sram1_we <= 4'd0;
2234         main_sram1_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]);
2235         main_sram1_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]);
2236         main_sram1_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]);
2237         main_sram1_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]);
2238 end
2239 assign main_sram1_adr1 = main_interface3_adr[8:0];
2240 assign main_interface3_dat_r = main_sram1_dat_r1;
2241 assign main_sram1_dat_w = main_interface3_dat_w;
2242 assign main_interface3_adr = main_interface1_reader_sram_converted_width_adr;
2243 assign main_interface3_dat_w = main_interface1_reader_sram_converted_width_dat_w;
2244 assign main_interface1_reader_sram_converted_width_dat_r = main_interface3_dat_r;
2245 assign main_interface3_sel = main_interface1_reader_sram_converted_width_sel;
2246 assign main_interface3_cyc = main_interface1_reader_sram_converted_width_cyc;
2247 assign main_interface3_stb = main_interface1_reader_sram_converted_width_stb;
2248 assign main_interface1_reader_sram_converted_width_ack = main_interface3_ack;
2249 assign main_interface3_we = main_interface1_reader_sram_converted_width_we;
2250 assign main_interface3_cti = main_interface1_reader_sram_converted_width_cti;
2251 assign main_interface3_bte = main_interface1_reader_sram_converted_width_bte;
2252 assign main_interface1_reader_sram_converted_width_err = main_interface3_err;
2253 always @(*) begin
2254         main_slave_sel <= 4'd0;
2255         main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0);
2256         main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1);
2257         main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2);
2258         main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3);
2259 end
2260 assign main_interface0_writer_sram_converted_width_adr = main_bus_adr;
2261 assign main_interface0_writer_sram_converted_width_dat_w = main_bus_dat_w;
2262 assign main_interface0_writer_sram_converted_width_sel = main_bus_sel;
2263 assign main_interface0_writer_sram_converted_width_stb = main_bus_stb;
2264 assign main_interface0_writer_sram_converted_width_we = main_bus_we;
2265 assign main_interface0_writer_sram_converted_width_cti = main_bus_cti;
2266 assign main_interface0_writer_sram_converted_width_bte = main_bus_bte;
2267 assign main_interface1_writer_sram_converted_width_adr = main_bus_adr;
2268 assign main_interface1_writer_sram_converted_width_dat_w = main_bus_dat_w;
2269 assign main_interface1_writer_sram_converted_width_sel = main_bus_sel;
2270 assign main_interface1_writer_sram_converted_width_stb = main_bus_stb;
2271 assign main_interface1_writer_sram_converted_width_we = main_bus_we;
2272 assign main_interface1_writer_sram_converted_width_cti = main_bus_cti;
2273 assign main_interface1_writer_sram_converted_width_bte = main_bus_bte;
2274 assign main_interface0_reader_sram_converted_width_adr = main_bus_adr;
2275 assign main_interface0_reader_sram_converted_width_dat_w = main_bus_dat_w;
2276 assign main_interface0_reader_sram_converted_width_sel = main_bus_sel;
2277 assign main_interface0_reader_sram_converted_width_stb = main_bus_stb;
2278 assign main_interface0_reader_sram_converted_width_we = main_bus_we;
2279 assign main_interface0_reader_sram_converted_width_cti = main_bus_cti;
2280 assign main_interface0_reader_sram_converted_width_bte = main_bus_bte;
2281 assign main_interface1_reader_sram_converted_width_adr = main_bus_adr;
2282 assign main_interface1_reader_sram_converted_width_dat_w = main_bus_dat_w;
2283 assign main_interface1_reader_sram_converted_width_sel = main_bus_sel;
2284 assign main_interface1_reader_sram_converted_width_stb = main_bus_stb;
2285 assign main_interface1_reader_sram_converted_width_we = main_bus_we;
2286 assign main_interface1_reader_sram_converted_width_cti = main_bus_cti;
2287 assign main_interface1_reader_sram_converted_width_bte = main_bus_bte;
2288 assign main_interface0_writer_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[0]);
2289 assign main_interface1_writer_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[1]);
2290 assign main_interface0_reader_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[2]);
2291 assign main_interface1_reader_sram_converted_width_cyc = (main_bus_cyc & main_slave_sel[3]);
2292 assign main_bus_ack = (((main_interface0_writer_sram_converted_width_ack | main_interface1_writer_sram_converted_width_ack) | main_interface0_reader_sram_converted_width_ack) | main_interface1_reader_sram_converted_width_ack);
2293 assign main_bus_err = (((main_interface0_writer_sram_converted_width_err | main_interface1_writer_sram_converted_width_err) | main_interface0_reader_sram_converted_width_err) | main_interface1_reader_sram_converted_width_err);
2294 assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_writer_sram_converted_width_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_writer_sram_converted_width_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface0_reader_sram_converted_width_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface1_reader_sram_converted_width_dat_r));
2295 always @(*) begin
2296         builder_maccore_wishbone_ack <= 1'd0;
2297         builder_next_state <= 1'd0;
2298         builder_maccore_wishbone_dat_r <= 32'd0;
2299         builder_maccore_adr <= 14'd0;
2300         builder_maccore_we <= 1'd0;
2301         builder_maccore_dat_w <= 32'd0;
2302         builder_next_state <= builder_state;
2303         case (builder_state)
2304                 1'd1: begin
2305                         builder_maccore_wishbone_ack <= 1'd1;
2306                         builder_maccore_wishbone_dat_r <= builder_maccore_dat_r;
2307                         builder_next_state <= 1'd0;
2308                 end
2309                 default: begin
2310                         builder_maccore_dat_w <= builder_maccore_wishbone_dat_w;
2311                         if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin
2312                                 builder_maccore_adr <= builder_maccore_wishbone_adr;
2313                                 builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0));
2314                                 builder_next_state <= 1'd1;
2315                         end
2316                 end
2317         endcase
2318 end
2319 assign builder_shared_adr = builder_array_muxed0;
2320 assign builder_shared_dat_w = builder_array_muxed1;
2321 assign builder_shared_sel = builder_array_muxed2;
2322 assign builder_shared_cyc = builder_array_muxed3;
2323 assign builder_shared_stb = builder_array_muxed4;
2324 assign builder_shared_we = builder_array_muxed5;
2325 assign builder_shared_cti = builder_array_muxed6;
2326 assign builder_shared_bte = builder_array_muxed7;
2327 assign main_wb_bus_dat_r = builder_shared_dat_r;
2328 assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0));
2329 assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0));
2330 assign builder_request = {main_wb_bus_cyc};
2331 assign builder_grant = 1'd0;
2332 always @(*) begin
2333         builder_slave_sel <= 2'd0;
2334         builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8);
2335         builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0);
2336 end
2337 assign main_bus_adr = builder_shared_adr;
2338 assign main_bus_dat_w = builder_shared_dat_w;
2339 assign main_bus_sel = builder_shared_sel;
2340 assign main_bus_stb = builder_shared_stb;
2341 assign main_bus_we = builder_shared_we;
2342 assign main_bus_cti = builder_shared_cti;
2343 assign main_bus_bte = builder_shared_bte;
2344 assign builder_maccore_wishbone_adr = builder_shared_adr;
2345 assign builder_maccore_wishbone_dat_w = builder_shared_dat_w;
2346 assign builder_maccore_wishbone_sel = builder_shared_sel;
2347 assign builder_maccore_wishbone_stb = builder_shared_stb;
2348 assign builder_maccore_wishbone_we = builder_shared_we;
2349 assign builder_maccore_wishbone_cti = builder_shared_cti;
2350 assign builder_maccore_wishbone_bte = builder_shared_bte;
2351 assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]);
2352 assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]);
2353 assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
2354 assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
2355 always @(*) begin
2356         builder_shared_ack <= 1'd0;
2357         builder_error <= 1'd0;
2358         builder_shared_dat_r <= 32'd0;
2359         builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
2360         builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
2361         if (builder_done) begin
2362                 builder_shared_dat_r <= 32'd4294967295;
2363                 builder_shared_ack <= 1'd1;
2364                 builder_error <= 1'd1;
2365         end
2366 end
2367 assign builder_done = (builder_count == 1'd0);
2368 assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 2'd2);
2369 assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0];
2370 always @(*) begin
2371         builder_csrbank0_reset0_re <= 1'd0;
2372         builder_csrbank0_reset0_we <= 1'd0;
2373         if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
2374                 builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we;
2375                 builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we);
2376         end
2377 end
2378 assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0];
2379 always @(*) begin
2380         builder_csrbank0_scratch0_we <= 1'd0;
2381         builder_csrbank0_scratch0_re <= 1'd0;
2382         if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
2383                 builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we;
2384                 builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we);
2385         end
2386 end
2387 assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0];
2388 always @(*) begin
2389         builder_csrbank0_bus_errors_we <= 1'd0;
2390         builder_csrbank0_bus_errors_re <= 1'd0;
2391         if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin
2392                 builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we;
2393                 builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we);
2394         end
2395 end
2396 always @(*) begin
2397         main_maccore_maccore_soc_rst <= 1'd0;
2398         if (main_maccore_maccore_reset_re) begin
2399                 main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0];
2400         end
2401 end
2402 assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1];
2403 assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0];
2404 assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0];
2405 assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0];
2406 assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we;
2407 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
2408 assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0];
2409 always @(*) begin
2410         builder_csrbank1_sram_writer_slot_we <= 1'd0;
2411         builder_csrbank1_sram_writer_slot_re <= 1'd0;
2412         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
2413                 builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we;
2414                 builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we);
2415         end
2416 end
2417 assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0];
2418 always @(*) begin
2419         builder_csrbank1_sram_writer_length_we <= 1'd0;
2420         builder_csrbank1_sram_writer_length_re <= 1'd0;
2421         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
2422                 builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we;
2423                 builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we);
2424         end
2425 end
2426 assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0];
2427 always @(*) begin
2428         builder_csrbank1_sram_writer_errors_re <= 1'd0;
2429         builder_csrbank1_sram_writer_errors_we <= 1'd0;
2430         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
2431                 builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we;
2432                 builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we);
2433         end
2434 end
2435 assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0];
2436 always @(*) begin
2437         builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
2438         builder_csrbank1_sram_writer_ev_status_we <= 1'd0;
2439         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
2440                 builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we;
2441                 builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we);
2442         end
2443 end
2444 assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
2445 always @(*) begin
2446         builder_csrbank1_sram_writer_ev_pending_we <= 1'd0;
2447         builder_csrbank1_sram_writer_ev_pending_re <= 1'd0;
2448         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
2449                 builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we;
2450                 builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we);
2451         end
2452 end
2453 assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
2454 always @(*) begin
2455         builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
2456         builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
2457         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
2458                 builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we;
2459                 builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we);
2460         end
2461 end
2462 assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0];
2463 always @(*) begin
2464         main_reader_start_start_we <= 1'd0;
2465         main_reader_start_start_re <= 1'd0;
2466         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
2467                 main_reader_start_start_re <= builder_interface1_bank_bus_we;
2468                 main_reader_start_start_we <= (~builder_interface1_bank_bus_we);
2469         end
2470 end
2471 assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0];
2472 always @(*) begin
2473         builder_csrbank1_sram_reader_ready_re <= 1'd0;
2474         builder_csrbank1_sram_reader_ready_we <= 1'd0;
2475         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
2476                 builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we;
2477                 builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we);
2478         end
2479 end
2480 assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0];
2481 always @(*) begin
2482         builder_csrbank1_sram_reader_level_we <= 1'd0;
2483         builder_csrbank1_sram_reader_level_re <= 1'd0;
2484         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
2485                 builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we;
2486                 builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we);
2487         end
2488 end
2489 assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0];
2490 always @(*) begin
2491         builder_csrbank1_sram_reader_slot0_we <= 1'd0;
2492         builder_csrbank1_sram_reader_slot0_re <= 1'd0;
2493         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
2494                 builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we;
2495                 builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we);
2496         end
2497 end
2498 assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0];
2499 always @(*) begin
2500         builder_csrbank1_sram_reader_length0_re <= 1'd0;
2501         builder_csrbank1_sram_reader_length0_we <= 1'd0;
2502         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
2503                 builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we;
2504                 builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we);
2505         end
2506 end
2507 assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0];
2508 always @(*) begin
2509         builder_csrbank1_sram_reader_ev_status_we <= 1'd0;
2510         builder_csrbank1_sram_reader_ev_status_re <= 1'd0;
2511         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
2512                 builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we;
2513                 builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we);
2514         end
2515 end
2516 assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
2517 always @(*) begin
2518         builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
2519         builder_csrbank1_sram_reader_ev_pending_re <= 1'd0;
2520         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
2521                 builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we;
2522                 builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we);
2523         end
2524 end
2525 assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
2526 always @(*) begin
2527         builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0;
2528         builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0;
2529         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
2530                 builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we;
2531                 builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we);
2532         end
2533 end
2534 assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0];
2535 always @(*) begin
2536         builder_csrbank1_preamble_crc_we <= 1'd0;
2537         builder_csrbank1_preamble_crc_re <= 1'd0;
2538         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
2539                 builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we;
2540                 builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we);
2541         end
2542 end
2543 assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0];
2544 always @(*) begin
2545         builder_csrbank1_preamble_errors_we <= 1'd0;
2546         builder_csrbank1_preamble_errors_re <= 1'd0;
2547         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
2548                 builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we;
2549                 builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we);
2550         end
2551 end
2552 assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0];
2553 always @(*) begin
2554         builder_csrbank1_crc_errors_re <= 1'd0;
2555         builder_csrbank1_crc_errors_we <= 1'd0;
2556         if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
2557                 builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we;
2558                 builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we);
2559         end
2560 end
2561 assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status;
2562 assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we;
2563 assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0];
2564 assign main_writer_length_we = builder_csrbank1_sram_writer_length_we;
2565 assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0];
2566 assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we;
2567 assign main_writer_status_status = main_writer_available0;
2568 assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status;
2569 assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we;
2570 assign main_writer_pending_status = main_writer_available1;
2571 assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status;
2572 assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we;
2573 assign main_writer_available2 = main_writer_enable_storage;
2574 assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage;
2575 assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status;
2576 assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we;
2577 assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0];
2578 assign main_reader_level_we = builder_csrbank1_sram_reader_level_we;
2579 assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage;
2580 assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0];
2581 assign main_reader_status_status = main_reader_event00;
2582 assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status;
2583 assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we;
2584 assign main_reader_pending_status = main_reader_event01;
2585 assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status;
2586 assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we;
2587 assign main_reader_event02 = main_reader_enable_storage;
2588 assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage;
2589 assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status;
2590 assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we;
2591 assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0];
2592 assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we;
2593 assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0];
2594 assign main_crc_errors_we = builder_csrbank1_crc_errors_we;
2595 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
2596 assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0];
2597 always @(*) begin
2598         builder_csrbank2_crg_reset0_re <= 1'd0;
2599         builder_csrbank2_crg_reset0_we <= 1'd0;
2600         if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
2601                 builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we;
2602                 builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we);
2603         end
2604 end
2605 assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0];
2606 always @(*) begin
2607         builder_csrbank2_rx_inband_status_we <= 1'd0;
2608         builder_csrbank2_rx_inband_status_re <= 1'd0;
2609         if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
2610                 builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we;
2611                 builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we);
2612         end
2613 end
2614 assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0];
2615 always @(*) begin
2616         builder_csrbank2_mdio_w0_we <= 1'd0;
2617         builder_csrbank2_mdio_w0_re <= 1'd0;
2618         if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
2619                 builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we;
2620                 builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we);
2621         end
2622 end
2623 assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0];
2624 always @(*) begin
2625         builder_csrbank2_mdio_r_re <= 1'd0;
2626         builder_csrbank2_mdio_r_we <= 1'd0;
2627         if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
2628                 builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we;
2629                 builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we);
2630         end
2631 end
2632 assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage;
2633 always @(*) begin
2634         main_maccore_ethphy_status <= 3'd0;
2635         main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status;
2636         main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed;
2637         main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status;
2638 end
2639 assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0];
2640 assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we;
2641 assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0];
2642 assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1];
2643 assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2];
2644 assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0];
2645 assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status;
2646 assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we;
2647 assign builder_csr_interconnect_adr = builder_maccore_adr;
2648 assign builder_csr_interconnect_we = builder_maccore_we;
2649 assign builder_csr_interconnect_dat_w = builder_maccore_dat_w;
2650 assign builder_maccore_dat_r = builder_csr_interconnect_dat_r;
2651 assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
2652 assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
2653 assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
2654 assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
2655 assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
2656 assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
2657 assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
2658 assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
2659 assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
2660 assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
2661 always @(*) begin
2662         builder_array_muxed0 <= 30'd0;
2663         case (builder_grant)
2664                 default: begin
2665                         builder_array_muxed0 <= main_wb_bus_adr;
2666                 end
2667         endcase
2668 end
2669 always @(*) begin
2670         builder_array_muxed1 <= 32'd0;
2671         case (builder_grant)
2672                 default: begin
2673                         builder_array_muxed1 <= main_wb_bus_dat_w;
2674                 end
2675         endcase
2676 end
2677 always @(*) begin
2678         builder_array_muxed2 <= 4'd0;
2679         case (builder_grant)
2680                 default: begin
2681                         builder_array_muxed2 <= main_wb_bus_sel;
2682                 end
2683         endcase
2684 end
2685 always @(*) begin
2686         builder_array_muxed3 <= 1'd0;
2687         case (builder_grant)
2688                 default: begin
2689                         builder_array_muxed3 <= main_wb_bus_cyc;
2690                 end
2691         endcase
2692 end
2693 always @(*) begin
2694         builder_array_muxed4 <= 1'd0;
2695         case (builder_grant)
2696                 default: begin
2697                         builder_array_muxed4 <= main_wb_bus_stb;
2698                 end
2699         endcase
2700 end
2701 always @(*) begin
2702         builder_array_muxed5 <= 1'd0;
2703         case (builder_grant)
2704                 default: begin
2705                         builder_array_muxed5 <= main_wb_bus_we;
2706                 end
2707         endcase
2708 end
2709 always @(*) begin
2710         builder_array_muxed6 <= 3'd0;
2711         case (builder_grant)
2712                 default: begin
2713                         builder_array_muxed6 <= main_wb_bus_cti;
2714                 end
2715         endcase
2716 end
2717 always @(*) begin
2718         builder_array_muxed7 <= 2'd0;
2719         case (builder_grant)
2720                 default: begin
2721                         builder_array_muxed7 <= main_wb_bus_bte;
2722                 end
2723         endcase
2724 end
2725 always @(*) begin
2726         main_maccore_ethphy__r_status <= 1'd0;
2727         main_maccore_ethphy__r_status <= main_maccore_ethphy_r;
2728         main_maccore_ethphy__r_status <= builder_multiregimpl0_regs1;
2729 end
2730 assign main_ps_preamble_error_toggle_o = builder_multiregimpl1_regs1;
2731 assign main_ps_crc_error_toggle_o = builder_multiregimpl2_regs1;
2732 assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl3_regs1;
2733 assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl4_regs1;
2734 assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl5_regs1;
2735 assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl6_regs1;
2736
2737
2738 //------------------------------------------------------------------------------
2739 // Synchronous Logic
2740 //------------------------------------------------------------------------------
2741
2742 always @(posedge eth_rx_clk) begin
2743         main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl;
2744         main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data;
2745         main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg;
2746         main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0];
2747         main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg;
2748         if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin
2749                 main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0];
2750                 main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1];
2751                 main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3];
2752         end
2753         builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state;
2754         if (main_liteethmaccrc32checker_crc_ce) begin
2755                 main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next;
2756         end
2757         if (main_liteethmaccrc32checker_crc_reset) begin
2758                 main_liteethmaccrc32checker_crc_reg <= 32'd4294967295;
2759         end
2760         if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin
2761                 if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin
2762                         main_liteethmaccrc32checker_syncfifo_produce <= 1'd0;
2763                 end else begin
2764                         main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1);
2765                 end
2766         end
2767         if (main_liteethmaccrc32checker_syncfifo_do_read) begin
2768                 if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin
2769                         main_liteethmaccrc32checker_syncfifo_consume <= 1'd0;
2770                 end else begin
2771                         main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1);
2772                 end
2773         end
2774         if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin
2775                 if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin
2776                         main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1);
2777                 end
2778         end else begin
2779                 if (main_liteethmaccrc32checker_syncfifo_do_read) begin
2780                         main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1);
2781                 end
2782         end
2783         if (main_liteethmaccrc32checker_fifo_reset) begin
2784                 main_liteethmaccrc32checker_syncfifo_level <= 3'd0;
2785                 main_liteethmaccrc32checker_syncfifo_produce <= 3'd0;
2786                 main_liteethmaccrc32checker_syncfifo_consume <= 3'd0;
2787         end
2788         builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state;
2789         if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin
2790                 main_crc32_checker_source_valid <= main_crc32_checker_sink_valid;
2791                 main_crc32_checker_source_first <= main_crc32_checker_sink_first;
2792                 main_crc32_checker_source_last <= main_crc32_checker_sink_last;
2793                 main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data;
2794                 main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be;
2795                 main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error;
2796         end
2797         if (main_ps_preamble_error_i) begin
2798                 main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i);
2799         end
2800         if (main_ps_crc_error_i) begin
2801                 main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i);
2802         end
2803         if (main_rx_converter_converter_source_ready) begin
2804                 main_rx_converter_converter_strobe_all <= 1'd0;
2805         end
2806         if (main_rx_converter_converter_load_part) begin
2807                 if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin
2808                         main_rx_converter_converter_demux <= 1'd0;
2809                         main_rx_converter_converter_strobe_all <= 1'd1;
2810                 end else begin
2811                         main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1);
2812                 end
2813         end
2814         if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin
2815                 if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin
2816                         main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first;
2817                         main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last;
2818                 end else begin
2819                         main_rx_converter_converter_source_first <= 1'd0;
2820                         main_rx_converter_converter_source_last <= 1'd0;
2821                 end
2822         end else begin
2823                 if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin
2824                         main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first);
2825                         main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last);
2826                 end
2827         end
2828         if (main_rx_converter_converter_load_part) begin
2829                 case (main_rx_converter_converter_demux)
2830                         1'd0: begin
2831                                 main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data;
2832                         end
2833                         1'd1: begin
2834                                 main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data;
2835                         end
2836                         2'd2: begin
2837                                 main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data;
2838                         end
2839                         2'd3: begin
2840                                 main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data;
2841                         end
2842                 endcase
2843         end
2844         if (main_rx_converter_converter_load_part) begin
2845                 main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1);
2846         end
2847         main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary;
2848         main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next;
2849         if (eth_rx_rst) begin
2850                 main_maccore_ethphy_source_valid <= 1'd0;
2851                 main_maccore_ethphy_source_payload_data <= 8'd0;
2852                 main_maccore_ethphy_link_status <= 1'd0;
2853                 main_maccore_ethphy_clock_speed <= 1'd0;
2854                 main_maccore_ethphy_duplex_status <= 1'd0;
2855                 main_maccore_ethphy_rx_ctl_reg <= 2'd0;
2856                 main_maccore_ethphy_rx_data_reg <= 8'd0;
2857                 main_maccore_ethphy_rx_ctl_reg_d <= 2'd0;
2858                 main_liteethmaccrc32checker_crc_reg <= 32'd4294967295;
2859                 main_liteethmaccrc32checker_syncfifo_level <= 3'd0;
2860                 main_liteethmaccrc32checker_syncfifo_produce <= 3'd0;
2861                 main_liteethmaccrc32checker_syncfifo_consume <= 3'd0;
2862                 main_crc32_checker_source_valid <= 1'd0;
2863                 main_crc32_checker_source_payload_data <= 8'd0;
2864                 main_crc32_checker_source_payload_last_be <= 1'd0;
2865                 main_crc32_checker_source_payload_error <= 1'd0;
2866                 main_rx_converter_converter_source_payload_data <= 40'd0;
2867                 main_rx_converter_converter_source_payload_valid_token_count <= 3'd0;
2868                 main_rx_converter_converter_demux <= 2'd0;
2869                 main_rx_converter_converter_strobe_all <= 1'd0;
2870                 main_rx_cdc_cdc_graycounter0_q <= 6'd0;
2871                 main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0;
2872                 builder_liteethmacpreamblechecker_state <= 1'd0;
2873                 builder_liteethmaccrc32checker_state <= 2'd0;
2874         end
2875         builder_multiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q;
2876         builder_multiregimpl6_regs1 <= builder_multiregimpl6_regs0;
2877 end
2878
2879 always @(posedge eth_tx_clk) begin
2880         builder_liteethmacgap_state <= builder_liteethmacgap_next_state;
2881         if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin
2882                 main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value;
2883         end
2884         builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state;
2885         if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin
2886                 main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value;
2887         end
2888         if (main_liteethmaccrc32inserter_is_ongoing0) begin
2889                 main_liteethmaccrc32inserter_cnt <= 2'd3;
2890         end else begin
2891                 if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin
2892                         main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready);
2893                 end
2894         end
2895         if (main_liteethmaccrc32inserter_ce) begin
2896                 main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next;
2897         end
2898         if (main_liteethmaccrc32inserter_reset) begin
2899                 main_liteethmaccrc32inserter_reg <= 32'd4294967295;
2900         end
2901         builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state;
2902         if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin
2903                 main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid;
2904                 main_crc32_inserter_source_first <= main_crc32_inserter_sink_first;
2905                 main_crc32_inserter_source_last <= main_crc32_inserter_sink_last;
2906                 main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data;
2907                 main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be;
2908                 main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error;
2909         end
2910         builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state;
2911         if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin
2912                 main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value;
2913         end
2914         builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state;
2915         if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin
2916                 if (main_tx_converter_converter_last) begin
2917                         main_tx_converter_converter_mux <= 1'd0;
2918                 end else begin
2919                         main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1);
2920                 end
2921         end
2922         main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary;
2923         main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next;
2924         if (eth_tx_rst) begin
2925                 main_liteethmaccrc32inserter_reg <= 32'd4294967295;
2926                 main_liteethmaccrc32inserter_cnt <= 2'd3;
2927                 main_crc32_inserter_source_valid <= 1'd0;
2928                 main_crc32_inserter_source_payload_data <= 8'd0;
2929                 main_crc32_inserter_source_payload_last_be <= 1'd0;
2930                 main_crc32_inserter_source_payload_error <= 1'd0;
2931                 main_padding_inserter_counter <= 16'd0;
2932                 main_tx_converter_converter_mux <= 2'd0;
2933                 main_tx_cdc_cdc_graycounter1_q <= 6'd0;
2934                 main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0;
2935                 builder_liteethmacgap_state <= 1'd0;
2936                 builder_liteethmacpreambleinserter_state <= 2'd0;
2937                 builder_liteethmaccrc32inserter_state <= 2'd0;
2938                 builder_liteethmacpaddinginserter_state <= 1'd0;
2939                 builder_liteethmactxlastbe_state <= 1'd0;
2940         end
2941         builder_multiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q;
2942         builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
2943 end
2944
2945 always @(posedge por_clk) begin
2946         main_maccore_int_rst <= sys_reset;
2947 end
2948
2949 always @(posedge sys_clk) begin
2950         if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin
2951                 if (main_maccore_maccore_bus_error) begin
2952                         main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1);
2953                 end
2954         end
2955         if (main_ps_preamble_error_o) begin
2956                 main_preamble_errors_status <= (main_preamble_errors_status + 1'd1);
2957         end
2958         if (main_ps_crc_error_o) begin
2959                 main_crc_errors_status <= (main_crc_errors_status + 1'd1);
2960         end
2961         main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o;
2962         main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o;
2963         main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary;
2964         main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next;
2965         main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary;
2966         main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next;
2967         if (main_writer_slot_ce) begin
2968                 main_writer_slot <= (main_writer_slot + 1'd1);
2969         end
2970         if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin
2971                 main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1);
2972         end
2973         if (main_writer_stat_fifo_do_read) begin
2974                 main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1);
2975         end
2976         if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin
2977                 if ((~main_writer_stat_fifo_do_read)) begin
2978                         main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1);
2979                 end
2980         end else begin
2981                 if (main_writer_stat_fifo_do_read) begin
2982                         main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1);
2983                 end
2984         end
2985         builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state;
2986         if (main_writer_counter_t_next_value_ce) begin
2987                 main_writer_counter <= main_writer_counter_t_next_value;
2988         end
2989         if (main_writer_errors_status_f_next_value_ce) begin
2990                 main_writer_errors_status <= main_writer_errors_status_f_next_value;
2991         end
2992         if (main_reader_eventsourcepulse_clear) begin
2993                 main_reader_eventsourcepulse_pending <= 1'd0;
2994         end
2995         if (main_reader_eventsourcepulse_trigger) begin
2996                 main_reader_eventsourcepulse_pending <= 1'd1;
2997         end
2998         if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin
2999                 main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1);
3000         end
3001         if (main_reader_cmd_fifo_do_read) begin
3002                 main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1);
3003         end
3004         if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin
3005                 if ((~main_reader_cmd_fifo_do_read)) begin
3006                         main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1);
3007                 end
3008         end else begin
3009                 if (main_reader_cmd_fifo_do_read) begin
3010                         main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1);
3011                 end
3012         end
3013         builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state;
3014         if (main_reader_counter_next_value_ce) begin
3015                 main_reader_counter <= main_reader_counter_next_value;
3016         end
3017         main_interface0_ack <= 1'd0;
3018         if (((main_interface0_cyc & main_interface0_stb) & (~main_interface0_ack))) begin
3019                 main_interface0_ack <= 1'd1;
3020         end
3021         main_interface1_ack <= 1'd0;
3022         if (((main_interface1_cyc & main_interface1_stb) & (~main_interface1_ack))) begin
3023                 main_interface1_ack <= 1'd1;
3024         end
3025         main_interface2_ack <= 1'd0;
3026         if (((main_interface2_cyc & main_interface2_stb) & (~main_interface2_ack))) begin
3027                 main_interface2_ack <= 1'd1;
3028         end
3029         main_interface3_ack <= 1'd0;
3030         if (((main_interface3_cyc & main_interface3_stb) & (~main_interface3_ack))) begin
3031                 main_interface3_ack <= 1'd1;
3032         end
3033         main_slave_sel_r <= main_slave_sel;
3034         builder_state <= builder_next_state;
3035         builder_slave_sel_r <= builder_slave_sel;
3036         if (builder_wait) begin
3037                 if ((~builder_done)) begin
3038                         builder_count <= (builder_count - 1'd1);
3039                 end
3040         end else begin
3041                 builder_count <= 20'd1000000;
3042         end
3043         builder_interface0_bank_bus_dat_r <= 1'd0;
3044         if (builder_csrbank0_sel) begin
3045                 case (builder_interface0_bank_bus_adr[8:0])
3046                         1'd0: begin
3047                                 builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w;
3048                         end
3049                         1'd1: begin
3050                                 builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w;
3051                         end
3052                         2'd2: begin
3053                                 builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w;
3054                         end
3055                 endcase
3056         end
3057         if (builder_csrbank0_reset0_re) begin
3058                 main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r;
3059         end
3060         main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re;
3061         if (builder_csrbank0_scratch0_re) begin
3062                 main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r;
3063         end
3064         main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re;
3065         main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re;
3066         builder_interface1_bank_bus_dat_r <= 1'd0;
3067         if (builder_csrbank1_sel) begin
3068                 case (builder_interface1_bank_bus_adr[8:0])
3069                         1'd0: begin
3070                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w;
3071                         end
3072                         1'd1: begin
3073                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w;
3074                         end
3075                         2'd2: begin
3076                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w;
3077                         end
3078                         2'd3: begin
3079                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w;
3080                         end
3081                         3'd4: begin
3082                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w;
3083                         end
3084                         3'd5: begin
3085                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w;
3086                         end
3087                         3'd6: begin
3088                                 builder_interface1_bank_bus_dat_r <= main_reader_start_start_w;
3089                         end
3090                         3'd7: begin
3091                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w;
3092                         end
3093                         4'd8: begin
3094                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w;
3095                         end
3096                         4'd9: begin
3097                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w;
3098                         end
3099                         4'd10: begin
3100                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w;
3101                         end
3102                         4'd11: begin
3103                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w;
3104                         end
3105                         4'd12: begin
3106                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w;
3107                         end
3108                         4'd13: begin
3109                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w;
3110                         end
3111                         4'd14: begin
3112                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w;
3113                         end
3114                         4'd15: begin
3115                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w;
3116                         end
3117                         5'd16: begin
3118                                 builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w;
3119                         end
3120                 endcase
3121         end
3122         main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re;
3123         main_writer_length_re <= builder_csrbank1_sram_writer_length_re;
3124         main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re;
3125         main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re;
3126         if (builder_csrbank1_sram_writer_ev_pending_re) begin
3127                 main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r;
3128         end
3129         main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re;
3130         if (builder_csrbank1_sram_writer_ev_enable0_re) begin
3131                 main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r;
3132         end
3133         main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re;
3134         main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re;
3135         main_reader_level_re <= builder_csrbank1_sram_reader_level_re;
3136         if (builder_csrbank1_sram_reader_slot0_re) begin
3137                 main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r;
3138         end
3139         main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re;
3140         if (builder_csrbank1_sram_reader_length0_re) begin
3141                 main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r;
3142         end
3143         main_reader_length_re <= builder_csrbank1_sram_reader_length0_re;
3144         main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re;
3145         if (builder_csrbank1_sram_reader_ev_pending_re) begin
3146                 main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r;
3147         end
3148         main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re;
3149         if (builder_csrbank1_sram_reader_ev_enable0_re) begin
3150                 main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r;
3151         end
3152         main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re;
3153         main_preamble_crc_re <= builder_csrbank1_preamble_crc_re;
3154         main_preamble_errors_re <= builder_csrbank1_preamble_errors_re;
3155         main_crc_errors_re <= builder_csrbank1_crc_errors_re;
3156         builder_interface2_bank_bus_dat_r <= 1'd0;
3157         if (builder_csrbank2_sel) begin
3158                 case (builder_interface2_bank_bus_adr[8:0])
3159                         1'd0: begin
3160                                 builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w;
3161                         end
3162                         1'd1: begin
3163                                 builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w;
3164                         end
3165                         2'd2: begin
3166                                 builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w;
3167                         end
3168                         2'd3: begin
3169                                 builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w;
3170                         end
3171                 endcase
3172         end
3173         if (builder_csrbank2_crg_reset0_re) begin
3174                 main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r;
3175         end
3176         main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re;
3177         main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re;
3178         if (builder_csrbank2_mdio_w0_re) begin
3179                 main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r;
3180         end
3181         main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re;
3182         main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re;
3183         if (sys_rst) begin
3184                 main_maccore_maccore_reset_storage <= 2'd0;
3185                 main_maccore_maccore_reset_re <= 1'd0;
3186                 main_maccore_maccore_scratch_storage <= 32'd305419896;
3187                 main_maccore_maccore_scratch_re <= 1'd0;
3188                 main_maccore_maccore_bus_errors_re <= 1'd0;
3189                 main_maccore_maccore_bus_errors <= 32'd0;
3190                 main_maccore_ethphy_reset_storage <= 1'd0;
3191                 main_maccore_ethphy_reset_re <= 1'd0;
3192                 main_maccore_ethphy_re <= 1'd0;
3193                 main_maccore_ethphy__w_storage <= 3'd0;
3194                 main_maccore_ethphy__w_re <= 1'd0;
3195                 main_maccore_ethphy__r_re <= 1'd0;
3196                 main_preamble_crc_re <= 1'd0;
3197                 main_preamble_errors_status <= 32'd0;
3198                 main_preamble_errors_re <= 1'd0;
3199                 main_crc_errors_status <= 32'd0;
3200                 main_crc_errors_re <= 1'd0;
3201                 main_tx_cdc_cdc_graycounter0_q <= 6'd0;
3202                 main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0;
3203                 main_rx_cdc_cdc_graycounter1_q <= 6'd0;
3204                 main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0;
3205                 main_writer_slot_re <= 1'd0;
3206                 main_writer_length_re <= 1'd0;
3207                 main_writer_errors_status <= 32'd0;
3208                 main_writer_errors_re <= 1'd0;
3209                 main_writer_status_re <= 1'd0;
3210                 main_writer_pending_re <= 1'd0;
3211                 main_writer_pending_r <= 1'd0;
3212                 main_writer_enable_storage <= 1'd0;
3213                 main_writer_enable_re <= 1'd0;
3214                 main_writer_counter <= 32'd0;
3215                 main_writer_slot <= 1'd0;
3216                 main_writer_stat_fifo_level <= 2'd0;
3217                 main_writer_stat_fifo_produce <= 1'd0;
3218                 main_writer_stat_fifo_consume <= 1'd0;
3219                 main_reader_ready_re <= 1'd0;
3220                 main_reader_level_re <= 1'd0;
3221                 main_reader_slot_re <= 1'd0;
3222                 main_reader_length_re <= 1'd0;
3223                 main_reader_eventsourcepulse_pending <= 1'd0;
3224                 main_reader_status_re <= 1'd0;
3225                 main_reader_pending_re <= 1'd0;
3226                 main_reader_pending_r <= 1'd0;
3227                 main_reader_enable_storage <= 1'd0;
3228                 main_reader_enable_re <= 1'd0;
3229                 main_reader_cmd_fifo_level <= 2'd0;
3230                 main_reader_cmd_fifo_produce <= 1'd0;
3231                 main_reader_cmd_fifo_consume <= 1'd0;
3232                 main_reader_counter <= 11'd0;
3233                 main_interface0_ack <= 1'd0;
3234                 main_interface1_ack <= 1'd0;
3235                 main_interface2_ack <= 1'd0;
3236                 main_interface3_ack <= 1'd0;
3237                 main_slave_sel_r <= 4'd0;
3238                 builder_liteethmacsramwriter_state <= 3'd0;
3239                 builder_liteethmacsramreader_state <= 2'd0;
3240                 builder_slave_sel_r <= 2'd0;
3241                 builder_count <= 20'd1000000;
3242                 builder_state <= 1'd0;
3243         end
3244         builder_multiregimpl0_regs0 <= main_maccore_ethphy_data_r;
3245         builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
3246         builder_multiregimpl1_regs0 <= main_ps_preamble_error_toggle_i;
3247         builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
3248         builder_multiregimpl2_regs0 <= main_ps_crc_error_toggle_i;
3249         builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
3250         builder_multiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q;
3251         builder_multiregimpl4_regs1 <= builder_multiregimpl4_regs0;
3252         builder_multiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q;
3253         builder_multiregimpl5_regs1 <= builder_multiregimpl5_regs0;
3254 end
3255
3256
3257 //------------------------------------------------------------------------------
3258 // Specialized Logic
3259 //------------------------------------------------------------------------------
3260
3261 DELAYG #(
3262         .DEL_MODE("SCLK_ALIGNED"),
3263         .DEL_VALUE(7'd80)
3264 ) DELAYG (
3265         .A(main_maccore_ethphy_eth_tx_clk_o),
3266         .Z(rgmii_eth_clocks_tx)
3267 );
3268
3269 DELAYG #(
3270         .DEL_MODE("SCLK_ALIGNED"),
3271         .DEL_VALUE(1'd0)
3272 ) DELAYG_1 (
3273         .A(main_maccore_ethphy_tx_ctl_oddrx1f),
3274         .Z(rgmii_eth_tx_ctl)
3275 );
3276
3277 DELAYG #(
3278         .DEL_MODE("SCLK_ALIGNED"),
3279         .DEL_VALUE(1'd0)
3280 ) DELAYG_2 (
3281         .A(main_maccore_ethphy_tx_data_oddrx1f[0]),
3282         .Z(rgmii_eth_tx_data[0])
3283 );
3284
3285 DELAYG #(
3286         .DEL_MODE("SCLK_ALIGNED"),
3287         .DEL_VALUE(1'd0)
3288 ) DELAYG_3 (
3289         .A(main_maccore_ethphy_tx_data_oddrx1f[1]),
3290         .Z(rgmii_eth_tx_data[1])
3291 );
3292
3293 DELAYG #(
3294         .DEL_MODE("SCLK_ALIGNED"),
3295         .DEL_VALUE(1'd0)
3296 ) DELAYG_4 (
3297         .A(main_maccore_ethphy_tx_data_oddrx1f[2]),
3298         .Z(rgmii_eth_tx_data[2])
3299 );
3300
3301 DELAYG #(
3302         .DEL_MODE("SCLK_ALIGNED"),
3303         .DEL_VALUE(1'd0)
3304 ) DELAYG_5 (
3305         .A(main_maccore_ethphy_tx_data_oddrx1f[3]),
3306         .Z(rgmii_eth_tx_data[3])
3307 );
3308
3309 DELAYG #(
3310         .DEL_MODE("SCLK_ALIGNED"),
3311         .DEL_VALUE(7'd80)
3312 ) DELAYG_6 (
3313         .A(rgmii_eth_rx_ctl),
3314         .Z(main_maccore_ethphy_rx_ctl_delayf)
3315 );
3316
3317 DELAYG #(
3318         .DEL_MODE("SCLK_ALIGNED"),
3319         .DEL_VALUE(7'd80)
3320 ) DELAYG_7 (
3321         .A(rgmii_eth_rx_data[0]),
3322         .Z(main_maccore_ethphy_rx_data_delayf[0])
3323 );
3324
3325 DELAYG #(
3326         .DEL_MODE("SCLK_ALIGNED"),
3327         .DEL_VALUE(7'd80)
3328 ) DELAYG_8 (
3329         .A(rgmii_eth_rx_data[1]),
3330         .Z(main_maccore_ethphy_rx_data_delayf[1])
3331 );
3332
3333 DELAYG #(
3334         .DEL_MODE("SCLK_ALIGNED"),
3335         .DEL_VALUE(7'd80)
3336 ) DELAYG_9 (
3337         .A(rgmii_eth_rx_data[2]),
3338         .Z(main_maccore_ethphy_rx_data_delayf[2])
3339 );
3340
3341 DELAYG #(
3342         .DEL_MODE("SCLK_ALIGNED"),
3343         .DEL_VALUE(7'd80)
3344 ) DELAYG_10 (
3345         .A(rgmii_eth_rx_data[3]),
3346         .Z(main_maccore_ethphy_rx_data_delayf[3])
3347 );
3348
3349 assign rgmii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz;
3350 assign main_maccore_ethphy_data_r = rgmii_eth_mdio;
3351
3352 //------------------------------------------------------------------------------
3353 // Memory storage: 5-words x 12-bit
3354 //------------------------------------------------------------------------------
3355 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 12
3356 // Port 1 | Read: Async | Write: ---- |
3357 reg [11:0] storage[0:4];
3358 reg [11:0] storage_dat0;
3359 always @(posedge eth_rx_clk) begin
3360         if (main_liteethmaccrc32checker_syncfifo_wrport_we)
3361                 storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w;
3362         storage_dat0 <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr];
3363 end
3364 always @(posedge eth_rx_clk) begin
3365 end
3366 assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_dat0;
3367 assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr];
3368
3369
3370 //------------------------------------------------------------------------------
3371 // Memory storage_1: 32-words x 42-bit
3372 //------------------------------------------------------------------------------
3373 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 42
3374 // Port 1 | Read: Sync  | Write: ---- |
3375 reg [41:0] storage_1[0:31];
3376 reg [41:0] storage_1_dat0;
3377 reg [41:0] storage_1_dat1;
3378 always @(posedge sys_clk) begin
3379         if (main_tx_cdc_cdc_wrport_we)
3380                 storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w;
3381         storage_1_dat0 <= storage_1[main_tx_cdc_cdc_wrport_adr];
3382 end
3383 always @(posedge eth_tx_clk) begin
3384         storage_1_dat1 <= storage_1[main_tx_cdc_cdc_rdport_adr];
3385 end
3386 assign main_tx_cdc_cdc_wrport_dat_r = storage_1_dat0;
3387 assign main_tx_cdc_cdc_rdport_dat_r = storage_1_dat1;
3388
3389
3390 //------------------------------------------------------------------------------
3391 // Memory storage_2: 32-words x 42-bit
3392 //------------------------------------------------------------------------------
3393 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 42
3394 // Port 1 | Read: Sync  | Write: ---- |
3395 reg [41:0] storage_2[0:31];
3396 reg [41:0] storage_2_dat0;
3397 reg [41:0] storage_2_dat1;
3398 always @(posedge eth_rx_clk) begin
3399         if (main_rx_cdc_cdc_wrport_we)
3400                 storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w;
3401         storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr];
3402 end
3403 always @(posedge sys_clk) begin
3404         storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr];
3405 end
3406 assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0;
3407 assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1;
3408
3409
3410 //------------------------------------------------------------------------------
3411 // Memory storage_3: 2-words x 35-bit
3412 //------------------------------------------------------------------------------
3413 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 35
3414 // Port 1 | Read: Async | Write: ---- |
3415 reg [34:0] storage_3[0:1];
3416 reg [34:0] storage_3_dat0;
3417 always @(posedge sys_clk) begin
3418         if (main_writer_stat_fifo_wrport_we)
3419                 storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w;
3420         storage_3_dat0 <= storage_3[main_writer_stat_fifo_wrport_adr];
3421 end
3422 always @(posedge sys_clk) begin
3423 end
3424 assign main_writer_stat_fifo_wrport_dat_r = storage_3_dat0;
3425 assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
3426
3427
3428 //------------------------------------------------------------------------------
3429 // Memory storage_4: 2-words x 14-bit
3430 //------------------------------------------------------------------------------
3431 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 14
3432 // Port 1 | Read: Async | Write: ---- |
3433 reg [13:0] storage_4[0:1];
3434 reg [13:0] storage_4_dat0;
3435 always @(posedge sys_clk) begin
3436         if (main_reader_cmd_fifo_wrport_we)
3437                 storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
3438         storage_4_dat0 <= storage_4[main_reader_cmd_fifo_wrport_adr];
3439 end
3440 always @(posedge sys_clk) begin
3441 end
3442 assign main_reader_cmd_fifo_wrport_dat_r = storage_4_dat0;
3443 assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
3444
3445
3446 //------------------------------------------------------------------------------
3447 // Memory mem_grain0: 383-words x 8-bit
3448 //------------------------------------------------------------------------------
3449 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3450 // Port 1 | Read: Sync  | Write: ---- |
3451 reg [7:0] mem_grain0[0:382];
3452 reg [8:0] mem_grain0_adr0;
3453 reg [7:0] mem_grain0_dat1;
3454 always @(posedge sys_clk) begin
3455         if (main_writer_memory0_we)
3456                 mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
3457         mem_grain0_adr0 <= main_writer_memory0_adr;
3458 end
3459 always @(posedge sys_clk) begin
3460         mem_grain0_dat1 <= mem_grain0[main_sram0_adr0];
3461 end
3462 assign main_writer_memory0_dat_r[7:0] = mem_grain0[mem_grain0_adr0];
3463 assign main_sram0_dat_r0[7:0] = mem_grain0_dat1;
3464
3465
3466 //------------------------------------------------------------------------------
3467 // Memory mem_grain1: 383-words x 8-bit
3468 //------------------------------------------------------------------------------
3469 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3470 // Port 1 | Read: Sync  | Write: ---- |
3471 reg [7:0] mem_grain1[0:382];
3472 reg [8:0] mem_grain1_adr0;
3473 reg [7:0] mem_grain1_dat1;
3474 always @(posedge sys_clk) begin
3475         if (main_writer_memory0_we)
3476                 mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
3477         mem_grain1_adr0 <= main_writer_memory0_adr;
3478 end
3479 always @(posedge sys_clk) begin
3480         mem_grain1_dat1 <= mem_grain1[main_sram0_adr0];
3481 end
3482 assign main_writer_memory0_dat_r[15:8] = mem_grain1[mem_grain1_adr0];
3483 assign main_sram0_dat_r0[15:8] = mem_grain1_dat1;
3484
3485
3486 //------------------------------------------------------------------------------
3487 // Memory mem_grain2: 383-words x 8-bit
3488 //------------------------------------------------------------------------------
3489 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3490 // Port 1 | Read: Sync  | Write: ---- |
3491 reg [7:0] mem_grain2[0:382];
3492 reg [8:0] mem_grain2_adr0;
3493 reg [7:0] mem_grain2_dat1;
3494 always @(posedge sys_clk) begin
3495         if (main_writer_memory0_we)
3496                 mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
3497         mem_grain2_adr0 <= main_writer_memory0_adr;
3498 end
3499 always @(posedge sys_clk) begin
3500         mem_grain2_dat1 <= mem_grain2[main_sram0_adr0];
3501 end
3502 assign main_writer_memory0_dat_r[23:16] = mem_grain2[mem_grain2_adr0];
3503 assign main_sram0_dat_r0[23:16] = mem_grain2_dat1;
3504
3505
3506 //------------------------------------------------------------------------------
3507 // Memory mem_grain3: 383-words x 8-bit
3508 //------------------------------------------------------------------------------
3509 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3510 // Port 1 | Read: Sync  | Write: ---- |
3511 reg [7:0] mem_grain3[0:382];
3512 reg [8:0] mem_grain3_adr0;
3513 reg [7:0] mem_grain3_dat1;
3514 always @(posedge sys_clk) begin
3515         if (main_writer_memory0_we)
3516                 mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
3517         mem_grain3_adr0 <= main_writer_memory0_adr;
3518 end
3519 always @(posedge sys_clk) begin
3520         mem_grain3_dat1 <= mem_grain3[main_sram0_adr0];
3521 end
3522 assign main_writer_memory0_dat_r[31:24] = mem_grain3[mem_grain3_adr0];
3523 assign main_sram0_dat_r0[31:24] = mem_grain3_dat1;
3524
3525
3526 //------------------------------------------------------------------------------
3527 // Memory mem_grain0_1: 383-words x 8-bit
3528 //------------------------------------------------------------------------------
3529 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3530 // Port 1 | Read: Sync  | Write: ---- |
3531 reg [7:0] mem_grain0_1[0:382];
3532 reg [8:0] mem_grain0_1_adr0;
3533 reg [7:0] mem_grain0_1_dat1;
3534 always @(posedge sys_clk) begin
3535         if (main_writer_memory1_we)
3536                 mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
3537         mem_grain0_1_adr0 <= main_writer_memory1_adr;
3538 end
3539 always @(posedge sys_clk) begin
3540         mem_grain0_1_dat1 <= mem_grain0_1[main_sram1_adr0];
3541 end
3542 assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[mem_grain0_1_adr0];
3543 assign main_sram1_dat_r0[7:0] = mem_grain0_1_dat1;
3544
3545
3546 //------------------------------------------------------------------------------
3547 // Memory mem_grain1_1: 383-words x 8-bit
3548 //------------------------------------------------------------------------------
3549 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3550 // Port 1 | Read: Sync  | Write: ---- |
3551 reg [7:0] mem_grain1_1[0:382];
3552 reg [8:0] mem_grain1_1_adr0;
3553 reg [7:0] mem_grain1_1_dat1;
3554 always @(posedge sys_clk) begin
3555         if (main_writer_memory1_we)
3556                 mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
3557         mem_grain1_1_adr0 <= main_writer_memory1_adr;
3558 end
3559 always @(posedge sys_clk) begin
3560         mem_grain1_1_dat1 <= mem_grain1_1[main_sram1_adr0];
3561 end
3562 assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[mem_grain1_1_adr0];
3563 assign main_sram1_dat_r0[15:8] = mem_grain1_1_dat1;
3564
3565
3566 //------------------------------------------------------------------------------
3567 // Memory mem_grain2_1: 383-words x 8-bit
3568 //------------------------------------------------------------------------------
3569 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3570 // Port 1 | Read: Sync  | Write: ---- |
3571 reg [7:0] mem_grain2_1[0:382];
3572 reg [8:0] mem_grain2_1_adr0;
3573 reg [7:0] mem_grain2_1_dat1;
3574 always @(posedge sys_clk) begin
3575         if (main_writer_memory1_we)
3576                 mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
3577         mem_grain2_1_adr0 <= main_writer_memory1_adr;
3578 end
3579 always @(posedge sys_clk) begin
3580         mem_grain2_1_dat1 <= mem_grain2_1[main_sram1_adr0];
3581 end
3582 assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[mem_grain2_1_adr0];
3583 assign main_sram1_dat_r0[23:16] = mem_grain2_1_dat1;
3584
3585
3586 //------------------------------------------------------------------------------
3587 // Memory mem_grain3_1: 383-words x 8-bit
3588 //------------------------------------------------------------------------------
3589 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3590 // Port 1 | Read: Sync  | Write: ---- |
3591 reg [7:0] mem_grain3_1[0:382];
3592 reg [8:0] mem_grain3_1_adr0;
3593 reg [7:0] mem_grain3_1_dat1;
3594 always @(posedge sys_clk) begin
3595         if (main_writer_memory1_we)
3596                 mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
3597         mem_grain3_1_adr0 <= main_writer_memory1_adr;
3598 end
3599 always @(posedge sys_clk) begin
3600         mem_grain3_1_dat1 <= mem_grain3_1[main_sram1_adr0];
3601 end
3602 assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[mem_grain3_1_adr0];
3603 assign main_sram1_dat_r0[31:24] = mem_grain3_1_dat1;
3604
3605
3606 //------------------------------------------------------------------------------
3607 // Memory mem_grain0_2: 383-words x 8-bit
3608 //------------------------------------------------------------------------------
3609 // Port 0 | Read: Sync  | Write: ---- |
3610 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3611 reg [7:0] mem_grain0_2[0:382];
3612 reg [8:0] mem_grain0_2_adr0;
3613 reg [8:0] mem_grain0_2_adr1;
3614 always @(posedge sys_clk) begin
3615         mem_grain0_2_adr0 <= main_reader_memory0_adr;
3616 end
3617 always @(posedge sys_clk) begin
3618         if (main_sram0_we[0])
3619                 mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
3620         mem_grain0_2_adr1 <= main_sram0_adr1;
3621 end
3622 assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[mem_grain0_2_adr0];
3623 assign main_sram0_dat_r1[7:0] = mem_grain0_2[mem_grain0_2_adr1];
3624
3625
3626 //------------------------------------------------------------------------------
3627 // Memory mem_grain1_2: 383-words x 8-bit
3628 //------------------------------------------------------------------------------
3629 // Port 0 | Read: Sync  | Write: ---- |
3630 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3631 reg [7:0] mem_grain1_2[0:382];
3632 reg [8:0] mem_grain1_2_adr0;
3633 reg [8:0] mem_grain1_2_adr1;
3634 always @(posedge sys_clk) begin
3635         mem_grain1_2_adr0 <= main_reader_memory0_adr;
3636 end
3637 always @(posedge sys_clk) begin
3638         if (main_sram0_we[1])
3639                 mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
3640         mem_grain1_2_adr1 <= main_sram0_adr1;
3641 end
3642 assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[mem_grain1_2_adr0];
3643 assign main_sram0_dat_r1[15:8] = mem_grain1_2[mem_grain1_2_adr1];
3644
3645
3646 //------------------------------------------------------------------------------
3647 // Memory mem_grain2_2: 383-words x 8-bit
3648 //------------------------------------------------------------------------------
3649 // Port 0 | Read: Sync  | Write: ---- |
3650 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3651 reg [7:0] mem_grain2_2[0:382];
3652 reg [8:0] mem_grain2_2_adr0;
3653 reg [8:0] mem_grain2_2_adr1;
3654 always @(posedge sys_clk) begin
3655         mem_grain2_2_adr0 <= main_reader_memory0_adr;
3656 end
3657 always @(posedge sys_clk) begin
3658         if (main_sram0_we[2])
3659                 mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
3660         mem_grain2_2_adr1 <= main_sram0_adr1;
3661 end
3662 assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[mem_grain2_2_adr0];
3663 assign main_sram0_dat_r1[23:16] = mem_grain2_2[mem_grain2_2_adr1];
3664
3665
3666 //------------------------------------------------------------------------------
3667 // Memory mem_grain3_2: 383-words x 8-bit
3668 //------------------------------------------------------------------------------
3669 // Port 0 | Read: Sync  | Write: ---- |
3670 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3671 reg [7:0] mem_grain3_2[0:382];
3672 reg [8:0] mem_grain3_2_adr0;
3673 reg [8:0] mem_grain3_2_adr1;
3674 always @(posedge sys_clk) begin
3675         mem_grain3_2_adr0 <= main_reader_memory0_adr;
3676 end
3677 always @(posedge sys_clk) begin
3678         if (main_sram0_we[3])
3679                 mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
3680         mem_grain3_2_adr1 <= main_sram0_adr1;
3681 end
3682 assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[mem_grain3_2_adr0];
3683 assign main_sram0_dat_r1[31:24] = mem_grain3_2[mem_grain3_2_adr1];
3684
3685
3686 //------------------------------------------------------------------------------
3687 // Memory mem_grain0_3: 383-words x 8-bit
3688 //------------------------------------------------------------------------------
3689 // Port 0 | Read: Sync  | Write: ---- |
3690 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3691 reg [7:0] mem_grain0_3[0:382];
3692 reg [8:0] mem_grain0_3_adr0;
3693 reg [8:0] mem_grain0_3_adr1;
3694 always @(posedge sys_clk) begin
3695         mem_grain0_3_adr0 <= main_reader_memory1_adr;
3696 end
3697 always @(posedge sys_clk) begin
3698         if (main_sram1_we[0])
3699                 mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
3700         mem_grain0_3_adr1 <= main_sram1_adr1;
3701 end
3702 assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[mem_grain0_3_adr0];
3703 assign main_sram1_dat_r1[7:0] = mem_grain0_3[mem_grain0_3_adr1];
3704
3705
3706 //------------------------------------------------------------------------------
3707 // Memory mem_grain1_3: 383-words x 8-bit
3708 //------------------------------------------------------------------------------
3709 // Port 0 | Read: Sync  | Write: ---- |
3710 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3711 reg [7:0] mem_grain1_3[0:382];
3712 reg [8:0] mem_grain1_3_adr0;
3713 reg [8:0] mem_grain1_3_adr1;
3714 always @(posedge sys_clk) begin
3715         mem_grain1_3_adr0 <= main_reader_memory1_adr;
3716 end
3717 always @(posedge sys_clk) begin
3718         if (main_sram1_we[1])
3719                 mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
3720         mem_grain1_3_adr1 <= main_sram1_adr1;
3721 end
3722 assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[mem_grain1_3_adr0];
3723 assign main_sram1_dat_r1[15:8] = mem_grain1_3[mem_grain1_3_adr1];
3724
3725
3726 //------------------------------------------------------------------------------
3727 // Memory mem_grain2_3: 383-words x 8-bit
3728 //------------------------------------------------------------------------------
3729 // Port 0 | Read: Sync  | Write: ---- |
3730 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3731 reg [7:0] mem_grain2_3[0:382];
3732 reg [8:0] mem_grain2_3_adr0;
3733 reg [8:0] mem_grain2_3_adr1;
3734 always @(posedge sys_clk) begin
3735         mem_grain2_3_adr0 <= main_reader_memory1_adr;
3736 end
3737 always @(posedge sys_clk) begin
3738         if (main_sram1_we[2])
3739                 mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
3740         mem_grain2_3_adr1 <= main_sram1_adr1;
3741 end
3742 assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[mem_grain2_3_adr0];
3743 assign main_sram1_dat_r1[23:16] = mem_grain2_3[mem_grain2_3_adr1];
3744
3745
3746 //------------------------------------------------------------------------------
3747 // Memory mem_grain3_3: 383-words x 8-bit
3748 //------------------------------------------------------------------------------
3749 // Port 0 | Read: Sync  | Write: ---- |
3750 // Port 1 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8
3751 reg [7:0] mem_grain3_3[0:382];
3752 reg [8:0] mem_grain3_3_adr0;
3753 reg [8:0] mem_grain3_3_adr1;
3754 always @(posedge sys_clk) begin
3755         mem_grain3_3_adr0 <= main_reader_memory1_adr;
3756 end
3757 always @(posedge sys_clk) begin
3758         if (main_sram1_we[3])
3759                 mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
3760         mem_grain3_3_adr1 <= main_sram1_adr1;
3761 end
3762 assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[mem_grain3_3_adr0];
3763 assign main_sram1_dat_r1[31:24] = mem_grain3_3[mem_grain3_3_adr1];
3764
3765
3766 ODDRX1F ODDRX1F(
3767         .D0(1'd1),
3768         .D1(1'd0),
3769         .SCLK(eth_tx_clk),
3770         .Q(main_maccore_ethphy_eth_tx_clk_o)
3771 );
3772
3773 FD1S3BX FD1S3BX(
3774         .CK(eth_tx_clk),
3775         .D(1'd0),
3776         .PD(main_maccore_ethphy_reset),
3777         .Q(builder_rst10)
3778 );
3779
3780 FD1S3BX FD1S3BX_1(
3781         .CK(eth_tx_clk),
3782         .D(builder_rst10),
3783         .PD(main_maccore_ethphy_reset),
3784         .Q(eth_tx_rst)
3785 );
3786
3787 FD1S3BX FD1S3BX_2(
3788         .CK(eth_rx_clk),
3789         .D(1'd0),
3790         .PD(main_maccore_ethphy_reset),
3791         .Q(builder_rst11)
3792 );
3793
3794 FD1S3BX FD1S3BX_3(
3795         .CK(eth_rx_clk),
3796         .D(builder_rst11),
3797         .PD(main_maccore_ethphy_reset),
3798         .Q(eth_rx_rst)
3799 );
3800
3801 ODDRX1F ODDRX1F_1(
3802         .D0(main_maccore_ethphy_sink_valid),
3803         .D1(main_maccore_ethphy_sink_valid),
3804         .SCLK(eth_tx_clk),
3805         .Q(main_maccore_ethphy_tx_ctl_oddrx1f)
3806 );
3807
3808 ODDRX1F ODDRX1F_2(
3809         .D0(main_maccore_ethphy_sink_payload_data[0]),
3810         .D1(main_maccore_ethphy_sink_payload_data[4]),
3811         .SCLK(eth_tx_clk),
3812         .Q(main_maccore_ethphy_tx_data_oddrx1f[0])
3813 );
3814
3815 ODDRX1F ODDRX1F_3(
3816         .D0(main_maccore_ethphy_sink_payload_data[1]),
3817         .D1(main_maccore_ethphy_sink_payload_data[5]),
3818         .SCLK(eth_tx_clk),
3819         .Q(main_maccore_ethphy_tx_data_oddrx1f[1])
3820 );
3821
3822 ODDRX1F ODDRX1F_4(
3823         .D0(main_maccore_ethphy_sink_payload_data[2]),
3824         .D1(main_maccore_ethphy_sink_payload_data[6]),
3825         .SCLK(eth_tx_clk),
3826         .Q(main_maccore_ethphy_tx_data_oddrx1f[2])
3827 );
3828
3829 ODDRX1F ODDRX1F_5(
3830         .D0(main_maccore_ethphy_sink_payload_data[3]),
3831         .D1(main_maccore_ethphy_sink_payload_data[7]),
3832         .SCLK(eth_tx_clk),
3833         .Q(main_maccore_ethphy_tx_data_oddrx1f[3])
3834 );
3835
3836 IDDRX1F IDDRX1F(
3837         .D(main_maccore_ethphy_rx_ctl_delayf),
3838         .SCLK(eth_rx_clk),
3839         .Q0(main_maccore_ethphy_rx_ctl[0]),
3840         .Q1(main_maccore_ethphy_rx_ctl[1])
3841 );
3842
3843 IDDRX1F IDDRX1F_1(
3844         .D(main_maccore_ethphy_rx_data_delayf[0]),
3845         .SCLK(eth_rx_clk),
3846         .Q0(main_maccore_ethphy_rx_data[0]),
3847         .Q1(main_maccore_ethphy_rx_data[4])
3848 );
3849
3850 IDDRX1F IDDRX1F_2(
3851         .D(main_maccore_ethphy_rx_data_delayf[1]),
3852         .SCLK(eth_rx_clk),
3853         .Q0(main_maccore_ethphy_rx_data[1]),
3854         .Q1(main_maccore_ethphy_rx_data[5])
3855 );
3856
3857 IDDRX1F IDDRX1F_3(
3858         .D(main_maccore_ethphy_rx_data_delayf[2]),
3859         .SCLK(eth_rx_clk),
3860         .Q0(main_maccore_ethphy_rx_data[2]),
3861         .Q1(main_maccore_ethphy_rx_data[6])
3862 );
3863
3864 IDDRX1F IDDRX1F_4(
3865         .D(main_maccore_ethphy_rx_data_delayf[3]),
3866         .SCLK(eth_rx_clk),
3867         .Q0(main_maccore_ethphy_rx_data[3]),
3868         .Q1(main_maccore_ethphy_rx_data[7])
3869 );
3870
3871 endmodule
3872
3873 // -----------------------------------------------------------------------------
3874 //  Auto-Generated by LiteX on 2022-02-22 13:54:55.
3875 //------------------------------------------------------------------------------