litex/boards/platforms/arty.py

   1 # This file is Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
   2 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # License: BSD
   4
   5 from litex.build.generic_platform import *
   6 from litex.build.xilinx import XilinxPlatform
   7 from litex.build.openocd import OpenOCD
   8
   9 # IOs ----------------------------------------------------------------------------------------------
  10
  11 _io = [
  12     ("user_led", 0, Pins("H5"),  IOStandard("LVCMOS33")),
  13     ("user_led", 1, Pins("J5"),  IOStandard("LVCMOS33")),
  14     ("user_led", 2, Pins("T9"),  IOStandard("LVCMOS33")),
  15     ("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
  16
  17     ("rgb_led", 0,
  18         Subsignal("r", Pins("G6")),
  19         Subsignal("g", Pins("F6")),
  20         Subsignal("b", Pins("E1")),
  21         IOStandard("LVCMOS33"),
  22     ),
  23
  24     ("rgb_led", 1,
  25         Subsignal("r", Pins("G3")),
  26         Subsignal("g", Pins("J4")),
  27         Subsignal("b", Pins("G4")),
  28         IOStandard("LVCMOS33"),
  29     ),
  30
  31     ("rgb_led", 2,
  32         Subsignal("r", Pins("J3")),
  33         Subsignal("g", Pins("J2")),
  34         Subsignal("b", Pins("H4")),
  35         IOStandard("LVCMOS33"),
  36     ),
  37
  38     ("rgb_led", 3,
  39         Subsignal("r", Pins("K1")),
  40         Subsignal("g", Pins("H6")),
  41         Subsignal("b", Pins("K2")),
  42         IOStandard("LVCMOS33"),
  43     ),
  44
  45     ("user_sw", 0, Pins("A8"),  IOStandard("LVCMOS33")),
  46     ("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
  47     ("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
  48     ("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
  49
  50     ("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
  51     ("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
  52     ("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
  53     ("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
  54
  55     ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
  56
  57     ("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
  58
  59     ("serial", 0,
  60         Subsignal("tx", Pins("D10")),
  61         Subsignal("rx", Pins("A9")),
  62         IOStandard("LVCMOS33")
  63     ),
  64
  65     ("spi", 0,
  66         Subsignal("clk",  Pins("F1")),
  67         Subsignal("cs_n", Pins("C1")),
  68         Subsignal("mosi", Pins("H1")),
  69         Subsignal("miso", Pins("G1")),
  70         IOStandard("LVCMOS33"),
  71     ),
  72
  73     ("i2c", 0,
  74         Subsignal("scl", Pins("L18")),
  75         Subsignal("sda", Pins("M18")),
  76         Subsignal("scl_pup", Pins("A14")),
  77         Subsignal("sda_pup", Pins("A13")),
  78         IOStandard("LVCMOS33"),
  79     ),
  80
  81     ("spiflash4x", 0,
  82         Subsignal("cs_n", Pins("L13")),
  83         Subsignal("clk",  Pins("L16")),
  84         Subsignal("dq",   Pins("K17", "K18", "L14", "M14")),
  85         IOStandard("LVCMOS33")
  86     ),
  87     ("spiflash", 0,
  88         Subsignal("cs_n", Pins("L13")),
  89         Subsignal("clk",  Pins("L16")),
  90         Subsignal("mosi", Pins("K17")),
  91         Subsignal("miso", Pins("K18")),
  92         Subsignal("wp",   Pins("L14")),
  93         Subsignal("hold", Pins("M14")),
  94         IOStandard("LVCMOS33"),
  95     ),
  96
  97     ("ddram", 0,
  98         Subsignal("a", Pins(
  99             "R2 M6 N4 T1 N6 R7 V6 U7",
 100             "R8 V7 R6 U6 T6 T8"),
 101             IOStandard("SSTL135")),
 102         Subsignal("ba",    Pins("R1 P4 P2"), IOStandard("SSTL135")),
 103         Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
 104         Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
 105         Subsignal("we_n",  Pins("P5"), IOStandard("SSTL135")),
 106         Subsignal("cs_n",  Pins("U8"), IOStandard("SSTL135")),
 107         Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")),
 108         Subsignal("dq", Pins(
 109             "K5 L3 K3 L6 M3 M1 L4 M2",
 110             "V4 T5 U4 V5 V1 T3 U3 R3"),
 111             IOStandard("SSTL135"),
 112             Misc("IN_TERM=UNTUNED_SPLIT_40")),
 113         Subsignal("dqs_p", Pins("N2 U2"),
 114             IOStandard("DIFF_SSTL135"),
 115             Misc("IN_TERM=UNTUNED_SPLIT_40")),
 116         Subsignal("dqs_n", Pins("N1 V2"),
 117             IOStandard("DIFF_SSTL135"),
 118             Misc("IN_TERM=UNTUNED_SPLIT_40")),
 119         Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
 120         Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
 121         Subsignal("cke",   Pins("N5"), IOStandard("SSTL135")),
 122         Subsignal("odt",   Pins("R5"), IOStandard("SSTL135")),
 123         Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
 124         Misc("SLEW=FAST"),
 125     ),
 126
 127     ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
 128     ("eth_clocks", 0,
 129         Subsignal("tx", Pins("H16")),
 130         Subsignal("rx", Pins("F15")),
 131         IOStandard("LVCMOS33"),
 132     ),
 133     ("eth", 0,
 134         Subsignal("rst_n",   Pins("C16")),
 135         Subsignal("mdio",    Pins("K13")),
 136         Subsignal("mdc",     Pins("F16")),
 137         Subsignal("rx_dv",   Pins("G16")),
 138         Subsignal("rx_er",   Pins("C17")),
 139         Subsignal("rx_data", Pins("D18 E17 E18 G17")),
 140         Subsignal("tx_en",   Pins("H15")),
 141         Subsignal("tx_data", Pins("H14 J14 J13 H17")),
 142         Subsignal("col",     Pins("D17")),
 143         Subsignal("crs",     Pins("G14")),
 144         IOStandard("LVCMOS33"),
 145     ),
 146 ]
 147
 148 # Connectors ---------------------------------------------------------------------------------------
 149
 150 _connectors = [
 151     ("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
 152     ("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
 153     ("pmodc", "U12 V12 V10 V11 U14 V14 T13 U13"),
 154     ("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"),
 155     ("ck_io", {
 156         # Outer Digital Header
 157         "ck_io0"  : "V15",
 158         "ck_io1"  : "U16",
 159         "ck_io2"  : "P14",
 160         "ck_io3"  : "T11",
 161         "ck_io4"  : "R12",
 162         "ck_io5"  : "T14",
 163         "ck_io6"  : "T15",
 164         "ck_io7"  : "T16",
 165         "ck_io8"  : "N15",
 166         "ck_io9"  : "M16",
 167         "ck_io10" : "V17",
 168         "ck_io11" : "U18",
 169         "ck_io12" : "R17",
 170         "ck_io13" : "P17",
 171
 172         # Inner Digital Header
 173         "ck_io26" : "U11",
 174         "ck_io27" : "V16",
 175         "ck_io28" : "M13",
 176         "ck_io29" : "R10",
 177         "ck_io30" : "R11",
 178         "ck_io31" : "R13",
 179         "ck_io32" : "R15",
 180         "ck_io33" : "P15",
 181         "ck_io34" : "R16",
 182         "ck_io35" : "N16",
 183         "ck_io36" : "N14",
 184         "ck_io37" : "U17",
 185         "ck_io38" : "T18",
 186         "ck_io39" : "R18",
 187         "ck_io40" : "P18",
 188         "ck_io41" : "N17",
 189
 190         # Outer Analog Header as Digital IO
 191         "ck_a0" : "F5",
 192         "ck_a1" : "D8",
 193         "ck_a2" : "C7",
 194         "ck_a3" : "E7",
 195         "ck_a4" : "D7",
 196         "ck_a5" : "D5",
 197
 198         # Inner Analog Header as Digital IO
 199         "ck_io20" : "B7",
 200         "ck_io21" : "B6",
 201         "ck_io22" : "E6",
 202         "ck_io23" : "E5",
 203         "ck_io24" : "A4",
 204         "ck_io25" : "A3",
 205         } ),
 206     ("XADC", {
 207         # Outer Analog Header
 208         "vaux4_n"  : "C5",
 209         "vaux4_p"  : "C6",
 210         "vaux5_n"  : "A5",
 211         "vaux5_p"  : "A6",
 212         "vaux6_n"  : "B4",
 213         "vaux6_p"  : "C4",
 214         "vaux7_n"  : "A1",
 215         "vaux7_p"  : "B1",
 216         "vaux15_n" : "B2",
 217         "vaux15_p" : "B3",
 218         "vaux0_n"  : "C14",
 219         "vaux0_p"  : "D14",
 220
 221         # Inner Analog Header
 222         "vaux12_n" : "B7",
 223         "vaux12_p" : "B6",
 224         "vaux13_n" : "E6",
 225         "vaux13_p" : "E5",
 226         "vaux14_n" : "A4",
 227         "vaux14_p" : "A3",
 228
 229         # Power Measurements
 230         "vsnsuv_n"   : "B17",
 231         "vsnsuv_p"   : "B16",
 232         "vsns5v0_n"  : "B12",
 233         "vsns5v0_p"  : "C12",
 234         "isns5v0_n"  : "F14",
 235         "isns5v0_n"  : "F13",
 236         "isns0v95_n" : "A16",
 237         "isns0v95_n" : "A15",
 238         } ),
 239 ]
 240
 241 # PMODS --------------------------------------------------------------------------------------------
 242
 243 def usb_pmod_io(pmod):
 244     return [
 245         # USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
 246         ("usb_uart", 0,
 247             Subsignal("tx", Pins(f"{pmod}:1")),
 248             Subsignal("rx", Pins(f"{pmod}:2")),
 249             IOStandard("LVCMOS33")
 250         ),
 251     ]
 252 _usb_uart_pmod_io = usb_pmod_io("pmodb") # USB-UART PMOD on JB.
 253
 254
 255 def i2s_pmod_io(pmod):
 256     return [
 257         # I2S PMOD: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
 258         ("i2s_rx_mclk", 0, Pins(f"{pmod}:4"), IOStandard("LVCMOS33")),
 259         ("i2s_rx", 0,
 260             Subsignal("clk", Pins(f"{pmod}:6")),
 261             Subsignal("sync", Pins(f"{pmod}:5")),
 262             Subsignal("rx", Pins(f"{pmod}:7")),
 263             IOStandard("LVCMOS33"),
 264         ),
 265         ("i2s_tx_mclk", 0, Pins(f"{pmod}:0"), IOStandard("LVCMOS33")),
 266         ("i2s_tx", 0,
 267             Subsignal("clk",Pins(f"{pmod}:2")),
 268             Subsignal("sync", Pins(f"{pmod}:1")),
 269             Subsignal("tx", Pins(f"{pmod}:3")),
 270             IOStandard("LVCMOS33"),
 271         ),
 272     ]
 273 _i2s_pmod_io = i2s_pmod_io("pmoda") # I2S PMOD on JA.
 274
 275 def sdcard_pmod_io(pmod):
 276     return [
 277         # SDCard PMOD:
 278         # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
 279         # - https://github.com/antmicro/arty-expansion-board
 280         ("spisdcard", 0,
 281             Subsignal("clk",  Pins(f"{pmod}:3")),
 282             Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
 283             Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
 284             Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
 285             Misc("SLEW=FAST"),
 286             IOStandard("LVCMOS33"),
 287         ),
 288         ("sdcard", 0,
 289             Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
 290             Subsignal("cmd",  Pins(f"{pmod}:1"), Misc("PULLUP True")),
 291             Subsignal("clk",  Pins(f"{pmod}:3")),
 292             Subsignal("cd",   Pins(f"{pmod}:6")),
 293             Misc("SLEW=FAST"),
 294             IOStandard("LVCMOS33"),
 295         ),
 296 ]
 297 _sdcard_pmod_io = sdcard_pmod_io("pmodd") # SDCARD PMOD on JD.
 298
 299 # Platform -----------------------------------------------------------------------------------------
 300
 301 class Platform(XilinxPlatform):
 302     default_clk_name   = "clk100"
 303     default_clk_period = 1e9/100e6
 304
 305     def __init__(self, variant="a7-35", toolchain="vivado"):
 306         device = {
 307             "a7-35":  "xc7a35ticsg324-1L",
 308             "a7-100": "xc7a100tcsg324-1"
 309         }[variant]
 310         XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 311         self.toolchain.bitstream_commands = \
 312             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 313         self.toolchain.additional_commands = \
 314             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
 315              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 316         if toolchain == "vivado": # FIXME
 317             self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
 318
 319     def create_programmer(self):
 320         bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
 321         return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
 322
 323     def do_finalize(self, fragment):
 324         XilinxPlatform.do_finalize(self, fragment)
 325         from litex.build.xilinx import symbiflow
 326         if not isinstance(self.toolchain, symbiflow.SymbiflowToolchain): # FIXME
 327             self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)