litex/boards/targets/de0nano.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import os
   7 import argparse
   8
   9 from migen import *
  10 from migen.genlib.resetsync import AsyncResetSynchronizer
  11
  12 from litex.build.io import DDROutput
  13
  14 from litex.boards.platforms import de0nano
  15
  16 from litex.soc.cores.clock import CycloneIVPLL
  17 from litex.soc.integration.soc_core import *
  18 from litex.soc.integration.soc_sdram import *
  19 from litex.soc.integration.builder import *
  20 from litex.soc.cores.led import LedChaser
  21
  22 from litedram.modules import IS42S16160
  23 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
  24
  25 # CRG ----------------------------------------------------------------------------------------------
  26
  27 class _CRG(Module):
  28     def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
  29         self.clock_domains.cd_sys    = ClockDomain()
  30         if sdram_rate == "1:2":
  31             self.clock_domains.cd_sys2x    = ClockDomain()
  32             self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
  33         else:
  34             self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  35
  36         # # #
  37
  38         # Clk / Rst
  39         clk50 = platform.request("clk50")
  40
  41         # PLL
  42         self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
  43         pll.register_clkin(clk50, 50e6)
  44         pll.create_clkout(self.cd_sys,    sys_clk_freq)
  45         if sdram_rate == "1:2":
  46             pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
  47             pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
  48         else:
  49             pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
  50
  51         # SDRAM clock
  52         sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
  53         self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
  54
  55 # BaseSoC ------------------------------------------------------------------------------------------
  56
  57 class BaseSoC(SoCCore):
  58     def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
  59         platform = de0nano.Platform()
  60
  61         # SoCCore ----------------------------------------------------------------------------------
  62         SoCCore.__init__(self, platform, sys_clk_freq,
  63             ident          = "LiteX SoC on DE0-Nano",
  64             ident_version  = True,
  65             **kwargs)
  66
  67         # CRG --------------------------------------------------------------------------------------
  68         self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
  69
  70         # SDR SDRAM --------------------------------------------------------------------------------
  71         if not self.integrated_main_ram_size:
  72             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
  73             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
  74             self.add_sdram("sdram",
  75                 phy                     = self.sdrphy,
  76                 module                  = IS42S16160(sys_clk_freq, sdram_rate),
  77                 origin                  = self.mem_map["main_ram"],
  78                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  79                 l2_cache_size           = kwargs.get("l2_size", 8192),
  80                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  81                 l2_cache_reverse        = True
  82             )
  83
  84         # Leds -------------------------------------------------------------------------------------
  85         self.submodules.leds = LedChaser(
  86             pads         = platform.request_all("user_led"),
  87             sys_clk_freq = sys_clk_freq)
  88         self.add_csr("leds")
  89
  90 # Build --------------------------------------------------------------------------------------------
  91
  92 def main():
  93     parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
  94     parser.add_argument("--build", action="store_true", help="Build bitstream")
  95     parser.add_argument("--load",  action="store_true", help="Load bitstream")
  96     parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
  97     builder_args(parser)
  98     soc_sdram_args(parser)
  99     args = parser.parse_args()
 100
 101     soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
 102     builder = Builder(soc, **builder_argdict(args))
 103     builder.build(run=args.build)
 104
 105     if args.load:
 106         prog = soc.platform.create_programmer()
 107         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
 108
 109 if __name__ == "__main__":
 110     main()