litex/boards/targets/kc705.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
   4 # This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # This file is Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
   6 # License: BSD
   7
   8 import os
   9 import argparse
  10
  11 from migen import *
  12
  13 from litex.boards.platforms import kc705
  14
  15 from litex.soc.cores.clock import *
  16 from litex.soc.integration.soc_core import *
  17 from litex.soc.integration.soc_sdram import *
  18 from litex.soc.integration.builder import *
  19 from litex.soc.cores.led import LedChaser
  20
  21 from litedram.modules import MT8JTF12864
  22 from litedram.phy import s7ddrphy
  23
  24 from liteeth.phy import LiteEthPHY
  25
  26 # CRG ----------------------------------------------------------------------------------------------
  27
  28 class _CRG(Module):
  29     def __init__(self, platform, sys_clk_freq):
  30         self.clock_domains.cd_sys    = ClockDomain()
  31         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
  32         self.clock_domains.cd_clk200 = ClockDomain()
  33
  34         # # #
  35
  36         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
  37         self.comb += pll.reset.eq(platform.request("cpu_reset"))
  38         pll.register_clkin(platform.request("clk200"), 200e6)
  39         pll.create_clkout(self.cd_sys,    sys_clk_freq)
  40         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
  41         pll.create_clkout(self.cd_clk200, 200e6)
  42
  43         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  44
  45 # BaseSoC ------------------------------------------------------------------------------------------
  46
  47 class BaseSoC(SoCCore):
  48     def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
  49         platform = kc705.Platform()
  50
  51         # SoCCore ----------------------------------------------------------------------------------
  52         SoCCore.__init__(self, platform, sys_clk_freq,
  53             ident          = "LiteX SoC on KC705",
  54             ident_version  = True,
  55             **kwargs)
  56
  57         # CRG --------------------------------------------------------------------------------------
  58         self.submodules.crg = _CRG(platform, sys_clk_freq)
  59
  60         # DDR3 SDRAM -------------------------------------------------------------------------------
  61         if not self.integrated_main_ram_size:
  62             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
  63                 memtype      = "DDR3",
  64                 nphases      = 4,
  65                 sys_clk_freq = sys_clk_freq,
  66                 cmd_latency  = 1)
  67             self.add_csr("ddrphy")
  68             self.add_sdram("sdram",
  69                 phy                     = self.ddrphy,
  70                 module                  = MT8JTF12864(sys_clk_freq, "1:4"),
  71                 origin                  = self.mem_map["main_ram"],
  72                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  73                 l2_cache_size           = kwargs.get("l2_size", 8192),
  74                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  75                 l2_cache_reverse        = True
  76             )
  77
  78         # Ethernet ---------------------------------------------------------------------------------
  79         if with_ethernet:
  80             self.submodules.ethphy = LiteEthPHY(
  81                 clock_pads = self.platform.request("eth_clocks"),
  82                 pads       = self.platform.request("eth"),
  83                 clk_freq   = self.clk_freq)
  84             self.add_csr("ethphy")
  85             self.add_ethernet(phy=self.ethphy)
  86
  87         # Leds -------------------------------------------------------------------------------------
  88         self.submodules.leds = LedChaser(
  89             pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
  90             sys_clk_freq = sys_clk_freq)
  91         self.add_csr("leds")
  92
  93 # Build --------------------------------------------------------------------------------------------
  94
  95 def main():
  96     parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
  97     parser.add_argument("--build", action="store_true", help="Build bitstream")
  98     parser.add_argument("--load",  action="store_true", help="Load bitstream")
  99     builder_args(parser)
 100     soc_sdram_args(parser)
 101     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
 102     args = parser.parse_args()
 103
 104     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
 105     builder = Builder(soc, **builder_argdict(args))
 106     builder.build(run=args.build)
 107
 108     if args.load:
 109         prog = soc.platform.create_programmer()
 110         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 111
 112 if __name__ == "__main__":
 113     main()