litex/boards/targets/kcu105.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import os
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.boards.platforms import kcu105
  12
  13 from litex.soc.cores.clock import *
  14 from litex.soc.integration.soc_core import *
  15 from litex.soc.integration.soc_sdram import *
  16 from litex.soc.integration.builder import *
  17 from litex.soc.cores.led import LedChaser
  18
  19 from litedram.modules import EDY4016A
  20 from litedram.phy import usddrphy
  21
  22 from liteeth.phy.ku_1000basex import KU_1000BASEX
  23
  24 # CRG ----------------------------------------------------------------------------------------------
  25
  26 class _CRG(Module):
  27     def __init__(self, platform, sys_clk_freq):
  28         self.clock_domains.cd_sys    = ClockDomain()
  29         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
  30         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
  31         self.clock_domains.cd_clk200 = ClockDomain()
  32
  33         # # #
  34
  35         self.submodules.pll = pll = USMMCM(speedgrade=-2)
  36         self.comb += pll.reset.eq(platform.request("cpu_reset"))
  37         pll.register_clkin(platform.request("clk125"), 125e6)
  38         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
  39         pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
  40
  41         self.specials += [
  42             Instance("BUFGCE_DIV", name="main_bufgce_div",
  43                 p_BUFGCE_DIVIDE=4,
  44                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
  45             Instance("BUFGCE", name="main_bufgce",
  46                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
  47             AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
  48         ]
  49
  50         self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys)
  51
  52 # BaseSoC ------------------------------------------------------------------------------------------
  53
  54 class BaseSoC(SoCCore):
  55     def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
  56         platform = kcu105.Platform()
  57
  58         # SoCCore ----------------------------------------------------------------------------------
  59         SoCCore.__init__(self, platform, sys_clk_freq,
  60             ident          = "LiteX SoC on KCU105",
  61             ident_version  = True,
  62             **kwargs)
  63
  64         # CRG --------------------------------------------------------------------------------------
  65         self.submodules.crg = _CRG(platform, sys_clk_freq)
  66
  67         # DDR4 SDRAM -------------------------------------------------------------------------------
  68         if not self.integrated_main_ram_size:
  69             self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
  70                 memtype          = "DDR4",
  71                 sys_clk_freq     = sys_clk_freq,
  72                 iodelay_clk_freq = 200e6,
  73                 cmd_latency      = 1)
  74             self.add_csr("ddrphy")
  75             self.add_sdram("sdram",
  76                 phy                     = self.ddrphy,
  77                 module                  = EDY4016A(sys_clk_freq, "1:4"),
  78                 origin                  = self.mem_map["main_ram"],
  79                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  80                 l2_cache_size           = kwargs.get("l2_size", 8192),
  81                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  82                 l2_cache_reverse        = True
  83             )
  84
  85         # Ethernet ---------------------------------------------------------------------------------
  86         if with_ethernet:
  87             self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
  88                 data_pads    = self.platform.request("sfp", 0),
  89                 sys_clk_freq = self.clk_freq)
  90             self.add_csr("ethphy")
  91             self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
  92             self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
  93             self.add_ethernet(phy=self.ethphy)
  94
  95         # Leds -------------------------------------------------------------------------------------
  96         self.submodules.leds = LedChaser(
  97             pads         = platform.request_all("user_led"),
  98             sys_clk_freq = sys_clk_freq)
  99         self.add_csr("leds")
 100
 101 # Build --------------------------------------------------------------------------------------------
 102
 103 def main():
 104     parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
 105     parser.add_argument("--build", action="store_true", help="Build bitstream")
 106     parser.add_argument("--load",  action="store_true", help="Load bitstream")
 107     builder_args(parser)
 108     soc_sdram_args(parser)
 109     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
 110     args = parser.parse_args()
 111
 112     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
 113     builder = Builder(soc, **builder_argdict(args))
 114     builder.build(run=args.build)
 115
 116     if args.load:
 117         prog = soc.platform.create_programmer()
 118         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 119
 120 if __name__ == "__main__":
 121     main()