litex/boards/targets/minispartan6.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
   4 # This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
   6 # License: BSD
   7
   8 import os
   9 import argparse
  10 from fractions import Fraction
  11
  12 from migen import *
  13 from migen.genlib.resetsync import AsyncResetSynchronizer
  14
  15 from litex.build.io import DDROutput
  16
  17 from litex.boards.platforms import minispartan6
  18
  19 from litex.soc.cores.clock import S6PLL
  20 from litex.soc.integration.soc_core import *
  21 from litex.soc.integration.soc_sdram import *
  22 from litex.soc.integration.builder import *
  23 from litex.soc.cores.led import LedChaser
  24
  25 from litedram.modules import AS4C16M16
  26 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
  27
  28 # CRG ----------------------------------------------------------------------------------------------
  29
  30 class _CRG(Module):
  31     def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
  32         self.clock_domains.cd_sys    = ClockDomain()
  33         if sdram_rate == "1:2":
  34             self.clock_domains.cd_sys2x    = ClockDomain()
  35             self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
  36         else:
  37             self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  38
  39         # # #
  40
  41         # Clk / Rst
  42         clk32 = platform.request("clk32")
  43
  44         # PLL
  45         self.submodules.pll = pll = S6PLL(speedgrade=-1)
  46         pll.register_clkin(clk32, 32e6)
  47         pll.create_clkout(self.cd_sys, sys_clk_freq)
  48         if sdram_rate == "1:2":
  49             pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
  50             pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
  51         else:
  52             pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
  53
  54         # SDRAM clock
  55         sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
  56         self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
  57
  58 # BaseSoC ------------------------------------------------------------------------------------------
  59
  60 class BaseSoC(SoCCore):
  61     def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", **kwargs):
  62         platform = minispartan6.Platform()
  63
  64         # SoCCore ----------------------------------------------------------------------------------
  65         SoCCore.__init__(self, platform, sys_clk_freq,
  66             ident          = "LiteX SoC on MiniSpartan6",
  67             ident_version  = True,
  68             **kwargs)
  69
  70         # CRG --------------------------------------------------------------------------------------
  71         self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
  72
  73         # SDR SDRAM --------------------------------------------------------------------------------
  74         if not self.integrated_main_ram_size:
  75             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
  76             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
  77             self.add_sdram("sdram",
  78                 phy                     = self.sdrphy,
  79                 module                  = AS4C16M16(sys_clk_freq, sdram_rate),
  80                 origin                  = self.mem_map["main_ram"],
  81                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  82                 l2_cache_size           = kwargs.get("l2_size", 8192),
  83                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  84                 l2_cache_reverse        = True
  85             )
  86
  87         # Leds -------------------------------------------------------------------------------------
  88         self.submodules.leds = LedChaser(
  89             pads         = platform.request_all("user_led"),
  90             sys_clk_freq = sys_clk_freq)
  91         self.add_csr("leds")
  92
  93 # Build --------------------------------------------------------------------------------------------
  94
  95 def main():
  96     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
  97     parser.add_argument("--build",        action="store_true", help="Build bitstream")
  98     parser.add_argument("--load",         action="store_true", help="Load bitstream")
  99     parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
 100     builder_args(parser)
 101     soc_sdram_args(parser)
 102     args = parser.parse_args()
 103
 104     soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
 105     builder = Builder(soc, **builder_argdict(args))
 106     builder.build(run=args.build)
 107
 108     if args.load:
 109         prog = soc.platform.create_programmer()
 110         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 111
 112 if __name__ == "__main__":
 113     main()