litex/boards/targets/netv2.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import os
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.boards.platforms import netv2
  12
  13 from litex.soc.cores.clock import *
  14 from litex.soc.integration.soc_core import *
  15 from litex.soc.integration.soc_sdram import *
  16 from litex.soc.integration.builder import *
  17 from litex.soc.cores.led import LedChaser
  18
  19 from litedram.modules import K4B2G1646F
  20 from litedram.phy import s7ddrphy
  21
  22 from liteeth.phy.rmii import LiteEthPHYRMII
  23
  24 # CRG ----------------------------------------------------------------------------------------------
  25
  26 class _CRG(Module):
  27     def __init__(self, platform, sys_clk_freq):
  28         self.clock_domains.cd_sys       = ClockDomain()
  29         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
  30         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  31         self.clock_domains.cd_clk200    = ClockDomain()
  32         self.clock_domains.cd_clk100    = ClockDomain()
  33         self.clock_domains.cd_eth       = ClockDomain()
  34
  35         # # #
  36
  37         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  38         pll.register_clkin(platform.request("clk50"), 50e6)
  39         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  40         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
  41         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  42         pll.create_clkout(self.cd_clk200,    200e6)
  43         pll.create_clkout(self.cd_clk100,    100e6)
  44         pll.create_clkout(self.cd_eth,       50e6)
  45
  46         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  47
  48 # BaseSoC ------------------------------------------------------------------------------------------
  49
  50 class BaseSoC(SoCCore):
  51     def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
  52         platform = netv2.Platform()
  53
  54         # SoCCore ----------------------------------------------------------------------------------
  55         SoCCore.__init__(self, platform, sys_clk_freq,
  56             ident          = "LiteX SoC on NeTV2",
  57             ident_version  = True,
  58             **kwargs)
  59
  60         # CRG --------------------------------------------------------------------------------------
  61         self.submodules.crg = _CRG(platform, sys_clk_freq)
  62
  63         # DDR3 SDRAM -------------------------------------------------------------------------------
  64         if not self.integrated_main_ram_size:
  65             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  66                 memtype      = "DDR3",
  67                 nphases      = 4,
  68                 sys_clk_freq = sys_clk_freq)
  69             self.add_csr("ddrphy")
  70             self.add_sdram("sdram",
  71                 phy                     = self.ddrphy,
  72                 module                  = K4B2G1646F(sys_clk_freq, "1:4"),
  73                 origin                  = self.mem_map["main_ram"],
  74                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  75                 l2_cache_size           = kwargs.get("l2_size", 8192),
  76                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  77                 l2_cache_reverse        = True
  78             )
  79
  80         # Ethernet ---------------------------------------------------------------------------------
  81         if with_ethernet:
  82             self.submodules.ethphy = LiteEthPHYRMII(
  83                 clock_pads = self.platform.request("eth_clocks"),
  84                 pads       = self.platform.request("eth"))
  85             self.add_csr("ethphy")
  86             self.add_ethernet(phy=self.ethphy)
  87
  88         # Leds -------------------------------------------------------------------------------------
  89         self.submodules.leds = LedChaser(
  90             pads         = platform.request_all("user_led"),
  91             sys_clk_freq = sys_clk_freq)
  92         self.add_csr("leds")
  93
  94 # Build --------------------------------------------------------------------------------------------
  95
  96 def main():
  97     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
  98     parser.add_argument("--build", action="store_true", help="Build bitstream")
  99     parser.add_argument("--load",  action="store_true", help="Load bitstream")
 100     builder_args(parser)
 101     soc_sdram_args(parser)
 102     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
 103     args = parser.parse_args()
 104
 105     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
 106     builder = Builder(soc, **builder_argdict(args))
 107     builder.build(run=args.build)
 108
 109     if args.load:
 110         prog = soc.platform.create_programmer()
 111         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 112
 113 if __name__ == "__main__":
 114     main()