litex/boards/targets/nexys4ddr.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import os
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.boards.platforms import nexys4ddr
  12
  13 from litex.soc.cores.clock import *
  14 from litex.soc.integration.soc_core import *
  15 from litex.soc.integration.soc_sdram import *
  16 from litex.soc.integration.builder import *
  17 from litex.soc.cores.led import LedChaser
  18
  19 from litedram.modules import MT47H64M16
  20 from litedram.phy import s7ddrphy
  21
  22 from liteeth.phy.rmii import LiteEthPHYRMII
  23
  24 # CRG ----------------------------------------------------------------------------------------------
  25
  26 class _CRG(Module):
  27     def __init__(self, platform, sys_clk_freq):
  28         self.clock_domains.cd_sys       = ClockDomain()
  29         self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
  30         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
  31         self.clock_domains.cd_clk200    = ClockDomain()
  32         self.clock_domains.cd_eth       = ClockDomain()
  33
  34         # # #
  35
  36         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
  37         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
  38         pll.register_clkin(platform.request("clk100"), 100e6)
  39         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  40         pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
  41         pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
  42         pll.create_clkout(self.cd_clk200,    200e6)
  43         pll.create_clkout(self.cd_eth,       50e6)
  44
  45         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  46
  47 # BaseSoC ------------------------------------------------------------------------------------------
  48
  49 class BaseSoC(SoCCore):
  50     def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
  51         platform = nexys4ddr.Platform()
  52
  53         # SoCCore ----------------------------------_-----------------------------------------------
  54         SoCCore.__init__(self, platform, sys_clk_freq,
  55             ident          = "LiteX SoC on Nexys4DDR",
  56             ident_version  = True,
  57             **kwargs)
  58
  59         # CRG --------------------------------------------------------------------------------------
  60         self.submodules.crg = _CRG(platform, sys_clk_freq)
  61
  62         # DDR2 SDRAM -------------------------------------------------------------------------------
  63         if not self.integrated_main_ram_size:
  64             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  65                 memtype      = "DDR2",
  66                 nphases      = 2,
  67                 sys_clk_freq = sys_clk_freq)
  68             self.add_csr("ddrphy")
  69             self.add_sdram("sdram",
  70                 phy                     = self.ddrphy,
  71                 module                  = MT47H64M16(sys_clk_freq, "1:2"),
  72                 origin                  = self.mem_map["main_ram"],
  73                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  74                 l2_cache_size           = kwargs.get("l2_size", 8192),
  75                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  76                 l2_cache_reverse        = True
  77             )
  78
  79         # Ethernet ---------------------------------------------------------------------------------
  80         if with_ethernet:
  81             self.submodules.ethphy = LiteEthPHYRMII(
  82                 clock_pads = self.platform.request("eth_clocks"),
  83                 pads       = self.platform.request("eth"))
  84             self.add_csr("ethphy")
  85             self.add_ethernet(phy=self.ethphy)
  86
  87         # Leds -------------------------------------------------------------------------------------
  88         self.submodules.leds = LedChaser(
  89             pads         = platform.request_all("user_led"),
  90             sys_clk_freq = sys_clk_freq)
  91         self.add_csr("leds")
  92
  93 # Build --------------------------------------------------------------------------------------------
  94
  95 def main():
  96     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
  97     parser.add_argument("--build", action="store_true", help="Build bitstream")
  98     parser.add_argument("--load",  action="store_true", help="Load bitstream")
  99     builder_args(parser)
 100     soc_sdram_args(parser)
 101     parser.add_argument("--sys-clk-freq",  default=75e6,          help="System clock frequency (default=75MHz)")
 102     parser.add_argument("--with-ethernet", action="store_true",   help="Enable Ethernet support")
 103     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
 104     parser.add_argument("--with-sdcard", action="store_true",     help="Enable SDCard support")
 105     args = parser.parse_args()
 106
 107     soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 108         with_ethernet=args.with_ethernet,
 109         **soc_sdram_argdict(args))
 110     assert not (args.with_spi_sdcard and args.with_sdcard)
 111     if args.with_spi_sdcard:
 112         soc.add_spi_sdcard()
 113     if args.with_sdcard:
 114         soc.add_sdcard()
 115     builder = Builder(soc, **builder_argdict(args))
 116     builder.build(run=args.build)
 117
 118     if args.load:
 119         prog = soc.platform.create_programmer()
 120         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 121
 122 if __name__ == "__main__":
 123     main()