litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2018 David Shah <dave@ds0.me>
   5 # License: BSD
   6
   7 import os
   8 import argparse
   9 import sys
  10
  11 from migen import *
  12 from migen.genlib.resetsync import AsyncResetSynchronizer
  13
  14 from litex.build.io import DDROutput
  15
  16 from litex.boards.platforms import ulx3s
  17
  18 from litex.build.lattice.trellis import trellis_args, trellis_argdict
  19
  20 from litex.soc.cores.clock import *
  21 from litex.soc.integration.soc_core import *
  22 from litex.soc.integration.soc_sdram import *
  23 from litex.soc.integration.builder import *
  24 from litex.soc.cores.led import LedChaser
  25
  26 from litedram import modules as litedram_modules
  27 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
  28
  29 # CRG ----------------------------------------------------------------------------------------------
  30
  31 class _CRG(Module):
  32     def __init__(self, platform, sys_clk_freq, with_usb_pll=False, sdram_rate="1:1"):
  33         self.clock_domains.cd_sys    = ClockDomain()
  34         if sdram_rate == "1:2":
  35             self.clock_domains.cd_sys2x    = ClockDomain()
  36             self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
  37         else:
  38             self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  39
  40         # # #
  41
  42         # Clk / Rst
  43         clk25 = platform.request("clk25")
  44         rst   = platform.request("rst")
  45
  46         # PLL
  47         self.submodules.pll = pll = ECP5PLL()
  48         self.comb += pll.reset.eq(rst)
  49         pll.register_clkin(clk25, 25e6)
  50         pll.create_clkout(self.cd_sys,    sys_clk_freq)
  51         if sdram_rate == "1:2":
  52             pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
  53             pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
  54         else:
  55            pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
  56         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
  57
  58         # USB PLL
  59         if with_usb_pll:
  60             self.submodules.usb_pll = usb_pll = ECP5PLL()
  61             usb_pll.register_clkin(clk25, 25e6)
  62             self.clock_domains.cd_usb_12 = ClockDomain()
  63             self.clock_domains.cd_usb_48 = ClockDomain()
  64             usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
  65             usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
  66
  67         # SDRAM clock
  68         sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
  69         self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
  70
  71         # Prevent ESP32 from resetting FPGA
  72         self.comb += platform.request("wifi_gpio0").eq(1)
  73
  74 # BaseSoC ------------------------------------------------------------------------------------------
  75
  76 class BaseSoC(SoCCore):
  77     def __init__(self, device="LFE5U-45F", toolchain="trellis",
  78         sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs):
  79
  80         platform = ulx3s.Platform(device=device, toolchain=toolchain)
  81
  82         # SoCCore ----------------------------------------------------------------------------------
  83         SoCCore.__init__(self, platform, sys_clk_freq,
  84             ident          = "LiteX SoC on ULX3S",
  85             ident_version  = True,
  86             **kwargs)
  87
  88         # CRG --------------------------------------------------------------------------------------
  89         with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
  90         self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, sdram_rate=sdram_rate)
  91
  92         # SDR SDRAM --------------------------------------------------------------------------------
  93         if not self.integrated_main_ram_size:
  94             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
  95             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
  96             self.add_sdram("sdram",
  97                 phy                     = self.sdrphy,
  98                 module                  = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
  99                 origin                  = self.mem_map["main_ram"],
 100                 size                    = kwargs.get("max_sdram_size", 0x40000000),
 101                 l2_cache_size           = kwargs.get("l2_size", 8192),
 102                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
 103                 l2_cache_reverse        = True
 104             )
 105
 106         # Leds -------------------------------------------------------------------------------------
 107         self.submodules.leds = LedChaser(
 108             pads         = platform.request_all("user_led"),
 109             sys_clk_freq = sys_clk_freq)
 110         self.add_csr("leds")
 111
 112 # Build --------------------------------------------------------------------------------------------
 113
 114 def main():
 115     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
 116     parser.add_argument("--build", action="store_true", help="Build bitstream")
 117     parser.add_argument("--load",  action="store_true", help="Load bitstream")
 118     parser.add_argument("--toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
 119     parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
 120     parser.add_argument("--sys-clk-freq", default=50e6,           help="System clock frequency (default=50MHz)")
 121     parser.add_argument("--sdram-module", default="MT48LC16M16",  help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
 122     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
 123     parser.add_argument("--with-sdcard", action="store_true",     help="Enable SDCard support")
 124     parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
 125     builder_args(parser)
 126     soc_sdram_args(parser)
 127     trellis_args(parser)
 128     args = parser.parse_args()
 129
 130     soc = BaseSoC(device=args.device, toolchain=args.toolchain,
 131         sys_clk_freq     = int(float(args.sys_clk_freq)),
 132         sdram_module_cls = args.sdram_module,
 133         sdram_rate       = args.sdram_rate,
 134         **soc_sdram_argdict(args))
 135     assert not (args.with_spi_sdcard and args.with_sdcard)
 136     if args.with_spi_sdcard:
 137         soc.add_spi_sdcard()
 138     if args.with_sdcard:
 139         soc.add_sdcard()
 140     builder = Builder(soc, **builder_argdict(args))
 141     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
 142     builder.build(**builder_kargs, run=args.build)
 143
 144     if args.load:
 145         prog = soc.platform.create_programmer()
 146         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
 147
 148 if __name__ == "__main__":
 149     main()