litex/soc/cores/cpu/__init__.py

   1 # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # This file is Copyright (c) 2017-2018 Tim 'mithro' Ansell <me@mith.ro>
   3 # License: BSD
   4
   5 from migen import *
   6
   7 # CPU ----------------------------------------------------------------------------------------------
   8
   9 class CPU(Module):
  10     name                 = None
  11     data_width           = None
  12     endianness           = None
  13     gcc_triple           = None
  14     gcc_flags            = None
  15     clang_triple         = None
  16     clang_flags          = None
  17     linker_output_format = None
  18     interrupts           = {}
  19     mem_map              = {}
  20     io_regions           = {}
  21     use_rom              = False
  22
  23     def __init__(self, *args, **kwargs):
  24         pass
  25
  26 class CPUNone(CPU):
  27     variants             = ["standard"]
  28     data_width           = 32
  29     endianness           = "little"
  30     reset_address        = 0x00000000
  31     io_regions           = {0x00000000: 0x100000000} # origin, length
  32     periph_buses         = []
  33     memory_buses         = []
  34     mem_map              = {"csr": 0x00000000}
  35
  36 CPU_GCC_TRIPLE_RISCV32 = (
  37     "riscv64-unknown-elf",
  38     "riscv32-unknown-elf",
  39     "riscv64-elf",
  40     "riscv32-elf",
  41     "riscv-none-embed",
  42     "riscv64-linux",
  43     "riscv64-linux-gnu-gcc",
  44     "riscv-sifive-elf",
  45     "riscv64-none-elf",
  46 )
  47
  48 CPU_GCC_TRIPLE_RISCV64 = (
  49     "riscv64-unknown-elf",
  50     "riscv64-elf",
  51     "riscv64-linux",
  52     "riscv64-linux-gnu-gcc",
  53     "riscv-sifive-elf",
  54     "riscv64-none-elf",
  55 )
  56
  57 # CPUS ---------------------------------------------------------------------------------------------
  58
  59 # LM32
  60 from litex.soc.cores.cpu.lm32 import LM32
  61
  62 # OpenRisc
  63 from litex.soc.cores.cpu.mor1kx import MOR1KX
  64
  65 # OpenPower
  66 from litex.soc.cores.cpu.microwatt import Microwatt
  67
  68 # RISC-V (32-bit)
  69 from litex.soc.cores.cpu.serv import SERV
  70 from litex.soc.cores.cpu.picorv32 import PicoRV32
  71 from litex.soc.cores.cpu.minerva import Minerva
  72 from litex.soc.cores.cpu.vexriscv import VexRiscv
  73 from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
  74 from litex.soc.cores.cpu.cv32e40p import CV32E40P
  75
  76 # RISC-V (64-bit)
  77 from litex.soc.cores.cpu.rocket import RocketRV64
  78 from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
  79
  80 # Zynq
  81 from litex.soc.cores.cpu.zynq7000 import Zynq7000
  82
  83
  84 CPUS = {
  85     # None
  86     "None"        : CPUNone,
  87
  88     # External (CPU class provided externally by design/user)
  89     "external"    : None,
  90
  91     # LM32
  92     "lm32"        : LM32,
  93
  94     # OpenRisc
  95     "mor1kx"      : MOR1KX,
  96
  97     # OpenPower
  98     "microwatt"   : Microwatt,
  99
 100     # RISC-V (32-bit)
 101     "serv"        : SERV,
 102     "picorv32"    : PicoRV32,
 103     "minerva"     : Minerva,
 104     "vexriscv"    : VexRiscv,
 105     "vexriscv_smp": VexRiscvSMP,
 106     "cv32e40p"    : CV32E40P,
 107
 108     # RISC-V (64-bit)
 109     "rocket"      : RocketRV64,
 110     "blackparrot" : BlackParrotRV64,
 111
 112     # Zynq
 113     "zynq7000"    : Zynq7000,
 114 }