soc/cores/cpu/vexriscv_smp integration
[litex.git] / litex / soc / cores / cpu / vexriscv_smp / crt0.S
1 .global main
2 .global isr
3 .global _start
4
5 .global smp_lottery_target
6 .global smp_lottery_lock
7 .global smp_lottery_args
8 .global smp_slave
9
10 _start:
11 j crt_init
12 nop
13 nop
14 nop
15 nop
16 nop
17 nop
18 nop
19
20 .global trap_entry
21 trap_entry:
22 sw x1, - 1*4(sp)
23 sw x5, - 2*4(sp)
24 sw x6, - 3*4(sp)
25 sw x7, - 4*4(sp)
26 sw x10, - 5*4(sp)
27 sw x11, - 6*4(sp)
28 sw x12, - 7*4(sp)
29 sw x13, - 8*4(sp)
30 sw x14, - 9*4(sp)
31 sw x15, -10*4(sp)
32 sw x16, -11*4(sp)
33 sw x17, -12*4(sp)
34 sw x28, -13*4(sp)
35 sw x29, -14*4(sp)
36 sw x30, -15*4(sp)
37 sw x31, -16*4(sp)
38 addi sp,sp,-16*4
39 call isr
40 lw x1 , 15*4(sp)
41 lw x5, 14*4(sp)
42 lw x6, 13*4(sp)
43 lw x7, 12*4(sp)
44 lw x10, 11*4(sp)
45 lw x11, 10*4(sp)
46 lw x12, 9*4(sp)
47 lw x13, 8*4(sp)
48 lw x14, 7*4(sp)
49 lw x15, 6*4(sp)
50 lw x16, 5*4(sp)
51 lw x17, 4*4(sp)
52 lw x28, 3*4(sp)
53 lw x29, 2*4(sp)
54 lw x30, 1*4(sp)
55 lw x31, 0*4(sp)
56 addi sp,sp,16*4
57 mret
58 .text
59
60 crt_init:
61 la sp, _fstack + 4
62 la a0, trap_entry
63 csrw mtvec, a0
64 sw x0, smp_lottery_lock, a1
65
66 data_init:
67 la a0, _fdata
68 la a1, _edata
69 la a2, _fdata_rom
70 data_loop:
71 beq a0,a1,data_done
72 lw a3,0(a2)
73 sw a3,0(a0)
74 add a0,a0,4
75 add a2,a2,4
76 j data_loop
77 data_done:
78
79 smp_tyranny:
80 csrr a0, mhartid
81 beqz a0, bss_init
82 call smp_slave
83
84
85
86 bss_init:
87 la a0, _fbss
88 la a1, _ebss
89 bss_loop:
90 beq a0,a1,bss_done
91 sw zero,0(a0)
92 add a0,a0,4
93 j bss_loop
94 bss_done:
95
96 call main
97 infinit_loop:
98 j infinit_loop
99
100
101
102 //Initialized to avoid having them set to zero by BSS clear
103 .bss
104 smp_lottery_target: .word 0
105 smp_lottery_args: .word 0; .word 0; .word 0
106 smp_lottery_lock: .word 0
107