litex/soc/cores/cpu/vexriscv_smp/system.h

   1 #ifndef __SYSTEM_H
   2 #define __SYSTEM_H
   3
   4 #include <csr-defs.h>
   5
   6 #ifdef __cplusplus
   7 extern "C" {
   8 #endif
   9
  10 __attribute__((unused)) static void flush_cpu_icache(void)
  11 {
  12   asm volatile(
  13     ".word(0x100F)\n"
  14     "nop\n"
  15     "nop\n"
  16     "nop\n"
  17     "nop\n"
  18     "nop\n"
  19   );
  20 }
  21
  22 __attribute__((unused)) static void flush_cpu_dcache(void)
  23 {
  24   asm volatile(".word(0x500F)\n");
  25 }
  26
  27 void flush_l2_cache(void);
  28
  29 void busy_wait(unsigned int ms);
  30
  31 #include <csr-defs.h>
  32
  33 #define csrr(reg) ({ unsigned long __tmp; \
  34   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
  35   __tmp; })
  36
  37 #define csrw(reg, val) ({ \
  38   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
  39   asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
  40   else \
  41   asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
  42
  43 #define csrs(reg, bit) ({ \
  44   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
  45   asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
  46   else \
  47   asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
  48
  49 #define csrc(reg, bit) ({ \
  50   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
  51   asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
  52   else \
  53   asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
  54
  55 #ifdef __cplusplus
  56 }
  57 #endif
  58
  59 #endif /* __SYSTEM_H */